WO2024045329A1

WO2024045329A1 - Semiconductor structure and method for manufacturing same

Info

Publication number: WO2024045329A1
Application number: PCT/CN2022/130071
Authority: WO
Inventors: 吕开敏
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-09-02
Filing date: 2022-11-04
Publication date: 2024-03-07
Also published as: WO2024045329A9; CN117690898A

Abstract

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a method for manufacturing same. The semiconductor structure comprises: a bearing structure; a chip module located on the bearing structure, the chip module comprising a plurality of stacked chips, each chip comprising a front surface and a rear surface which are opposite to each other, and a side surface connected between the front surface and the rear surface, the side surface of each chip being provided with a bonding pad, and the bonding pad being electrically connected to a circuit in the chip; and a circuit connection board, the circuit connection board being arranged opposite to the side surfaces of the plurality of chips and connected to the bonding pads of the plurality of chips, and the circuit connection board being further electrically connected to the bearing structure. The embodiments of the present disclosure at least can reduce the size of a semiconductor structure and improve the performance of the semiconductor structure.

Description

半导体结构和半导体结构的制造方法Semiconductor structures and methods of manufacturing semiconductor structures

交叉引用cross reference

本申请引用于2022年9月2日递交的名称为“半导体结构和半导体结构的制造方法”的第202211073615.8号中国专利申请，其通过引用被全部并入本申请。This application refers to Chinese Patent Application No. 202211073615.8 titled "Semiconductor Structure and Manufacturing Method of Semiconductor Structure" submitted on September 2, 2022, which is fully incorporated into this application by reference.

技术领域Technical field

本公开实施例属于半导体领域，具体涉及一种半导体结构和半导体结构的制造方法。Embodiments of the present disclosure belong to the field of semiconductors, and specifically relate to a semiconductor structure and a manufacturing method of the semiconductor structure.

背景技术Background technique

低功耗内存(Low Power Double Data Rate，LPDDR)具有低功耗和小体积的优点。LPDDR可以采用堆叠封装，以满足不同类型移动设备的需要。堆叠封装将原本一维的存储器布局扩展到三维，即将很多个芯片堆叠在一起并进行封装，从而大幅度提高了芯片的密度，并实现了大容量和高带宽。Low power memory (Low Power Double Data Rate, LPDDR) has the advantages of low power consumption and small size. LPDDR can be packaged in stacks to meet the needs of different types of mobile devices. Stacked packaging extends the original one-dimensional memory layout to three dimensions, that is, stacking many chips together and packaging them, thereby greatly increasing the density of the chips and achieving large capacity and high bandwidth.

然而随着堆叠层数的增多，LPDDR的体积增大，且性能有待提升。However, as the number of stacked layers increases, the size of LPDDR increases and its performance needs to be improved.

发明内容Contents of the invention

本公开实施例提供一种半导体结构和半导体结构的制造方法，至少有利于降低半导体结构的体积，并提升半导体结构的性能。Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure, which are at least beneficial to reducing the volume of the semiconductor structure and improving the performance of the semiconductor structure.

根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，其中，半导体结构包括：承载结构；芯片模块，位于所述承载结构上，所述芯片模块包括多个堆叠设置的芯片；所述芯片具有相对的正面和背面，以及连接在二者之间的侧面；所述芯片的侧面具有焊盘，所述焊盘与所述芯片内的电路电连接；电路连接板，所述电路连接板与多个所述芯片的侧面相对设置，且与多个所述芯片的所述焊盘相连，所述电路连接板还与所述承载结构电连接。According to some embodiments of the present disclosure, on one hand, embodiments of the present disclosure provide a semiconductor structure, wherein the semiconductor structure includes: a carrying structure; a chip module located on the carrying structure, and the chip module includes a plurality of stacked chips; The chip has an opposite front and a back, and a side connected between the two; the side of the chip has a soldering pad, and the soldering pad is electrically connected to the circuit in the chip; a circuit connection board, the circuit The connection board is arranged opposite to the side surfaces of the plurality of chips and is connected to the pads of the plurality of chips. The circuit connection board is also electrically connected to the carrying structure.

根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制造方法，制造方法包括：提供芯片，所述芯片具有相对的正面和背面，以及连接在二者之间的侧面；在所述芯片的侧面形成焊盘，所述焊盘所述芯片内的电路电连接；将多个所述芯片堆叠设置以形成芯片模块；提供电路连接板，将所述电路连接板与多个所述芯片的侧面相对设置，且将所述电路连接板与多个所述芯片的所述焊盘相连；提供承载结构，将所述芯片模块和所述电路连接板设置在所述承载结构上，且将所述电路连接板与所述承载结构电连接。According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a method for manufacturing a semiconductor structure. The manufacturing method includes: providing a chip, the chip having an opposite front and a back, and a side connected between the two. ; Form a welding pad on the side of the chip, and the welding pad is electrically connected to the circuit in the chip; stack a plurality of the chips to form a chip module; provide a circuit connection board, and connect the circuit connection board with multiple The sides of each of the chips are arranged oppositely, and the circuit connection board is connected to the pads of a plurality of the chips; a load-bearing structure is provided, and the chip module and the circuit connection board are arranged on the load-bearing structure on the circuit board, and electrically connect the circuit connection board to the load-bearing structure.

本公开实施例提供的技术方案至少具有以下优点：芯片内的电路与芯片侧面的焊盘电连接，焊盘与电路连接板相连，电路连接板与承载结构电连接。相比于引线键合，电路连接板所占据的空间位置更小，且不易发生脱离或断裂，从而有利于提高半导体结构的性能。The technical solution provided by the embodiment of the present disclosure has at least the following advantages: the circuit in the chip is electrically connected to the pad on the side of the chip, the pad is connected to the circuit connection board, and the circuit connection board is electrically connected to the carrying structure. Compared with wire bonding, the circuit connection board occupies a smaller space and is less prone to detachment or breakage, which is beneficial to improving the performance of the semiconductor structure.

附图说明Description of drawings

此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

图1-图2分别示出了两种LPDDR结构的示意图；Figures 1-2 respectively show schematic diagrams of two LPDDR structures;

图3、图5、图7分别示出了本公开一实施例提供的不同半导体结构的剖面图；Figures 3, 5, and 7 respectively show cross-sectional views of different semiconductor structures provided by an embodiment of the present disclosure;

图4、图6、图8-图11分别示出了本公开一实施例提供的不同半导体结构的俯向透视图；Figures 4, 6, and 8-11 respectively show top perspective views of different semiconductor structures provided by an embodiment of the present disclosure;

图12-图15示出了本公开另一实施例提供的半导体结构的制造方法中各步骤对应的剖面示意图。12-15 show schematic cross-sectional views corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

具体实施方式Detailed ways

参考图1-图2，经分析发现，在LPDDR中，多个芯片的排列方向垂直于承载结构的上表面，芯片100与承载结构200使用引线键合的方式进行电信号连接，引线键合所需要的线环(wire loop)和键合手指(bond finger)等结构占用比较大空间，此外，随着堆叠层数的增多，引线300的长度越来越长，引线300过长会影响产品的运行速率，且增大发热程度。同时引线300会有断裂、脱离等不良等风险，从而降低产品的可靠性和良率。Referring to Figures 1 and 2, it is found through analysis that in LPDDR, the arrangement direction of multiple chips is perpendicular to the upper surface of the load-bearing structure. The chip 100 and the load-bearing structure 200 use wire bonding for electrical signal connection. The wire bonding method The required structures such as wire loops and bond fingers occupy a relatively large space. In addition, as the number of stacked layers increases, the length of the lead 300 becomes longer and longer. If the lead 300 is too long, it will affect the quality of the product. operating speed and increase heat generation. At the same time, the lead 300 may have defects such as breakage and detachment, thereby reducing the reliability and yield of the product.

本公开实施例提供一种半导体结构，其中，芯片的侧面具有焊盘，焊盘与电路连接板相连，电路连接板与承载结构电连接，从而可以实现芯片内的电路与承载结构的电连接。电路连接板的所占据的体积更小，且电路连接板与承载结构的连接强度更高，能够避免发生脱离、断裂的风险，从而提高半导体结构的可靠性和良率。Embodiments of the present disclosure provide a semiconductor structure, in which the side of the chip has a welding pad, the welding pad is connected to a circuit connection board, and the circuit connection board is electrically connected to the load-bearing structure, thereby realizing electrical connection between the circuit in the chip and the load-bearing structure. The circuit connection board occupies a smaller volume, and the connection strength between the circuit connection board and the load-bearing structure is higher, which can avoid the risk of detachment and breakage, thereby improving the reliability and yield of the semiconductor structure.

下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided to enable readers to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can also be implemented.

如图3-图11所示，本公开一实施例提供一种半导体结构，半导体结构包括：承载结构4；芯片模块10，位于承载结构4上，芯片模块10包括多个堆叠设置的芯片1；芯片1具有相对的正面A和背面B，以及连接在二者之间的侧面C；芯片1的侧面C具有焊盘23，焊盘23与芯片1内的电路电连接；电路连接板3，电路连接板3与多个芯片1的侧面C相对设置，且与多个芯片1的焊盘23相连，电路连接板3还与承载结构4电连接。As shown in Figures 3 to 11, an embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a carrying structure 4; a chip module 10 located on the carrying structure 4; the chip module 10 includes a plurality of stacked chips 1; Chip 1 has an opposite front A and a back B, and a side C connected between them; the side C of chip 1 has a pad 23, which is electrically connected to the circuit in chip 1; the circuit connection board 3, the circuit The connection board 3 is arranged opposite to the side surface C of the plurality of chips 1 and is connected to the pads 23 of the plurality of chips 1 . The circuit connection board 3 is also electrically connected to the carrying structure 4 .

这样的设计至少具有如下优点：Such a design has at least the following advantages:

第一，由于芯片1的侧面C与电路连接板3相对设置，因此，相比于将焊盘23设置在正面A或背面B，焊盘23设置在芯片1的侧面C有利于增加焊盘23与电路连接板3的接触面积，从而提高焊接的牢固性，避免发生脱离的风险。First, since the side C of the chip 1 is opposite to the circuit connection board 3 , compared with arranging the bonding pad 23 on the front A or the back B, arranging the bonding pad 23 on the side C of the chip 1 is conducive to increasing the number of bonding pads 23 The contact area with the circuit connection board 3 can thereby improve the firmness of the welding and avoid the risk of detachment.

第二，电路连接板3上可以设置多条走线，从而实现各芯片1与承载结构4的电连接。电路连接板3作为走线的载体，使得走线的布局更为灵活和简便，有利于提高半导体结构的性能，并简化生产工艺。相比于采用引线或大块导电板实现芯片1与承载结构4的电连接，电路连接板3的体积更小，且散热效果更佳。Second, multiple traces can be provided on the circuit connection board 3 to realize the electrical connection between each chip 1 and the carrying structure 4 . The circuit connection board 3 serves as a carrier for wiring, making the layout of the wiring more flexible and simpler, which is beneficial to improving the performance of the semiconductor structure and simplifying the production process. Compared with using leads or large conductive plates to achieve electrical connection between the chip 1 and the load-bearing structure 4, the circuit connection board 3 is smaller in size and has better heat dissipation effect.

以下将对半导体结构进行详细说明。The semiconductor structure will be described in detail below.

在一些实施例中，参考图3、图5、图7，承载结构4可以为基板，比如有机基板或陶瓷基板等。多个芯片1可以包括存储芯片和逻辑芯片，存储芯片与逻辑芯片进行通信，存储芯片可以为动态随机存取存储器(DRAM，Dynamic Random Access Memory)。其中，靠近基板的芯片1可以为逻辑芯片，远离基板的芯片1可以为存储芯片。In some embodiments, referring to FIG. 3 , FIG. 5 , and FIG. 7 , the load-bearing structure 4 may be a substrate, such as an organic substrate or a ceramic substrate. The plurality of chips 1 may include a memory chip and a logic chip. The memory chip communicates with the logic chip. The memory chip may be a dynamic random access memory (DRAM, Dynamic Random Access Memory). Among them, the chip 1 close to the substrate may be a logic chip, and the chip 1 far away from the substrate may be a memory chip.

在另一些实施例中，承载结构4可以是逻辑芯片，多个芯片1均为存储芯片；或者，承载结构4可以是基板，多个芯片1均为存储芯片。In other embodiments, the carrying structure 4 can be a logic chip, and the plurality of chips 1 are all memory chips; or the carrying structure 4 can be a substrate, and the plurality of chips 1 are all memory chips.

承载结构4的上表面具有多个焊接部5，用于与电路连接板3进行焊接。The upper surface of the load-bearing structure 4 has a plurality of welding portions 5 for welding with the circuit connection board 3 .

以下将对电路连接板3进行详细说明。The circuit connection board 3 will be described in detail below.

参考图3-图11，电路连接板3的材料可以选用具有优良散热性能的材料，比如硅基板、树脂板、陶瓷板等。电路连接板3上的走线的材料可以为铜。Referring to Figures 3 to 11, the material of the circuit connection board 3 can be selected from materials with excellent heat dissipation properties, such as silicon substrates, resin boards, ceramic boards, etc. The material of the traces on the circuit connection board 3 may be copper.

电路连接板3朝向芯片模块10的一侧可以具有焊垫7，用于增大芯片1与电路连接板3的焊接面积，进而增加焊接强度。在一些实施例中，焊垫7的尺寸可以和焊盘23的尺寸相同。在另一些实施例中，焊垫7的尺寸也可以略微大于焊盘23的尺寸，即，为对准误差提高一定的设计余量。The side of the circuit connection board 3 facing the chip module 10 may have a welding pad 7 to increase the welding area between the chip 1 and the circuit connection board 3, thereby increasing the welding strength. In some embodiments, the size of bonding pad 7 may be the same as the size of bonding pad 23 . In other embodiments, the size of the bonding pad 7 may also be slightly larger than the size of the bonding pad 23 , that is, a certain design margin is increased for alignment errors.

另外，电路连接板3朝向芯片模块10的一侧可以具有凹槽，焊垫7设置在凹槽中，从而有利于充分利用电路连接板3的空间位置。在另一些实施例中，焊垫7可以凸设于电路连接板3的表面，从而使得电路连接板3的表面与芯片模块10的侧壁相间隔，即在电路连接板3与芯片模块10之间形成散热区域。In addition, the side of the circuit connection board 3 facing the chip module 10 may have a groove, and the soldering pad 7 is disposed in the groove, thereby making full use of the spatial position of the circuit connection board 3 . In other embodiments, the soldering pads 7 can be protruded on the surface of the circuit connection board 3 , so that the surface of the circuit connection board 3 is spaced apart from the side walls of the chip module 10 , that is, between the circuit connection board 3 and the chip module 10 form a heat dissipation area.

需要注意的是，电路连接板3上的多个焊垫7是相互分立的，而非一整块的导电板。这样设计的好处在于：第一，间隔设置的焊垫7的发热程度更低，能够降低对芯片1的不良影响；第二，相比于整块导电板，单个焊垫7与芯片1的胀缩程度的差异更小，能够减小二者的挤压程度，避免产生脱落或机械裂纹。第三，一整块导电板会限制多个芯片1与电路连接板3的连接位置，而多个焊垫7相互独立，则可以灵活布局各芯片1的焊盘23。第四，相比于整块导电板，间隔设置的焊垫7可以节约材料，降低生产成本；且焊垫7所占据的空间位置更小，有利于缩小半导体结构的体积。第五，焊垫7的面积更小，从而有利于增多焊垫7的数量，即提供更多的信号接口。第六，直接将焊垫7与焊盘23相焊接即可实现电路连接板3与芯片1的电连接，工艺更加简单；若采用整块导电板，还需先形成导电板，再将导电板与电路连接板3进行焊接，因此，工艺步骤更为繁杂。It should be noted that the plurality of soldering pads 7 on the circuit connection board 3 are separate from each other and are not a single conductive board. The advantages of this design are: first, the heat generated by the spaced pads 7 is lower, which can reduce the adverse impact on the chip 1; second, compared with the entire conductive plate, the expansion of a single pad 7 and the chip 1 is The difference in shrinkage degree is smaller, which can reduce the degree of extrusion between the two and avoid falling off or mechanical cracks. Third, a whole conductive plate will limit the connection positions of multiple chips 1 and the circuit connection board 3, and the multiple bonding pads 7 are independent of each other, so the bonding pads 23 of each chip 1 can be flexibly laid out. Fourth, compared with the entire conductive plate, the spaced bonding pads 7 can save materials and reduce production costs; and the space occupied by the bonding pads 7 is smaller, which is beneficial to reducing the volume of the semiconductor structure. Fifth, the area of the bonding pads 7 is smaller, which is beneficial to increasing the number of bonding pads 7 , that is, providing more signal interfaces. Sixth, the electrical connection between the circuit connection board 3 and the chip 1 can be achieved by directly welding the pad 7 to the pad 23, and the process is simpler; if a whole conductive plate is used, a conductive plate needs to be formed first, and then the conductive plate Welding is performed with the circuit connection board 3, so the process steps are more complicated.

参考图3、图5、图7，在垂直于承载结构4上表面的方向上，焊盘23的宽度与芯片1的厚度的比例为0.5～1。示例地，焊盘23的宽度与芯片1的厚度相同，即焊盘23较大的宽度能够增大焊接面积，从而有利于增大焊接强度。在一些实施例中，焊盘23的宽度为芯片1厚度的二分之一。需要说明的是，可以采用TSV(Through-Silicon Vias，硅穿孔)的形成工艺形成焊盘23，因此，在焊盘23的宽度较小时，工艺难度更低，工艺时间更短。后续将对此进行详细说明。Referring to Figures 3, 5, and 7, in the direction perpendicular to the upper surface of the carrying structure 4, the ratio of the width of the pad 23 to the thickness of the chip 1 is 0.5 to 1. For example, the width of the bonding pad 23 is the same as the thickness of the chip 1 , that is, a larger width of the bonding pad 23 can increase the welding area, which is beneficial to increasing the welding strength. In some embodiments, the width of pad 23 is half the thickness of chip 1 . It should be noted that the bonding pad 23 can be formed using a TSV (Through-Silicon Vias) formation process. Therefore, when the width of the bonding pad 23 is smaller, the process difficulty is lower and the process time is shorter. This will be explained in detail later.

在一些实施例中，电路连接板3上的走线可以位于电路连接板3朝向芯片模块10的一侧，从而能够便于焊垫7与走线进行电连接。In some embodiments, the traces on the circuit connection board 3 may be located on the side of the circuit connection board 3 facing the chip module 10 , thereby facilitating the electrical connection between the bonding pads 7 and the traces.

此外，多个芯片1所需要的相同信号可以利用电路连接板3上的同一走线连接至承载结构4，如此，有利于减少走线数量，进而可以缩小电路连接板3的体积；此外，还有利于减少电路连接板3与承载结构4之间的焊接部5，从而简化电路连接板3与承载结构4的连接工艺。在另一些实施例中，每个芯片1也可以单独连接电路连接板3上的走线，而不与其它芯片1共用电路连接板3上的走线。In addition, the same signals required by multiple chips 1 can be connected to the carrying structure 4 using the same trace on the circuit connection board 3, which is beneficial to reducing the number of traces and thereby reducing the size of the circuit connection board 3; in addition, It is beneficial to reduce the welding portion 5 between the circuit connection board 3 and the load-bearing structure 4, thereby simplifying the connection process between the circuit connection board 3 and the load-bearing structure 4. In other embodiments, each chip 1 can also be individually connected to the traces on the circuit connection board 3 without sharing the traces on the circuit connection board 3 with other chips 1 .

以下将对芯片1进行详细说明。 Chip 1 will be described in detail below.

在一些实施例中，参考图4、图6、图8、图9，多个芯片1在承载结构4上表面的正投影重叠。如此，芯片模块10的形状更规整，有利于缩小半导体结构的体积。In some embodiments, referring to Figures 4, 6, 8, and 9, the orthographic projections of multiple chips 1 on the upper surface of the carrier structure 4 overlap. In this way, the shape of the chip module 10 is more regular, which is beneficial to reducing the size of the semiconductor structure.

在另一些实施例中，参考图10-图11，相邻芯片1交错设置，即相邻芯片1在承载结构4上表面的正投影具有部分重叠，如此，有利于增大相邻芯片1之间的散热空间以提高散热效果，进而减小芯片模块10与电路连接板3的胀缩程度的差异。具体地，参考图10，相邻芯片1的错位方向平行于电路连接板3的延伸方向，如此，相邻芯片1的焊盘23既可以连接同一电路连接板3，也可以连接不同的电路连接板3。参考图11，相邻芯片1的错位方向垂直于电路连接板3的延伸方向，相应地，可以设置两个相对设置的电路连接板3，以使得相邻芯片1的焊盘23可以分别连接两个电路连接板3。In other embodiments, referring to FIGS. 10 and 11 , adjacent chips 1 are staggered, that is, the orthographic projections of adjacent chips 1 on the upper surface of the bearing structure 4 partially overlap. This is beneficial to increasing the distance between adjacent chips 1 . There is a heat dissipation space between them to improve the heat dissipation effect, thereby reducing the difference in expansion and contraction of the chip module 10 and the circuit connection board 3 . Specifically, referring to Figure 10, the misalignment direction of adjacent chips 1 is parallel to the extension direction of the circuit connection board 3. In this way, the pads 23 of the adjacent chips 1 can be connected to the same circuit connection board 3 or to different circuit connections. Plate 3. Referring to Figure 11, the misalignment direction of adjacent chips 1 is perpendicular to the extension direction of the circuit connection board 3. Correspondingly, two opposite circuit connection boards 3 can be provided so that the pads 23 of the adjacent chips 1 can respectively connect the two circuit connection boards 3. 3 circuit connection boards.

参考图3-图11，芯片1的表面具有衬垫21和布线层220，且布线层220连接在衬垫21与焊盘23之间。也就是说，衬垫21可以作为芯片1内的电路的引出接口，布线层220可以改变引出接口的布局，从而实现衬垫21与焊盘23的电连接。此外，布线层220可以采用具有较高导热性的材料，从而有助于提高芯片1的散热速度。布线层220和衬垫21的材料可以为铝、铜等金属。Referring to FIGS. 3 to 11 , the surface of the chip 1 has a pad 21 and a wiring layer 220 , and the wiring layer 220 is connected between the pad 21 and the pad 23 . That is to say, the pad 21 can serve as the lead-out interface of the circuit in the chip 1 , and the wiring layer 220 can change the layout of the lead-out interface, thereby realizing the electrical connection between the pad 21 and the pad 23 . In addition, the wiring layer 220 can be made of materials with higher thermal conductivity, thereby helping to increase the heat dissipation speed of the chip 1 . The wiring layer 220 and the pad 21 may be made of metal such as aluminum or copper.

在一些实施例中，参考图3和图5，衬垫21和布线层220位于芯片1的正面A，且衬垫21与芯片1内的电路相连。也就是说，在芯片1内的电路制造完成后，可以采用原有的后段工艺形成衬垫21和布线层220，从而可以简化生产工艺。In some embodiments, referring to FIGS. 3 and 5 , the pad 21 and the wiring layer 220 are located on the front side A of the chip 1 , and the pad 21 is connected to the circuit within the chip 1 . That is to say, after the circuit manufacturing in the chip 1 is completed, the original back-end process can be used to form the pad 21 and the wiring layer 220, thereby simplifying the production process.

在另一些实施例中，参考图7，衬垫21和布线层220位于芯片1的背面B，且芯片1还包括贯穿的导电通孔24，导电通孔24与芯片1内的电路相连，并与衬垫21相连。示例地，导电通孔24可以为硅穿孔(Through-Silicon Vias,TSV)。导电通孔24能够提高芯片1的散热程度，从而提高半导体结构的性能。此外，导电通孔24与焊垫7可以在同一工艺步骤中形成，从而降低生产成本。后续将对此进行详细说明。In other embodiments, referring to FIG. 7 , the pad 21 and the wiring layer 220 are located on the backside B of the chip 1 , and the chip 1 also includes a penetrating conductive via 24 , and the conductive via 24 is connected to the circuit in the chip 1 , and Connected to pad 21. For example, the conductive via 24 may be a through-silicon via (TSV). The conductive vias 24 can improve the heat dissipation of the chip 1, thereby improving the performance of the semiconductor structure. In addition, the conductive vias 24 and the bonding pads 7 can be formed in the same process step, thereby reducing production costs. This will be explained in detail later.

参考图3、图5、图7在一些实施例中，对于相邻两个芯片1，一芯片1的正面A与另一芯片1的背面B相对设置。也就是说，芯片模块10中所有芯片1的正面A的朝向相同，所有芯片1的背面B的朝向也相同，半导体结构的均一性更好。需要说明的是，由于芯片1的正面A的发热程度更大，因此，若相邻芯片1的两个正面A相对设置，则可能造成热量堆积。Referring to FIGS. 3 , 5 , and 7 , in some embodiments, for two adjacent chips 1 , the front A of one chip 1 is opposite to the back B of the other chip 1 . That is to say, the front surfaces A of all chips 1 in the chip module 10 are oriented in the same direction, and the back surfaces B of all chips 1 are also oriented in the same direction, so the uniformity of the semiconductor structure is better. It should be noted that since the front side A of the chip 1 generates a greater degree of heat, if the two front sides A of adjacent chips 1 are arranged opposite to each other, heat accumulation may occur.

在一些实施例中，芯片模块10所有的衬垫21均位于芯片1的正面A，因此，采用上述正面A对背面B的堆叠方式可以使得相邻芯片1的衬垫21的距离相同，从而可以提高半导体结构的均一性。在另一些实施例中，芯片模块10的所有衬垫21也可以位于芯片1的背面B。In some embodiments, all the pads 21 of the chip module 10 are located on the front side A of the chip 1. Therefore, using the above stacking method of front side A to back side B can make the distance between the pads 21 of adjacent chips 1 the same, so that the distance between the pads 21 of adjacent chips 1 can be the same. Improve the uniformity of semiconductor structures. In other embodiments, all pads 21 of the chip module 10 may also be located on the backside B of the chip 1 .

在一些实施例中，参考图4、图6、图8-图11，每个芯片1具有多个衬垫21和多个焊垫7，布线层220包括多条间隔设置的布线22，且多条布线22分别与不同的衬垫21相连，从而用于引出不同的信号。In some embodiments, referring to Figures 4, 6, and 8-11, each chip 1 has multiple pads 21 and multiple bonding pads 7. The wiring layer 220 includes multiple spaced apart wirings 22, and multiple The wiring lines 22 are respectively connected to different pads 21 to draw out different signals.

参考图3-图6以及图9-图11，电路连接板3的数量为多个，芯片模块10具有多个侧壁，多个电路连接板3分别位于芯片模块10的不同侧壁；每个电路连接板3与部分芯片1的焊盘23相连，且每个芯片1的焊盘23与至少一个电路连接板3相连。即，每个芯片1具有多个侧面C，多个电路连接板3与芯片1的不同侧面C相对设置。示例地，芯片1在承载结构4上的正投影的形状为矩形，则每个芯片1有四个侧面C，芯片模块10共有四个侧壁。电路连接板3的数量最多可以为四个，即芯片模块10的每个侧壁都可以设有一个电路连接板3。Referring to Figures 3-6 and 9-11, there are multiple circuit connection boards 3, the chip module 10 has multiple side walls, and the multiple circuit connection boards 3 are respectively located on different side walls of the chip module 10; each The circuit connection board 3 is connected to the pads 23 of some of the chips 1 , and the pads 23 of each chip 1 are connected to at least one circuit connection board 3 . That is, each chip 1 has a plurality of side surfaces C, and a plurality of circuit connection boards 3 are arranged opposite to different side surfaces C of the chip 1 . For example, the shape of the orthographic projection of the chip 1 on the carrying structure 4 is a rectangle, then each chip 1 has four sides C, and the chip module 10 has a total of four side walls. The number of circuit connection boards 3 can be up to four, that is, each side wall of the chip module 10 can be provided with one circuit connection board 3 .

也就是说，在电路连接板3的数量较多时，可以为芯片模块10提供更充足的焊接位置和走线位置，从而便于将芯片模块10与电路连接板3进行电连接。That is to say, when the number of circuit connection boards 3 is large, more sufficient welding positions and wiring positions can be provided for the chip module 10 , thereby facilitating the electrical connection between the chip module 10 and the circuit connection board 3 .

在另一些实施例中，参考图7和图8，图8为图7所示的半导体结构的俯向透视图，电路连接板3的数量为一个，且所有芯片1的焊盘23均与电路连接板3相连。即，电路连接板3的数量较少，能够节约成本，缩小半导体结构的体积；此外，还能够减少电路连接板3与芯片模块10和承载结构4的焊接步骤，提高生产效率。In other embodiments, referring to FIGS. 7 and 8 , FIG. 8 is a top perspective view of the semiconductor structure shown in FIG. 7 , the number of circuit connection boards 3 is one, and the pads 23 of all chips 1 are in contact with the circuit. The connecting plate 3 is connected. That is, a smaller number of circuit connection boards 3 can save costs and reduce the size of the semiconductor structure; in addition, it can also reduce the number of welding steps between the circuit connection board 3 and the chip module 10 and the load-bearing structure 4, thereby improving production efficiency.

示例地，芯片模块10中的芯片1的数量可以与电路连接板3的数量成正比。即，在芯片1的数量较多时，可以提供更多的电路连接板3，以便于能够满足每个芯片1的走线需求；在芯片1的数量较少时，可以提供较少的电路连接板3，以降低生产成本，减小半导体结构的体积。举例而言，芯片模块10的芯片1数量少于四个，可以采用一个电路连接板3；芯片1数量为4个至8个，可以采用两个电路连接板3；芯片1数量超过八个，可以用采用三个或四个电路连接板3。By way of example, the number of chips 1 in the chip module 10 may be proportional to the number of circuit connection boards 3 . That is, when the number of chips 1 is large, more circuit connection boards 3 can be provided to meet the wiring requirements of each chip 1; when the number of chips 1 is small, fewer circuit connection boards can be provided. 3. To reduce production costs and reduce the size of semiconductor structures. For example, if the number of chips 1 of the chip module 10 is less than four, one circuit connection board 3 can be used; if the number of chips 1 is 4 to 8, two circuit connection boards 3 can be used; if the number of chips 1 exceeds eight, Three or four circuit connection boards 3 can be used.

具体地，参考图3-图6，电路连接板3为两个，且两个电路连接板3位于芯片模块10的相对两侧。即，芯片1的电路可以从相对两侧的电路连接板3引出。这样的设计至少包括如下优点：第一，由于两个电路连接板3之间的距离较远，从而可以降低信号干扰，还能够便于对承载结构4上的走线进行布局。第二，由于电路连接板3是焊接在芯片模块10侧壁的，因此，电路连接板3也能够对芯片模块10起到固定作用，电路连接板3位于芯片模块10的相对两侧，能够提高结构强度。第三，芯片模块10相对两侧的面积是相同的，因此，两个电路连接板3的面积可以相同，从而有利于提高半导体结构的均一性。第四，半导体结构的对称性更好，能够便于后续对半导体结构进行封装。Specifically, referring to FIGS. 3 to 6 , there are two circuit connection boards 3 , and the two circuit connection boards 3 are located on opposite sides of the chip module 10 . That is, the circuit of the chip 1 can be led out from the circuit connection boards 3 on opposite sides. Such a design at least includes the following advantages: First, since the distance between the two circuit connection boards 3 is relatively long, signal interference can be reduced, and it can also facilitate the layout of the wiring on the load-bearing structure 4 . Second, since the circuit connection board 3 is welded to the side wall of the chip module 10, the circuit connection board 3 can also play a role in fixing the chip module 10. The circuit connection board 3 is located on the opposite sides of the chip module 10, which can improve Structural strength. Third, the areas on opposite sides of the chip module 10 are the same. Therefore, the areas of the two circuit connection boards 3 can be the same, which is beneficial to improving the uniformity of the semiconductor structure. Fourth, the symmetry of the semiconductor structure is better, which can facilitate subsequent packaging of the semiconductor structure.

在一些实施例中，参考图3-图4、图7-图11，每个芯片1具有多个焊盘23，且同一芯片1的多个焊盘23与同一电路连接板3相连。即，每个芯片1的电路从一个电路连接板3引出。由此，便于统一同一芯片1的焊盘23、布线层220以及衬垫21的位置。In some embodiments, referring to FIGS. 3-4 and 7-11 , each chip 1 has multiple pads 23 , and the multiple pads 23 of the same chip 1 are connected to the same circuit connection board 3 . That is, the circuit of each chip 1 is led out from one circuit connection board 3 . This makes it easy to unify the positions of the pads 23 , wiring layers 220 and pads 21 of the same chip 1 .

示例地，参考图3-图4，图4为图3所示的半导体结构的俯向透视图，多个奇数层的芯片1的焊盘23连接同一电路连接板3；多个偶数层的芯片1的焊盘23连接同一电路连接板3。也就是说，相邻两个芯片1的焊盘23与不同的电路连接板3相连，从而可以避免相邻芯片1的信号干扰。同理，参考图9，若芯片模块10与三个电路连接板3相连时，相邻的三个芯片1的焊盘23可以分别连接三个电路连接板3。若芯片模块10与四个电路连接板3相连时，相邻的四个芯片1的焊盘23可以分别连接四个电路连接板3。For example, referring to Figures 3-4, Figure 4 is a top perspective view of the semiconductor structure shown in Figure 3. The pads 23 of multiple odd-numbered layer chips 1 are connected to the same circuit connection board 3; multiple even-numbered layer chips are connected to the same circuit connection board 3. The pad 23 of 1 is connected to the same circuit connection board 3 . That is to say, the pads 23 of two adjacent chips 1 are connected to different circuit connection boards 3 , thereby avoiding signal interference from the adjacent chips 1 . Similarly, referring to FIG. 9 , if the chip module 10 is connected to three circuit connection boards 3 , the pads 23 of three adjacent chips 1 can be connected to the three circuit connection boards 3 respectively. If the chip module 10 is connected to four circuit connection boards 3, the pads 23 of four adjacent chips 1 can be connected to the four circuit connection boards 3 respectively.

继续参考图3-图4，奇数层和偶数层的芯片1的衬垫21分别位于芯片1的相对两侧，且分别靠近与其电连接的电路连接板3。具体地，芯片模块10具有相对的第一侧和第二侧，相邻芯片1的衬垫21分别位于第一侧和第二侧。位于第一侧的衬垫21与位于第一侧的电路连接板3相连，位于第二侧的衬垫21与位于第二侧的电路连接板3相连。如此，在芯片1同一侧的相邻衬垫21的距离更远，从而有利于降低信号干扰；此外，还有利于缩短布线22的长度，以降低线阻。Continuing to refer to FIGS. 3 and 4 , the pads 21 of the odd-numbered and even-numbered layers of the chip 1 are respectively located on opposite sides of the chip 1 and are respectively close to the circuit connection board 3 electrically connected thereto. Specifically, the chip module 10 has opposite first and second sides, and the pads 21 of adjacent chips 1 are respectively located on the first and second sides. The pad 21 on the first side is connected to the circuit connection board 3 on the first side, and the pad 21 on the second side is connected to the circuit connection board 3 on the second side. In this way, the distance between adjacent pads 21 on the same side of the chip 1 is further, which is beneficial to reducing signal interference; in addition, it is also beneficial to shorten the length of the wiring 22 to reduce line resistance.

同理，参考图9，若芯片模块10与三个电路连接板3相连时，则相邻的三个芯片1的衬垫21可以分别靠近芯片模块10的三个侧壁。若芯片模块10与四个电路连接板3相连时，则相邻的四个芯片1的衬垫21可以分别靠近芯片模块10的四个侧壁。Similarly, referring to FIG. 9 , if the chip module 10 is connected to three circuit connection boards 3 , the pads 21 of the three adjacent chips 1 can be close to the three side walls of the chip module 10 respectively. If the chip module 10 is connected to four circuit connection boards 3 , the pads 21 of the four adjacent chips 1 can be close to the four side walls of the chip module 10 respectively.

在另一些实施例中，参考图5-图6，图6为图5所示的半导体结构的俯向透视图，同一芯片1的多个焊盘23也可以与不同的电路连接板3相连，如此，可以增大同一芯片1上的多个焊盘23的距离，避免发生错误的电连接。此外，多个芯片1相同的电路可以与同一电路连接板3电连接。换言之，每个芯片1需要多种不同的信号，可以将这些信号进行分类，使得多个芯片1的相同信号与同一电路连接板3相连，如此，可以降低不同信号之间的干扰。由此可知，根据信号的种类选择不同的电路连接板3，也便于多个芯片1利用电路连接板3上的同一走线，从而减少走线数量。In other embodiments, referring to Figures 5-6, Figure 6 is a top perspective view of the semiconductor structure shown in Figure 5. Multiple pads 23 of the same chip 1 can also be connected to different circuit connection boards 3. In this way, the distance between multiple pads 23 on the same chip 1 can be increased to avoid incorrect electrical connections. In addition, the same circuits of multiple chips 1 can be electrically connected to the same circuit connection board 3 . In other words, each chip 1 requires a variety of different signals, and these signals can be classified so that the same signals from multiple chips 1 are connected to the same circuit connection board 3. In this way, interference between different signals can be reduced. It can be seen from this that selecting different circuit connection boards 3 according to the type of signals also facilitates multiple chips 1 to use the same trace on the circuit connection board 3, thereby reducing the number of traces.

在一些实施例中，参考图4、图6、图9-图11，与同一电路连接板3的多个芯片1的焊盘23可以在垂直于承载结构4上表面的方向上对齐，即焊盘23在承载结构4上表面的正投影重合，如此，半导体结构的均一性更好，工艺更简单。举例而言，多个芯片1具有相同信号的焊盘23在承载结构4上表面的正投影重合，因此，若这些焊盘23与电路连接板3上的同一走线相连，可以缩短走线的长度，从而减小走线的电阻。In some embodiments, referring to Figures 4, 6, and 9-11, the pads 23 of multiple chips 1 of the same circuit connection board 3 can be aligned in a direction perpendicular to the upper surface of the load-bearing structure 4, that is, welded The orthographic projection of the disk 23 on the upper surface of the carrying structure 4 coincides with each other. In this way, the uniformity of the semiconductor structure is better and the process is simpler. For example, the orthographic projections of the pads 23 of multiple chips 1 with the same signal on the upper surface of the carrying structure 4 overlap. Therefore, if these pads 23 are connected to the same trace on the circuit connection board 3, the length of the trace can be shortened. length, thereby reducing the resistance of the trace.

在另一些实施例中，参考图8，与同一电路连接板3的连接的相邻芯片1的焊盘23可以在承载结构4上表面的方向上交错设置，即焊盘23在承载结构4上表面的正投影错开设置或具有部分重叠，从而有利于减小信号干扰。由前述可知，电路连接板3上的焊垫7是相互独立的，而非一整块导电板，因此，可以根据芯片1的焊盘23位置对焊垫7的位置进行灵活调整。In other embodiments, referring to FIG. 8 , the bonding pads 23 of adjacent chips 1 connected to the same circuit connection board 3 may be staggered in the direction of the upper surface of the bearing structure 4 , that is, the bonding pads 23 are on the bearing structure 4 The orthographic projections of the surfaces are staggered or have partial overlap, which helps reduce signal interference. As can be seen from the foregoing, the bonding pads 7 on the circuit connection board 3 are independent of each other, rather than a whole conductive plate. Therefore, the position of the bonding pad 7 can be flexibly adjusted according to the position of the bonding pad 23 of the chip 1 .

参考图3、图5、图7，相邻芯片1之间还具有粘结层6。芯片1和电路连接板3的热胀冷缩程度可能存在差异，粘结层6具有一定的弹性，因此可以起到缓冲作用。比如，芯片1的膨胀程度比电路连接板3的膨胀程度更大时，相邻芯片1可以挤压粘结层6，从而保证芯片1与电路连接板3的焊接强度。此外，由于粘结层6还可以固定位于其两侧的芯片1，从而提高芯片模块10的结构强度。Referring to Figures 3, 5 and 7, there is an adhesive layer 6 between adjacent chips 1. The degree of thermal expansion and contraction of the chip 1 and the circuit connection board 3 may be different, and the adhesive layer 6 has a certain elasticity, so it can play a buffering role. For example, when the expansion degree of chip 1 is greater than the expansion degree of circuit connection board 3, the adjacent chip 1 can squeeze the adhesive layer 6 to ensure the welding strength of chip 1 and circuit connection board 3. In addition, since the adhesive layer 6 can also fix the chips 1 located on both sides thereof, the structural strength of the chip module 10 is improved.

示例地，在垂直于承载结构4上表面的方向上，粘结层6的厚度与芯片1的厚度的比例为0.2～0.4。值得说明地的是，若粘结层6的厚度过小，则其粘结力可能较小，且缓冲作用较小；若粘结层6的厚度过大，则可能造成空间位置的浪费。在粘结层6的厚度与芯片1的厚度的比例保持在上述范围时，有利于兼顾上述两方面的问题。For example, in the direction perpendicular to the upper surface of the load-bearing structure 4 , the ratio of the thickness of the adhesive layer 6 to the thickness of the chip 1 is 0.2 to 0.4. It is worth noting that if the thickness of the adhesive layer 6 is too small, the adhesive force may be small and the buffering effect may be small; if the thickness of the adhesive layer 6 is too large, space may be wasted. When the ratio of the thickness of the adhesive layer 6 to the thickness of the chip 1 is maintained in the above range, it is beneficial to take into account the above two aspects.

在一些实施例中，参考参考图3和图5，粘结层6包括第一粘结层61和第二粘结层62，第二粘结层62位于第一粘结层61上，第二粘结层62的弹性模量大于第一粘结层61的弹性模量。即，第二粘结层62抵抗弹性变形的能力更强。需要说明的是，粘结层6是由一张较大的粘结膜切割而来的，第二粘结层62不易发生变形，从而可以在切割时防止翘曲；而第二粘结层62的粘结力较大，可以保证粘结性能。在另一些实施例中，参考图7，粘结层6也可以为单层结构，由此，结构更加简单，成本更低；或者，粘结层6也可以为三层及三层以上的复合结构。In some embodiments, referring to FIGS. 3 and 5 , the adhesive layer 6 includes a first adhesive layer 61 and a second adhesive layer 62 , the second adhesive layer 62 is located on the first adhesive layer 61 , and the second adhesive layer 62 is disposed on the first adhesive layer 61 . The elastic modulus of the adhesive layer 62 is greater than the elastic modulus of the first adhesive layer 61 . That is, the second adhesive layer 62 has a stronger ability to resist elastic deformation. It should be noted that the adhesive layer 6 is cut from a larger adhesive film, and the second adhesive layer 62 is not easily deformed, thereby preventing warping during cutting; and the second adhesive layer 62 The bonding force is large and the bonding performance can be guaranteed. In other embodiments, referring to FIG. 7 , the adhesive layer 6 can also be a single-layer structure, so that the structure is simpler and the cost is lower; or the adhesive layer 6 can also be a composite of three or more layers. structure.

在一些实施例中，粘结层6在承载结构4上的正投影面积等于芯片1在承载结构4上的正投影面积；即粘结层6的侧面可以与芯片1的侧面齐平，从而便于粘结层6的侧面与电路连接板3相连。由此，粘结层6的缓冲作用更强、粘结力更大，且粘结层6的侧面还能够用于粘结电路连接板3，从而提高结构强度。In some embodiments, the orthographic projection area of the adhesive layer 6 on the carrier structure 4 is equal to the orthographic projection area of the chip 1 on the carrier structure 4; that is, the side surfaces of the adhesive layer 6 can be flush with the side surfaces of the chip 1, thereby facilitating The side surfaces of the adhesive layer 6 are connected to the circuit connection board 3 . As a result, the adhesive layer 6 has a stronger buffering effect and a greater adhesive force, and the side surfaces of the adhesive layer 6 can also be used to bond the circuit connection board 3, thereby improving the structural strength.

需要说明是，在相邻两个芯片1的堆叠方式为正面A对背面B时，粘结层6与一芯片1的正面A粘结，并与另一芯片1的背面B粘结，因此，多个粘结层6的受热程度相对一致，能够避免部分粘结层6因热量堆积而出现不同的老化程度。It should be noted that when two adjacent chips 1 are stacked in the form of front A to back B, the adhesive layer 6 is bonded to the front A of one chip 1 and bonded to the back B of the other chip 1. Therefore, The degree of heating of the plurality of adhesive layers 6 is relatively consistent, which can avoid different degrees of aging of some adhesive layers 6 due to heat accumulation.

在一些实施例中，参考图5-图6，电路连接板3背向芯片模块10的表面上还设置有散热层8，从而有利于提高电路连接板3和芯片模块10的散热速度。散热程度提高有利于降低芯片1和电路连接板3的膨胀程度的差异，从而避免焊盘23与焊垫7发生脱离。由于电路连接板3的表面相对平整，从而便于为散热层8提供安装位置。In some embodiments, referring to FIGS. 5 and 6 , a heat dissipation layer 8 is also provided on the surface of the circuit connection board 3 facing away from the chip module 10 , thereby improving the heat dissipation speed of the circuit connection board 3 and the chip module 10 . The improved degree of heat dissipation is conducive to reducing the difference in expansion degrees of the chip 1 and the circuit connection board 3, thereby preventing the bonding pad 23 from being separated from the bonding pad 7. Since the surface of the circuit connection board 3 is relatively flat, it is convenient to provide an installation position for the heat dissipation layer 8 .

举例而言，散热层8可以为散热芯片1，比如微流道散热芯片。微流道散热芯片中设有微流通道，冷却液体可以进入微流通道吸收热量，此后从微流通道排成以带走热量，通过控制冷却液体在微流通孔中的流动速度以控制散热速率，另外可以选用两相冷却液体，即冷却液体可以因温度变化而产生相变，从而带走更多热量。在另一些实施例中，散热层8还可以其它高导热材料，比如铜、石墨烯、氮化铝等材料。For example, the heat dissipation layer 8 can be a heat dissipation chip 1, such as a microfluidic heat dissipation chip. There are microfluidic channels in the microfluidic heat dissipation chip. The cooling liquid can enter the microfluidic channel to absorb heat, and then be discharged from the microfluidic channel to take away the heat. The heat dissipation rate is controlled by controlling the flow speed of the cooling liquid in the microfluidic holes. , in addition, a two-phase cooling liquid can be selected, that is, the cooling liquid can undergo a phase change due to temperature changes, thereby taking away more heat. In other embodiments, the heat dissipation layer 8 can also be made of other highly thermally conductive materials, such as copper, graphene, aluminum nitride and other materials.

此外，散热层8还可以具有粗糙的表面，以增加散热面积，从而提高散热效果。比如，散热层8的表面可以包括纳米粗糙结构或微米粗糙结构。In addition, the heat dissipation layer 8 may also have a rough surface to increase the heat dissipation area, thereby improving the heat dissipation effect. For example, the surface of the heat dissipation layer 8 may include a nano-rough structure or a micro-rough structure.

在另一些实施例中，散热层8可以位于不设有电路连接板3的芯片模块10的侧壁，由此散热层与芯片模块10的距离更近，能够更好地引导芯片模块10的散热过程。In other embodiments, the heat dissipation layer 8 can be located on the side wall of the chip module 10 that does not have the circuit connection board 3 . Therefore, the heat dissipation layer is closer to the chip module 10 and can better guide the heat dissipation of the chip module 10 . process.

综上所述，通过电路连接板3和焊垫7将芯片1内的电路与承载结构4进行电连接。由此，可以有效的减少引线键合工艺所需要的线环和键合手指需要的空间，从而可以增加芯片1的设计空间，增加容量，此外，完整的焊接结构还可以提高产品的可靠性。此外，可以采用粘结层6、散热层8等结构以降低芯片1和电路连接板3发热而产生的不良影响，从而保证半导体结构的性能。To sum up, the circuit in the chip 1 is electrically connected to the carrying structure 4 through the circuit connection board 3 and the bonding pad 7 . As a result, the space required for wire loops and bonding fingers required in the wire bonding process can be effectively reduced, thereby increasing the design space and capacity of the chip 1. In addition, the complete welding structure can also improve the reliability of the product. In addition, structures such as the adhesive layer 6 and the heat dissipation layer 8 can be used to reduce the adverse effects caused by the heat generated by the chip 1 and the circuit connection board 3, thereby ensuring the performance of the semiconductor structure.

如图12-图15、图3所示，本公开另一实施例提供一种半导体结构的制造方法，以下将结合附图对本申请一实施例提供的半导体结构的制造方法进行详细说明。As shown in FIGS. 12 to 15 and 3 , another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided by an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

参考图12，提供芯片1，芯片1具有相对的正面A和背面B，以及连接在二者之间的侧面；在芯片1的侧面形成焊盘23，焊盘23芯片1内的电路电连接。Referring to Figure 12, a chip 1 is provided. The chip 1 has an opposite front side A and a back side B, and a side connected between the two; a bonding pad 23 is formed on the side of the chip 1, and the bonding pad 23 electrically connects the circuits in the chip 1.

示例地，形成焊盘23的步骤包括：在芯片1的边缘形成通孔，形成填充通孔的焊盘23；对芯片1的边缘进行切割处理，以露出焊盘23的侧面。在一些实施例中，若衬垫21和布线层220形成在芯片1的背面B，则可以在形成焊垫7的过程中，形成贯穿芯片1的导电通孔24，从而简化生产工艺。此外，焊盘23可以覆盖芯片1的整个侧面C，即用于填充焊盘23的通孔贯穿芯片1。For example, the step of forming the bonding pad 23 includes: forming a through hole on the edge of the chip 1 and forming the bonding pad 23 filling the through hole; and cutting the edge of the chip 1 to expose the side of the bonding pad 23 . In some embodiments, if the pad 21 and the wiring layer 220 are formed on the backside B of the chip 1, the conductive via 24 can be formed through the chip 1 during the formation of the bonding pad 7, thereby simplifying the production process. In addition, the bonding pad 23 may cover the entire side C of the chip 1 , that is, the through hole used to fill the bonding pad 23 penetrates the chip 1 .

示例地，可以采用干法刻蚀的方法形成通孔，此后在通孔中沉积金属材料以作为焊盘23。如此，可以避免重构晶圆，生产工艺更加简单。在另一些实施例中，也可以在形成布线层220后，将多个芯片1进行堆叠设置，从而形成芯片模块10，采用模塑工艺将多个芯片模块10进行重构，从而形成重构晶圆。在重构晶圆的侧面形成焊盘23后，再对重构晶圆进行切割，以划分为多个独立的芯片模块10。For example, dry etching can be used to form the through hole, and then a metal material is deposited in the through hole to serve as the pad 23. In this way, wafer reconstruction can be avoided and the production process is simpler. In other embodiments, after the wiring layer 220 is formed, multiple chips 1 can be stacked to form a chip module 10, and a molding process can be used to reconstruct the multiple chip modules 10 to form a reconstructed crystal. round. After the bonding pads 23 are formed on the side of the reconstructed wafer, the reconstructed wafer is then cut into multiple independent chip modules 10 .

在形成焊盘23之前，还包括：在芯片1的表面形成衬垫21和布线层220，从而将芯片1内的电路与焊盘23电连接。示例地，在芯片1表面形成第一绝缘层，对第一绝缘层进行图形化处理，以形成用于填充衬垫21的开口；在开口中沉积导电材料以作为衬垫21。此后，在第一绝缘层上形成第二绝缘层，对第二绝缘层进行图形化处理，以形成用于填充布线层220的沟槽，在沟槽中沉积导线材料以作为布线层220。Before forming the bonding pad 23 , it also includes forming a pad 21 and a wiring layer 220 on the surface of the chip 1 to electrically connect the circuit in the chip 1 to the bonding pad 23 . For example, a first insulating layer is formed on the surface of the chip 1, and the first insulating layer is patterned to form an opening for filling the pad 21; a conductive material is deposited in the opening to serve as the pad 21. Thereafter, a second insulating layer is formed on the first insulating layer, the second insulating layer is patterned to form a trench for filling the wiring layer 220 , and a conductive wire material is deposited in the trench to serve as the wiring layer 220 .

参考图13，将多个芯片1堆叠设置以形成芯片模块10。示例地，芯片1按照两侧交错的方式进行堆叠的方式，即相邻芯片1的焊盘23交错设置。芯片1与芯片1之间可以通过粘结层6进行粘连。粘结层6的材料可以为固晶用胶膜(die attach film，DAF)。粘结工艺较为简单，能够节约成本。此外，粘结层6中还可以掺杂有金属离子，以提高芯片1的散热效果。需要说明的是，在堆叠过程中，位于底层的芯片1的下表面可以暂时不用粘附粘结层6，以便于后续对芯片模块10的进行翻转。Referring to FIG. 13 , a plurality of chips 1 are stacked to form a chip module 10 . For example, the chips 1 are stacked in a staggered manner on both sides, that is, the bonding pads 23 of adjacent chips 1 are staggered. Chip 1 can be adhered to each other through an adhesive layer 6 . The material of the adhesive layer 6 may be die attach film (DAF). The bonding process is relatively simple and can save costs. In addition, the adhesive layer 6 can also be doped with metal ions to improve the heat dissipation effect of the chip 1 . It should be noted that during the stacking process, the adhesive layer 6 may not be adhered to the lower surface of the bottom chip 1 temporarily to facilitate the subsequent flipping of the chip module 10 .

参考图14-图15，提供电路连接板3，将电路连接板3与多个芯片1的侧面相对设置，且将电路连接板3与多个芯片1的焊盘23相连。示例地，参考图14，将堆叠好的芯片模块10垂直焊接在第一块电路连接板3上。参考图15，翻转芯片模块10以使得第一块电路连接板3朝下设置，在芯片模块10的侧壁焊接第二块电路连接板3，以使得两块电路连接板3相对设置。Referring to FIGS. 14 and 15 , a circuit connection board 3 is provided, the circuit connection board 3 is arranged opposite to the sides of the plurality of chips 1 , and the circuit connection board 3 is connected to the pads 23 of the plurality of chips 1 . For example, referring to FIG. 14 , the stacked chip module 10 is vertically welded to the first circuit connection board 3 . Referring to FIG. 15 , the chip module 10 is turned over so that the first circuit connection board 3 is placed downward, and the second circuit connection board 3 is welded to the side wall of the chip module 10 so that the two circuit connection boards 3 are placed oppositely.

参考图3，提供承载结构4，将芯片模块10和电路连接板3设置在承载结构4上，且将电路连接板3与承载结构4电连接。示例地，将芯片模块10再次翻转后，以使电路连接板3垂直于承载结构4，并且将芯片1的焊盘23与电路连接板3的焊垫7进行对准，此后，将电路连接板3焊接在承载结构4上。Referring to FIG. 3 , a bearing structure 4 is provided, the chip module 10 and the circuit connection board 3 are disposed on the bearing structure 4 , and the circuit connection board 3 is electrically connected to the bearing structure 4 . For example, after the chip module 10 is turned over again, the circuit connection board 3 is perpendicular to the carrying structure 4, and the bonding pad 23 of the chip 1 is aligned with the bonding pad 7 of the circuit connection board 3. After that, the circuit connection board is 3 is welded to the load-bearing structure 4.

此外，在焊接之前，还可以在芯片模块10的底部粘附粘结层6，此粘结层6用于粘结承载结构4和底层的芯片1。此外，此粘结层6可以在承载结构4和芯片1的发生胀缩时起到缓冲作用。In addition, before welding, an adhesive layer 6 can also be adhered to the bottom of the chip module 10 . This adhesive layer 6 is used to bond the load-bearing structure 4 and the underlying chip 1 . In addition, the adhesive layer 6 can play a buffering role when the carrying structure 4 and the chip 1 expand and contract.

综上所述，在本申请实施例中，通过重布线层工艺(RDL，ReDistribution Layer)将芯片1表面的衬垫21将信号引到芯片1的边缘。芯片1堆叠所形成的芯片模块10可以垂直焊接在电路连接板3上。To sum up, in the embodiment of the present application, the pad 21 on the surface of the chip 1 leads the signal to the edge of the chip 1 through a redistribution layer process (RDL, ReDistribution Layer). The chip module 10 formed by stacking the chips 1 can be soldered vertically on the circuit connection board 3 .

在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。In the description of this specification, reference to the terms "some embodiments," "exemplarily," etc. means that a particular feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present disclosure or in the example. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.

Claims

一种半导体结构，包括：A semiconductor structure including:

承载结构；load-bearing structure;

芯片模块，位于所述承载结构上，所述芯片模块包括多个堆叠设置的芯片；A chip module is located on the carrying structure, and the chip module includes a plurality of stacked chips;

所述芯片具有相对的正面和背面，以及连接在二者之间的侧面；所述芯片的侧面具有焊盘，所述焊盘与所述芯片内的电路电连接；The chip has an opposite front and a back, and a side connected between the two; the side of the chip has a soldering pad, and the soldering pad is electrically connected to the circuit in the chip;

电路连接板，所述电路连接板与多个所述芯片的侧面相对设置，且与多个所述芯片的所述焊盘相连，所述电路连接板还与所述承载结构电连接。A circuit connection board is arranged opposite to the side surfaces of a plurality of chips and is connected to the pads of a plurality of chips. The circuit connection board is also electrically connected to the load-bearing structure.
根据权利要求1所述的半导体结构，其中，所述芯片的表面具有衬垫和布线层，且所述布线层连接在所述衬垫与所述焊盘之间；The semiconductor structure according to claim 1, wherein the surface of the chip has pads and wiring layers, and the wiring layer is connected between the pads and the pads;

所述衬垫和所述布线层位于所述芯片的正面，且所述衬垫与所述芯片内的电路相连；或者，The pad and the wiring layer are located on the front side of the chip, and the pad is connected to the circuit within the chip; or,

所述衬垫和所述布线层位于所述芯片的背面，且所述芯片还包括贯穿的导电通孔，所述导电通孔与所述芯片内的电路相连，并与所述衬垫相连。The pad and the wiring layer are located on the back side of the chip, and the chip also includes a through conductive via, which is connected to the circuit in the chip and connected to the pad.
根据权利要求2所述的半导体结构，其中，The semiconductor structure of claim 2, wherein

所述电路连接板的数量为一个，且所有所述芯片的所述焊盘均与所述电路连接板相连；或者，The number of the circuit connection board is one, and the pads of all the chips are connected to the circuit connection board; or,

所述电路连接板的数量为多个，所述芯片模块具有多个侧壁，多个所述电路连接板分别位于所述芯片模块的不同侧壁；每个所述电路连接板与部分所述芯片的所述焊盘相连，且每个所述芯片的所述焊盘与至少一个所述电路连接板相连。There are multiple circuit connection boards, the chip module has multiple side walls, and a plurality of circuit connection boards are located on different side walls of the chip module; each of the circuit connection boards is connected to part of the The pads of the chips are connected, and the pads of each chip are connected to at least one of the circuit connection boards.
根据权利要求3所述的半导体结构，其中，所述电路连接板为两个，且两个所述电路连接板位于所述芯片模块的相对两侧。The semiconductor structure according to claim 3, wherein there are two circuit connection boards, and the two circuit connection boards are located on opposite sides of the chip module.
根据权利要求4所述的半导体结构，其中，每个所述芯片具有多个所述焊盘，且同一所述芯片的多个所述焊盘与同一所述电路连接板相连。The semiconductor structure according to claim 4, wherein each chip has a plurality of bonding pads, and the plurality of bonding pads of the same chip are connected to the same circuit connection board.
根据权利要求5所述的半导体结构，其中，The semiconductor structure of claim 5, wherein

多个奇数层的所述芯片的所述焊盘连接同一所述电路连接板；The pads of the chips of multiple odd-numbered layers are connected to the same circuit connection board;

多个偶数层的所述芯片的所述焊盘连接同一所述电路连接板。The pads of the chips of multiple even-numbered layers are connected to the same circuit connection board.
根据权利要求6所述的半导体结构，其中，The semiconductor structure of claim 6, wherein

奇数层和偶数层的所述芯片的所述衬垫分别位于所述芯片的相对两侧，且分别靠近与其电连接的所述电路连接板。The pads of the odd-numbered and even-numbered chips are respectively located on opposite sides of the chip and are respectively close to the circuit connection board electrically connected thereto.
根据权利要求7所述的半导体结构，其中，The semiconductor structure of claim 7, wherein

在垂直于承载结构上表面的方向上，多个奇数层的所述芯片的所述衬垫正对设置；多个偶数层的所述芯片的所述衬垫正对设置。In a direction perpendicular to the upper surface of the load-bearing structure, the pads of the chips of a plurality of odd-numbered layers are arranged facing each other; and the pads of the chips of a plurality of even-numbered layers are arranged facing each other.
根据权利要求1所述的半导体结构，其中，相邻所述芯片之间还具有粘结层。The semiconductor structure according to claim 1, wherein there is an adhesive layer between adjacent chips.
根据权利要求9所述的半导体结构，其中，所述粘结层包括第一粘结层和第二粘结层，所述第二粘结层位于所述第一粘结层上，所述第二粘结层的弹性模量大于所述第一粘结层的弹性模量。The semiconductor structure of claim 9, wherein the adhesive layer includes a first adhesive layer and a second adhesive layer, the second adhesive layer is located on the first adhesive layer, and the third adhesive layer The elastic modulus of the second adhesive layer is greater than the elastic modulus of the first adhesive layer.
根据权利要求9所述的半导体结构，其中，在垂直于承载结构上表面的方向上，所述粘结层的厚度与所述芯片的厚度的比例为0.2～0.4。The semiconductor structure according to claim 9, wherein the ratio of the thickness of the adhesive layer to the thickness of the chip in a direction perpendicular to the upper surface of the carrying structure is 0.2 to 0.4.
根据权利要求9所述的半导体结构，其中，所述粘结层在所述承载结构上的正投影面积等于所述芯片在所述承载结构上的正投影面积；The semiconductor structure according to claim 9, wherein the orthogonal projected area of the adhesive layer on the carrier structure is equal to the orthogonal projected area of the chip on the carrier structure;

所述粘结层的侧面还与所述电路连接板相连。The side surface of the adhesive layer is also connected to the circuit connection board.
根据权利要求1所述的半导体结构，其中，在垂直于承载结构上表面的方向上，所述焊盘的宽度与所述芯片的厚度的比例为0.5～1。The semiconductor structure according to claim 1, wherein the ratio of the width of the pad to the thickness of the chip in a direction perpendicular to the upper surface of the carrying structure is 0.5 to 1.
根据权利要求1所述的半导体结构，其中，对于相邻两个所述芯片，一所述芯片的正面与另一所述芯片的背面相对设置。The semiconductor structure according to claim 1, wherein for two adjacent chips, a front side of one chip is opposite to a back side of the other chip.
一种半导体结构的制造方法，包括：A method of manufacturing a semiconductor structure, including:

提供芯片，所述芯片具有相对的正面和背面，以及连接在二者之间的侧面；在所述芯片的侧面形成焊盘，所述焊盘所述芯片内的电路电连接；Provide a chip, the chip has an opposite front and a back, and a side connected between the two; a bonding pad is formed on the side of the chip, and the pad is electrically connected to the circuit in the chip;

将多个所述芯片堆叠设置以形成芯片模块；Stacking a plurality of the chips to form a chip module;

提供电路连接板，将所述电路连接板与多个所述芯片的侧面相对设置，且将所述电路连接板与多个所述芯片的所述焊盘相连；Providing a circuit connection board, disposing the circuit connection board opposite to the sides of the plurality of chips, and connecting the circuit connection board to the pads of the plurality of chips;

提供承载结构，将所述芯片模块和所述电路连接板设置在所述承载结构上，且将所述电路连接板与所述承载结构电连接。A bearing structure is provided, the chip module and the circuit connection board are arranged on the bearing structure, and the circuit connection board is electrically connected to the bearing structure.
根据权利要求15所述的半导体结构的制造方法，其中，形成所述焊盘的步骤包括：The method of manufacturing a semiconductor structure according to claim 15, wherein the step of forming the bonding pad includes:

在所述芯片的边缘形成通孔，形成填充所述通孔的所述焊盘；Form a through hole at the edge of the chip and form the pad filling the through hole;

对所述芯片的边缘进行切割处理，以露出所述焊盘的侧面。The edge of the chip is cut to expose the side of the pad.