CN109755215B - Semiconductor package and method of manufacturing the same - Google Patents
Semiconductor package and method of manufacturing the same Download PDFInfo
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- CN109755215B CN109755215B CN201711061893.0A CN201711061893A CN109755215B CN 109755215 B CN109755215 B CN 109755215B CN 201711061893 A CN201711061893 A CN 201711061893A CN 109755215 B CN109755215 B CN 109755215B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000005520 cutting process Methods 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 238000004806 packaging method and process Methods 0.000 claims description 6
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- 229910052710 silicon Inorganic materials 0.000 abstract description 4
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- 229910052751 metal Inorganic materials 0.000 description 19
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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Abstract
The application discloses a semiconductor package and a manufacturing method thereof, the semiconductor package includes: the chip set comprises a plurality of single chips which are stacked, the single chips are interconnected through a plurality of via holes, the chip set is provided with a hole cutting pad exposed to the side edge, and the hole cutting pad is formed by axially and vertically cutting one outer via hole of the chip set; and the side chip is vertically jointed to the side edge of the chip group, the side chip comprises a plurality of connecting pieces on the active surface of the side chip, and the end parts of the connecting pieces are jointed to the hole cutting pads of the chip group so as to realize the electrical connection between the chip group and the side chip. The side chip in this application directly is connected with the chipset electricity through the hole cutting pad that forms at via hole axial vertical direction, compares in prior art base chip and the mode that the bottommost monomer chip of piling up the chipset passes through silicon through-hole interconnect, and the interconnection route of the side chip of this application scheme and chipset shortens, and signal integrality is better.
Description
Technical Field
The present disclosure relates to the field of semiconductor packaging, and more particularly, to a semiconductor package and a method for manufacturing the same.
Background
Through Silicon Via (TSV) interconnection technology is widely applied to the field of semiconductor packaging, and is a technical solution for realizing interconnection of stacked chips in a 3D integrated circuit. The TSV technology is a technology for realizing interconnection between chips by making vertical conduction between the chips and between the wafer and the wafer. For one 3D package through-silicon-via interconnection technique in the prior art, in a 3D package, the connection of the base chip and the bottommost unit chip of the stacked chip set is interconnected by TSVs (as shown by arrows in fig. 4 and 5). As can be seen from fig. 4 and 5, the interconnection path of the base chip and the lowermost individual chip of the stacked chip set is long, which may affect the integrity of the signal to some extent.
Disclosure of Invention
An object of the present application is to provide a semiconductor package capable of shortening an interconnection path and a method of manufacturing the same.
In order to achieve the above object, in a first aspect of the present application, there is provided a semiconductor package, a chip set including a plurality of unit chips stacked and interconnected by a plurality of via holes, the chip set having a hole cutting pad exposed to a side, the hole cutting pad being formed by an outer via hole of the chip set by an axial vertical cutting; and the side chip is vertically jointed to the side edge of the chip group, the side chip comprises a plurality of connecting pieces on the active surface of the side chip, and the end parts of the connecting pieces are jointed to the hole cutting pads of the chip group so as to realize the electrical connection of the chip group and the side chip.
Optionally, the semiconductor package further includes a redistribution layer formed on the chipset, and the redistribution layer penetrates through the connector of the side chip and the internal circuit of the side chip to be electrically connected to the hole cutting pad.
Optionally, the semiconductor package further includes a plurality of solder balls disposed on the plurality of pads of the redistribution layer.
Optionally, the redistribution layer is directly formed on an active surface of an uppermost single chip of the chipset.
Optionally, the single chips are bonded without adhesive, and the individual length of the hole cutting pad is smaller than the thickness definition of the single chips.
Optionally, the filler material of the hole cutting pad is copper.
Optionally, the side chips include an integration of a physical layer chip and a control layer chip, and the single chip includes a dynamic random access memory chip.
Alternatively, the connecting members located in the same vertical row are electrically connected to each other using the internal circuits of the side chips.
In a second aspect of the present application, there is provided a method for manufacturing a semiconductor package, the method comprising: the chip group is manufactured in a wafer level chip packaging mode and comprises a plurality of single chips which are stacked, and the single chips are interconnected through a plurality of via holes; vertically cutting along the axial direction of an outer side through hole of the chip set to form a hole cutting pad exposed to the side edge; arranging a plurality of connecting pieces on an active surface of a side chip to form the side chip; and bonding the end of the connector of the side chip to the hole cutting pad of the chip group to electrically connect the chip group and the side chip.
Optionally, the method further includes forming a redistribution layer on the chipset, and electrically connecting the redistribution layer to the hole cutting pad through the connecting member of the side chip and the internal circuit of the side chip.
Optionally, the method further comprises disposing a plurality of solder balls on the plurality of pads of the redistribution layer.
Optionally, the redistribution layer is directly formed on an active surface of an uppermost single chip of the chipset.
Optionally, the single chips are bonded without adhesive, and the individual length of the hole cutting pad is smaller than the thickness definition of the single chips.
Optionally, the filler material of the hole cutting pad is copper.
Optionally, the side chips include an integration of a physical layer chip and a control layer chip, and the single chip includes a dynamic random access memory chip.
Alternatively, the connecting members located in the same vertical row are electrically connected to each other using the internal circuits of the side chips.
Through the technical scheme of the invention, the side chips are directly and electrically connected with the chip set through the hole cutting pads formed in the axial vertical direction of the via holes, and compared with the mode that the substrate chip and the bottommost single chip of the stacked chip set are interconnected through the silicon through holes in the prior art, the interconnection path between the side chips and the chip set is shortened, and the signal integrity is better.
Additional features and advantages of the present application will be described in detail in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
fig. 1 is a sectional view illustrating a semiconductor package according to an embodiment of the present application along a-a' line in a direction B of fig. 2;
fig. 2 is a plan view illustrating a semiconductor package according to an embodiment of the present application;
fig. 3A to 3P are sectional views of a semiconductor package in a method for manufacturing the semiconductor package according to an embodiment of the present application; and
fig. 4 and 5 show cross-sectional views of a 3D package in the prior art.
Description of the reference numerals
100 semiconductor package 110 chip set
111 single chip 112 via hole
113-hole cutting pad 210 side chip
212 connector 213 pad
214 bump 310 redistribution layer
312 end pad 313 solder ball
400 first wafer group 410 second wafer group
420 third wafer group
Detailed Description
The following detailed description of embodiments of the present application will be made with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present application, are given by way of illustration and explanation only, and are not intended to limit the present application.
In this application, the use of directional words such as "upper, lower, left and right" generally means upper, lower, left and right as illustrated with reference to the drawings, unless stated to the contrary. "inner and outer" refer to the inner and outer contours of the respective component itself.
In the drawings, the shapes shown may be modified depending on manufacturing processes and/or tolerances. Accordingly, the exemplary embodiments of the present application are not limited to the specific shapes illustrated in the drawings, and may include shape changes caused during a manufacturing process. Furthermore, the different elements and regions in the drawings are only schematically shown, so that the application is not limited to the relative dimensions or distances shown in the drawings.
Fig. 1 is a sectional view illustrating a semiconductor package 100 according to an embodiment of the present application along a-a' line in a direction B of fig. 2. The semiconductor package 100 according to an embodiment of the present application may include a chipset 110 and a side chip 210.
The chip set 110 may include a plurality of unit chips 111 and via holes 112 stacked, the via holes 112 vertically penetrating the unit chips 111 for interconnection between the unit chips 111. The single chip 111 may be a Dynamic Random Access Memory (DRAM) chip, an Extended Data Output Random Access Memory (EDORAM) chip, a logic processing chip, etc., but is not limited thereto, and preferably, the single chip 111 is a Dynamic Random Access Memory (DRAM) chip. The chip set 110 formed by stacking the single chips 111 may be formed by stacking the same chips or may be formed by stacking a plurality of different chips. For example, the same DRAM chips may be stacked layer-by-layer to form the chipset 110. Preferably, the single chips 111 are bonded without using adhesive. However, those skilled in the art will appreciate that the formation of chipset 110 is not limited to those enumerated above.
In one example, both end surfaces of the via hole 112 are exposed to active surfaces of the lowermost unit chip 111 and the uppermost unit chip 111 of the chip set 110, respectively. In one example, the via hole 112 may be formed using a process for preparing a back via hole, a middle hole, and a front via hole. The via hole 112 may be formed inside the stacked single chips 111 of the chip set 110 by, for example, electroplating, and the material of the via hole 112 may include at least one of the following materials: gold, silver, platinum, aluminum, copper. However, those skilled in the art will appreciate that the materials and formation of the via 112 are not limited to those listed above.
In a preferred embodiment, the via 112 may be a metal pillar, and more preferably, the via 112 may be a copper pillar. The length of the via hole 112 is defined according to the thickness and connection state of the unit chip 111. There is an exposed hole cutting pad 113 on an outer side (e.g., right side in fig. 1) of the chip set 110, the hole cutting pad 113 is formed by axially vertical cutting along an outer via hole 112 of the chip set 110, and the formed hole cutting pad 113 is used for electrically connecting the side chip 210 and the chip set 110. With the connection of such a structure, the path of the chip group 110 in the semiconductor package 100 is shortened compared to the connection of the side chip 210 in the related art.
The redistribution layer 310 may be directly formed on the active surface of the uppermost individual chip 111 of the chipset 110. The redistribution layer 310 may have circuits (not shown) formed therein. For example, a rerouting technique may be used to form circuits in rerouting layer 310. The circuit can be designed in different patterns as desired. The circuit formed in the re-wiring layer 310 may directly connect the end surfaces of the via holes 112 exposed on the active surface of the uppermost unit chip 111 of the chip group 110. The redistribution layer 310 may include a dielectric layer. The material of the dielectric layer may be, for example, a polymer film material, such as benzocyclobutene (BCB), Polyimide (PI), etc., but is not limited thereto. The redistribution layer 310 may also include other insulating materials. The redistribution layer 310 may include a plurality of terminal pads 312 electrically connected to the circuit (or the terminal pads 312 are part of the circuit). The semiconductor package 100 may further include solder balls 313 disposed on the end pads 312 of the re-wiring layer 310. For example, the solder balls 313 may be connected to the circuit of the redistribution layer 310 by means of plating. The redistribution layer 310 is electrically connected to the hole cutting pad 113 through the connection member 212 of the side chip 210 and the internal circuit of the side chip 210. The internal circuit of the side chip 210 can adopt the same circuit forming method as that in the re-wiring layer 310.
The uppermost package to which the semiconductor package 100 is connected may be any type of fan-out Ball Grid Array (BGA) semiconductor package.
Fig. 3A to 3P are sectional views illustrating a semiconductor package in a method for manufacturing the semiconductor package according to an embodiment of the present application.
As a general concept, a method for manufacturing a semiconductor package 100 according to an embodiment of the present application may include: the chip set 110 is manufactured by a wafer-level chip packaging manner, the chip set 110 includes a plurality of single chips 111 arranged in a stacked manner, and the single chips 111 are interconnected through a plurality of via holes 112; vertically cutting along the axial direction of a via hole 112 at the outer side of the chip set 110 to form a hole cutting pad 113 exposed at the side edge; providing a plurality of connectors 212 on the active face of the side chip 210 to form said side chip 210; and bonding the ends of the connection members 212 of the side chips 210 to the hole cutting pads 113 of the chip group 110 to electrically connect the chip group 110 with the side chips 210.
The method for manufacturing a semiconductor package according to the embodiment of the present application may be applied to a 3D package, particularly, a 3D stack package.
The method for manufacturing a semiconductor package according to an embodiment of the present application may include the steps of:
the chipset 110 is made according to the above scheme; and bonding the chipset 110 with the side chip 210.
The method for manufacturing a semiconductor package according to an embodiment of the present application may be used in a Wafer Level Chip Scale Packaging (WLCSP) process.
More specifically, taking a four-layer wafer stack as an example, referring to fig. 3A to 3P, a method for manufacturing a semiconductor package according to an embodiment of the present application may include the following steps.
Referring to fig. 3A, in step S100, two wafers are provided, a bonding surface of the two wafers and a back surface of an upper wafer opposite to the bonding surface of the upper wafer are ground, after grinding, a thickness of the upper wafer is smaller than that of a lower wafer, the wafer with the thick thickness in the two wafers is defined as a bottom wafer, and the two wafers are bonded by using a low temperature bonding process to form a first wafer group 400.
In step S102, referring to fig. 3B, a metal seed layer is formed on the active surface of the upper wafer and a photoresist is formed on the metal seed layer. For example, the metal seed layer may be formed by deposition. And photoetching the photoresist to form a first cavity guide hole which is positioned on the active surface of the upper wafer and is used for exposing the active surface of the upper wafer to be bonded with other wafers, and etching the first cavity guide hole to form a first cavity rear guide hole. The photoresist and the metal seed layer are removed. The etching can adopt dry etching, wet etching and laser ablation.
In step S104, referring to fig. 3C, a metal adhesion/barrier/seed layer may be deposited on the first cavity via by PVD, PECVD, or MOCVD. The metal adhesion layer material may be tantalum (Ta), but is not limited thereto. After the deposition process is complete, the first cavity pilot hole is plated to form the back via of via 112.
In step S106, referring to fig. 3D, the end face of the back via is chemically and mechanically polished to make the end face of the front via flush with the active surface of the uppermost wafer of the first wafer group 400.
In step S108, referring to fig. 3E, a new wafer is bonded on the active surface of the upper wafer of the first wafer set 400 to form a second wafer set 410. Before bonding, the bonding surface of the new wafer bonded to the first wafer group 400 is ground, and then the new wafer is bonded to the first wafer group 400 by using a low-temperature bonding process.
In step S110, referring to fig. 3F, a metal seed layer is formed on the active surface of the uppermost wafer of the second wafer group 410 and a photoresist is formed on the metal seed layer. For example, the metal seed layer may be formed by deposition. And photoetching the photoresist to form a second cavity guide hole which is positioned on the active surface of the upper wafer and is exposed to be bonded with other wafers, and etching the second cavity guide hole to form a second cavity guide hole. The photoresist and the metal seed layer are removed. The etching can adopt dry etching, wet etching and laser ablation
In step 112, referring to fig. 3G, a metal adhesion/barrier/seed layer may be deposited for the second cavity via using PVD, PECVD, or MOCVD process. The metal adhesion layer material may be tantalum (Ta), but is not limited thereto. After the deposition process is complete, the second cavity pilot hole is plated to form the middle hole of the via hole 112.
In step S114, referring to fig. 3H, the end surface of the middle hole is chemically and mechanically polished to make the end surface of the middle hole flush with the active surface of the uppermost wafer of the second wafer set 410.
In step S116, referring to fig. 3I, a new wafer is bonded on the active surface of the wafer above the third wafer group 420 to form the third wafer group 420. Before bonding, the bonding surface of the new wafer bonded to the second wafer set 410 is ground, and then the new wafer is bonded to the second wafer set 410 by using a low-temperature bonding process.
In step S118, referring to fig. 3J, a metal seed layer is formed on the active surface of the uppermost wafer of the third wafer group 420 and a photoresist is formed on the metal seed layer. For example, the metal seed layer may be formed by deposition. And photoetching the photoresist to form a third cavity guide hole which is positioned on the active surface of the upper wafer and is exposed to be bonded with other wafers, and etching the third cavity guide hole to form a third cavity guide hole. The photoresist and the metal seed layer are removed. The etching can adopt dry etching, wet etching and laser ablation
In step S120, referring to fig. 3K, a metal adhesion layer/barrier layer/seed layer is deposited on the third cavity via hole by PVD, PECVD, or MOCVD. The metal adhesion layer material may be tantalum (Ta), but is not limited thereto. After the deposition process is completed, the third cavity pilot hole is plated to form a front via hole of the via hole, thereby completing the fabrication of the via hole 112.
In step S122, referring to fig. 3L, the end surface of the front via is chemically and mechanically polished to make the end surface of the front via flush with the active surface of the uppermost wafer of the third wafer set 420.
In step S124, referring to fig. 3M, a tape 123 is attached on the active surface of the uppermost wafer of the third wafer group 420, and a redistribution layer 310 is formed on the tape 123, the redistribution layer 310 having circuits arranged therein. The redistribution layer 310 may be formed by deposition. The deposition may include, for example, CVD, PVD. For example, the circuit in the rewiring layer 310 may be formed by a rewiring technique. Rewiring techniques are well known to those skilled in the art and will not be described in detail herein.
In step S126, referring to fig. 3M, the bottom-most wafer is subjected to back thinning. Wafer thinning techniques are well known to those skilled in the art and will not be described in detail herein.
In step 128, referring to fig. 3N, a fan-out Ball Grid Array (BGA) semiconductor package is performed on the active surface of the redistribution layer 310.
In step 130, referring to fig. 3O, the third wafer group 420 is vertically cut along the axial direction of the via hole 112, and the cut surfaces of the several wafer groups 110 are formed as the hole cutting pads 113. Wafer dicing techniques are well known to those skilled in the art and will not be described further herein.
In step 132, referring to fig. 3P, the chipset 110 and the side chip 210 are electrically connected through the via cutting pad 113.
Through the technical scheme of the invention, the side chip 210 is directly electrically connected with the chip set 110 through the hole cutting pad 113 formed in the axial vertical direction of the via hole 112, compared with the mode that the substrate chip and the single chip at the bottommost layer of the stacked chip set are interconnected through the silicon via hole in the prior art, the interconnection path between the side chip 210 and the chip set 110 is shortened, and the signal integrity is better.
The preferred embodiments of the present application have been described in detail with reference to the accompanying drawings, however, the present application is not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the present application within the technical idea of the present application, and these simple modifications are all within the protection scope of the present application.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations are not described separately in this application.
In addition, any combination of the various embodiments of the present application is also possible, and the same should be considered as disclosed in the present application as long as it does not depart from the idea of the present application.
Claims (16)
1. A semiconductor package, comprising:
the chip set comprises a plurality of single chips which are stacked, the single chips are interconnected through a plurality of via holes, the via holes are formed in the stacked single chips of the chip set, two end faces of the via holes are respectively exposed on active surfaces of the bottommost single chip and the topmost single chip of the chip set, the chip set is provided with a hole cutting pad exposed on a side edge, and the hole cutting pad is formed by axially and vertically cutting one outer side via hole of the chip set;
the side chip is vertically jointed with the side edge of the chip group, the side chip comprises a plurality of connecting pieces on the active surface of the side chip, each connecting piece comprises a bonding pad and a bump, the bonding pad is arranged on the active surface of the side chip, the bump is jointed with the bonding pad, and the bump at the end part of each connecting piece is bonded with the hole cutting pad of the chip group so as to realize the electric connection between the chip group and the side chip.
2. The semiconductor package according to claim 1, further comprising a redistribution layer formed on the chipset, the redistribution layer penetrating the connection member of the side chip and an internal circuit of the side chip to be electrically connected to the hole cutting pad.
3. The semiconductor package according to claim 2, further comprising a plurality of solder balls disposed on the plurality of pads of the redistribution layer.
4. The semiconductor package according to claim 2, wherein the redistribution layer is formed directly on an active surface of an uppermost monolithic chip of the chipset.
5. The semiconductor package according to claim 1, wherein the die are bonded without adhesive, and the respective lengths of the hole cutting pads are smaller than the thickness of the die.
6. The semiconductor package of claim 1, wherein the fill material of the hole cutting pad is copper.
7. The semiconductor package of claim 1, wherein the side chips comprise an integration of a physical layer chip and a control layer chip, and the monolithic chip comprises a dynamic random access memory chip.
8. The semiconductor package according to any one of claims 1 to 7, wherein the connection members located in the same vertical row are electrically connected to each other using an internal circuit of the side chip.
9. A method for manufacturing a semiconductor package, the method comprising:
the chip group is manufactured in a wafer-level chip packaging mode and comprises a plurality of single chips which are stacked, the single chips are interconnected through a plurality of through holes, the through holes are formed in the stacked single chips of the chip group, and two end faces of each through hole are respectively exposed on active faces of the bottommost single chip and the topmost single chip of the chip group;
vertically cutting along the axial direction of an outer side through hole of the chip set to form a hole cutting pad exposed to the side edge;
arranging a plurality of connecting pieces on the active surface of the side chip to form the side chip, wherein the connecting pieces comprise bonding pads and bumps, the bonding pads are arranged on the active surface of the side chip, and the bumps are jointed with the bonding pads; and bonding the bumps of the ends of the connectors of the side chips to the hole cutting pads of the chip group to achieve electrical connection of the chip group and the side chips.
10. The method of claim 9, further comprising forming a redistribution layer on the chipset, and electrically connecting the redistribution layer to the via cutting pad through the connection member of the side chip and an internal circuit of the side chip.
11. The method of claim 10, further comprising disposing a plurality of solder balls on a plurality of pads of the redistribution layer.
12. The method of claim 10, wherein the redistribution layer is formed directly on an active surface of an uppermost monolithic chip of the chipset.
13. The method of claim 9, wherein the die is bonded without adhesive, and the individual length of the hole cutting pads is less than the thickness definition of the die.
14. The method of claim 9, wherein the fill material of the hole cutting pad is copper.
15. The method of claim 9, wherein the side chips comprise an integration of physical layer and control layer chips, and wherein the monolithic chip comprises a dynamic random access memory chip.
16. Method according to any of claims 9-15, characterized in that the connecting pieces in the same vertical row are electrically connected to each other by means of the internal circuitry of the side chips.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711061893.0A CN109755215B (en) | 2017-11-02 | 2017-11-02 | Semiconductor package and method of manufacturing the same |
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| CN201711061893.0A CN109755215B (en) | 2017-11-02 | 2017-11-02 | Semiconductor package and method of manufacturing the same |
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| CN109755215B true CN109755215B (en) | 2021-07-27 |
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| CN112366198B (en) * | 2020-09-02 | 2021-08-10 | 珠海越亚半导体股份有限公司 | Connector for realizing multi-surface interconnection and manufacturing method thereof |
| CN117677204A (en) * | 2022-08-10 | 2024-03-08 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method of semiconductor structure and semiconductor device |
| CN117810185A (en) * | 2022-09-22 | 2024-04-02 | 长鑫存储技术有限公司 | Semiconductor packaging structure and preparation method thereof |
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| CN101542726A (en) * | 2008-11-19 | 2009-09-23 | 香港应用科技研究院有限公司 | Semiconductor chip with silicon through holes and side bonding pads |
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| CN102556948A (en) * | 2010-11-23 | 2012-07-11 | 霍尼韦尔国际公司 | Batch fabricated 3d interconnect |
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| KR100486832B1 (en) * | 2002-02-06 | 2005-05-03 | 삼성전자주식회사 | Semiconductor Chip, Chip Stack Package And Manufacturing Method |
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