CN101506974B - 利用沟槽隔离形成的无闭锁垂直瞬态电压抑制二极管阵列结构 - Google Patents

利用沟槽隔离形成的无闭锁垂直瞬态电压抑制二极管阵列结构 Download PDF

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CN101506974B
CN101506974B CN2007800317560A CN200780031756A CN101506974B CN 101506974 B CN101506974 B CN 101506974B CN 2007800317560 A CN2007800317560 A CN 2007800317560A CN 200780031756 A CN200780031756 A CN 200780031756A CN 101506974 B CN101506974 B CN 101506974B
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马督儿·博德
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Alpha and Omega Semiconductor Inc
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Abstract

一种大体上按照垂直半导体功率器件制程来制造瞬态电压抑制二极管(TVS)阵列结构的方法，此方法包含以下步骤：在半导体衬底上的具有第一导电类型的外延层上开设若干个隔离沟槽，并在二个隔离沟槽之间应用体区掩膜来掺杂具有第二导电类型的体区。此方法进一步包含以下步骤：使用源极掩膜来植入若干个具有第一导电类型的掺杂区域，以构成若干个二极管，其中，若干个隔离沟槽隔离并阻止由于不同导电类型的掺杂区域之间的闭锁效应所引发的寄生PNP晶体管或寄生NPN晶体管。

Description

利用沟槽隔离形成的无闭锁垂直瞬态电压抑制二极管阵列结构
技术领域
本发明涉及一种瞬态电压抑制二极管(transient voltage suppressing；TVS)的电路结构及其制造方法。尤其涉及一种使用沟槽隔离技术来制造垂直瞬态电压抑制二极管阵列的改良的电路结构及其制造方法，用以解决闭锁效应这一技术性上的困难。
背景技术
传统技术中，对于瞬态电压抑制二极管(TVS)阵列结构的设计与制造方法一直存在着一种技术性上的困难。该技术性的困难，也就是指在瞬态电压抑制二极管阵列结构中的多个PN结二极管通常是使用标准的互补式金属氧化物半导体(CMOS)制程步骤来形成在半导体衬底上，因此，往往会产生固有的PNP寄生晶体管与NPN寄生晶体管。在静电放电(electrostatic discharge；ESD)的情况下或发生瞬态电压时，会有较大的电压施加于瞬态电压抑制二极管阵列结构，寄生NPN晶体管或寄生PNP晶体管就会开启并触发闭锁(latch-up)效应，而导致一种突然且猛烈的电压骤回(snapback)现象。这种突然且猛烈的骤回现象极有可能会对于***的稳定性产生不可预期的影响甚至造成损害。另外，在瞬态电压抑制二极管阵列结构中的寄生NPN晶体管或寄生PNP晶体管的闭锁效应可能会进一步导致其它突如其然或不可预期的电压-电流瞬态(transient)变化。然而，由瞬态电压抑制二极管阵列结构中寄生NPN晶体管或寄生PNP晶体管的闭锁现象所造成的技术性难题却无法轻易地获得解决。
特别是，瞬态电压抑制二极管通常用于防止集成电路遭受突然的过电压而产生损害。一种集成电路被设计为在正常范围的电压下运行。然而，在许多情况下，例如静电放电时，电流会快速地产生瞬态变化并且减轻，而高电压可能就会突如其然且无法控制地对于电路造成冲击。当发生这种过电压的情况时，就需要瞬态电压抑制二极管去执行防护功能来避免可能会对集成电路造成的伤害。随着越来越多的器件是通过集成电路来实现的，集成电路将变得很容易受到过电压的损害，而对于瞬态电压抑制二极管的损害防护的需求也将随之增加。瞬态电压抑制二极管的典型应用包含有通用串行总线(USB)电源与数据线防护、数字影像接口(Digital video interface)、高速以太网络(Ethernet)、笔记本计算机、显示器以及平面显示器等。
图1A与图1B分别显示一种瞬态电压抑制二极管器件的电路图与电流-电压图。一种理想的瞬态电压抑制二极管应当可以在输入电压Vin小于击穿电压Vb时，将电流全部加以阻挡，即获得零电流(zero-current)，从而最小化漏电流。再者，理想上，当输入电压Vin大于击穿电压Vb时，瞬态电压抑制二极管在这种情况下应该具有接近零的电阻，以致于瞬态电压能够被有效地抑制下来。一种利用具有击穿电压的PN结器件来实现的瞬态电压抑制二极管可以在瞬态输入电压超过击穿电压的情况时，允许电流传导而获得瞬态电压的防护。然而，如图1B中所示，由于PN结类型的瞬态电压抑制二极管具有高电阻，因此不具有少数载子并且其抑制效果不佳。同样地，利用双极型NPN/PNP来实现的瞬态电压抑制二极管具有双极型晶体管的雪崩触发(avalanche-triggered)启动，雪崩电流会随双极增益而放大，而基极将会涌进少数载子，且双极型瞬态电压抑制二极管能够获得较佳的抑制电压。
随着电子技术的发展，越来越多的器件与应用需要瞬态电压抑制二极管阵列结构来提供静电放电(ESD)防护，特别是针对于高带宽数据总线的防护。图2A为一种四沟道瞬态电压抑制二极管的电路图；图2B是瞬态电压抑制二极管阵列结构的侧面剖视图，仅仅显示了该阵列器件的核心部份。如图2A与图2B所示的瞬态电压抑制二极管阵列包含串联的若干个高压侧控向二极管(high-side steering diode)与低压侧控向二极管(low-side steering diode)，其中高压侧控向二极管连接到Vcc，低压侧控向二极管连接到接地电位。高压侧控向二极管与低压侧控向二极管还并联一主线齐纳二极管(Zenerdiode)，控向二极管比齐纳二极管小了许多并具有较低的结电容(junctioncapacitance)。此外，如图2C所示，这样的实施方法进一步产生另一个问题，也就是由于寄生NPN晶体管与寄生PNP晶体管所导致的硅控整流器(SCR)操作产生的闭锁效应。主线齐纳二极管击穿会触发其上的寄生NPN晶体管开启，进一步开启硅控整流器而造成闭锁效应。在高温时，即使寄生NPN晶体管并未开启，但流经寄生NPN晶体管的NP结的高的漏电流可能也会开启硅控整流器，从而导致闭锁效应。为了抑制由寄生PNP晶体管与寄生NPN晶体管所导致的硅控整流器操作产生的闭锁效应，如图2B所示，实施在半导体衬底上的实际器件需要在半导体衬底上横向延伸一段距离，此距离可以高达10微米或更多，但是其抑制效果通常不够有效。
如图3A与图3B所示，其说明在以太网络差分保护电路(Ethernetdifferential protection circuit)由于寄生PNP晶体管上的闭锁效应所导致的特殊困难。在此以太网络防护电路中，Vcc与接地管脚都是以浮置(floating)方式设置的。然而，在这个设计中的寄生的硅控整流器结构并不足够弱，仍会导致如图3B所示的突变电压的骤回现象。这样的突发与强烈的骤回现象可能会对于***的稳定性造成不可预期的影响甚至产生伤害。由于寄生PNP晶体管本来就存在于互补式金属氧化物半导体(CMOS)的制程中，且实际上Vcc与接地管脚浮置会让闭锁效应恶化，这些困难并无法轻易地获得解决。另外，也需要额外的埋入层(buried layers)来抑制寄生PNP晶体管的增益，这将导致复杂的器件结构与极高的制造成本。
因此，在电路设计和器件制造领域，仍然需要提供一种新颖改良的电路结构与制造方法来解决以上所述的各种困难。尤其是，目前仍然需要提供新颖改良的瞬态电压抑制二极管电路，以便能够有效率并容易地防止寄生PNP晶体管或寄生NPN晶体管的闭锁效应。
发明内容
本发明一方面在于提供一种崭新的与改良的瞬态电压抑制二极管阵列结构，通过使用闭锁隔离沟槽来防止寄生PNP晶体管或寄生NPN晶体管的闭锁效应，从而克服前述传统瞬态电压抑制二极管阵列所造成的诸多困难与限制。
本发明的另一方面在于提供一种使用隔离沟槽的无闭锁垂直瞬态电压抑制二极管阵列结构，将绝缘沟槽设置在二极管之间，使得相邻的二极管之间的横向距离能够被缩短，而不涉及闭锁效应。
简单来说，本发明的一个较佳实施例公开一种瞬态电压抑制二极管阵列结构，其包含若干个形成在半导体衬底上的二极管，以作为不同导电类型的若干个掺杂区域，从而构成若干个PN结。该瞬态电压抑制二极管阵列结构进一步包含有设置在前述二极管之间的一绝缘沟槽，用于隔离并防止寄生PNP晶体管或寄生NPN晶体管所造成的闭锁效应(latch-up)。
本发明进一步公开一种集成有瞬态电压抑制二极管阵列结构的电子器件的制造方法。此制造方法包含以下步骤：通过掺杂具有不同导电类型的若干个掺杂区域，在半导体衬底上制造瞬态电压抑制二极管阵列，从而在这些掺杂区域之间的PN结之间形成若干个二极管。此制造方法进一步包含以下步骤：在上述掺杂区域之间形成绝缘沟槽，用来隔离掺杂区域，并用来防止在半导体衬底上不同导电类型的掺杂区域之间的寄生PNP晶体管或寄生NPN晶体管所引发的闭锁效应。
进一步地，一种瞬态电压抑制二极管阵列结构的制造方法，包含：
在半导体衬底上具有第一导电类型的外延层上开设若干个绝缘沟槽，然后使用一体区掩膜在二个绝缘沟槽之间掺杂一具有第二导电类型的体区；以及使用一源极掩膜来植入若干个具有第一导电类型的掺杂区域，以构成若干个二极管，其中，所述的绝缘沟槽将二极管加以隔离，并防止寄生PNP晶体管或寄生NPN晶体管在该半导体衬底上不同导电类型的掺杂区域之间所引发的闭锁效应。
所述的一种瞬态电压抑制二极管阵列结构的制造方法进一步包含以下步骤：使用一接触掩膜植入远离该体区的若干个具有第二导电类型的掺杂区域，用来与该外延层构成若干个高压侧二极管，并利用通过所述绝缘沟槽的若干个输入/输出接触衬垫来连接到被体区包围的低压侧二极管。
所述植入若干个具有第二导电类型的掺杂区域，以及使用一源极掩膜来植入若干个具有第一导电类型的掺杂区域，从而构成若干个二极管的步骤还进一步包含有以下步骤：形成一具有较大宽度的齐纳掺杂区域，其中，该齐纳掺杂区域和该外延层中的体区形成垂直堆栈PN结，用以构成一齐纳二极管。
所述的开设若干个绝缘沟槽的步骤还进一步包含以下步骤：邻近该齐纳二极管开设若干个绝缘沟槽，将该齐纳二极管加以隔离，用以防止不同导电类型的掺杂区域之间的闭锁效应的发生。
所述的一种瞬态电压抑制二极管阵列结构的制造方法进一步包含在该半导体衬底的下表面沉积一金属层，用来作为该瞬态电压抑制二极管阵列结构的电极。
所述的一种瞬态电压抑制二极管阵列结构的制造方法进一步包含在该半导体衬底的表面沉积一金属层，并对该金属层进行图案化，用来作为若干个输入/输出接触衬垫，并作为该瞬态电压抑制二极管阵列结构的电极，且该电极的导电类型和形成在该半导体衬底的下表面的电极的导电类型相反。
通过对照附图阅读对本发明的较佳实施例的详细描述，本发明的目的和优点对于本领域内的技术人员来说是显而易见的。
附图说明
图式说明：
图1A是一种传统的瞬态电压抑制二极管器件的电路图，图1B是电流-电压(I-V)图，即电流对应电压图，用来说明瞬态电压抑制二极管器件的反向特性；
图2A是一种传统的瞬态电压抑制二极管阵列结构电路图，该瞬态电压抑制二极管阵列包含若干个连接输入/输出(I/O)衬垫的高压侧二极管与低压侧二极管，还具有一并联所述高压侧二极管与低压侧二极管的主线齐纳二极管；
图2B是应用了图2A所示的一种传统的瞬态电压抑制二极管阵列结构的侧面剖视图；
图2C是图2B中器件的电位闭锁效应的等效电路图；
图3A是一种根据如图2B所示的以太网络差分保护电路的电路图，该保护电路需要将Vcc与GND管脚浮置，且需要埋入层来抑制具有防护电路结构的寄生硅控整流器(SCR)的增益；
图3B是一种用来说明一种静电放电防护或瞬态电压抑制二极管操作的电流-电压(I-V)图，当使用传统的瞬态电压抑制二极管阵列时，会导致不可预期的突发与强烈的骤回现象的发生；
图4是根据本发明所提供的一种使用沟槽隔离的瞬态电压抑制二极管阵列结构的侧面剖视图，其明显减少寄生NPN晶体管或寄生PNP晶体管的闭锁效应；
图5是根据本发明所提供的另一种使用沟槽隔离的瞬态电压抑制二极管阵列结构的侧面剖视图，其明显减少寄生PNP或NPN晶体管的闭锁效应；以及
图6是用以说明本发明的一种静电放电防护或瞬态电压抑制二极管操作的电流-电压(I-V)图，由于减少了闭锁效应，而可明显减轻骤回现象。
具体实施方式
图4是根据本发明所提供的一种新颖改良的瞬态电压抑制二极管阵列结构的部份的侧面剖视图。如图所示，此部份的瞬态电压抑制二极管阵列结构100具有两个沟道，两沟道设置在N型衬底101的上表面的N型外延层105上，而N型衬底101的下表面则连接到施以电压Vcc的阳极端110。该瞬态电压抑制二极管阵列连接在设置在下表面的阳极端110与设置在连接接地电压的上表面上的阴极端120之间。瞬态电压抑制二极管阵列结构100进一步包含连接到第一输入输出(IO)端135的第一高压侧二极管125与第一低压侧二极管130。另外，瞬态电压抑制二极管阵列结构100进一步包含连接到第二输入输出(IO)端150的第二高压侧二极管140与第二低压侧二极管145。第一高压侧二极管125是形成来作为P型掺杂区域125-P与N型外延层105之间的PN结。第一低压侧二极管130是形成来作为N型掺杂区域135-N与设置在阴极端120下方的P型体区160之间的PN结，且第一输入输出(IO)衬垫135连接到第一低压侧二极管130的N型掺杂区域135-N，还连接到第一高压侧二极管125的P型掺杂区域125-P。第二低压侧二极管145是形成来作为N型掺杂区域145-N与设置在阴极端120下方的P型体区160之间的PN结，且第二输入输出(IO)衬垫150连接到第二低压侧二极管145的N型掺杂区域145-N，还连接到第二高压侧二极管140的P型掺杂区域140-P。较大区域的齐纳二极管170是由P型体区160与N型外延层105之间的PN结形成的。NPN晶体管能够被齐纳二极管170触发，且NPN晶体管是由N型射极区域155、P型体区160与N型衬底101所形成的，从而并不需要太大的电阻就可传导大的瞬态电流。另外，瞬态电压抑制二极管阵列结构100进一步包含第一绝缘沟槽180-1，其形成在第一高压侧二极管125与第一低压侧二极管130之间。瞬态电压抑制二极管阵列结构100进一步包含第二绝缘沟槽180-2，其形成在第二高压侧二极管140与第二低压侧二极管145之间。绝缘沟槽可以防止寄生NPN与PNP晶体管所造成的闭锁效应，而所述的寄生NPN与PNP晶体管是固有形成在由高压侧与低压侧二极管所形成的多个PN结之间的。
图5是根据本发明所提供的另一个新颖改良的实施方式的瞬态电压抑制二极管阵列结构的侧面剖视图。除了在器件100’中具有额外的若干个提供了更好的隔离作用的沟槽外，图5中的器件100’类似于图4中的器件100。沟槽180’-1与180’-2将低压侧二极管与主线齐纳二极管区域分隔开来，因此击穿横向NPN，而横向NPN是由N型区域155、P型体区160与低压侧二极管阴极区域135-N与145-N所构成。
图6是用来说明本发明的一种静电放电(ESD)防护或瞬态电压抑制二极管操作的电流-电压(I-V)图，由于减低了闭锁效应，而可明显减轻骤回现象。如电流-电压图所示，电流-电压曲线220显示出在瞬态电压抑制二极管阵列结构中半导体衬底上不同掺杂区域之间所形成的寄生NPN晶体管或寄生PNP晶体管的闭锁效应，可能将导致以高电压及电流去开启寄生NPN晶体管或寄生PNP晶体管，因此引发一种突发的骤回现象。因为绝缘沟槽180-1与180-2的作用，闭锁效应将获得减轻，而且骤回现象会大大地减少。如电流-电压曲线210即是在发生骤回现象时所取得的曲线，其突发的电压变化会强烈地引起***的不稳定。
虽然本发明以前述的实施例公开如上，然其并非用来限定本发明。在不脱离本发明的精神和范围内，所进行的改动与润饰，均属本发明的专利保护范围。关于本发明所界定的保护范围请参考权利要求书。

Claims (11)

1.一种瞬态电压抑制二极管阵列结构，其特征在于，该结构包含：
若干个垂直二极管，形成在一半导体衬底上，作为不同导电类型的若干个掺杂区域，用来构成若干个PN结；以及
若干绝缘沟槽，设置在所述的二极管之间，用来隔离并防止寄生PNP晶体管或寄生NPN晶体管在该半导体衬底上不同导电类型的掺杂区域之间所引发的闭锁效应；
所述的半导体衬底包含一N-型衬底，用以支撑一N-型外延层，该半导体衬底具有一阳极与一阴极，该阳极设置在半导体衬底下表面，连接到一电源电压，该阴极设置在半导体衬底上表面，连接到地；
所述的半导体衬底进一步包含一P-型体区，该P-型体区设置在该N-型外延层上的二个绝缘沟槽之间，其中该体区进一步包围着一齐纳N-型掺杂区域，而形成一垂直堆栈PN结，从而在所述的二个绝缘沟槽之间构成一齐纳二极管。
2.如权利要求1所述的瞬态电压抑制二极管阵列结构，其特征在于，所述的齐纳二极管进一步被设置在其两侧的绝缘沟槽隔离，并使该齐纳二极管和所述瞬态电压抑制二极管阵列结构中的其他二极管隔离，以此防止闭锁效应的发生。
3.如权利要求1所述的瞬态电压抑制二极管阵列结构，其特征在于，该结构进一步包含至少二个输入/输出接触衬垫，每一输入/输出接触衬垫与二个PN结接触，分别作为通过绝缘沟槽进行隔离的一高压侧二极管与一低压侧二极管，所述的绝缘沟槽上覆盖着绝缘层，而所述的绝缘层上覆盖所述的输入/输出接触衬垫。
4.如权利要求1所述的瞬态电压抑制二极管阵列结构，其特征在于，其中该体区进一步包围着一N-型掺杂区域，从而和该P-型体区形成一PN结，用来作为所述瞬态电压抑制二极管阵列结构的低压侧二极管。
5.一种瞬态电压抑制二极管阵列结构，其特征在于，其设置在一半导体衬底上，该半导体衬底包含一N-型衬底，用以支撑一N-型外延层，其特征在于，所述的瞬态电压抑制二极管阵列结构进一步包含：
开设在所述外延层上的若干个绝缘沟槽，且在外延层上的二个绝缘沟槽之间具有一P-型的体区；以及
一齐纳掺杂区域，为N-型，且位于所述的P-型体区上，用来构成一齐纳二极管，该齐纳二极管包含垂直堆栈PN结，用来负载一瞬态电流以抑制一瞬态电压；其中，所述的P-型体区包围着该齐纳N-型掺杂区域，以形成所述的垂直堆栈PN结，从而在二个绝缘沟槽之间构成所述的齐纳二极管；
所述的齐纳二极管被二个邻近该齐纳二极管设置的绝缘沟槽加以隔离，从而使该齐纳二极管与该瞬态电压抑制二极管阵列结构的另一二极管相隔离，从而防止一闭锁效应的发生；
所述的P-型体区进一步包含一N-型的低压侧二极管掺杂区域，用以构成一低压侧二极管；以及该外延层进一步包含一P-型的掺杂区域，该掺杂区域和该外延层形成一PN结而构成一高压侧二极管，用来通过一输入/输出接触衬垫电性连接到该低压侧二极管；
所述的半导体衬底具有一阳极与一阴极，该阳极设置在该半导体衬底下表面以连接到一电源电压，该阴极设置在该半导体衬底上表面以连接到地。
6.一种瞬态电压抑制二极管阵列结构的制造方法，其特征在于，所述的方法包含：
在半导体衬底上具有第一导电类型的外延层上开设若干个绝缘沟槽，然后使用一体区掩膜在相邻二个绝缘沟槽之间掺杂一具有第二导电类型的体区；以及使用一源极掩膜来植入若干个具有第一导电类型的掺杂区域，以构成若干个二极管，其中，所述的绝缘沟槽将二极管加以隔离，并防止寄生PNP晶体管或寄生NPN晶体管在该半导体衬底上不同导电类型的掺杂区域之间所引发的闭锁效应。
7.如权利要求6所述的制造方法，其特征在于，所述的方法进一步包含以下步骤：使用一接触掩膜植入远离该体区的若干个具有第二导电类型的掺杂区域，用来与该外延层构成若干个高压侧二极管，并利用跨越所述绝缘沟槽的若干个输入/输出接触衬垫来连接到被体区包围的低压侧二极管。
8.如权利要求6所述的制造方法，其特征在于，所述植入若干个具有第二导电类型的掺杂区域，以及使用一源极掩膜来植入若干个具有第一导电类型的掺杂区域，从而构成若干个二极管的步骤还进一步包含有以下步骤：形成一齐纳掺杂区域，其中，该齐纳掺杂区域和该外延层中的体区形成垂直堆栈PN结，用以构成一齐纳二极管。
9.如权利要求8所述的制造方法，其特征在于，所述的开设若干个绝缘沟槽的步骤还进一步包含以下步骤：邻近该齐纳二极管开设若干个绝缘沟槽，将该齐纳二极管加以隔离，用以防止不同导电类型的掺杂区域之间的闭锁效应的发生。
10.如权利要求6所述的制造方法，其特征在于，该方法进一步包含在该半导体衬底的下表面沉积一金属层，用来作为该瞬态电压抑制二极管阵列结构的电极。
11.如权利要求10所述的制造方法，其特征在于，该方法进一步包含在该半导体衬底的表面沉积一金属层，并对该金属层进行图案化，用来作为若干个输入/输出接触衬垫，并作为该瞬态电压抑制二极管阵列结构的电极，且该电极的导电类型和形成在该半导体衬底的下表面的电极的导电类型相反。
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US7781826B2 (en) * 2006-11-16 2010-08-24 Alpha & Omega Semiconductor, Ltd. Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
US8218276B2 (en) * 2006-05-31 2012-07-10 Alpha and Omega Semiconductor Inc. Transient voltage suppressor (TVS) with improved clamping voltage
US9793256B2 (en) * 2006-11-30 2017-10-17 Alpha And Omega Semiconductor Incorporated Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
US9202938B2 (en) * 2006-11-30 2015-12-01 Alpha And Omega Semiconductor Incorporated Latch-up free vertical TVS diode array structure using trench isolation
DE102007024355B4 (de) * 2007-05-24 2011-04-21 Infineon Technologies Ag Verfahren zum Herstellen einer Schutzstruktur
US8217419B2 (en) * 2007-06-15 2012-07-10 Rohm Co., Ltd. Semiconductor device
US7579632B2 (en) * 2007-09-21 2009-08-25 Semiconductor Components Industries, L.L.C. Multi-channel ESD device and method therefor
US7666751B2 (en) 2007-09-21 2010-02-23 Semiconductor Components Industries, Llc Method of forming a high capacitance diode and structure therefor
US7538395B2 (en) * 2007-09-21 2009-05-26 Semiconductor Components Industries, L.L.C. Method of forming low capacitance ESD device and structure therefor
JP5365019B2 (ja) * 2008-02-08 2013-12-11 富士電機株式会社 半導体装置
US7911015B2 (en) * 2008-04-03 2011-03-22 Mitsubishi Electric Corporation Infrared detector and infrared solid-state imaging device
US7842969B2 (en) * 2008-07-10 2010-11-30 Semiconductor Components Industries, Llc Low clamp voltage ESD device and method therefor
US7955941B2 (en) * 2008-09-11 2011-06-07 Semiconductor Components Industries, Llc Method of forming an integrated semiconductor device and structure therefor
US8089095B2 (en) 2008-10-15 2012-01-03 Semiconductor Components Industries, Llc Two terminal multi-channel ESD device and method therefor
US7812367B2 (en) * 2008-10-15 2010-10-12 Semiconductor Components Industries, Llc Two terminal low capacitance multi-channel ESD device
CN101826716B (zh) * 2009-03-05 2014-05-21 万国半导体股份有限公司 设有势垒齐纳二极管的低压瞬时电压抑制器
US8288839B2 (en) * 2009-04-30 2012-10-16 Alpha & Omega Semiconductor, Inc. Transient voltage suppressor having symmetrical breakdown voltages
US8558276B2 (en) * 2009-06-17 2013-10-15 Alpha And Omega Semiconductor, Inc. Bottom source NMOS triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)
FR2953062B1 (fr) * 2009-11-24 2011-12-16 St Microelectronics Tours Sas Diode de protection bidirectionnelle basse tension
US8169000B2 (en) * 2010-07-15 2012-05-01 Amazing Microelectronic Corp. Lateral transient voltage suppressor with ultra low capacitance
US8237193B2 (en) * 2010-07-15 2012-08-07 Amazing Microelectronic Corp. Lateral transient voltage suppressor for low-voltage applications
CN102376702B (zh) 2010-08-20 2014-09-17 半导体元件工业有限责任公司 两端子多通道esd器件及其方法
US8431999B2 (en) * 2011-03-25 2013-04-30 Amazing Microelectronic Corp. Low capacitance transient voltage suppressor
US8664080B2 (en) * 2011-05-25 2014-03-04 Texas Instruments Incorporated Vertical ESD protection device
US8710627B2 (en) 2011-06-28 2014-04-29 Alpha And Omega Semiconductor Incorporated Uni-directional transient voltage suppressor (TVS)
US8698196B2 (en) 2011-06-28 2014-04-15 Alpha And Omega Semiconductor Incorporated Low capacitance transient voltage suppressor (TVS) with reduced clamping voltage
US8304838B1 (en) * 2011-08-23 2012-11-06 Amazing Microelectronics Corp. Electrostatic discharge protection device structure
CN102290419B (zh) * 2011-08-24 2013-02-13 浙江大学 一种基于齐纳二极管的瞬态电压抑制器
CN102290417B (zh) * 2011-08-24 2012-10-24 浙江大学 一种基于dtscr的瞬态电压抑制器
JP5749616B2 (ja) * 2011-09-27 2015-07-15 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
CN102332466B (zh) * 2011-10-18 2012-10-31 宜兴市环洲微电子有限公司 一种用于制作芯片的双台面硅片
TWI456736B (zh) * 2011-11-25 2014-10-11 Amazing Microelectronic Corp 避免漏電流之暫態電壓抑制器
CN102437156B (zh) * 2011-12-13 2014-02-26 杭州士兰集成电路有限公司 超低电容瞬态电压抑制器件及其制造方法
CN102593155B (zh) * 2012-03-01 2014-03-12 浙江大学 一种基于多孔道均流的瞬态电压抑制器
CN103367393B (zh) * 2012-03-28 2016-04-13 上海华虹宏力半导体制造有限公司 瞬态电压抑制器件及制造工艺方法
US8779518B2 (en) * 2012-12-04 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for ESD protection
US9337178B2 (en) 2012-12-09 2016-05-10 Semiconductor Components Industries, Llc Method of forming an ESD device and structure therefor
WO2014132938A1 (ja) 2013-02-28 2014-09-04 株式会社村田製作所 半導体装置
WO2014132939A1 (ja) * 2013-02-28 2014-09-04 株式会社村田製作所 半導体装置
CN205081096U (zh) * 2013-02-28 2016-03-09 株式会社村田制作所 Esd保护器件
CN205452284U (zh) 2013-04-05 2016-08-10 株式会社村田制作所 Esd保护器件
US9508841B2 (en) * 2013-08-01 2016-11-29 General Electric Company Method and system for a semiconductor device with integrated transient voltage suppression
CN103474427B (zh) * 2013-09-16 2016-01-06 杭州士兰集成电路有限公司 集成式单向超低电容tvs器件及其制造方法
CN104465643A (zh) * 2013-09-17 2015-03-25 立锜科技股份有限公司 瞬时电压抑制元件及其制造方法
KR101592232B1 (ko) 2014-02-17 2016-02-05 주식회사 시지트로닉스 저정전용량 tvs 제조방법 및 그 방법으로 제조된 tvs 소자
US10103540B2 (en) * 2014-04-24 2018-10-16 General Electric Company Method and system for transient voltage suppression devices with active control
TWI563627B (en) * 2014-06-13 2016-12-21 Richtek Technology Corp Transient voltage suppression device and manufacturing method thereof
CN105185782B (zh) * 2015-08-20 2018-05-11 北京燕东微电子有限公司 容性二极管组件及其制造方法
CN105185783B (zh) * 2015-08-20 2018-08-24 北京燕东微电子有限公司 容性二极管组件及其制造方法
TWI580002B (zh) * 2015-08-26 2017-04-21 立錡科技股份有限公司 暫態電壓抑制元件及其製造方法
US9640523B2 (en) 2015-09-08 2017-05-02 Hong Kong Applied Science and Technology Research Institute Company Limited Lateral-diode, vertical-SCR hybrid structure for high-level ESD protection
US10217733B2 (en) 2015-09-15 2019-02-26 Semiconductor Components Industries, Llc Fast SCR structure for ESD protection
CN105489612B (zh) * 2015-12-07 2019-07-23 上海长园维安微电子有限公司 基于soi基底的低漏电低电容tvs阵列及其制备方法
TWI584382B (zh) * 2016-02-01 2017-05-21 力祥半導體股份有限公司 暫態電壓抑制器之二極體元件及其製造方法
US10043793B2 (en) * 2016-02-03 2018-08-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and circuit
TWI675448B (zh) 2016-04-14 2019-10-21 力智電子股份有限公司 多通道暫態電壓抑制器
CN107346791B (zh) * 2016-05-06 2020-10-16 北大方正集团有限公司 瞬变电压抑制二极管的制备方法和瞬变电压抑制二极管
CN105932010B (zh) * 2016-05-10 2018-09-18 北京燕东微电子有限公司 瞬态电压抑制器
US10388781B2 (en) 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
CN106169508B (zh) * 2016-08-31 2022-12-20 北京燕东微电子有限公司 一种双向超低电容瞬态电压抑制器及其制作方法
US10347621B2 (en) * 2016-10-12 2019-07-09 Texas Instruments Incorporated Electrostatic discharge guard ring with snapback protection
US10157904B2 (en) 2017-03-31 2018-12-18 Alpha And Omega Semiconductor (Cayman) Ltd. High surge bi-directional transient voltage suppressor
US10062682B1 (en) 2017-05-25 2018-08-28 Alpha And Omega Semiconductor (Cayman) Ltd. Low capacitance bidirectional transient voltage suppressor
US10211199B2 (en) 2017-03-31 2019-02-19 Alpha And Omega Semiconductor (Cayman) Ltd. High surge transient voltage suppressor
CN107316863B (zh) * 2017-07-12 2019-05-07 新昌县佳良制冷配件厂 瞬态电压抑制器及其制作方法
US10141300B1 (en) 2017-10-19 2018-11-27 Alpha And Omega Semiconductor (Cayman) Ltd. Low capacitance transient voltage suppressor
TWI737915B (zh) 2018-06-05 2021-09-01 源芯半導體股份有限公司 暫態電壓抑制元件
CN109065541B (zh) * 2018-07-17 2021-04-13 张辉 一种双向瞬态电压抑制器及制备方法
JP6968042B2 (ja) * 2018-07-17 2021-11-17 三菱電機株式会社 ＳｉＣ−ＳＯＩデバイスおよびその製造方法
US10573635B2 (en) 2018-07-23 2020-02-25 Amazing Microelectronics Corp. Transient voltage suppression device with improved electrostatic discharge (ESD) robustness
US10825805B2 (en) * 2018-10-26 2020-11-03 Alpha & Omega Semiconductor (Cayman) Ltd. Low capacitance transient voltage suppressor including a punch-through silicon controlled rectifier as low-side steering diode
CN109326592B (zh) * 2018-10-26 2020-08-28 南京溧水高新创业投资管理有限公司 瞬态电压抑制器及其制造方法
CN111446691B (zh) * 2019-01-17 2023-12-01 源芯半导体股份有限公司 暂态电压抑制元件
RU2698741C1 (ru) * 2019-01-30 2019-08-29 Акционерное общество "Научно-исследовательский институт молекулярной электроники" Способ изготовления вертикального низковольтного ограничителя напряжения
TWI765166B (zh) * 2019-07-16 2022-05-21 源芯半導體股份有限公司 暫態電壓抑制元件
CN111696982B (zh) * 2020-06-09 2023-10-03 深圳能芯半导体有限公司 一种基体分离n型功率管esd电路和设置方法
US11349017B2 (en) 2020-06-23 2022-05-31 Amazing Microelectronic Corp. Bidirectional electrostatic discharge (ESD) protection device
US20230168298A1 (en) * 2021-11-29 2023-06-01 Amazing Microelectronic Corp. Diode test module for monitoring leakage current and its method thereof
CN114334956B (zh) * 2022-03-15 2022-06-07 成都市易冲半导体有限公司 具有耐极负电压高压引脚的交流功率开关的隔离防护结构
CN114759026B (zh) * 2022-04-21 2023-04-28 电子科技大学 新型双回滞静电保护器件
CN117174761B (zh) * 2023-11-02 2024-01-05 富芯微电子有限公司 一种电压非对称双向tvs器件及其制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685441B2 (ja) * 1986-06-18 1994-10-26 日産自動車株式会社 半導体装置
FR2689317B1 (fr) * 1992-03-26 1994-06-17 Sgs Thomson Microelectronics Circuit integre constituant un reseau de diodes de protection.
JPH06291337A (ja) * 1993-03-31 1994-10-18 Nec Kansai Ltd 定電圧ダイオード
FR2708145B1 (fr) * 1993-07-21 1995-10-06 Sgs Thomson Microelectronics Composant monolithique comprenant une diode de protection en parallèle avec une pluralité de paires de diodes en série.
WO1997013279A1 (en) * 1995-10-02 1997-04-10 Siliconix Incorporated Trench-gated mosfet including integral temperature detection diode
JP3904676B2 (ja) * 1997-04-11 2007-04-11 株式会社ルネサステクノロジ トレンチ型素子分離構造の製造方法およびトレンチ型素子分離構造
JP4256544B2 (ja) * 1998-08-25 2009-04-22 シャープ株式会社 半導体集積回路の静電気保護装置、その製造方法および静電気保護装置を用いた静電気保護回路
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6515345B2 (en) * 2001-02-21 2003-02-04 Semiconductor Components Industries Llc Transient voltage suppressor with diode overlaying another diode for conserving space
US6683334B2 (en) * 2002-03-12 2004-01-27 Microsemi Corporation Compound semiconductor protection device for low voltage and high speed data lines
TW561608B (en) * 2002-11-01 2003-11-11 Silicon Integrated Sys Corp Electrostatic discharge protection apparatus for too-high or too-low input voltage reference level
US6891207B2 (en) * 2003-01-09 2005-05-10 International Business Machines Corporation Electrostatic discharge protection networks for triple well semiconductor devices
US6867436B1 (en) * 2003-08-05 2005-03-15 Protek Devices, Lp Transient voltage suppression device
DE102004041622A1 (de) * 2003-08-29 2005-03-24 Fuji Electric Holdings Co. Ltd., Kawasaki Halbleiterbauteil
JP4423466B2 (ja) * 2004-02-17 2010-03-03 富士電機システムズ株式会社 半導体装置

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