CN101479845A - 利用小的钝化层开口的倒装互连 - Google Patents
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Abstract
在第一电气部件与第二电气部件(110,180;410,480)之间形成一种倒装电耦合件(100,200,300)。该耦合件(100,200,300)包括凸点(240,340)和接触焊盘(315)。第一电气部件(110,210,310,410)包括电耦合到第一电气部件(110,210,310,410)的接触焊盘(315)以及覆盖在第一电气部件(110,210,310,410)和接触焊盘(315)上的钝化层(130,230,330)。将钝化层(130,230,330)设置成具有位于接触焊盘(315)上方的开口(120,220,320)。沉积凸点(240,340),其覆盖在所述开口(120,220,320)上并基本覆盖在所述钝化层(130,230,330)上。凸点(240,340)被形成为与接触焊盘(315)电接触。设置凸点(240,340)以在倒装耦合过程期间耦合第一电气部件和第二电气部件(110,180;410,480)。
Description
本***涉及一种将倒装型电互连用于较小钝化层开口的互连方法和装置。
当前的集成电路(IC)正在向尺寸不断减小、复杂性不断增大的方面发展。随着部件密度的增大,电耦合部件的***已经变得至关重要,这是因为物理互连占据着可用表面积的很大部分,从而减弱了在该区域内设置电路的能力。
已知有一种电互连技术,其中由接触凸点形成互连的一个部分,由接触焊盘或表面形成互连的另一部分。在制造过程中,使凸点和焊盘彼此接触以形成电互连。美国专利No.6015652针对安装在基板上的IC披露了一种这样的互连***,被称为“倒装键合”,通过引用将该专利并入本文,如同它的全文是在本文中阐述了一样。这种典型的互连***减轻了与其他电互连***相关联的一些问题,但它仍占据了大量的可用表面积,否则这些可用表面积可以供电子部件使用。当直接为诸如专用集成电路(ASIC)之类的集成电路制造电互连时,这个问题更加严重了。
PCT专利申请WO 2004/052209披露了一种为了形成微型换能器而将ASIC电耦合到多个声学元件的***,通过引用将该专利并入本文,如同它的全文是在本文中阐述了一样。在所示的***中,凸点电耦合到声学元件或ASIC之一,焊盘电耦合到声学元件或ASIC中的另一个。该***实现了一种小的电气封装,例如可以形成这种封装来制造用于食管检查、腹腔镜检查和心内检查的超声换能器。但是,由于这些产品假定声学元件正下方的单元电路的间距匹配(pitch match),因此希望进一步减小该间距。目前的混合信号ASIC工艺和正常工作所需的电压仍然限制着进一步减小声学元件和控制电路。例如,对于使用位于185μm间距阵列上的柱形凸点的倒装互连***来说,大约有40%的ASIC面积由于这些凸点而不能用于电路。
在例如柱形凸点和电镀凸点的公知实践工艺中,凸点基本上位于通过钝化层开口的焊盘上,通常凸点在钝化层上几乎没有交迭或没有交迭。换言之,在现有***中,凸点的覆盖区(footprint)的尺寸非常接近接触焊盘的尺寸。柱形体与接触焊盘之间这种大的互连以及现有***中对柱形体和接触焊盘电耦合的约束条件是导致ASIC的部分不可用的主要原因。
本***的目的是克服现有技术中的不足和/或做出改进。本***的目的是制造高的凸点,同时使对ASIC面积的占用最小化。
根据本***,在第一电气部件与第二电气部件之间形成倒装电耦合件。该耦合件包括凸点和接触焊盘。第一电气部件包括电耦合到该第一电气部件的接触焊盘以及覆盖在该第一电气部件和接触焊盘上的钝化层。钝化层被设置为具有位于接触焊盘上方的开口。设置凸点,其覆盖在所述开口上并基本覆盖在所述钝化层上。所述凸点被形成为与接触焊盘电接触。所述凸点被设置成在倒装耦合过程期间耦合第一电气部件和第二电气部件。在一个实施例中,所述凸点覆盖的所述开口的表面积与钝化层的表面积之比在5%到85%或5%到30%的范围内。在一个实施例中,第一电气部件包括凸点下金属化层,其被配置成将接触焊盘电耦合到凸点。可以将凸点设置成是在电镀过程期间沉积的多个层。在一个实施例中,第一电气部件为ASIC和/或第二电气部件为换能器阵列。
本***还包括一种在第一电气部件与第二电气部件之间形成倒装电耦合件的方法,其中所述第一电气部件被钝化层覆盖。该方法包括如下动作:在第一电气部件的接触焊盘上方的钝化层中形成开口;沉积凸点,该凸点覆盖在所述开口上并基本覆盖在所述钝化层上;以及将所述凸点电耦合到所述接触焊盘。
在沉积所述凸点的动作之前,该方法可以包括沉积与所述接触焊盘电接触的凸点下金属化层的动作。在本实施例中,将所述凸点电耦合到所述接触焊盘的动作包括将所述凸点电耦合到所述凸点下金属化层的动作。可以除去所述凸点下金属化层的未被凸点覆盖的部分。可以溅射沉积所述凸点下金属化层。电镀所述凸点的多个层,直到所述凸点高度处于70-100μm的范围内,从而沉积所述凸点。
可以将第二电气部件倒装耦合到所述凸点。在倒装耦合的动作之后,可以切割第二电气部件,以利用第二电气部件形成多个元件。
在同一个或另一个实施例中,第一电气部件可以是声学元件且/或第二电气部件可以是ASIC。所述耦合件可以是存在于小于150μm的间距阵列中的多个电耦合件之一。
参考附图以举例的方式对本发明进行更加详细的介绍,在附图中:
图1示出了为根据本***实施例的倒装互连准备的ASIC的示例性俯视图;
图2示出了根据本***实施例的倒装互连的示例性横截面;
图3示出了根据本***实施例的图2所示的示例性倒装互连***的详细横截面区域;以及
图4示出了可耦合到根据本***的电气部件的示例性元件,例如声学元件板。
以下是对示例性实施例的描述,在结合附图阅读时,它们将展示上述特征和优点以及其他特征和优点。在下列描述中,出于解释的目的而非限制的目的,阐述了诸如特定架构、接口、技术等的具体细节以便进行示例。然而,对本领域普通技术人员显而易见的是,没有这些细节的其他实施例仍然将被理解为在所附权利要求的范围内。此外,为了明晰起见,省略了对公知器件、电路和方法的详细描述以免使本***的描述模糊不清。此外,应当清楚地理解,包括附图是出于示例的目的,并不代表本***的范围。在附图中,利用相似的附图标记来表示类似的元件。
图1示出了为根据本***实施例的倒装互连准备的诸如ASIC 110等集成电路的示例性俯视图100。ASIC 110被钝化层130覆盖,该钝化层130使下层的ASIC 110绝缘并保护它们。钝化层130与现有***相比具有小的开口120。该俯视图100包括两个上方元件,例如声学元件180的图示,这两个上方元件经由根据本***的开口120和凸点(图1中未示出)耦合到ASIC 110。
图2示出了根据本***实施例的倒装互连***200的示例性横截面。在本实施例中,以柱形凸点的形式示出了一种高纵横比的凸点240,在制造期间将该凸点电耦合到声学元件(未示出)的去匹配层表面。作为示例,凸点240可以是包括球形和/或柱形的任何形状。声学元件可以是用于产生超声能量发射的类型,如可用于超声换能器应用的类型。如上所述,作为示例,所述凸点240是高纵横比的凸点,从而解决了在制造和准备电耦合到ASIC 210的一个或多个元件时的裕量问题。
图4示出了可耦合到根据本***的电气部件(例如ASIC 410)的示例性元件,例如声学元件480的板。作为示例,对于将ASIC 410倒装耦合到声学阵列的应用而言,需要较大的凸点高度,例如70-100μm。如图4所示,这些类型的二维阵列通常具有非常多的(例如2000-10000个)声学元件480(换能器材料),这些声学元件480位于ASIC 410的正上方并通过凸点倒装键合到ASIC 410。可以通过任何适当的键合工艺来将凸点键合到声学阵列上,所述适当的键合工艺包括利用施加到凸点或声学阵列接触表面的导电粘合剂来将凸点键合到声学阵列上、超声波柱形凸点键合等。
ASIC 410的物理尺寸通常比声学材料板的尺寸大。在将该板倒装键合到ASIC 410之后,可以施加底层填料490以使该板相对于ASIC 410稳定,将二者总称为组件。底层填料有助于保护凸点以使其不受环境条件的影响,为组件提供额外的机械强度,底层填料可以充当热沉以帮助ASIC的有源部件散热,且可以帮助补偿声学部件480与ASIC 410之间的任何热膨胀差异。
然后,利用例如切割锯(dicing saw)(例如金刚石颗粒锯)来切割所述板(例如参见切口488),从而将所述板分成各个声学元件480,在倒装键合过程期间和之后,声学元件480位于每个凸点的上方(为清晰起见,图4中未示出凸点)。应当容易地理解,声学元件480可以是任何类型的并可以具有任何构造,包括便于3维(3D)成像的构造(例如,可用于3D超声成像应用)和/或矩阵换能器构造。
所需的切割裕量(dicing tolerance)增大了将ASIC 410电耦合到声学元件480的难度。分开各个声学元件480的切口488必须要足够深,以将所述板分割成各个声学元件480。然而,切割得太深会带来损伤下方的ASIC 410的风险(例如,切口可能会穿过ASIC表面区域)。有几种部件要求更大的切割深度裕量,这连带导致了要求大的凸点高度(例如70-100μm)。首先,板的厚度会有变化。通常,所述板是三种或更多种材料的层压体,即去匹配层486(例如碳化钨)、作为应答器的压电晶体484以及匹配层482(例如石墨)。例如,均具有不同物理属性的三种层压材料会导致所述板并非完全平坦。
此外,形成这么多(例如数千个)切口会导致切割锯的锯条磨损。因此,即使对于给定深度的切口而言,由于锯条磨损也会导致最后的切口与开始的切口具有不同的深度,因此切口通常被形成为解决较浅的后面切口的问题。此外,由先前在若干分立过程中接合(例如层压)到一起的很多部分构成的结构具有累加裕量的问题。例如,层厚的裕量加上层平坦度的裕量加上键合厚度的裕量会产生很大的累加裕量。
上面列出的所有部件加到一起,需要所述板与ASIC之间具有较大(例如70-100μm)的间隙。这种对大间隙的要求转化为对相应大的凸点高度的要求。
图3示出了根据本***实施例的示例性倒装互连***300的详细横截面区域。倒装互连***300包括电气部件,例如ASIC 310和凸点340。ASIC310具有被钝化层330(例如亚硝酸硅层)覆盖的接触焊盘315,例如铝焊盘。根据本***的实施例,与现有***相比,焊盘315形成得较小,例如直径为5-30μm。利用适当的工艺(例如通过电子平版印刷蚀刻工艺、等离子体背向溅射等)在接触焊盘315上形成通过钝化层330的开口320,并且该开口320通向接触焊盘315。在去除钝化层期间或在后续工艺期间,从接触焊盘315上去除诸如氧化铝之类的氧化物,以确保接下来形成的凸点下金属化层(UBM)350具有良好的电接触。可以在具有不同治金性质的多个层中,例如在顶部镀金的钛中形成UBM 350。UBM 350通常与钝化层330交迭以确保良导电粘附(例如电镀)到接触焊盘315。UBM 350还保护ASIC(例如密封所述接触焊盘)以使其免受环境条件的影响,例如氧化以及在后续步骤中使用的化学工艺的影响。UBM 350可以由任何适当的工艺形成,例如在ASIC 310的顶表面上方进行溅射沉积、电解镀敷、光沉积等。
然后,在穿过钝化层330的开口320上方形成凸点340。凸点340基本覆盖在钝化层330的一部分上。由于如上所述通常将凸点的尺寸按照下方的接触焊盘进行设计,因此典型的现有技术凸点仅覆盖在钝化层的非常小的部分上(例如<3%)。在现有***中,将凸点的尺寸设计成接触焊盘的尺寸是一种减少浪费ASIC面积的方法。在本***中,凸点340基本覆盖在钝化层330上,这在利用ASIC 310面积方面实现了更大的改进。例如,可以将本互连***适当地应用于150μm和更小的细间距阵列中。如本文所采用的那样,术语“凸点基本覆盖在钝化层上”意在表示凸点覆盖区的百分之十到九十五之间(10%<覆盖面积<95%)覆盖在钝化层上。在一个实施例中,凸点的覆盖区的超过百分之五十(例如70%-95%)可以覆盖在钝化层上,然而将接触焊盘的尺寸保持得较小,这实现了潜在改进的电路密度。
可以利用任何制造工艺,例如镀敷、机器加工、形成、引线键合、电子平版印刷等来制造凸点340。在一个实施例中,在电镀过程期间形成凸点340。该电镀过程包括制作电镀掩模,该电镀掩模界定了ASIC 310的表面上的要被电镀的区域。该电镀掩模还界定了凸点340的覆盖区。
在特定实施例中,可能希望利用多个独立的电镀工艺来形成凸点,以实现期望的特征分辨率和凸点高度。此外,如果采用了过深的电镀掩模,那么电镀条件(例如化学性质、温度和时间)可能导致电镀掩模劣化。多步骤电镀工艺可以导致凸点340如图3所示例的金字塔形。在本实施例中,对于每个电镀步骤,可以采用不同的掩模。凸点340的相继电镀层342、344、346中的每一个的尺寸可以越来越小,以便能够设置电镀掩模。相同尺寸的掩模可能会在正确设置掩模时产生问题,这导致凸点形状无法控制。凸点340可以由任何期望的金属形成,例如镍和/或镍合成物360。
在(例如)两个或更多电镀过程之后所完成的凸点340的高度可以在50-120μm的范围内,例如100μm高,并且凸点340的覆盖区在50-80μm的范围内,例如60μm的覆盖区。在完成凸点340之后,可以通过任何适当的工艺,例如化学蚀刻工艺除去除了位于凸点340下方的部分之外的UBM350。之后,可以通过任何适当的工艺来镀敷凸点340,例如通过金的无电镀(没有电极)工艺,这在凸点340上生成镀层370(例如金)。
有利地,根据本***的互连***对于接触焊盘而言占用了更小的ASIC面积,并且根据本***的互连***可以使得更多的ASIC面积用于电路(例如额外的特征),或者,根据本***的互连***可以比当前***实现更小的间距设计。
当然,应该认识到,可以将上述实施例或工艺中的任一个与一个或多个其他实施例或工艺组合,以便根据本***提供更进一步的改进。
最后,上面的论述仅仅意在对本***进行示例,而不应被视为将所附权利要求限制为任何特定实施例或实施例组。这样,尽管已经参考其特定示范性实施例(例如,ASIC、声学元件等)详细描述了本***,但是还应当认识到,在不脱离如下面的权利要求所阐述的本***的更广阔期望精神和范围的情况下,本领域的普通技术人员可以想到很多修改和备选实施例。因此,应该将本说明书和附图当作是示例的方式,它们并不是要限制所附权利要求的范围。
在解释所附权利要求时,应当理解:
a)“包括”一词不排除存在给定权利要求所列元件或动作之外的元件或动作;
b)元件前的“一个”或“一种”一词并不排除存在多个这种元件;
c)权利要求中的任何附图标记并不限制它们的范围;
d)若干“装置”可以由同一物品或硬件或软件实现的结构或功能来代表;
e)任何所披露的元件都可以包括硬件部分(例如,包括分立电子电路和集成电子电路)、软件部分(例如计算机程序)和其任意组合;
f)硬件部分可以包括模拟部分和数字部分之一或两者;
g)可以将所披露的任何装置或其部分组合到一起或进一步分成多个部分,除非另行给出具体声明;以及
h)不要求动作或步骤具有任何特定次序,除非另行具体指出。
Claims (20)
1、一种位于第一电气部件与第二电气部件(110,180;410,480)之间的倒装电耦合件(100,200,300),所述耦合件(100,200,300)包括:
所述第一电气部件(110,210,310,410),包括:
电耦合到所述第一电气部件(110,210,310,410)的接触焊盘(315);以及
覆盖在所述第一电气部件(110,210,310,410)和所述接触焊盘(315)上的钝化层(130,230,330),其中所述钝化层(130,230,330)被配置为具有位于所述接触焊盘(315)上方的开口(120,220,320);以及
覆盖在所述开口(120,220,320)上并基本覆盖在所述钝化层(130,230,330)上的凸点(240,340),所述凸点(240,340)与所述接触焊盘(315)电接触并被配置为在所述倒装耦合期间耦合所述第一电气部件和第二电气部件(110,180;410,480)。
2、根据权利要求1所述的耦合件(100,200,300),其中所述开口(120,220,320)的表面积与所述凸点(240,340)覆盖的所述钝化层(130,230,330)的表面积之比在5%到85%的范围内。
3、根据权利要求1所述的耦合件(100,200,300),其中所述凸点(240,340)覆盖的所述开口(120,220,320)的表面积与所述钝化层(130,230,330)的表面积之比在5%到30%的范围内。
4、根据权利要求1所述的耦合件(100,200,300),其中所述凸点(240,340)比所述开口(120,220,320)覆盖了所述钝化层(130,230,330)的更大表面积。
5、根据权利要求1所述的耦合件(100,200,300),其中所述第一电气部件(110,210,310,410)包括凸点下金属化层(350),其被配置成将所述接触焊盘(315)电耦合到所述凸点(240,340)。
6、根据权利要求1所述的耦合件(100,200,300),其中所述凸点(240,340)被配置成是在电镀过程期间沉积的多个层(342,344,346)。
7、根据权利要求1所述的耦合件(100,200,300),其中所述第一电气部件(110,210,310,410)为ASIC。
8、根据权利要求1所述的耦合件(100,200,300),其中所述第二电气部件(180,480)为换能器。
9、一种用于在第一电气部件与第二电气部件(110,180;410,480)之间形成倒装电耦合件(100,200,300)的方法,其中所述第一电气部件(110,210,310,410)被钝化层(130,230,330)覆盖,所述方法包括如下动作:
在所述第一电气部件(110,210,310,410)的接触焊盘(315)上方的所述钝化层(130,230,330)中形成开口1(120,220,320);
沉积凸点(240,340),所述凸点(240,340)覆盖在所述开口(120,220,320)上并基本覆盖在所述钝化层(130,230,330)上;以及
将所述凸点(240,340)电耦合到所述接触焊盘(315)。
10、根据权利要求9所述的方法,其中在沉积所述凸点(240,340)的动作之前,所述方法包括沉积与所述接触焊盘(315)电接触的凸点下金属化层(350)的动作,且其中将所述凸点(240,340)电耦合到所述接触焊盘(315)的动作包括将所述凸点(240,340)电耦合到所述凸点下金属化层(350)的动作。
11、根据权利要求10所述的方法,包括去除所述凸点下金属化层(315)的未被所述凸点(240,340)覆盖的部分的动作。
12、根据权利要求10所述的方法,其中沉积所述凸点下金属化层(315)的动作包括:溅射沉积所述凸点下金属化层(315)的动作。
13、根据权利要求9所述的方法,其中沉积所述凸点(240,340)的动作包括:电镀所述凸点(240,340)的多个层(342,344,346)直到凸点高度处于70-100μm范围内的动作。
14、根据权利要求9所述的方法,其中沉积所述凸点(240,340)的动作包括:沉积所述凸点(240,340)以便覆盖所述开口(120,220,320)与所述钝化层(130,230,330)的表面积之比在5%到30%范围内的动作。
15、根据权利要求9所述的方法,包括将所述凸点(240,340)倒装耦合到所述第二电气部件(180,480)的动作。
16、根据权利要求15所述的方法,包括在所述倒装耦合的动作之后切割所述第二电气部件(180,480)的动作。
17、根据权利要求15所述的方法,其中所述第二电气部件(180,480)为声学元件。
18、根据权利要求15所述的方法,其中所述倒装耦合件的动作是形成在小于150μm的间距阵列之内多个电耦合件之一。
19、根据权利要求18所述的方法,包括动作:在所述倒装耦合的动作之后切割所述第二电气部件(180,480)以利用所述第二电气部件(180,480)形成多个声学元件(480)。
20、根据权利要求15所述的方法,其中所述第一电气部件(110,210,310,410)为ASIC,且所述第二电气部件(180,480)为声学元件。
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US80576406P | 2006-06-26 | 2006-06-26 | |
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US (1) | US20090309217A1 (zh) |
EP (1) | EP2036124A2 (zh) |
JP (1) | JP2009542029A (zh) |
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RU2603435C2 (ru) | 2011-10-17 | 2016-11-27 | Конинклейке Филипс Н.В. | Устройство с переходными отверстиями в подложке и способ его производства |
US9180490B2 (en) | 2012-05-22 | 2015-11-10 | General Electric Company | Ultrasound transducer and method for manufacturing an ultrasound transducer |
US20140257107A1 (en) * | 2012-12-28 | 2014-09-11 | Volcano Corporation | Transducer Assembly for an Imaging Device |
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JP3855495B2 (ja) * | 1998-10-16 | 2006-12-13 | セイコーエプソン株式会社 | 半導体装置、それを用いた半導体実装基板、液晶表示装置、および電子機器 |
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US20060116584A1 (en) * | 2002-12-11 | 2006-06-01 | Koninklijke Philips Electronic N.V. | Miniaturized ultrasonic transducer |
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US20090309217A1 (en) | 2009-12-17 |
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