CN101425494B - 用于低寄生阻抗封装的顶部焊料加强的半导体器件及方法 - Google Patents

用于低寄生阻抗封装的顶部焊料加强的半导体器件及方法 Download PDF

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CN101425494B
CN101425494B CN2008101685621A CN200810168562A CN101425494B CN 101425494 B CN101425494 B CN 101425494B CN 2008101685621 A CN2008101685621 A CN 2008101685621A CN 200810168562 A CN200810168562 A CN 200810168562A CN 101425494 B CN101425494 B CN 101425494B
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layer
solder
semiconductor device
metal layer
nickel
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CN101425494A (zh
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弗兰茨娃·赫尔伯特
安荷·叭剌
刘凯
孙明
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Chongqing Wanguo Semiconductor Technology Co ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明提出一种用于低寄生阻抗封装的顶部焊料加强的半导体器件及方法。该顶部焊料器件包括带有图案化为接触区域和接触加强区域的顶部金属层的器件芯片。至少一个接触区域电连接到至少一个接触加强区域。每一个接触加强区域的顶部为用以增加复合厚度从而降低寄生阻抗的焊料层。制造顶部焊料器件的方法包括：a)通过光刻将顶部金属层图案化为接触区域和接触加强区域；b)使用模板印刷工艺在每一个接触加强区域的顶部形成焊料层以增加复合厚度。本发明的优点在于所提供的器件和方法使用标准的芯片层级的加工工艺，可以有效降低成本。

Description

用于低寄生阻抗封装的顶部焊料加强的半导体器件及方法
技术领域
本发明总体涉及电子封装领域。更具体地，本发明涉及功率半导体器件的封装。
背景技术
依据市场定位的需求，现今电子产品的总体趋势是在保持产品功能和低成本的同时实现产品小型化。毫无例外，相同的趋势也适合于功率半导体器件的部分。这里，减小伴随器件封装环境的多种寄生阻抗变得尤为重要，因为这些寄生阻抗通常造成不良的器件性能退化，诸如功率转换效率下降和/或来自其相关联的功率电子电路的噪声上升。
现有致力于低电阻，低电感功率半导体器件封装的多种先有技术。如图1所示，发明人为Luo(罗)等人的第6,841,852号美国专利叙述了一种带有引线框架108的集成电路IC封装，该引线框架108包括设置在芯片100下方的引线框架区块103a和设置在芯片100的至少两条相邻边上的键合金属区域101a。增大键合金属区域101a也就增加金属区域101a和芯片100之间的源极键合线104的数量，从而减少寄生电阻和电感。进一步，在从封装的塑料体106延伸的外部终端的表面面积如果没有最大化则将其增大，这样可以加速散热并且减小外部终端电阻。IC芯片100适用于MOSFET器件，键合金属区域101a用于源极终端101。键合金属区域101a可以由多种形状实现。
如图1所示，虽然使用多个平行的短源极键合线104可以稍许减少寄生阻抗(该情况下为电阻和电感)，但是单独使用短键合线仍可能导致总体较高的寄生阻抗，因为现在源极电流趋向于受到芯片上互连的限制，并且在标准IC制造工艺下，这些芯片上互连通常都非常薄。较厚的芯片上互连成本昂贵并且可能要求非标准制造工艺，这些都是非常不合要求的。另一方面，限制芯片尺寸以实现相应减少的归因于芯片上互连的寄生阻抗的最终结果可能是降低诸如其功率处理能力的总体器件性能。
如图2所示的发明人为Hu(胡)等人的题为“Design of device layout forintegration with power MOSFET packaging to achieve better lead wireconnections and lower on resistance”(与功率MOSFET集成封装的能够达到更好的引线连接及更低电阻的器件布图结构设计)的第5,767,567号美国专利公开了一种形成在半导体芯片上的MOSFET功率IC器件100，该器件包括多个源极接触区域150-1，150-2，150-3和150-4，用以通过多个引线135，160连接到引线框架120。功率IC器件100在源极接触区域150-1，150-2，150-3和150-4上包括多个引线接触点170用以将引线160牢固地附接到源极接触区域上。这些引线接触点170大体上均匀地分布在源极接触区域上以减少扩散电阻，从而改进器件导通电阻及器件性能。
如图2所示，由于引线接触点170大体上均匀地分布在源极接触区域150-1，150-2，150-3和150-4上，为了连接到源极接触区域的较远的区域要求使用带有相应较高的电阻和电感的某些长键合线，因此该方法仍将导致总体较高的寄生阻抗。另一方面，限制芯片尺寸以实现相应减少的归因于这些长键合线的寄生阻抗的最终结果可能是降低诸如其功率处理能力的总体器件性能。
发明人为Ho(何)等人的第11/226,913号美国专利申请和发明人为Sun(孙)等人的第11/544,453号美国专利申请公开了带有板互连的半导体器件封装。图3A的部分剖视透视图，图3B的取自2-2线的截面图和图3C的取自3-3线的截面图简要地显示了该两个专利申请的半导体器件封装。如图3B所示，当功率半导体芯片120的底部直接键合到引线框架的漏极接触部分107时，功率半导体芯片120的顶部用图案化的源极板125代替键合线连接到引线框架的源极接触部分110。同样，在图3C中，当功率半导体芯片120的底部直接键合到引线框架的漏极接触部分107时，功率半导体芯片120的顶部用图案化的栅极板137代替键合线连接到引线框架的栅极接触部分115，该图案化的栅极板137带有用于将栅极板137夹在功率半导体芯片120之上的锁球机构155，从而进一步方便封装工艺。密封剂135恰好覆盖住所有环境敏感部分用以保持长期的器件可靠性。
如上所述的板连接封装是一种高性能的封装，因为其特点是：
由于单板代替多个键合线用于连接各个区域导致的低成本；
由于器件电流遍及板截面的良好分布导致的低寄生电阻和电感；和
由于矩阵型夹取附贴可以设计成处理多器件芯片的同时封装而带来的高生产率。
然而，板连接封装的缺点在于其成本以及需要用于附贴所述板的非标准加工，而且所述板本身也必须为封装和芯片定制。同时，该工艺是处理已分离芯片的晶片后道封装层级的工艺。这意味着与其它芯片层级的工艺相比较高得多的成本。总之，存在通过与标准的晶片层级工艺相兼容同时不要求非标准加工的高性能低成本的封装重点减少与器件封装相关的寄生阻抗的需求。
发明内容
本发明的目的在于提供一种用于低寄生阻抗封装的顶部焊料加强的半导体器件。该顶部焊料加强的半导体器件包括：
带有用于将其多个活性终端互连至其操作环境的顶部金属层的半导体器件芯片。该顶部金属层被图案化成接触区域和接触加强区域。该器件芯片包括预留窗口的顶部钝化层，顶部金属层通过预留窗口的顶部钝化层连接到内部器件结构。至少一个接触区域通过芯片上互连或器件芯片的内部结构电连接到至少一个接触加强区域。每个接触加强区域的顶部添加焊料层，用以增加复合厚度，从而相应地减少抵抗侧面电流的寄生电阻和电感。以此方法减少归因于半导体器件芯片的不良的寄生阻抗。
在一个实施例中，焊料层可以由铅焊料，无铅焊料，锡银铜焊料，锡银焊料或锡铜焊料制成。相应的顶部金属层由与焊料层形成直接接触的铜制成。
对于其顶部金属层材料由于材料的不相容不能直接与焊料层材料形成空间均匀的电键合的半导体器件芯片，该半导体器件芯片还包括可焊接的并且导电的介入层。该介入层夹在顶部金属层和焊料层之间并且与顶部金属层和焊料层形成空间均匀的电焊料键合。接触加强区域可以进一步图案化，以加强相应电焊料键合的空间均匀性。
在另一个实施例中，顶部金属层由铝制成。相应地，介入层可以由允许焊料层与铝之间的间接接触的镍/金层，镍/钯层或镍/钯/金层制成。
在又一个实施例中，介入层的厚度可以从2微米左右到20微米左右。
一种制造这样的顶部焊料加强的半导体器件的方法包括：
a)在半导体器件芯片的制造过程中确保每一个接触加强区域通过半导体器件芯片的内部器件结构电连接到至少一个接触区域。
b)将顶部金属层通过光刻图案化为接触区域和接触加强区域。该图案化还涉及打开穿过半导体器件芯片的顶部钝化层的窗口，然后，通过这些窗口将顶部金属层连接到半导体器件芯片的内部器件结构。
c)在每一个接触加强区域的顶部形成用以增加复合厚度的焊料层。
在一个实施例中，这样的顶部焊料加强的半导体器件的制造方法进一步包括芯片分离之前在晶片层级上实行所有a)，b)和c)步骤以减少相关的器件处理和器件制造成本。然后，在步骤c)之后，这样制造的半导体器件芯片从其晶片上分离，接着对于每个独立的半导体器件芯片将接触区域互连到其相应的活性终端。
在另一个实施例中，对于具有介入层的半导体器件芯片，该方法还涉及淀积夹在顶部金属层和焊料层之间并且与顶部金属层和焊料层形成空间均匀的电焊料键合的可焊接的并且导电的介入层。
其中，介入层包括镍(Ni)层上的薄金(Au)层，顶部金属层为铝层，淀积介入层还包括铝上的镍/金层的化学镀。当介入层包括镍/钯/金层并且顶部金属层为铝层时，淀积介入层还包括铝上的镍/钯/金层的化学镀或电镀。
在一个实施例中，在每一个接触加强区域的顶部形成焊料层还涉及以下晶片层级的步骤：
c1)在半导体器件芯片的顶部表面覆盖掩模以暴露每个接触加强区域，通过模版印刷工艺在其上定位然后滴落一定数量的焊料球。
c2)热处理该一定数量的焊料球使其粘贴到每一个接触加强区域的表面。
c3)加热熔化该一定数量的焊料球并使其流到一起以扩展焊料，在每一个接触加强区域的顶部形成所需要的焊料层以减少所有暴露区域上的电阻。
本发明的优点在于本发明所提供的减少与器件封装相关的寄生阻抗的器件和方法使用标准加工工艺，同时，该工艺是芯片层级的工艺可以降低成本。
通过下文的叙述，本发明的各个方面及其多个实施例对于本领域的普通熟练技术人员将是显而易见的。
附图说明
为了更完整地叙述本发明的多个实施例，在叙述中将参考相应的附图。然而，附图仅是对本发明的图释，不能被认为是对本发明范围的限制。
图1和图2是传统的键合线封装的现有技术；
图3A至图3C是现有技术的板键合封装的透视图和截面图；
图4是具有添加到半导体器件测试芯片的顶部的不规则形状的回流焊料突起物的本发明的初步概念的示意图；
图5A和图5B所示为通过在芯片金属化的顶部添加介入层，然后在介入层的顶部滴落一定数量的焊料球，接着回流焊料球以形成所需要的均匀的熔化焊料层而应用于VDMOS功率MOSFET器件的本发明的精确概念；
图6所示为本发明的应用于LDMOS功率MOSFET器件的同一个精确概念的第一部分；
图7所示为本发明的应用于VDMOS功率MOSFET器件的除了介入层形状变化之外的同一个精确概念的第一部分；
图8A至图8D所示为使用本发明的制造步骤的晶片层级部分；以及图8E至图8H所示为使用本发明的制造步骤的后道晶片层级部分。
具体实施方式
上下文所述的内容及附图仅集中于本发明的一个或数个当前的优选实施例，也叙述了某些示例性的可选特征和/或替代实施例。叙述及附图的目的是意在说明本发明，而非对本发明的限制。因此，本领域的普通熟练技术人员将很容易意识到各种修改，变化和替代。这样的修改，变化和替代应该被认为也包含在本发明的范围之内。
图4所示为具有在VDMOS(Vertical double-diffusedMetal-Oxide-Semiconductor垂直双扩散金属氧化物半导体)芯片202的顶部添加不规则形状的回流焊料224的IC封装200的本发明的初步概念。焊料材料可以由铅焊料，无铅焊料，锡银铜焊料，锡银焊料或锡铜焊料制成。作为其漏极的VDMOS芯片202的底部附贴于具有用于连接到外部电路的延伸漏极引线框架终端209和漏极引线框架终端210的引线框架芯片区块208。其他的引线框架部分是用以连接到源极引线框架终端214的源极引线框架部分212a-212c，和用于相同目的的连接到栅极引线框架终端208的栅极引线部分216。VDMOS芯片202的顶部金属层具有栅极接触区域206和源极接触区域204，两者均由标准的铝材料制成。为了将顶部金属层桥接到引线框架，栅极键合线222设置成连接栅极接触区域206和栅极引线框架部分216。然而，考虑到所通过的高电流等级，若干源极键合线205设置成连接源极接触区域204和源极引线框架部分212a-212c。为了进一步缩短源极键合线205以减少寄生阻抗，源极键合线205被分为源极键合线组220a，源极键合线组220b和源极键合线组220c。源极键合线可以用金，铜和铝制成，或用铝“带”代替键合线。进一步，可以用金属板代替源极键合线205，将源极引线框架部分212a-212c熔接在一起而提供源极和源极引脚之间的连接。
由于可以使不规则形状的回流焊料224的厚度比VDMOS测试芯片202的顶部金属层厚得多，所以，归因于其它流经源极接触区域204的侧面电流的寄生阻抗相应地减少很多。另外，VDMOS测试芯片202上适当尺寸，适当形状和适当定位的不规则形状的回流焊料224的实际存在还允许另外缩短栅极键合线202和源极键合线205，因为该两者只需要到达VDMOS芯片202的与栅极引线框架部分216和源极引线框架部分212a-212c最近的边缘。其结果是在不必减小芯片尺寸的情况下另外减小归因于键合线的寄生阻抗。虽然IC封装200显示了来自焊料的非经掩模遮蔽的随机流动的回流焊料224的不规则形状造成结果电阻变化的问题，但是其根本原因应被理解为与在焊料材料与铝之间直接形成空间均匀的电键合相关的在两者之间的不相容。然而，第二个相关的问题是不能够保持不规则形状的回流焊料224和各个源极键合线205接触源极接触区域204的接触区域之间所要求的最小间隙。这样的所要求的最小间隙必须被保持以确保不规则形状的回流焊料224不延伸得太远以至于与用于互连这些键合线的线键合工艺发生机械干扰而造成工艺不可靠。即使焊料层224可以在线键合工艺之后施加，仍然要求该最小间隙，因为在接触键合线时回流焊料可能通过化学方式侵袭该键合线，从而造成长期的不可靠。下文将叙述在保持减小寄生阻抗的同时解决IC封装200的上述问题的方案。
图5A和图5B所示为通过在芯片金属化的顶部添加介入层，然后在介入层的顶部滴落一定数量的焊料球304，接着回流焊料球304以形成所需要的均匀的熔化焊料层304a而应用于图4的VDMOS型功率MOSFET器件的本发明的精确概念。作为其漏极的功率器件芯片300的底部附贴于引线框架310，引线框架310的用以连接到外部电路的延伸漏极引线框架终端在图中未显示以避免模糊细节。其他的简化引线框架部分是源极引脚306和栅极引脚308。虽然图中没有直接显示，功率器件芯片300的顶部金属层仍用标准材料铝制成。顶部金属层图案化为三个区域，每一个区域的顶部具有通过化学镀工艺在其上镀覆的镍/金(Ni/Au)介入层，从而在顶部金属化上形成镀镍/金区块开口302a，镀镍/金区块开口302b和镀镍/金区块开口302c。镀镍/金区块开口302a，302b和302c的镀镍/金层构成介入层。对于本领域的熟练技术人员而言，在该情况中的镀镍/金区块开口302a应该被认为其底部与顶部金属层部分直接接触，该顶部金属层部分转而通过预留窗口的顶部钝化层连接到功率VDMOS器件芯片300的源极。由于镀镍/金区块开口302b的作用是通过源极键合线组220c连接到源极引脚306，所以镀镍/金区块开口302b下的顶部金属层作为功率器件芯片300结构的一部分电连接到镀镍/金区块开口302a下的顶部金属层。对于本领域的熟练技术人员而言，该情况中的镀镍/金区块开口302c应该被认为其底部与另一个顶部金属层部分直接接触，该顶部金属层转而通过预留窗口的顶部钝化层连接到功率VDMOS器件芯片300的栅极。镀镍/金区块开口302c的作用是通过栅极键合线222连接到栅极引脚308。
镀镍/金介入层是导电的及可焊接的，并且能够与铝顶部金属层和焊料材料金相形成空间均匀电焊料键合。因此，如图5B所示，熔化和回流后，焊料球304转化为通过镀镍/金介入层与铝顶部金属层电接触的均匀的熔化焊料层304a。另外，通过化学镀工艺，可以使由厚镍层和薄金层组成的镀镍/金介入层的厚度处在2微米左右到20微米左右，比0.5微米左右到5微米左右的典型的顶部金属层的厚度厚得多。如果必要，化学镀镍/金介入层甚至可以制造得更厚，取决于化学镀工艺的速率，暴露的镀覆面积以及结果层的应力等。因此，顶部金属层顶部的均匀的熔化焊料层304a实现了大量增加的复合导体厚度及相应减少抵抗流经的表面电流的归因于功率器件芯片300的包括寄生电阻和寄生电感成分的寄生阻抗。值得注意的是，均匀的熔化焊料层304a将仅在暴露的镀镍/金区块开口302a区域中流动以有效地形成低电阻和低应力的厚源极金属化层。这样可以通过以自对准方式(使用通过区块掩模暴露的顶部金属)增加有效金属厚度进一步减少功率器件芯片300顶部的源极金属。由于同样的原因，均匀的熔化焊料层304a也被保证与镀镍/金区块开口302b和302c之间分离出可靠的引线键合所要求的最小间隙。在实际操作中，所要求的最小间隙被确定为处在100微米至150微米的范围内。从功能上讲，位于镀镍/金区块开口302a下的图案化顶部金属层区域可以被表征为本发明的接触加强区域。而位于镀镍/金区块开口302b和镀镍/金区块开口302c下的图案化顶部金属层区域可以被表征为传统的接触区域。为了将顶部金属层桥接到引线框架，设置栅极键合线222以连接镀镍/金区块开口302c和栅极引脚308。然而，考虑到流经的高电流水平，用源极键合线组220c连接镀镍/金区块开口302b和源极引脚306。键合线可以用金，铜或铝制成，其尺寸范围在25微米至200微米之间。另外，取决于封装结构也可以使用铝带。至此，可以清楚地表明，化学镀镍/金不是仅有的可用于介入层的材料。任何导电的，可焊接的并能够与铝顶部金属层和焊料材料金相形成空间均匀的电焊料键合的替代材料都可以用于实施本发明。以下所列为部分此类替代材料的实例：
镍/金(Ni/Au)层，镍/钯(Ni/Pd)层，镍/钯/金(Ni/Pd/Au)层。
另一重要方面是，其诸如铜(Cu)的顶部金属层材料在焊料层材料熔化时已经与其直接形成空间均匀的电键合的功率半导体器件在将焊料球304滴落在顶部金属层上之前不必在其顶部添加上述介入层。
图6说明本发明的应用于LDMOS(Lateral Double-diffusedMetal-Oxide-Semiconductor横向双扩散金属氧化物半导体)功率MOSFET器件芯片300的同一个精确概念的第一部分。该实施例除了下述方面外与图5A所示的实施例相同：
功率MOSFET器件芯片300的底表面为其源极，功率器件芯片300的顶表面包含带有镀镍/金区块开口302b的漏极和带有镀镍/金区块开口302c的栅极。镀镍/金区块开口302b和302c分别通过漏极键合线组226c和栅极键合线222连接到引线框架310的漏极引脚312和栅极引脚308。
图7所示为本发明的应用于VDMOS功率MOSFET器件芯片300的除了镀镍/金区块开口302a的形状变化并伴随焊料球304相应的不对称位置之外的同一个精确概念的第一部分。镀镍/金区块开口302a形状变化的自由度可以相当大，因为接下来的取决于特定的区块开口形状的焊料球熔化回流的工艺可以凭借经验导致不同程度均匀性的熔化焊料层304a。因此，在实际操作中，诸如十字形，星形，网格形，十指交叉形或螺旋形的区块开口形状的变化需要通过实验确定，直至找出相应的熔化焊料层304a的最佳空间均匀性，同时具备最小的材料应力和电阻。至此可以清楚地认识到，本发明的多个附加参数也可以进行调整，以进一步优化归因于功率器件芯片300的与封装相关的寄生阻抗的减小。以下所列为部分参数的实例：
焊料球304的数量和尺寸；
使用附加掩模独立于下层器件金属电极图案进行镀镍/金区块开口302a的图案化；
取决于芯片附贴温度，镀镍/金区块开口302a内的焊料的熔化和回流可以与芯片附贴工艺相结合；
镀镍/金区块开口302a和键合区块区域之间的距离可以精细调整以减小封装后的功率器件芯片300的总体尺寸。
图8A至图8D说明由于规模的经济性实现相应减少器件制造成本的使用本发明的制造步骤的晶片层级部分。图8A说明8个功率VDMOS器件芯片300a-300h的直至及包括其顶部金属层图案化的晶片层级的器件制造，该图案化将顶部金属层图案化为用于互连的多个通过区块开口314暴露的铝金属化区域。正如半导体器件制造领域所知，图案化顶部金属层涉及光刻打开穿过半导体器件晶片的顶部钝化层的多个窗口，然后通过这些窗口，蒸发通常为铝的顶部金属层和/或将其连接到半导体器件芯片的内部器件结构。
图8B所示为镍/金厚介入层有效淀积到多个穿过区块开口314暴露的铝金属化上从而形成相应数量的镀镍/金区块开口302a，镀镍/金区块开口302b和镀镍/金区块开口302c的后续的晶片化学镀工艺之后的结果。虽然图中没有具体显示，但镀镍/金区块开口302b通过内部器件芯片结构电连接到镀镍/金区块开口302a。再次说明，在本发明中，镀镍/金区块开口302a对应于接触加强区域，而镀镍/金区块开口302b和镀镍/金区块开口302c对应于接触区域。
然后，应用模版印刷工艺(CSP)，晶片通过掩模暴露金属化顶部的每一个镀镍/金区块开口302a(对应于接触加强区域)，在镀镍/金区块开口302a上定位和滴落多个焊料球304。然后，将晶片热处理使焊料球304粘结到暴露的金属表面。其结果如图8C所示。
接下来，将晶片安装在切割带上，使用标准切割工艺将晶片分离为各个功率器件芯片。处理后的功率器件芯片300和切割沟316如图8D所示。对于本领域的熟练技术人员而言，至此可以清楚地认识到，虽然此处的图示限于8个功率器件芯片300a-300h的情况，但是本发明的方法可以同样适用于其上具有数千个功率器件芯片的晶片规模制造环境。另外，本发明也不限于功率半导体器件的封装。
图8E至图8H所示为使用本发明的制造步骤的后道晶片层级部分。在图8E中，各个功率器件芯片300与粘结其上的焊料球304一起附贴到引线框架310。图8F所示为可选的回流工艺的结果，其中，进一步加热附贴的功率器件芯片300，使焊料球熔化和流到一起从而在镀镍/金区块开口302a的顶部形成均匀熔化的低电阻焊料层304a(对应于接触加强区域)。最后的效果是经增加的复合厚度以及相应减小的寄生电阻和寄生电感成分。如果上述图8E的芯片附贴加热循环对形成均匀熔化的焊料层304a充分，则回流工艺将不再必要，因此该步骤是可选的。
图8G所示为引线键合工艺的结果，其中，镀镍/金区块开口302b和镀镍/金区块开口302c(接触区域)分别通过键合线组318和键合线组320连接到引线框架310。为了可靠性而保持均匀熔化的焊料层304a(接触加强区域)和与其最接近的多个键合线之间的最小间隔，是通过适当的区块图案化设计相应地将镀镍/金区块开口302a与镀镍/金板302b和镀镍/金板302c相间隔的简单的课题。
最后，图8H所示为完成封装后的功率器件芯片300，其中模制塑封322被部分去除以显示某些与封装相关的部分。简单地说，该操作包括模制成型模制塑封322，电镀引线框架引脚，在封装外表面打上用以识别的标记，修齐并形成引脚，最后测试封装后的器件。
虽然上文的叙述包括许多特殊性，但是不能认为这些特殊性相应地限制了本发明的范围，而只能认为这些特殊性提供了对本发明的多个现有的优选实施例的说明。例如，仅通过对一些几何尺寸作出调整，本发明也就可以被修改为应用多种其他封装类型封装多种其他类型的半导体器件。
遍及本文的叙述和附图，参考具体的结构给出了多个示例性实施例。本领域的普通熟练技术人员可以认识到，本发明可以以多种其它的具体形式实施，同时本领域的普通熟练技术人员也不需要过度的经验就可以实现这样的其它实施例。因此，对于本专利文件的目的，本发明的范围不限于上文所述的示例性实施例，而由附后的权利要求定义。落入权利要求的意义及其等价范围内的任何及所有修改都应该被认为包含在本发明的精神和范围之内。

Claims (25)

1.一种用于低寄生阻抗封装的顶部焊料增强的半导体器件，该顶部焊料增强的半导体器件包括：
带有用于将其一定数量的活性终端互连至外部电路的顶部金属层的已制半导体器件芯片；和
位于所述顶部金属层的顶部的用于增加复合厚度从而降低抵抗流经的表面电流的包括寄生电阻和寄生电感成分的寄生阻抗的焊料层。
2.如权利要求1所述的半导体器件，其特征在于，其中所述顶部金属层被进一步图案化为第一多个接触区域和第二多个接触加强区域。
3.如权利要求2所述的半导体器件，其特征在于，其中
至少一个所述接触区域电连接到至少一个所述接触加强区域；以及
所述焊料层在所述接触加强区域上散布。
4.如权利要求1所述的半导体器件，其特征在于，其中所述已制半导体器件芯片还包括预留窗口的顶部钝化层，所述顶部金属层通过该顶部钝化层连接到内部器件结构。
5.如权利要求2所述的半导体器件，其特征在于，其中所述焊料层用铅焊料或无铅焊料制成，所述的无铅焊料包括锡银铜焊料，锡银焊料或锡铜焊料。
6.如权利要求5所述的半导体器件，其特征在于，该顶部焊料增强的半导体器件还包括介入层，该介入层夹在顶部金属层和焊料层之间并且与顶部金属层和焊料层形成空间均匀的电焊料键合。
7.如权利要求3或6所述的半导体器件，其特征在于，其中至少一个所述的接触加强区域被图案化，以进一步增加相应的电焊料键合的空间均匀性。
8.如权利要求7所述的半导体器件，其特征在于，其中所述接触加强区域的图案化从由十字形，星形，网格形，十指交叉形和螺旋形组成的组合中选择。
9.如权利要求5所述的半导体器件，其特征在于，其中所述顶部金属层由铜制成。
10.如权利要求6所述的半导体器件，其特征在于，其中顶部金属层与介入层的组合是：铝与镍/金层的组合，铝与镍/钯层的组合或者铝与镍/钯/金层的组合。
11.如权利要求10所述的半导体器件，其特征在于，其中所述镍/金层的厚度在2微米到20微米之间。
12.一种用于减小归因于具有用于将其一定数量的活性终端互连到其工作环境的顶部金属层的已制半导体器件芯片的不良寄生阻抗的方法，其特征在于，该方法包括：
a)将顶部金属层图案化为第一多个接触区域和第二多个接触加强区域；
b)通过已制半导体器件芯片的内部器件结构将至少一个接触区域电连接到至少一个接触加强区域；和
c)对于每一个所述接触加强区域，将焊料层附贴到其顶部以增加复合厚度，从而相应降低抵抗流经的表面电流的包括寄生电阻和寄生电感成分的寄生阻抗，从而通过所述至少一个接触区域减小归因于已制半导体器件芯片的不良寄生阻抗。
13.如权利要求12所述的方法，其特征在于，该方法还包括在芯片与晶片分离之前在晶片层级上实行所有步骤a)，b)和c)，从而减少已制半导体器件芯片的器件处理和器件制造成本。
14.如权利要求13所述的方法，其特征在于，该方法还包括：
d)从晶片上分离来自该晶片的每一个已制半导体器件芯片并将第一多个接触区域互连到其相应的活性终端。
15.如权利要求14所述的方法，其特征在于，其中将第一多个接触区域互连到其相应的活性终端的步骤还包括将接触区域和与其最近的接触加强区域之间的间隔至少保持在处于预先确定的最小间隔以保证互连工艺的可靠性。
16.如权利要求12所述的方法，其特征在于，其中图案化顶部金属层的步骤还包括打开穿过已制半导体器件芯片的顶部钝化层的多个窗口，然后通过所述多个窗口将顶部金属层连接到已制半导体器件芯片的内部器件结构。
17.如权利要求12所述的方法，其特征在于，其中附贴焊料层的步骤还包括提供用铅焊料或无铅焊料制成的焊料层材料；所述的无铅焊料包括锡银铜焊料，锡银焊料或锡铜焊料。
18.如权利要求17所述的方法，其特征在于，其中，对于由于材料不相容不能与焊料层材料直接形成空间均匀的电键合的顶部金属层材料，附贴焊料层的步骤还包括淀积可焊接的，导电的，夹在顶部金属层和焊料层之间并且与顶部金属层和焊料层形成空间均匀的电焊料键合的介入层。
19.如权利要求18所述的方法，其特征在于，其中将顶部金属层图案化为第一多个接触区域和第二多个接触加强区域的步骤还包括图案化至少一个所述接触加强区域以进一步增加相应的电焊料键合的空间均匀性。
20.如权利要求17所述的方法，其特征在于，其中所述顶部金属层用铜制成，以及在每一个所述接触加强区域的顶部附贴焊料层的步骤还包括建立焊料层和顶部金属层之间的直接接触。
21.如权利要求18所述的方法，其特征在于，其中顶部金属层与介入层的组合进一步还包括：铝与镍/金层的组合，铝与镍/钯层的组合或铝与镍/钯/金层的组合。
22.如权利要求21所述的方法，其特征在于，其中当顶部金属层与介入层的组合是铝与镍/金层的组合时，淀积介入层的步骤还包括在铝上化学镀覆镍/金层。
23.如权利要求21所述的方法，其特征在于，其中当顶部金属层与介入层的组合是铝与镍/钯/金层的组合时，淀积介入层的步骤还包括在铝上化学镀覆镍/钯/金层。
24.如权利要求21所述的方法，其特征在于，其中当顶部金属层与介入层的组合是铝与镍/钯/金层的组合时，淀积介入层的步骤还包括在铝上电镀镍/钯/金层。
25.如权利要求12所述的方法，其特征在于，其中在每一个所述接触加强区域的顶部附贴焊料层的步骤还包括：
c1)通过掩模暴露每个所述接触加强区域，通过模版印刷工艺在其上定位然后滴落多个焊料球；
c2)热处理该多个焊料球使其粘贴在每一个所述接触加强区域的表面的顶部；
c3)加热熔化该多个焊料球并使其流到一起以在每一个所述接触加强区域的顶部形成焊料层。
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