CN101399245B - 具有桥式互连平板的半导体封装结构 - Google Patents

具有桥式互连平板的半导体封装结构 Download PDF

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CN101399245B
CN101399245B CN2008101609859A CN200810160985A CN101399245B CN 101399245 B CN101399245 B CN 101399245B CN 2008101609859 A CN2008101609859 A CN 2008101609859A CN 200810160985 A CN200810160985 A CN 200810160985A CN 101399245 B CN101399245 B CN 101399245B
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semiconductor package
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CN101399245A (zh
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石磊
孙明
刘凯
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Chongqing Wanguo Semiconductor Technology Co ltd
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Alpha and Omega Semiconductor Inc
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  • Wire Bonding (AREA)

Abstract

本发明涉及一种具有桥式互连平板的半导体封装结构，该半导体封装包含一具有漏极导线、源极导线与栅极导线的导线框架、以及耦合至导线框架的半导体芯片，该半导体芯片具有若干个金属化源极接触区域。桥式源极互连平板具有桥形部分、若干个设置于桥形部分两侧的低凹部分、若干个设置于低凹部分与桥形部分两侧的平面部分、与依靠于其中一个平面部分的连接部分，且桥式源极互连平板是连接源极导线与金属化源极接触区域。同时，当平面部分设置于桥形部分的平面与低凹部分的平面中间的平面时，桥形部分会设置在低凹部分的平面之上的平面上。

Description

具有桥式互连平板的半导体封装结构
技术领域
本发明涉及一种具有桥式互连平板的半导体封装结构，特别是指一种包含有桥式源极互连平板来连接功率半导体装置源极金属化接触区域与导线框架的源极导线的，具有桥式互连平板的半导体封装结构。
背景技术
已知的半导体装置通常是采用互连板(plate interconnections)或是接合线(bonding wire)来作为连接导线框架的导线。例如美国专利公告第5,821,611号专利，公开了一种半导体装置，包含有具有尖端形成岛状区域的第一导线、半导体芯片单元透过焊锡层而固定于第一导线的岛状区域，且具有若干个电极凸块，突出于岛状区域、以及若干个额外导线(additional lead)，每一个额外导线皆具有尖端并透过对应的焊锡沉积(solder deposit)电性连接于电极凸块。额外导线包含有至少第二与第三导线，藉由加热熔炉使这些导线融入电极凸块，然而，在加热过程中，锡球凸块可能会喷溅(spread)而产生无法预期的形状。
前案如美国专利公告第6,040,626号专利，公开了一种半导体封装，是在金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-EffectTransistor；MOSFET)的顶面具有混合连接，包含有用以连接源极的低电阻板部分、以及用以连接栅极的连接线，然而，由于引线接合制程中容易使得装置介电层损坏，而使连接线可能在装置内导致短路或是开路。
前案如美国专利公告第6,249,041号专利，公开了一种具有直接连接导线的半导体封装结构，半导体装置包含有半导体芯片，且在半导体芯片顶面或是底面具有接触区域，第一导线组件是由半硬式(semi-rigid)导体材料薄板所构成，且具有导线组件接触区域，附着于半导体芯片的其中一个接触区域。第一导线组件也包含至少一个导线，由导线组件接点延伸并与之连接；第二导线组件也是由半硬式导体材料薄板所构成，并具有导线组件接触区域，而附着于半导体芯片的其中的一个接触区域的导线组件；第二导线组件也包含至少一个导线，连接于并由导线组件接触区域延伸。而封装材料(encapsulant)覆盖于半导体芯片、第一导线组件的导线组件接触区域、以及第二导线组件的导线组合接触区域；由于导线组合直接连接于芯片，使得封装提供半导体装置具有低电阻抗与热阻抗。藉由电性导体黏接层使导线组合接触区域维持在与导线接触区域接触的状态，此电性导体黏接层可为填充银的环氧树脂(epoxy)或是聚亚酰胺树脂膏(polyimide paste)、锡球凸块(solder bump)，如果需要的话，黏着层可能会经过烤炉来加以固化，但是黏着层却不包含有软焊锡或是锡膏。
美国专利公告第6,479,888号专利公开了另外一种具有直接连接导线的半导体封装，MOSFET包含有若干个内导线，电性连接于半导体颗粒(semiconductor pellet)的一个表面电极，且此半导体颗粒在主要的平面上具有一个场效晶体管(field effect transistor)，透过由凸块所构成的栅极连接区域与源极连接区域，使得内导线得于机械上且电性上都连接于主要平面上。
在使用图案化平板(patterned plate)或是互连卡勾(clip interconnection)所遭遇的共同问题是在焊锡回焊的过程中，平板或是卡勾可能会漂移，导致互连的错位(misalignment)，在某些情况下，这些错位可能会导致源极区域与栅极区域的短路，而会降低封装的优良率(Assembly Yield)。
另一个使用模型平板或是互连卡勾所遭遇的问题是，因为热膨胀导致半导体的硅材料与平板或卡勾的金属材料之间的错误匹配(mismatch)，且平板或卡勾的接触区域越大，因为错误匹配所产生的应力也就越大，而容易导致芯片的崩坏(crack)，因此，为了降低此应力，也只能采用较小的平板或是卡勾，然而，也使得接触区域变小，而导致更高的阻抗。
因此，在此领域中亟需要一种半导体封装，包含有功率半导体装置够过图案化平板连接于源极导线与栅极导线，同时也可以克服现有技术所演生的问题，同时，也需要一种图案化互连平板，可于焊锡回流过程中不会漂移，而能确保卡勾的精确位置。同时，也亟需要一种具有金属化接触区域的半导体封装，而可于焊锡过程中限制焊锡流动；也亟需要一种金属化接触区域由镍/金(Ni/Au)所构成。也亟需要一种半导体封装制程，可以增加生产率(throughput)并提供简单的组件制程控制。也亟需要一种半导体封装方法，可以提供图案化平板至功率半导体装置的软附着制程；也亟需要一种半导体封装，具有外露的源极板，也亟需要一种具有降低电阻的半导体封装。更亟需要一种可以增进散热特性的半导体封装；也亟需要一种可以改善机械性质的半导体封装，也亟需要一种具有压印桥式导线框架平板(stamped bridgedlead frame plate)的半导体封装。
发明内容
本发明克服上述现有技术中存在的各种限制和缺点，提供一种半导体封装结构，其具有桥式源极互连平板于源极导线与功率半导体源极金属化接触区域之间。桥式源极平板的桥形部分可以被露出，用以改善热耗散(thermaldissipation)。桥式源极平板可提供和源极金属化接触区域较少的接触区域。桥式源极平板可包含数个凹涡，相对于源极金属接触区域来定位。成型的材料会流过桥形部分的周围及下方，以帮助将桥式源极板固定在适当的地方。
根据本发明的另一个目的，一种半导体封装结构包含有导线框架、该导线框架具有漏极导线、源极导线与栅极导线。半导体芯片耦合至导线框架并具有至少一个金属化源极接触区域。图案化源极板具有一桥形部分、若干个低凹部分、若干个平面部分与一连接部分；该低凹部分设置于桥形部分的两侧，该平面部分设置于低凹部分与桥接部分的两侧，该连接部分依靠于其中一个平面部分。此图案化源极板连接于源极导线与至少一金属化源极接触区域。至于封装材料则覆盖半导体芯片以及漏极导线、源极导线与栅极导线的至少一部分。
根据本发明的另一个目的，一种半导体封装结构包含有导线框架，该导线框架具有漏极导线、源极导线与栅极导线。半导体芯片耦合至导线框架，此半导体芯片具有若干个镍/金(Ni/Au)或其它焊接可湿润金属(solderwettable metal)的金属化源极接触区域。图案化源极板具有一桥形部分、若干个低凹部分、若干个平面部分与一连接部分；且低凹部分设置于桥形部分的两侧，平面部分设置于低凹部分与桥接部分的两侧，连接部分依靠于其中一个平面部分。此图案化源极板连接源极导线与若干个金属化源极接触区域。至于封装材料则覆盖半导体芯片以及漏极导线、源极导线与栅极导线的至少一部分。
上述描述仅为概述、而非广泛揭露，本发明的更重要的特征可由下面的实施方式作进一步的了解，而且也可使本发明对此领域的贡献更加明确；当然，本发明额外的特征也可在下面的实施方式中描述，同时也形成了申请专利范围的技术标的。
此一方面来说，在解释本发明的至少一个实施例之前，本发明并不会被下述文字、附图所呈现的实施态样的描述、描述组件的顺序更换所限制。当然，本发明也具有以其它实施方式来完成或是以其它种方式来加以实现、重制，同时，说明书连同摘要中所使用的语法、措辞或是技术用语仅是用以详细描述，不应该作为本发明范围的限制。
因此，本技术领域中，熟悉该项技术者皆可以根据本发明所描述的概念为基础，以其它种方式及***的设计来加以实现本发明的数个目的，故，申请专利范围也包含了所有根据从本发明的技术特征与范围所衍生的等效方法及***。
附图说明
图1为本发明中具有桥式源极互连平板的半导体封装结构的透视图；
图2为根据图1所示的半导体封装结构的俯视图；
图3为根据图1所示的半导体封装结构的侧视图；
图4为根据图1所示的半导体封装结构的剖面图；
图5为本发明中成型的半导体封装结构的示意图，其具有外露的桥形部分的桥式源极互连平板；
图6为本发明中成型的半导体封装结构的示意图，其具有不外露的桥形部分的桥式源极互连平板；
图7为本发明中具有桥式源极互连平板的半导体封装结构的一种可选择实施例的示意图；
第8为本发明中具有桥式源极互连平板的半导体封装结构的另一种可选择实施例的示意图；
图9为根据图8所示的半导体封装结构的俯视图；
图10为根据图8所示的半导体封装结构的侧视图；
图11为根据图8所示的半导体封装结构的剖面图；
图12为本发明中的半导体封装结构的一种可选择实施例的剖面图；以及
图13为根据图12所示的半导体封装结构的俯视图。
具体实施方式
以下详细说明本发明的最佳实施例，且以下说明并非用以限制本发明的申请专利范围，仅为配合附图说明阐述本发明的主要原理，而主张的权利要求则定义于权利要求书中。
本发明主要提出一种半导体封装结构，其具有一桥式源极互连平板，且该桥式源极互连平板位于导线框架源极导线与一个或数个功率半导体器件的金属化源极接触区域之间。上述桥式源极板包含一平板连接，其具有一升起的部分或桥形部分(a raised or bridge portion)。桥形部分是位于和数个金属化源极接触区域相接触的低凹部分的平面上方。桥式源极互连平板具有缩小了接触区域的金属化源极接触区域。在封装期间，接合材料会流过桥形部分的下方并提供机械强度给桥式源极互连平板。金属化源极接触区域较佳的为镍/金(Ni/Au)的电镀(plating)或是溅镀(sputtering)的表面。金属化源极接触区域可提供对于桥式源极互连平板较佳的结合度，以及降低因为介电层在引线接合(wire bonding)过程中损坏所导致的过度结合(overbonding)而引发的短路现象。金属化源极接触区域更进一步排除需要使用焊锡凸块(solder bump)以及环氧树脂黏胶层来作为软焊锡(soft solder)或是焊接锡膏(solder paste)来连接桥式源极板至金属化源极区域的状况。
本发明的实施例一请参阅图1至图6所示，半导体封装结构100的通常设计包含有导线框架105，导线框架105具有芯片衬垫107、源极接触部分110与栅极接触部分115。源极接触部分110包含源极导线111，栅极接触部分115包含栅极导线117，且芯片衬垫107包含漏极导线109。功率半导体芯片120可具有金属化漏极区域(图中未示)，并藉由焊锡回流(solder reflow)耦接于芯片衬垫107。栅极接触部分115与栅极金属化接触区域之间可以利用栅极平板或引线接合进行连接。
如图1所示，源极接触部分110与栅极接触部分115是非常靠近于芯片衬垫107的。然而，这些接触部分是和芯片衬垫107分隔开来的，这点可以从图2的俯视图中看出来。这同样适用于图7与图8的示意图。
半导体源极金属化接触区域与栅极金属化接触区域可利用镍/金(Ni/Au)或镍/钯/金(Ni/Pd/Au)的电镀或溅镀或其它凸块下金属化制程(under bumpmetallization process)的方式来形成。
桥式源极板130包含有利用金属平板以压印(stamped)或冲压(punched)所形成的一桥形部分131、数个低凹部分133、数个平面部分135与一个连接部分137；该低凹部分133位于桥形部分131的两侧，该平面部分135位于桥形部分131与低凹部分133的两侧，该连接部分137依靠在一个平面部分135上。桥形部分131所设置的平面超过低凹部分133的平面，同时，平面部分135所设置的平面介于桥形部分131的平面与低凹部分133的平面之间。桥式源极板130可以使用一个芯片藉由数个步骤或单一步骤进行压印或冲压。连接部分137接触于源极接触部分110，同时，低凹部分133接触一个或数个源极金属化接触区域。桥式源极板130可以通过使用软焊锡或是焊接锡膏的焊锡回流耦合至金属化源极接触区域。金属化源极接触区域可以覆盖功率半导体芯片120的上表面的大部分，用以改善热耗散以及减少阻抗与电感。
特别请参阅图5，在本发明的较佳实施例中，半导体封装结构500的通常设计包含有桥式源极板桥形部分131的上表面510，其露出于封装材料520。此露出的上表面510提供了由功率半导体芯片120所产生的热量的热耗散。此外，该露出的上表面510提供了安装表面可供安装额外散热器，用以增加额外的热耗散。而位于桥状部分131下方的封装材料也对于增加半导体封装结构500的机械强度作了贡献。
请参阅图6，本发明的另一个实施例中，半导体封装结构600的通常设计包含有封装材料610，封装材料610覆盖于功率半导体芯片120上以及至少一部分的漏极导线、源极导线与栅极导线上。桥形部分131的上表面510并没有在封装材料610外露出。
本发明的另一个实施例中，请参阅图7，半导体封装结构700的通常设计包含有导线框架705，导线框架705具有芯片衬垫107、源极接触部分110与栅极接触部分115。源极接触部分110包含数条源极导线111，栅极接触部分115包含一栅极导线117，而芯片衬垫107包含数条漏极导线109。功率半导体芯片120可具有金属化漏极区域(图中未示)，藉由焊锡回流耦接于芯片衬垫107上。
桥式源极板130包含有利用金属平板以压印(stamped)或冲压(punched)所形成的一桥形部分131、数个低凹部分133、数个平面部分135与一个连接部分137；该低凹部分133位于桥形部分131的两侧，该平面部分135位于桥形部分131与低凹部分133的两侧，该连接部分137依靠在其中一个平面部分135之上。桥式源极板130可以使用一个芯片藉由数个步骤或单一步骤进行压印或冲压。连接部分137接触于源极接触部分110，同时，低凹部分133接触一个或数个源极金属化接触区域。桥式源极板130包含一对凹涡(dimple)710，分别形成于低凹部分133的两侧。凹涡710相对于低凹部分133的上表面720是凹下的，该凹涡710并具有下表面(图中未示)，其是超过低凹部分133的下表面的平面的。在一个可选择的实施例中，凹涡710具有数个穿孔(图中未示)。凹涡互连平板(Dimpled plate interconnections)是被公开在美国专利申请第11/799,467号的专利申请案中，题目为“具有凹涡互连平板的半导体封装结构(Semiconductor Package Having Dimpled PlateInterconnections)”，其所公开的内容可以完全予以合并。
我们已经发现桥式源极板130并不会因为个别的源极平板凹涡710接触一个或多个源极金属化接触区域的数量而倾向于漂移(floating)。再者，金属化接触区域的优势是会在焊锡回流期间，将软焊与焊接锡膏限制在金属化接触区域的边缘内，藉以减少发生无法预期的形状与短路的意外。
栅极板750将栅极导线117的栅极接触部分115电性连接至在功率半导体芯片120上的栅极金属化接触区域(图中未示)。栅极板凹涡760是被定位并压印或冲压在栅极板750上，以在焊锡回流期间可以对准功率半导体芯片120的栅极金属化接触区域。栅极板凹涡760可以选择包含穿孔770。穿孔770会使得固定球(1ocking balls)的形成发生在焊锡回流期间，以提供机械强度给栅极板750。凹涡710是可选择的并属于本发明的1个可选择的实施例中，半导体封装结构具有栅极卡勾(gate clip)750，但不具有源极凹涡710。数个低凹部分133可以在不使用凹涡的情况下，使用软焊锡或是焊接锡膏，并藉由焊锡回流耦合至功率半导体芯片120的金属化源极接触区域。在另一个可选择的实施例中，栅极板750没有栅极板凹涡760，且栅极板750可以在不使用凹涡的情况下，使用软焊锡或是焊接锡膏，并藉由焊锡回流耦合至功率半导体芯片120的金属化源极接触区域。
本发明的另一个实施例中，请参阅图8至图11，半导体封装结构800的通常设计包含有导线框架805，该导线框架805具有芯片衬垫107、源极接触部分110与栅极接触部分115。源极接触部分110包含数条源极导线111，栅极接触部分115包含栅极导线117，而芯片衬垫107包含数条漏极导线109。功率半导体芯片120可具有金属化漏极区域(图中未示)，并藉由焊锡回流耦接于芯片衬垫107。
桥式源极板130包含有对金属平板进行压印或冲压所形成的一桥形部分131、数个低凹部分133、数个平面部分135与一连接部分137；低凹部分133位于桥形部分131的两侧，平面部分135位于桥形部分131与低凹部分133的两侧，连接部分137依靠于其中一个平面部分135。桥形部分131所设置的平面是超过低凹部分133的平面的，同时，平面部分135所设置的平面是介于桥形部分131的平面与低凹部分133的平面之间的。桥式源极板130可以使用一个芯片藉由数个步骤或单一步骤进行压印或冲压。连接部分137接触于源极接触部分110，同时，低凹部分133接触于一个或数个源极金属化接触区域。金属化源极接触区域可以覆盖功率半导体芯片120的上表面的大部分，用以改善热耗散以及减少阻抗与电感。在本发明的一个可选择的实施例中，数个源极板凹涡(图中未示)可以用来将低凹部分133连接至功率半导体芯片120的金属化源极接触区域。
栅极接触部分115是藉由接合线810而耦合至栅极金属化接触区域820的。
桥式源极板130能够使用在不同的封装类型中。请参阅图12与图13，为本发明所述的平板-导线半导体封装结构(flat-lead package)1200。功率半导体芯片120在其下表面具有漏极接触区域，在其上表面具有源极接触区域与栅极接触区域，且该功率半导体芯片120耦合至导线框架1205的芯片衬垫1207上。该导线框架1205也包含有源极接触区域1210与栅极接触区域1215，但是这些部分都没有直接在物理上或电性上彼此接触。芯片衬垫1207的漏极导线1209会建立起和功率半导体芯片120的漏极之间的电性连接。桥式源极板130将功率半导体芯片120的源极接触区域连接至源极接触部分110的源极导线1211，且接合线810连接功率半导体芯片120的栅极接触区域至栅极接触部分1215的栅极导线1217。或者，栅极板(图中未示)将功率半导体芯片120的栅极接触区域连接至栅极导线1217。和之前所描述的其它实施例不同，其它实施例中在成型材料外面的漏极导线109、源极导线111与栅极导线117是弯曲的，而本实施例中，半导体封装结构1200提供的是较小尺寸封装(lower profile package)，其所具有的平板漏极导线1209、平板源极导线1211与平板栅极导线1217是不弯曲的延伸至成型材料1299的外面的。芯片衬垫1207的部分底部可以露出，以提供和漏极之间的电性接触，并提供较佳的热耗散。或者，导线也可以切断在成型材料1299的侧表面处，而提供成型材料封装1299的下表面与侧表面的电性接触。
半导体源极与栅极金属化接触区域可由镍/金，或是镍/钯/金通过电镀或喷溅，或是其它凸块金属化制程而形成。进一步来说，功率半导体芯片120通常可以是金属氧化物半导体场效应晶体管(MOSFET)，其上表面具有源极接触区域与栅极接触区域，而下表面具有漏极接触区域。然而，在部分特殊的情况下，亦可设计为该MOSFET芯片的下表面具有源极接触区域，而上表面具有漏极接触区域和栅极接触区域。底部源极MOSFET半导体器件，可参考如美国专利申请第11/495,803号所公开的题目为“底部源极横向双扩散金属氧化物半导体场效应晶体管的结构及其制造方法(BOTTOM SOURCELDMOSFET STRUCTURE AND METHOD)”的申请案，其所公开的内容可以完全予以合并。当本发明中的桥式平板应用于上述实施例所述的具有底部源极MOSFET芯片的封装时，藉由桥式平板可将底部源极芯片的漏极连接至漏极导线，则源极接触区域与漏极接触区域可以被切换。
本发明的有利之处在于提供一种具有桥式部位的桥式互连平板，在一个较佳实施例中，桥式部位是外露的，从而增进热性能。在另外一个较佳实施例中，凹涡相对于金属化接触区域被定位在桥式平板的低凹部位上。凹涡平板可以确保桥式互连平板不会在焊锡回流过程中漂移，因此可以确保平板位置的精准与精确；而桥式平板可以通过压印或是冲压来降低成本。
虽然本发明以前述的实施例揭示如上，然其并非用以限定本发明。在不脱离本发明的精神和范围内，所作的修改与润饰，均属本发明的专利保护范围。关于本发明所界定的保护范围请参考权利要求书。

Claims (23)

1.一种半导体封装结构，其特征在于，包含：
一导线框架，具有一漏极导线、一源极导线与一栅极导线；
一半导体芯片，其耦合至该导线框架，该半导体芯片具有至少一金属化源极接触区域；
一桥式源极板，其具有一桥形部分、若干个低凹部分、若干个平面部分与一连接部分，且这些低凹部分设置于该桥形部分的两侧，这些平面部分设置于这些低凹部分与该桥形部分的两侧，该连接部分依靠于其中一个平面部分，该桥式源极板连接源极导线与至少一金属化源极接触区域；以及
一封装材料，覆盖在该半导体芯片以及该漏极导线、该源极导线与该栅极导线上的至少一部分，使得所述的桥形部分的一上表面是露出于封装材料的。
2.如权利要求1所述的半导体封装结构，其特征在于，还包含若干个凹涡，其形成在所述的低凹部分上，这些凹涡是被定位来用以和该至少一金属化源极接触区域相接触。
3.如权利要求2所述的半导体封装结构，其特征在于，所述的凹涡包含一穿孔，通过该穿孔，所述的桥式源极互连平板与至少一个金属化源极接触区域焊接连接。
4.如权利要求2所述的半导体封装结构，其特征在于，所述的至少一金属化源极接触区域包含一镍/金的上层。
5.如权利要求1所述的半导体封装结构，其特征在于，所述的若干低凹部分和该至少一金属化源极接触区域相接触。
6.如权利要求1所述的半导体封装结构，其特征在于，所述的栅极导线藉由一接合线连接至一金属化栅极接触区域。
7.如权利要求1所述的半导体封装结构，其特征在于，所述的栅极导线藉由一栅极板连接至一金属化栅极接触区域。
8.如权利要求1所述的半导体封装结构，其特征在于，所述的桥形部分所设置的平面是超过这些低凹部分的平面的。
9.如权利要求8所述的半导体封装结构，其特征在于，所述的若干平面部分所设置的平面是介于桥形部分的平面与低凹部分的平面之间的。
10.如权利要求1所述的半导体封装结构，其特征在于，所述的连接部分是电性耦合于一导线框架的源极接触部分。
11.如权利要求1所述的半导体封装结构，其特征在于，所述的至少一金属化源极接触区域包含镍/金。
12.如权利要求1所述的半导体封装结构，其特征在于，所述的至少一金属化源极接触区域包含镍/钯/金。
13.一种半导体封装结构，其特征在于，包含：
一导线框架，具有一芯片衬垫以及第一导线、第二导线与第三导线，该第一导线电性连接至该芯片衬垫；
一半导体芯片，具有一第一金属化接触区域以及一第二金属化接触区域与一第三金属化接触区域，该第一金属化接触区域是位于该半导体芯片的下表面并耦合至芯片衬垫，该第二金属化接触区域与该第三金属化接触区域是位于相对于该下表面的芯片上表面上；
一桥式板，具有一桥形部分、若干低凹部分与若干平面部分，且这些低凹部分设置于该桥形部分的两侧，这些平面部分设置于这些低凹部分与该桥形部分的两侧，该桥式板是连接该第二导线与该第二金属化接触区域；以及
一封装材料，覆盖所述的半导体芯片以及第一导线、第二导线与第三导线的至少一部分，使得所述的桥形部分的一上表面是露出于该封装材料的。
14.如权利要求13所述的半导体封装结构，其特征在于，还包含至少一凹涡，其形成于这些低凹部分上，这些凹涡是被定位来用以和该第二金属化接触区域相接触的。
15.如权利要求14所述的半导体封装结构，其特征在于，所述的凹涡包含一穿孔，通过该穿孔，所述的桥式互连平板与第二金属化源极接触区域焊接连接。
16.如权利要求13所述的半导体封装结构，其特征在于，所述的桥形部分所设置的平面是超过这些低凹部分的平面的。
17.如权利要求16所述的半导体封装结构，其特征在于，所述的平面部分所设置的平面是介于该桥形部分的平面与这些低凹部分的平面之间的。
18.如权利要求13所述的半导体封装结构，其特征在于，所述的桥式板还包含一连接部分，其依靠于其中一个平面部分，并耦合至第二导线。
19.如权利要求13所述的半导体封装结构，其特征在于，所述的延伸至封装材料外面的第一导线、第二导线与第三导线的部分是弯曲的。
20.如权利要求13所述的半导体封装结构，其特征在于，所述的延伸至封装材料外面的第一导线、第二导线与第三导线的部分是平的。
21.如权利要求13所述的半导体封装结构，其特征在于，所述的第一导线、第二导线与第三导线是终止于该封装材料的侧表面的。
22.如权利要求13所述的半导体封装结构，其特征在于，所述的芯片衬垫的一下表面是露出于该封装材料的。
23.如权利要求13所述的半导体封装结构，其特征在于，所述的桥式板是通过压印或冲压的方式来形成所述的低凹部分与桥形部分的。
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US7884469B2 (en) 2011-02-08
US7622796B2 (en) 2009-11-24
US20080087992A1 (en) 2008-04-17
CN101399245A (zh) 2009-04-01
US20090236708A1 (en) 2009-09-24

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