TWI426589B - 用於低寄生阻抗封裝的頂部焊料加強的半導體裝置及方法 - Google Patents

用於低寄生阻抗封裝的頂部焊料加強的半導體裝置及方法 Download PDF

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Publication number
TWI426589B
TWI426589B TW097137618A TW97137618A TWI426589B TW I426589 B TWI426589 B TW I426589B TW 097137618 A TW097137618 A TW 097137618A TW 97137618 A TW97137618 A TW 97137618A TW I426589 B TWI426589 B TW I426589B
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Taiwan
Prior art keywords
solder
layer
contact
semiconductor device
nickel
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TW097137618A
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English (en)
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TW200919683A (en
Inventor
Hebert Francois
Bhalla Anup
Liu Kai
Sun Ming
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Alpha & Omega Semiconductor
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Publication of TW200919683A publication Critical patent/TW200919683A/zh
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Description

用於低寄生阻抗封裝的頂部焊料加強的半導體裝置及方法
本發明總體涉及電子封裝領域。更具體地，本發明涉及功率半導體器件的封裝。
依據市場定位的需求，現今電子產品的總體趨勢是在保持產品功能和低成本的同時實現產品小型化。毫無例外，相同的趨勢也適合於功率半導體器件的部分。這裏，減小伴隨器件封裝環境的多種寄生阻抗變得尤為重要，因為這些寄生阻抗通常造成不希望有的器件性能退化，諸如功率轉換效率下降和/或來自其相關聯的功率電子電路的雜訊上升。
現有致力於低電阻，低電感功率半導體器件封裝的多種先有技術。如第1圖所示，發明人為Luo(羅)等人的第6,841,852號美國專利敍述了一種帶有引線框架108的積體電路IC封裝，該引線框架108包括設置在晶片100下方的引線框架區塊103a和設置在晶片100的至少兩條相鄰邊上的鍵合金屬區域101a。增大鍵合金屬區域101a也就增加金屬區域101a和晶片100之間的源極鍵合線104的數量,從而減少寄生電阻和電感。進一步,在從封裝的塑膠體106延伸的外部終端的表面面積如果沒有最大化則將其增大,這樣可以加速散熱並且減小外部終端電阻。IC晶片100適用於MOSFET器件,鍵合金屬區域101a用於源極終端101。鍵合金屬區域101a可以由多種形狀實現。
如第1圖所示，雖然使用多個平行的短源極鍵合線104可以稍許減少寄生阻抗(該情況下為電阻和電感)，但是單獨使用短鍵合線仍可能導致總體較高的寄生阻抗，因為現在源極電流趨向於受到晶片上互連的限制，並且在標準IC製造工藝下，這些晶片上互連通常都非常薄。較厚的晶片上互連成本昂貴並且可能要求非標準製造工藝，這些都是非常不合要求的。另一方面，限制晶片尺寸以實現相應減少的歸因於晶片上互連的寄生阻抗的最終結果可能是降低諸如其功率處理能力的總體器件性能。
如第2圖所示的發明人為Hu(胡)等人的題為“Design of device layout for integration with power MOSFET packaging to achieve better lead wire connections and lower on resistance”(與功率MOSFET集成封裝的能夠達到更好的引線連接及更低電阻的器件布圖結構設計)的第5,767,567號美國專利公開了一種形成在半導體晶片上的MOSFET功率IC器件100，該器件包括多個源極接觸區域150-1，150-2，150-3和150-4，用以通過多個引線135，160連接到引線框架120。功率IC器件100在源極接觸區域150-1，150-2，150-3和150-4上包括多個引線接觸點170用以將引線160牢固地附接到源極接觸區域上。這些引線接觸點170大體上均勻地分佈在源極接觸區域上以減少擴散電阻，從而改進器件導通電阻及器件性能。
如第2圖所示，由於引線接觸點170大體上均勻地分佈在源極接觸區域150-1，150-2，150-3和150-4上，為了連接到源極接觸區域的較遠的區域要求使用帶有相應較高的電阻和電感的某些長鍵合線，因此該方法仍將導致總體較高的寄生阻抗。另一方面，限制晶片尺寸以實現相應減少的歸因於這些長鍵合線的寄生阻抗的最終結果可能是降低諸如其功率處理能力的總體器件性能。
發明人為Ho(何)等人的第11/226,913號美國專利申請和發明人為Sun(係)等人的第11/544,453號美國專利申請公開了帶有板互連的半導體器件封裝。第3A圖的部分剖視透視圖，第3B圖的取自2-2線的截面圖和第3C圖的取自3-3線的截面圖簡要地顯示了該兩個專利申請的半導體器件封裝。如第3B圖所示，當功率半導體晶片120的底部直接鍵合到引線框架的漏極接觸部分107時，功率半導體晶片120的頂部用圖案化的源極板125代替鍵合線連接到引線框架的源極接觸部分110。同樣，在第3C圖中，當功率半導體晶片120的底部直接鍵合到引線框架的漏極接觸部分107時，功率半導體晶片120的頂部用圖案化的柵極板137代替鍵合線連接到引線框架的柵極接觸部分115，該圖案化的柵極板137帶有用於將柵極板137夾在功率半導體晶片120之上的鎖球機構155，從而進一步方便封裝工藝。密封劑135恰好覆蓋住所有環境敏感部分用以保持長期的器件可靠性。
如上所述的板連接封裝是一種高性能的封裝，因為其特點是：由於單板代替多個鍵合線用於連接各個區域導致的低成本；由於器件電流遍及板截面的良好分佈導致的低寄生電阻和電感；和由於矩陣型夾取附貼可以設計成處理多器件晶片的同時封裝而帶來的高生產率。
然而，板連接封裝的缺點在於其成本以及需要用於附貼所述板的非標準加工，而且所述板本身也必須為封裝和晶片定制。同時，該工藝是處理已分離晶片的晶片後道封裝層級的工藝。這意味著與其他晶片層級的工藝相比較高得多的成本。總之，存在通過與標準的晶片層級工藝相相容同時不要求非標準加工的高性能低成本的封裝重點減少與器件封裝相關的寄生阻抗的需求。
本發明的目的在於提供一種用於低寄生阻抗封裝的頂部焊料加強的半導體器件。該頂部焊料加強的半導體器件包括：帶有用於將其多個活動終端互連至其操作環境的頂部金屬層的半導體器件晶片。該頂部金屬層被圖案化成接觸區域和接觸加強區域。該器件晶片包括預留視窗的頂部鈍化層，頂部金屬層通過預留視窗的頂部鈍化層連接到內部器件結構。至少一個接觸區域通過晶片上互連或器件晶片的內部結構電連接到至少一個接觸加強區域。每個接觸加強區域的頂部添加焊料層，用以增加複合厚度，從而抵抗側面電流相應地減少寄生電阻和電感。以此方法減少歸因於半導體器件晶片的不希望有的寄生阻抗。
在一個實施例中，焊料層可以由鉛焊料，無鉛焊料，錫銀銅焊料，錫銀焊料或錫銅焊料製成。相應的頂部金屬層由與焊料層形成直接接觸的銅製成。
對於其頂部金屬層材料由於材料的不相容不能直接與焊料層材料形成空間均勻的電鍵合的半導體器件晶片，該半導體器件晶片還包括可焊接的並且導電的介入層。該介入層夾在頂部金屬層和焊料層之間並且與頂部金屬層和焊料層形成空間均勻的電焊料鍵合。接觸加強區域可以進一步圖案化，以加強相應電焊料鍵合的空間均勻性。
在另一個實施例中，頂部金屬層由鋁製成。相應地，介入層可以由允許焊料層與鋁之間的間接接觸的鎳/金層，鎳/鈀層或鎳/鈀/金層製成。
在又一個實施例中，介入層的厚度可以從2微米左右到20微米左右。
一種製造這樣的頂部焊料加強的半導體器件的方法包括：
a)在半導體器件晶片的製造過程中確保每一個接觸加強區域通過半導體器件晶片的內部器件結構電連接到至少一個接觸區域。
b)將頂部金屬層通過光刻圖案化為接觸區域和接觸加強區域。該圖案化還涉及打開穿過半導體器件晶片的頂部鈍化層的視窗，然後，通過這些視窗將頂部金屬層連接到半導體器件晶片的內部器件結構。
c)在每一個接觸加強區域的頂部形成用以增加複合厚度的焊料層。
在一個實施例中，這樣的頂部焊料加強的半導體器件的製造方法進一步包括晶片分離之前在晶片層級上實行所有a)，b)和c)步驟以減少相關的器件處理和器件製造成本。然後，在步驟c)之後，這樣製造的半導體器件晶片從其晶片上分離，接著對於每個獨立的半導體器件晶片將接觸區域互連到其相應的活動終端。
在另一個實施例中，對於具有介入層的半導體器件晶片，該方法還涉及澱積夾在頂部金屬層和焊料層之間並且與頂部金屬層和焊料層形成空間均勻的電焊料鍵合的可焊接的並且導電的介入層。
其中，介入層包括鎳(Ni)層上的薄金(Au)層，頂部金屬層為鋁層，澱積介入層還包括鋁上的鎳/金層的化學鍍。當介入層包括鎳/鈀/金層並且頂部金屬層為鋁層時，澱積介入層還包括鋁上的鎳/鈀/金層的化學鍍或電鍍。
在一個實施例中，在每一個接觸加強區域的頂部形成焊料層還涉及以下晶片層級的步驟：
c1)在半導體器件晶片的頂部表面覆蓋掩模以暴露每個接觸加強區域，通過模版印刷工藝在其上定位然後滴落一定數量的焊料球。
c2)熱處理該一定數量的焊料球使其粘貼到每一個接觸加強區域的表面。
c3)加熱熔化該一定數量的焊料球並使其流到一起以擴展焊料，在每一個接觸加強區域的頂部形成所需要的焊料層以減少所有暴露區域上的電阻。
本發明的優點在於本發明所提供的減少與器件封裝相關的寄生阻抗的器件和方法使用標準加工工藝，同時，該工藝是晶片層級的工藝可以降低成本。
通過下文的敍述，本發明的各個方面及其多個實施例對於本領域的普通熟練技術人員將是顯而易見的。
上下文所述的內容及附圖僅集中于本發明的一個或數個當前的優選實施例，也敍述了某些示例性的可選特徵和/或替代實施例。敍述及附圖的目的是意在說明本發明，而非對本發明的限制。因此，本領域的普通熟練技術人員將很容易意識到各種修改，變化和替代。這樣的修改，變化和替代應該被認為也包含在本發明的範圍之內。
第4圖所示為具有在VDMOS(Vertical double-diffused Metal-Oxide-Semiconductor垂直雙擴散金屬氧化物半導體)晶片202的頂部添加不規則形狀的回流焊料224的IC封裝200的本發明的初步概念。焊料材料可以由鉛焊料，無鉛焊料，錫銀銅焊料，錫銀焊料或錫銅焊料製成。作為其漏極的VDMOS晶片202的底部附貼於具有用於連接到外部電路的延伸漏極引線框架終端209和漏極引線框架終端210的引線框架晶片區塊208。其他的引線框架部分是用以連接到源極引線框架終端214的源極引線框架部分212a-212c，和用於相同目的的連接到柵極引線框架終端208的柵極引線部分216。VDMOS晶片202的頂部金屬層具有柵極接觸區域206和源極接觸區域204，兩者均由標準的鋁材料製成。為了將頂部金屬層橋接到引線框架，柵極鍵合線222設置成連接柵極接觸區域206和柵極引線框架部分216。然而，考慮到所通過的高電流等級，若干源極鍵合線205設置成連接源極接觸區域204和源極引線框架部分212a-212c。為了進一步縮短源極鍵合線205以減少寄生阻抗，源極鍵合線205被分為源極鍵合線組220a，源極鍵合線組220b和源極鍵合線組220c。源極鍵合線可以用金，銅和鋁製成，或用鋁“帶”代替鍵合線。進一步，可以用金屬板代替源極鍵合線205，將源極引線框架部分212a-212c熔接在一起而提供源極和源極引腳之間的連接。
由於可以使不規則形狀的回流焊料224的厚度比VDMOS測試晶片202的頂部金屬層厚得多，所以，歸因於其他流經源極接觸區域204的側面電流的寄生阻抗相應地減少很多。另外，VDMOS測試晶片202上適當尺寸，適當形狀和適當定位的不規則形狀的回流焊料224的實際存在還允許另外縮短柵極鍵合線202和源極鍵合線205，因為該兩者只需要到達VDMOS晶片202的與柵極引線框架部分216和源極引線框架部分212a-212c最近的邊緣。其結果是在不必減小晶片尺寸的情況下另外減小歸因於鍵合線的寄生阻抗。雖然IC封裝200顯示了來自焊料的非經掩模遮蔽的隨機流動的回流焊料224的不規則形狀造成結果電阻變化的問題，但是其根本原因應被理解為與在焊料材料與鋁之間直接形成空間均勻的電鍵合相關的在兩者之間的不相容。然而，第二個相關的問題是不能夠保持不規則形狀的回流焊料224和各個源極鍵合線205接觸源極接觸區域204的接觸區域之間所要求的最小間隙。這樣的所要求的最小間隙必須被保持以確保不規則形狀的回流焊料224不延伸得太遠以至於與用於互連這些鍵合線的線鍵合工藝發生機械干擾而造成工藝不可靠。即使焊料層224可以線上鍵合工藝之後施加，仍然要求該最小間隙，因為在接觸鍵合線時回流焊料可能通過化學方式侵襲該鍵合線，從而造成長期的不可靠。下文將敍述在保持減小寄生阻抗的同時解決IC封裝200的上述問題的方案。
第5A圖和第5B圖所示為通過在晶片金屬化的頂部添加介入層，然後在介入層的頂部滴落一定數量的焊料球304，接著回流焊料球304以形成所需要的均勻的熔化焊料層304a而應用於第4圖的VDMOS型功率MOSFET器件的本發明的精確概念。作為其漏極的功率器件晶片300的底部附貼於引線框架310，引線框架310的用以連接到外部電路的延伸漏極引線框架終端在圖中未顯示以避免模糊細節。其他的簡化引線框架部分是源極引腳306和柵極引腳308。雖然圖中沒有直接顯示，功率器件晶片300的頂部金屬層仍用標準材料鋁製成。頂部金屬層圖案化為三個區域，每一個區域的頂部具有通過化學鍍工藝在其上鍍覆的鎳/金(Ni/Au)介入層，從而在頂部金屬化上形成鍍鎳/金區塊開口302a，鍍鎳/金區塊開口302b和鍍鎳/金區塊開口302c。鍍鎳/金區塊開口302a，302b和302c的鍍鎳/金層構成介入層。對於本領域的熟練技術人員而言，在該情況中的鍍鎳/金區塊開口302a應該被認為其底部與頂部金屬層部分直接接觸，該頂部金屬層部分轉而通過預留視窗的頂部鈍化層連接到功率VDMOS器件晶片300的源極。由於鍍鎳/金區塊開口302b的作用是通過源極鍵合線組220c連接到源極引腳306，所以鍍鎳/金區塊開口302b下的頂部金屬層作為功率器件晶片300結構的一部分電連接到鍍鎳/金區塊開口302a下的頂部金屬層。對於本領域的熟練技術人員而言，該情況中的鍍鎳/金區塊開口302c應該被認為其底部與另一個頂部金屬層部分直接接觸，該頂部金屬層轉而通過預留視窗的頂部鈍化層連接到功率VDMOS器件晶片300的柵極。鍍鎳/金區塊開口302c的作用是通過柵極鍵合線222連接到柵極引腳308。
鍍鎳/金介入層是導電的及可焊接的，並且能夠與鋁頂部金屬層和焊料材料金相形成空間均勻電焊料鍵合。因此，如第5B圖所示，熔化和回流後，焊料球304轉化為通過鍍鎳/金介入層與鋁頂部金屬層電接觸的均勻的熔化焊料層304a。另外，通過化學鍍工藝，可以使由厚鎳層和薄金層組成的鍍鎳/金介入層的厚度處在2微米左右到20微米左右，比0.5微米左右到5微米左右的典型的頂部金屬層的厚度厚得多。如果必要，化學鍍鎳/金介入層甚至可以製造得更厚，取決於化學鍍工藝的速率，暴露的鍍覆面積以及結果層的應力等。因此，頂部金屬層頂部的均勻的熔化焊料層304a實現了大量增加的複合導體厚度及抵抗流經的表面電流相應減少的歸因於功率器件晶片300的包括寄生電阻和寄生電感成分的寄生阻抗。值得注意的是，均勻的熔化焊料層304a將僅在暴露的鍍鎳/金區塊開口302a區域中流動以有效地形成低電阻和低應力的厚源極金屬化層。這樣可以通過以自對準方式(使用通過區塊掩模暴露的頂部金屬)增加有效金屬厚度進一步減少功率器件晶片300頂部的源極金屬。由於同樣的原因，均勻的熔化焊料層304a也被保證與鍍鎳/金區塊開口302b和302c之間分離出可靠的引線鍵合所要求的最小間隙。在實際操作中，所要求的最小間隙被確定為處在100微米至150微米的範圍內。從功能上講，位於鍍鎳/金區塊開口302a下的圖案化頂部金屬層區域可以被表徵為本發明的接觸加強區域。而位於鍍鎳/金區塊開口302b和鍍鎳/金區塊開口302c下的圖案化頂部金屬層區域可以被表徵為傳統的接觸區域。為了將頂部金屬層橋接到引線框架，設置柵極鍵合線222以連接鍍鎳/金區塊開口302c和柵極引腳308。然而，考慮到流經的高電流水準，用源極鍵合線組220c連接鍍鎳/金區塊開口302b和源極引腳306。鍵合線可以用金，銅或鋁製成，其尺寸範圍在25微米至200微米之間。另外，取決於封裝結構也可以使用鋁帶。至此，可以清楚地表明，化學鍍鎳/金不是僅有的可用於介入層的材料。任何導電的，可焊接的並能夠與鋁頂部金屬層和焊料材料金相形成空間均勻的電焊料鍵合的替代材料都可以用於實施本發明。以下所列為部分此類替代材料的實例：鎳/金(Ni/Au)層，鎳/鈀(Ni/Pd)層，鎳/鈀/金(Ni/Pd/Au)層。
另一重要方面是，其諸如銅(Cu)的頂部金屬層材料在焊料層材料熔化時已經與其直接形成空間均勻的電鍵合的功率半導體器件在將焊料球304滴落在頂部金屬層上之前不必在其頂部添加上述介入層。
第6圖說明本發明的應用於LDMOS(Lateral Double-diffused Metal-Oxide-Semiconductor橫向雙擴散金屬氧化物半導體)功率MOSFET器件晶片300的同一個精確概念的第一部分。該實施例除了下述方面外與第5A圖所示的實施例相同：功率MOSFET器件晶片300的底表面為其源極，功率器件晶片300的頂表面包含帶有鍍鎳/金區塊開口302b的漏極和帶有鍍鎳/金區塊開口302c的柵極。鍍鎳/金區塊開口302b和302c分別通過漏極鍵合線組226c和柵極鍵合線222連接到引線框架310的漏極引腳312和柵極引腳308。
第7圖所示為本發明的應用於VDMOS功率MOSFET器件晶片300的除了鍍鎳/金區塊開口302a的形狀變化並伴隨焊料球304相應的不對稱位置之外的同一個精確概念的第一部分。鍍鎳/金區塊開口302a形狀變化的自由度可以相當大，因為接下來的取決於特定的區塊開口形狀的焊料球熔化回流的工藝可以憑藉經驗導致不同程度均勻性的熔化焊料層304a。因此，在實際操作中，諸如十字形，星形，網格形，十指交叉形或螺旋形的區塊開口形狀的變化需要通過實驗確定，直至找出相應的熔化焊料層304a的最佳空間均勻性，同時具備最小的材料應力和電阻。至此可以清楚地認識到，本發明的多個附加參數也可以進行調整，以進一步優化歸因於功率器件晶片300的與封裝相關的寄生阻抗的減小。以下所列為部分參數的實例：焊料球304的數量和尺寸；使用附加掩模獨立於下層器件金屬電極圖案進行鍍鎳/金區塊開口302a的圖案化；取決於晶片附貼溫度，鍍鎳/金區塊開口302a內的焊料的熔化和回流可以與晶片附貼工藝相結合；鍍鎳/金區塊開口302a和鍵合區塊區域之間的距離可以精細調整以減小封裝後的功率器件晶片300的總體尺寸。
第8A圖至第8D圖說明由於規模的經濟性實現相應減少器件製造成本的使用本發明的製造步驟的晶片層級部分。第8A圖說明8個功率VDMOS器件晶片300a-300h的直至及包括其頂部金屬層圖案化的晶片層級的器件製造，該圖案化將頂部金屬層圖案化為用於互連的多個通過區塊開口314暴露的鋁金屬化區域。正如半導體器件製造領域所知，圖案化頂部金屬層涉及光刻打開穿過半導體器件晶片的頂部鈍化層的多個視窗，然後通過這些視窗，蒸發通常為鋁的頂部金屬層和/或將其連接到半導體器件晶片的內部器件結構。
第8B圖所示為鎳/金厚介入層有效澱積到多個穿過區塊開口314暴露的鋁金屬化上從而形成相應數量的鍍鎳/金區塊開口302a，鍍鎳/金區塊開口302b和鍍鎳/金區塊開口302c的後續的晶片化學鍍工藝之後的結果。雖然圖中沒有具體顯示，但鍍鎳/金區塊開口302b通過內部器件晶片結構電連接到鍍鎳/金區塊開口302a。再次說明，在本發明中，鍍鎳/金區塊開口302a對應于接觸加強區域，而鍍鎳/金區塊開口302b和鍍鎳/金區塊開口302c對應於接觸區域。
然後，應用模版印刷工藝(CSP)，晶片通過掩模暴露金屬化頂部的每一個鍍鎳/金區塊開口302a(對應于接觸加強區域)，在鍍鎳/金區塊開口302a上定位和滴落多個焊料球304。然後，將晶片熱處理使焊料球304粘結到暴露的金屬表面。其結果如第8C圖所示。
接下來，將晶片安裝在切割帶上，使用標準切割工藝將晶片分離為各個功率器件晶片。處理後的功率器件晶片300和切割溝316如第8D圖所示。對於本領域的熟練技術人員而言，至此可以清楚地認識到，雖然此處的圖示限於8個功率器件晶片300a-300h的情況，但是本發明的方法可以同樣適用於其上具有數千個功率器件晶片的晶片規模製造環境。另外，本發明也不限於功率半導體器件的封裝。
第8E圖至第8H圖所示為使用本發明的製造步驟的後道晶片層級部分。在第8E圖中，各個功率器件晶片300與粘結其上的焊料球304一起附貼到引線框架310。第8F圖所示為可選的回流工藝的結果，其中，進一步加熱附貼的功率器件晶片300，使焊料球熔化和流到一起從而在鍍鎳/金區塊開口302a的頂部形成均勻熔化的低電阻焊料層304a(對應于接觸加強區域)。最後的效果是經增加的複合厚度以及相應減小的寄生電阻和寄生電感成分。如果上述第8E圖的晶片附貼加熱迴圈對形成均勻熔化的焊料層304a充分，則回流工藝將不再必要，因此該步驟是可選的。
第8G圖所示為引線鍵合工藝的結果，其中，鍍鎳/金區塊開口302b和鍍鎳/金區塊開口302c(接觸區域)分別通過鍵合線組318和鍵合線組320連接到引線框架310。為了可靠性而保持均勻熔化的焊料層304a(接觸加強區域)和與其最接近的多個鍵合線之間的最小間隔，是通過適當的區塊圖案化設計相應地將鍍鎳/金區塊開口302a與鍍鎳/金板302b和鍍鎳/金板302c相間隔的簡單的課題。
最後，第8H圖所示為完成封裝後的功率器件晶片300，其中模制塑封322被部分去除以顯示某些與封裝相關的部分。簡單地說，該操作包括模制成型模制塑封322，電鍍引線框架引腳，在封裝外表面打上用以識別的標記，修齊並形成引腳，最後測試封裝後的器件。
雖然上文的敍述包括許多特殊性，但是不能認為這些特殊性相應地限制了本發明的範圍，而只能認為這些特殊性提供了對本發明的多個現有的優選實施例的說明。例如，僅通過對一些幾何尺寸作出調整，本發明也就可以被修改為應用多種其他封裝類型封裝多種其他類型的半導體器件。
遍及本文的敍述和附圖，參考具體的結構給出了多個示例性實施例。本領域的普通熟練技術人員可以認識到，本發明可以以多種其他的具體形式實施，同時本領域的普通熟練技術人員也不需要過度的經驗就可以實現這樣的其他實施例。因此，對於本專利檔的目的，本發明的範圍不限於上文所述的示例性實施例，而由附後的權利要求定義。落入權利要求的意義及其等價範圍內的任何及所有修改都應該被認為包含在本發明的精神和範圍之內。
220a、220b、220c．．．源極鍵合線組
222．．．柵極鍵合線
300．．．功率器件晶片
302a、302b、302c．．．鍍鎳/金區塊開口
304．．．焊料球
306．．．源極引腳
308．．．柵極引腳
108、120、310．．．引線框架
120．．．功率半導體晶片
100．．．晶片
101．．．源極終端
101a．．．增大鍵合金屬區域
103a．．．引線框架區塊
104．．．短源極鍵合線
106．．．塑膠體
107．．．漏極接觸部分
110．．．源極接觸部分
135、160．．．引線
135．．．密封劑
150-1、150-2、150-3、150-4、204．．．源極接觸區域
170．．．引線接觸點
115．．．柵極接觸部分
137．．．柵極板
155．．．鎖球機構
125．．．源極板
200．．．IC封裝
202．．．VDMOS晶片、柵極鍵合線
VDMOS．．．垂直雙擴散金屬氧化物半導體
206．．．柵極接觸區域
205．．．源極鍵合線
208．．．引線框架晶片區塊、柵極引線框架終端
209．．．延伸漏極引線框架終端
210、214．．．漏極引線框架終端
212a、212b、212c．．．源極引線框架部分
216．．．柵極引線框架部分
300a-300h．．．VDMOS器件晶片
314．．．區塊開口
316．．．切割溝
318、320．．．鍵合線組
322．．．模制塑封
為了更完整地敍述本發明的多個實施例，在敍述中將參考相應的附圖。然而，附圖僅是對本發明的圖釋，不能被認為是對本發明範圍的限制。
第1圖和第2圖是傳統的鍵合線封裝的現有技術；
第3A圖至第3C圖是現有技術的板鍵合封裝的透視圖和截面圖；
第4圖是具有添加到半導體器件測試晶片的頂部的不規則形狀的回流焊料突起物的本發明的初步概念的示意圖；
第5A圖和第5B圖所示為通過在晶片金屬化的頂部添加介入層，然後在介入層的頂部滴落一定數量的焊料球，接著回流焊料球以形成所需要的均勻的熔化焊料層而應用於VDMOS功率MOSFET器件的本發明的精確概念；
第6圖所示為本發明的應用於LDMOS功率MOSFET器件的同一個精確概念的第一部分；
第7圖所示為本發明的應用於VDMOS功率MOSFET器件的除了介入層形狀變化之外的同一個精確概念的第一部分；
第8A圖至第8D圖所示為使用本發明的製造步驟的晶片層級部分；以及
第8E圖至第8H圖所示為使用本發明的製造步驟的後道晶片層級部分。
220c．．．源極鍵合線組
222．．．柵極鍵合線
300．．．功率器件晶片
302a、302b、302c．．．鍍鎳/金區塊開口
304．．．焊料球
306．．．源極引腳
308．．．柵極引腳
310．．．引線框架

Claims (24)

  1. 一種用於低寄生阻抗封裝的頂部焊料增強的半導體裝置，該頂部焊料增強的半導體裝置包括：帶有用於將其一定數量的活動終端互連至外部電路的頂部金屬層的已制半導體裝置晶片；和位於所述頂部金屬層的頂部的用於增加複合厚度從而抵抗流經的表面電流降低包括寄生電阻和寄生電感成分的寄生阻抗的焊料層；所述頂部金屬層被進一步圖案化為多個接觸區域和多個接觸加強區域；所述焊料層在所述接觸加強區域上散佈，所述接觸區域經由金屬鍵合到引線框架。
  2. 如申請專利範圍第1項所述的頂部焊料加強的半導體裝置，其特徵在於，其中所述接觸區域和所述接觸加強區域相分離。
  3. 如申請專利範圍第1項所述的頂部焊料加強的半導體裝置，其特徵在於，其中至少一個所述接觸區域電連接到至少一個所述接觸加強區域。
  4. 如申請專利範圍第1項所述的頂部焊料加強的半導體裝置，其特徵在於，其中所述已制半導體裝置晶片還包括預留視窗的頂部鈍化層，所述頂部金屬層經由該頂部鈍化層連接到內部裝置結構。
  5. 如申請專利範圍第1項所述的頂部焊料加強的半導體裝置，其特徵在於，其中所述焊料層用鉛焊料，無鉛焊料，錫銀銅焊料，錫銀焊料或錫銅焊料製成。
  6. 如申請專利範圍第5項所述的頂部焊料加強的半導體裝置，其特徵在於，該頂部焊料加強的半導體裝置還包括介入層，該介入層夾在頂部金屬層和焊料層之間並且與頂部金屬層和焊料層形成空間均勻的電焊料鍵合。
  7. 如申請專利範圍第6項所述的頂部焊料加強的半導體裝置，其特徵在於，其中至少一個所述的接觸加強區域被圖案化，以進一步增加相應的電焊料鍵合的空間均勻性。
  8. 如申請專利範圍第7項所述的頂部焊料加強的半導體裝置，其特徵在於，其中所述接觸加強區域的圖案化從由十字形，星形，網格形，十指交叉形和螺旋形組成的組合中選擇。
  9. 如申請專利範圍第5項所述的頂部焊料加強的半導體裝置，其特徵在於，其中所述頂部金屬層由銅製成。
  10. 如申請專利範圍第6項所述的頂部焊料加強的半導體裝置，其特徵在於，其中頂部金屬層與介入層的組合可以選擇的是：鋁與鎳/金層的組合，鋁與鎳/鈀層的組合或者鋁與鎳/鈀/金層的組合。
  11. 如申請專利範圍第10項所述的頂部焊料加強的半導體裝置，其特徵在於，其中所述鎳/金層的厚度在2微米 左右到20微米左右之間。
  12. 一種用於減小歸因於具有用於將其一定數量的活動終端互連到其工作環境的頂部金屬層的已制半導體裝置晶片的不希望有的寄生阻抗的方法，其特徵在於，該方法包括：a)將頂部金屬層圖案化為第一多個接觸區域和第二多個接觸加強區域；b)經由已制半導體裝置晶片的內部裝置結構將至少一個接觸區域電連接到至少一個接觸加強區域；和c)對於每一個所述接觸加強區域，將焊料層附貼到其頂部以增加複合厚度，從而抵抗流經的表面電流相應降低包括寄生電阻和寄生電感成分的寄生阻抗，從而經由所述至少一個接觸區域減小歸因於已制半導體裝置晶片的不希望有的寄生阻抗；該方法還包括：d)從晶片上分離來自該晶片的每一個已制半導體裝置晶片並將所述第一多個接觸區域互連到其相應的活動終端。
  13. 如申請專利範圍第12項所述的減小不希望有的寄生阻抗的方法，其特徵在於，該方法還包括在晶片與晶片分離之前在晶片層級上實行所有步驟a)，b)和c)，從而減少已制半導體裝置晶片的裝置處理和裝置製造成本。
  14. 如申請專利範圍第12項所述的減小不希望有的寄生阻 抗的方法，其特徵在於，其中將所述第一多個接觸區域互連到其相應的活動終端的步驟還包括將任何接觸區域和與其最近的接觸加強區域之間的間隔至少保持在處於預先確定的最小間隔以保證互連工藝的可靠性。
  15. 如申請專利範圍第12項所述的減小不希望有的寄生阻抗的方法，其特徵在於，其中圖案化頂部金屬層的步驟還包括打開穿過已制半導體裝置晶片的頂部鈍化層的多個視窗，然後經由所述多個視窗將頂部金屬層連接到已制半導體裝置晶片的內部裝置結構。
  16. 如申請專利範圍第12項所述的減小不希望有的寄生阻抗的方法，其特徵在於，其中附貼焊料層的步驟還包括提供用鉛焊料，無鉛焊料，錫銀銅焊料，錫銀焊料或錫銅焊料製成的焊料層材料。
  17. 如申請專利範圍第16項所述的減小不希望有的寄生阻抗的方法，其特徵在於，其中，對於由於材料不相容不能與焊料層材料直接形成空間均勻的電鍵合的頂部金屬層材料，附貼焊料層的步驟還包括澱積可焊接的，導電的，夾在頂部金屬層和焊料層之間並且與頂部金屬層和焊料層形成空間均勻的電焊料鍵合的介入層。
  18. 如申請專利範圍第17項所述的減小不希望有的寄生阻抗的方法，其特徵在於，其中將頂部金屬層圖案化為第一多個接觸區域和第二多個接觸加強區域的步驟還 包括圖案化至少一個所述接觸加強區域以進一步增加相應的電焊料鍵合的空間均勻性。
  19. 如申請專利範圍第16項所述的減小不希望有的寄生阻抗的方法，其特徵在於，其中所述頂部金屬層用銅製成，以及在每一個所述接觸加強區域的頂部附貼焊料層的步驟還包括建立焊料層和頂部金屬層之間的直接接觸。
  20. 如申請專利範圍第17項所述的減小不希望有的寄生阻抗的方法，其特徵在於，其中頂部金屬層與介入層的組合進一步還包括：鋁與鎳/金層的組合，鋁於鎳/鈀層的組合和鋁與鎳/鈀/金層的組合。
  21. 如申請專利範圍第20項所述的減小不希望有的寄生阻抗的方法，其特徵在於，其中當頂部金屬層與介入層的組合是鋁與鎳/金層的組合時，澱積介入層的步驟還包括在鋁上化學鍍覆鎳/金層。
  22. 如申請專利範圍第20項所述的減小不希望有的寄生阻抗的方法，其特徵在於，其中當頂部金屬層與介入層的組合是鋁與鎳/鈀/金層的組合時，澱積介入層的步驟還包括在鋁上化學鍍覆鎳/鈀/金層。
  23. 如申請專利範圍第20項所述的減小不希望有的寄生阻抗的方法，其特徵在於，其中當頂部金屬層與介入層的組合是鋁與鎳/鈀/金層的組合時，澱積介入層的步驟還包括在鋁上電鍍鎳/鈀/金層。
  24. 如申請專利範圍第12項所述的減小不希望有的寄生阻 抗的方法，其特徵在於，其中在每一個所述接觸加強區域的頂部附貼焊料層的步驟還包括：c1)經由掩模暴露每個所述接觸加強區域，通過模版印刷工藝在其上定位然後滴落多個焊料球；c2)熱處理該多個焊料球使其粘貼在每一個所述接觸加強區域的表面的頂部；c3)加熱熔化該多個焊料球並使其流到一起以在每一個所述接觸加強區域的頂部形成焊料層。
TW097137618A 2007-10-31 2008-09-30 用於低寄生阻抗封裝的頂部焊料加強的半導體裝置及方法 TWI426589B (zh)

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