CN101295683A - 改善散热与接地屏蔽功能的半导体装置封装结构及其方法 - Google Patents

改善散热与接地屏蔽功能的半导体装置封装结构及其方法 Download PDF

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CN101295683A
CN101295683A CNA200810092255XA CN200810092255A CN101295683A CN 101295683 A CN101295683 A CN 101295683A CN A200810092255X A CNA200810092255X A CN A200810092255XA CN 200810092255 A CN200810092255 A CN 200810092255A CN 101295683 A CN101295683 A CN 101295683A
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substrate
order
contact mat
semiconductor device
device package
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杨文焜
林殿方
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Yupei Science & Technology Co Ltd
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Yupei Science & Technology Co Ltd
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Abstract

本发明是提供一种改善散热与接地屏蔽功能的半导体装置封装结构及其方法，其封装结构包含一基板，具有接触垫，以及填充导电材料的通孔，用以实现散热及接地屏蔽功能；一具有焊垫的晶粒，通过一具有高导热能力的黏着材料，附着于接触垫上，用以散热；一重布层形成于基板与晶粒上，以耦合焊垫与形成于基板上的接触垫。本发明的结构可改善其厚度，并增进结构的散热与接地屏蔽能力。再者本发明的封装结构可实现一层迭封装结构。

Description

改善散热与接地屏蔽功能的半导体装置封装结构及其方法
技术领域
本发明为有关半导体封装结构及其制造方法，特别是关于薄型半导体封装结构。
背景技术
于半导体装置领域中，其装置的密度不断地增加；因此，缩小装置的尺寸需求也渐增。集成电路的发展是高度地影响芯片封装技术，因此当电子组件的尺寸视为趋势时，封装技术势必也随之起舞。基于上述理由，现今封装技术的趋势是朝向球型门阵列(BGA)、覆晶技术(FC-BGA)、芯片级封装(CSP)、晶圆级封装(WLP)；其中晶圆级封装结构具有极小的尺寸以及极优良的电性等等优点。使用晶圆级封装技术，可减少成本与制程时间，且完成的晶圆级封装结构的尺寸与晶粒大小相同；因此，此技术可满足电子装置微小化的需求。
虽然晶圆级封装有上述的诸多优点，但存在某些问题影响了晶圆级封装技术的接受度。例如，某些封装技术需要晶粒直接形成于基板上部表面上。再者，一般半导体晶粒的焊垫透过重布程序重布之，包含一重布层重布至区域数组形式中的多个金属垫。其增层亦增加封装的尺寸。因此，封装的厚度增加。此将抵触减少芯片尺寸的需求。芯片利用增层层层堆积，因此其结构的散热与接地屏蔽为另一个需要解决的问题。
发明内容
本发明的目的是提供一种封装结构，具有较小的体积、较好的散热以及接地屏蔽效能，以克服前述问题。
本发明的目的是提供一基板具有电路以及填充金属材料的通孔，以连接配置于基板反面上的接垫。
本发明的目的是提供一薄型化的封装结构，且本发明的优点是提供一具有高导热能力的黏着材料。
本发明是提供一种用以改善散热与接地屏蔽功能的半导体装置封装结构，包含：一基板，具有一第一接触垫，且至少具有一通孔(through hole)形成于其基板内。一金属层，形成于其基板下部表面处，其中至少一通孔自第一接触垫连接至金属层，用以散热(heat dissipation)与接地屏蔽(ground shielding)。一晶粒，具有一焊垫(bonding pad)通过一具有高导热的黏着材料附着于其第一接触垫上。一介电层，形成于其晶粒上，且一第二接触垫形成于其基板的上部表面处。一重布层(RDL)，形成于其晶粒上方并耦合其焊垫至第二接触垫，用以电性连接。一锡球，形成于基板上部表面上的第二接触垫上。
所述用以改善散热与接地屏蔽功能的半导体装置封装结构，还包含一保护层，形成于该重布层上；其中该保护层材质包括聚亚酰胺(polyimide，PI)树脂化合物、硅胶。
所述用以改善散热与接地屏蔽功能的半导体装置封装结构，其中所述的该金属层的材质包括散热材料；以及该金属层可作为天线。
所述用以改善散热与接地屏蔽功能的半导体装置封装结构，其中所述的第二接触垫亦形成于该基板下部表面上，堆栈另一半导体装置封装结构，用以形成一层迭封装(package onpackage，PoP)结构。
所述用以改善散热与接地屏蔽功能的半导体装置封装结构其中所述基板的材质包括FR5/FR4/BT(Bismaleimide triazine)或金属/合金。
本发明亦提供一种制造用以改善散热与接地屏蔽的半导体装置封装结构的方法，包含：提供一基板，其基板具有一第一接触垫、一第二接触垫以及至少一个通孔。配置一黏着材料于具有一焊垫的晶粒背面上。附着其晶粒于其第一接触垫上。形成增层(build up layer)以耦合其第二接触垫与其焊垫。通过涂布(coating)或印刷(printing)方式形成顶部保护层于其晶粒与其基板上。置放一锡球于其第二接触垫上；以及回焊(reflowing)其锡球，用以形成锡球于其第二接触垫上。
所述用以制造改善散热与接地屏蔽功能的半导体装置封装结构的方法，还包含设置该晶粒与该基板，而后附着该基板的该锡球至印刷电路板(PCB)的连接垫，用以形成一覆晶(flip-chip)结构于该基板与该印刷电路板之间，其中该基板的该第一接触垫构成一用于该晶粒的电磁屏蔽(EM shiel ding)。
所述用以制造改善散热与接地屏蔽功能的半导体装置封装结构的方法，还包含堆栈另一半导体封装结构于该半导体封装结构上，用以形成一层迭封装结构。
所述用以制造改善散热与接地屏蔽功能的半导体装置封装结构的方法，其中所述的基板包括FR4/FR5/BT基板或金属/合金基板；以及其中该保护层材质包括聚亚酰胺(polyimide，PI)树脂化合物、硅胶。
所述用以制造改善散热与接地屏蔽功能的半导体装置封装结构的方法，还包含涂布一材料层，用以消除由该晶粒所产生的热能。
本发明的有益效果：
本发明的封装结构，具有较小的体积、较好的散热以及接地屏蔽效能。本发明的基板具有电路以及填充金属材料的通孔，以连接配置于基板反面上的接垫。本发明的薄型化的封装结构，且本发明提供具有高导热能力的黏着材料。本发明提供一金属层，以实现较佳的散热能力；特别是，用于高功率装置，本发明提供极优的接地屏蔽用于射频或高频装置。于较佳实施例中，本发明包括一作为天线功能的金属层。本发明提供层迭封装(PoP)的设计，利用简单的制程，以整合装置并缩小堆栈的尺寸。
附图说明
图1根据本发明的较佳实施例，为本发明封装结构的截面图。
图2根据本发明的另一较佳实施例，为本发明的封装结构的截面图。
图3根据本发明的较佳实施例，为本发明堆栈封装结构的截面图。
图4根据本发明的较佳实施例，为图1的封装结构配置于一印刷电路板上的截面图。
图5根据本发明的较佳实施例，为图3的封装结构配置于一印刷电路板上的截面图。
主要组件符号说明
100    基板
102    通孔
104    金属层
106    金属层
108    锡金属垫
110    晶粒
112    接触垫
114    黏着材料
116    介电层
118    重布层
120    保护层
122    锡球
124    锡金属垫
128    金属层
130    通孔
132    锡球
300    基板
302    锡球
304    锡球
400    基板
402    印刷电路板
404    金属垫
406    锡球
408    晶粒
410    金属层
502    印刷电路板
504    金属垫
506    锡球
508    金属层
指定代表图：
(一)本发明指定摘要代表图为：图1。
(二)本摘要代表图的组件符号简单说明：
100    基板
102    通孔
104    金属层
106    金属层
108    锡金属垫
110    晶粒
112    接触垫
114    黏着材料
116    介电层
118    重布层
120    保护层
122    锡球
具体实施方式
本发明将配合其较佳实施例与随附之图示详述于下。应可理解者为本发明中所有的较佳实施例仅为例示之用，并非用以限制。因此除文中的较佳实施例外，本发明亦可广泛地应用在其它实施例中。且本发明并不受限于任何实施例，应以随附之申请专利范围及其同等领域而定。
图1根据本发明的较佳实施例，为本发明封装结构的截面图。参照图1，一基板100提供形成于其内的通孔102。基板100最好由FR5/FR4/BT(Bismaleimide triazine)或金属/合金等材质所制成。其中通孔102为填充导电材料，例如，金属，最好为铜。一导电层，例如一金属层104，附着于基板100的一表面上；以及一导电(金属)层(第一接触垫)106形成于基板100的另一表面上。利用通孔102连接金属层104与106，以完成较佳的散热目的，特别是用于高功率装置。再者，本发明的设计亦可提供高功率装置极优的接地屏蔽效能。此外，其金属层可作为天线功能。于本发明另一较佳实施例，用以增进散热能力的材料涂布于金属层104上。锡金属垫(第二接触垫)108形成于金属层(第一接触垫)106旁，两者间具有一距离。上述的封装结构，自金属层104至锡球端点，其厚度最好约为300微米(μm)，其中锡球厚度约为0.33毫米(mm)。
具有接触垫112形成于其上的晶粒(芯片)110通过黏着材料114配置于金属层(第一接触垫)106上。在一实施例中，黏着材料114具有优良的导热能力，以利于消除由晶粒110所产生的热能。晶粒110厚度最好为20至75微米范围间。
一感光介电层116形成于晶粒110与基板100的上表面上。透过微影或曝光显影制程，形成多个开口于介电层116内。多个开口为个别地对位至接触垫(或输出/输入垫)112以及于基板100上部表面上的部份锡金属垫(第二接触垫)108。重布层(redistribution layer)118，也可称为导电布线118，通过选择性地移除部份形成于介电层116上的金属层，形成于介电层116上。其中透过输出/输入垫112，重布层118使晶粒110与锡金属垫(第二接触垫)108保持电性连接。
利用保护层120覆盖重布层118，其中保护层120的材质包括聚亚酰胺(polyimide，PI)树脂化合物、硅胶。锡球122个别形成于锡金属垫(第二接触垫)108上，用以导电。其中锡球122的高度端视其直径而定，约为0.2至0.35毫米。
图2为本发明的另一较佳实施例。参照图2，除了图2的下部金属层104分割为两个主要部份，包含锡金属垫(第二接触垫)124与金属层128外，图2的封装结构为相似于图1的实施例。通孔130形成于基板100内，并填充导电材料(例如金属或合金)至通孔130内，以保持锡金属垫(第二接触垫)108与124间的电性连接。再者，锡球132各别形成于锡球122对面的锡金属垫(第二接触垫)124上。此设计可提供堆栈结构。
图3根据本发明的实施例，为一堆栈封装设计。参照图3所示的封装结构，通过稍微修改前述图1与图2的封装结构，堆栈结构(基板)100。其封装结构共享形成于两者间的锡球。与图2相似的结构(基板)300堆栈于结构100上。锡球302两端为保持上下间电性连接。形成于结构300上的锡球304可耦合至其它组件，例如，内存装置。此结构即为层迭封装结构。
图4为图1的封装结构配置于一印刷电路板上的截面图。图1的封装结构配置于印刷电路板402上，且其印刷电路板402具有数个金属垫404形成于其上。锡球406(stage type)配置于金属垫402上，保持芯片(晶粒)408与印刷电路板402间电性连接。印刷电路板402顶部与晶粒408对面的金属层410表面间的距离约300微米。因此，形成一覆晶结构于基板400与印刷电路板402间。基板400的导电材料构成一用于芯片408的电磁屏蔽(EM shielding)。
图5为图3的封装结构配置于一印刷电路板上的截面图。图3的封装结构配置于印刷电路板502上，且其印刷电路板502具有数个金属垫504形成于其上。锡球506(stage type)配置于结构300上(如图3所示)，且黏着于金属垫504上，因此，具有颠倒架构(upside down configuration)的层迭封装结构是配置于印刷电路板502上。于本发明另一较佳实施例，可涂布增进散热能力的材料层于金属层508上。
本发明亦提供用以制造改善散热与接地屏蔽功能的半导体装置封装结构的方法。本发明的方法提供一基板(面板型)，具有预先形成的电路与接触垫以及通孔。其通孔填入导电材料，用以保持芯片与金属层间的电性连接。其金属层于随后的步骤，配置于基板的反面上。基板的材质最好为FR5/FR4/BT或金属/合金。于本发明另一较佳实施例，具有导电材料以及导电垫的另一通孔，其导电材料例如金属，填入其通孔。其导电垫，例如，金属球垫，形成于基板的通孔上，上述的导电材料与导电垫为预先形成于基板内，用以保持与导电金属垫间的电性连接。
随后，一黏着材料(具有高导热能力)系配置于基板上，而后使用取放(pick and place)设备，使芯片附着于基板的具有黏着材料的一侧；其中芯片的厚度约20至75微米。
一但晶粒重布于基板上(面板基底)，之后，通过湿及/或干清洗，执行清洗程序以清洁晶粒表面。下一步骤是涂布介电层材料于面板表面。随后，执行微影制程以打开通孔(或引洞(viahole))(接触金属垫)以及焊垫。执行电浆清洗步骤清洗引洞与焊垫的表面。下一步骤是溅镀钛/铜作为晶种金属层，而后涂布光阻于介电层与晶种金属层以形成重布层的图案。之后，使用电镀制程以形成铜/金或/铜/镍/金作为重布层金属，随后，通过去除光阻与金属湿蚀刻以形成重布层金属布线。
而后，下一步骤是涂布或印刷顶部介电层并打开接触金属垫。可重复上述步骤以形成多个重布层与介电层，例如晶种(seed)层、光阻、电镀或去除(strip)/蚀刻等等步骤。
之后，锡球是置放于锡金属接触垫上，随后通过回焊锡球使之个别附着于锡金属接触垫上。下个步骤是切割(singulate)面板以完成封装结构。应可了解「金属(metal)」可为任何导电材质、金属、合金或导电的化合物。于本发明另一较佳实施例，上述方法更包含堆栈另一封装结构于其封装结构上，以形成层迭封装结构(PoP)。
晶粒与基板(封装形式)通过表面黏着技术(SMT)结合，随后，通过附着基板的锡球以连接印刷电路板的接垫，用以形成覆晶结构于基板与印刷电路板之间；其中基板的导电材料可构成用于晶粒的电磁屏蔽。
对熟悉此领域技艺者，本发明虽以较佳实例阐明如上，然其并非用以限定本发明的精神。在不脱离本发明的精神与范围内所作的修改与类似的配置，均应包含在下述的申请专利范围内，此范围应覆盖所有类似修改与类似结构，且应做最宽广的诠释。

Claims (10)

1.一种用以改善散热与接地屏蔽功能的半导体装置封装结构，其特征在于，包含：
一基板，具有至少一第一接触垫与一通孔形成于该基板内；
一金属层，形成于该基板下部表面处，并通过该通孔耦合至该第一接触垫，用以散热与接地屏蔽；
一晶粒，具有至少一焊垫，通过一具有高导热的黏着材料附着于该第一接触垫上；
一介电层，形成于该晶粒与形成于该基板的上部表面处的一第二接触垫上；
一重布层，形成于该晶粒上方并耦合至该焊垫，用以电性连接；且
一锡球，形成于该基板的该上部表面上的该第二接触垫。
2.如权利要求1所述用以改善散热与接地屏蔽功能的半导体装置封装结构，其特征在于，还包含一保护层，形成于该重布层上；其中该保护层材质包括聚亚酰胺树脂化合物、硅胶。
3.如权利要求1所述用以改善散热与接地屏蔽功能的半导体装置封装结构，其特征在于，其中所述的该金属层的材质包括散热材料；以及该金属层可作为天线。
4.如权利要求1所述用以改善散热与接地屏蔽功能的半导体装置封装结构，其特征在于，其中所述的第二接触垫亦形成于该基板下部表面上，堆栈另一半导体装置封装结构，用以形成一层迭封装结构。
5.如权利要求1所述用以改善散热与接地屏蔽功能的半导体装置封装结构，其特征在于，其中所述基板的材质包括FR5/FR4/BT或金属/合金。
6.一种用以制造改善散热与接地屏蔽功能的半导体装置封装结构的方法，其特征在于，包含：
提供一基板，该基板具有至少一第一接触垫、一第二接触垫以及一通孔；
配置一黏着材料于具有一焊垫的晶粒背面上；附着该晶粒于该第一接触垫；
形成增层以耦合该第二接触垫与该焊垫；
通过涂布或印刷方式形成一顶部保护层于该晶粒与该基板上；
置放一锡球于该第二接触垫上；且
回焊该锡球，用以形成该锡球于该第二接触垫上。
7.如权利要求6所述用以制造改善散热与接地屏蔽功能的半导体装置封装结构的方法，其特征在于，还包含设置该晶粒与该基板，而后附着该基板的该锡球至印刷电路板的连接垫，用以形成一覆晶结构于该基板与该印刷电路板之间，其中该基板的该第一接触垫构成一用于该晶粒的电磁屏蔽。
8.如权利要求6所述用以制造改善散热与接地屏蔽功能的半导体装置封装结构的方法，其特征在于，还包含堆栈另一半导体封装结构于该半导体封装结构上，用以形成一层迭封装结构。
9.如权利要求6所述用以制造改善散热与接地屏蔽功能的半导体装置封装结构的方法，其特征在于，其中所述的基板包括FR4/FR5/BT基板或金属/合金基板；以及其中该保护层材质包括聚亚酰胺树脂化合物、硅胶。
10.如权利要求6所述用以制造改善散热与接地屏蔽功能的半导体装置封装结构的方法，其特征在于，还包含涂布一材料层，用以消除由该晶粒所产生的热能。
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