CN101211883A - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

Info

Publication number
CN101211883A
CN101211883A CNA2006101728223A CN200610172822A CN101211883A CN 101211883 A CN101211883 A CN 101211883A CN A2006101728223 A CNA2006101728223 A CN A2006101728223A CN 200610172822 A CN200610172822 A CN 200610172822A CN 101211883 A CN101211883 A CN 101211883A
Authority
CN
China
Prior art keywords
chip
those
packaging structure
bonding wires
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006101728223A
Other languages
English (en)
Inventor
邱介宏
乔永超
吴燕毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Original Assignee
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BERMUDA CHIPMOS TECHNOLOGIES Co Ltd filed Critical BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Priority to CNA2006101728223A priority Critical patent/CN101211883A/zh
Priority to US11/733,782 priority patent/US20080157304A1/en
Publication of CN101211883A publication Critical patent/CN101211883A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

本发明公开了一种芯片封装结构，包括一芯片、一导线架、多条第一焊线以及多条第二焊线。芯片具有一主动面、一背面与多个芯片焊垫，其中这些芯片焊垫配置于主动面上。导线架包括一芯片座、一绝缘层、多个转接焊垫与多个内引脚。芯片的背面是固着于芯片座上。绝缘层是配置于芯片以外的芯片座上。多个转接焊垫配置于绝缘层上。多条第一焊线分别连接这些芯片焊垫与转接焊垫。多条第二焊线分别连接这些转接焊垫与内引脚。此芯片封装结构具有较小的体积以及较高的良率。

Description

芯片封装结构
技术领域
本发明是有关于一种半导体元件及其制造方法，且特别是有关于一种芯片封装结构及其制造方法。
背景技术
在半导体产业中，集成电路(integrated circuits，IC)的生产主要可分为三个阶段：集成电路的设计(IC design)、集成电路的制作(IC process)及集成电路的封装(IC package)。
在集成电路的制作中，芯片(chip)是经由晶圆(wafer)制作、形成集成电路以及切割晶圆(wafer sawing)等步骤而完成。晶圆具有一主动面(activesurface)，其泛指晶圆的具有主动元件(active device)的表面。当晶圆内部的集成电路完成之后，晶圆的主动面还配置有多个焊垫(bonding pad)，以使最终由晶圆切割所形成的芯片可经由这些焊垫而向外电性连接于一承载器(carrier)。承载器例如为一导线架(leadframe)或一封装基板(package substrate)。芯片可以打线接合(wire bonding)或覆晶接合(flip chip bonding)的方式连接至承载器上，使得芯片的这些焊垫可电性连接于承载器的接点，以构成一芯片封装结构。
图1A是现有的一种芯片封装结构的侧视剖面示意图，而图1B是图1A的芯片封装结构的部分构件的上视示意图。请同时参考图1A与图1B，现有的芯片封装结构100包括一芯片110、一导线架120、多条第一焊线(bonding wire)130、多条第二焊线140、多条第三焊线150与一密封剂(encapsulant)160。芯片110具有一主动面112与配置于主动面112上的多个第一焊垫114与第二焊垫116。芯片110固着于导线架120下方，而导线架120包括多个内引脚(inner lead)122与一汇流架(bus bar)124。这些内引脚122与汇流架124位于芯片110的主动面112的上方或下方，且汇流架124的形状为环形。
请参考图1B，由于芯片110的第一焊垫114具有相同电位，而这些第一焊垫114例如是接地焊垫或电源焊垫，因此这些等电位的第一焊垫114可分别通过这些第一焊线130连接至汇流架124，而汇流架124再通过这些第二焊线140连接至相对应的部分内引脚122。然而，汇流架124的存在会使得整个芯片封装结构100的体积较大。此外，芯片110的作为传输信号用的第二焊垫116(例如电位随时改变的信号焊垫)必须分别通过第三焊线150连接至相对应的其他内引脚122，且这些第三焊线150通常需跨越部分第一焊线130、部分第二焊线140与汇流架124。因此，这些第三焊线150的长度较长，使得这些第三焊线150容易坍塌而造成电性短路。或者，这些第三焊线150容易在封胶时发生坍塌或被灌入的密封剂扯断而造成电性断路。
发明内容
本发明提供一种芯片封装结构，以缩小芯片封装结构的体积。
本发明提供一种芯片封装结构，以降低焊线坍塌的可能性。
为解决上述问题，本发明提出一种芯片封装结构，包括一芯片、一导线架、多条第一焊线以及多条第二焊线。芯片具有一主动面、一背面与多个芯片焊垫，其中这些芯片焊垫配置于主动面上。导线架包括一芯片座、一绝缘层、多个转接焊垫与多个内引脚。芯片的背面是固着于芯片座上。绝缘层是配置于芯片以外的芯片座上。多个转接焊垫配置于绝缘层上。多条第一焊线分别连接这些芯片焊垫与转接焊垫。多条第二焊线分别连接这些转接焊垫与内引脚。
在本发明一实施例中，上述绝缘层可为环状或是条状，配置于芯片以外之芯片座上。
在本发明一实施例中，上述绝缘层是呈一U型结构，配置于芯片以外的芯片座上。
在本发明一实施例中，此芯片封装结构还包括一密封剂，此密封剂包覆主动面、芯片座、内引脚、这些第一焊线与第二焊线。
除了上述呈环状、条状或是U型结构的绝缘层以外，也可采用多个彼此分离的绝缘垫取代上述绝缘层，这些绝缘垫同样是配置于芯片以外的芯片座上，且这些转接焊垫分别配置于这些绝缘垫上。
在本发明的芯片封装结构中，位于芯片座上的绝缘层可作为现有的导线架中的汇流架来使用，如此，即毋需于芯片座***设置一汇流架，以缩小芯片封装结构整体的体积。此外，本发明的芯片焊垫分别通过第一焊线连接至转接焊垫，而转接焊垫再通过第二焊线连接至导线架的内引脚，所以，这些第一焊线与第二焊线的长度较短。如此，即可避免焊线在封胶制程中发生坍塌或被灌入的密封剂扯断而造成电性断路的情形发生，进而提升本发明的芯片封装结构的生产良率。
为让本发明的上述特征和优点能更明显易懂，下文特举较佳实施例，并配合附图作详细说明如下。
附图说明
图1A是现有的一种芯片封装结构的侧视剖面示意图。
图1B是图1A的芯片封装结构的部分构件的上视示意图。
图2A是本发明第一实施例的一种芯片封装结构的侧视剖面示意图。
图2B是图2A的芯片封装结构的导线架的上视示意图。
图3A及3B是具有不同绝缘层形状的芯片封装结构的上视示意图。
图4是本发明第二实施例的一种芯片封装结构的上视示意图。
具体实施方式
第一实施例
图2A是本发明第一实施例的一种芯片封装结构的侧视剖面示意图，而图2B是图2A的芯片封装结构的导线架的上视示意图。请同时参考图2A及图2B，第一实施例的芯片封装结构200包括一芯片210、一导线架220、多条第一焊线230与多条第二焊线240。芯片210具有一主动面210a、一背面210b以及多个芯片焊垫212，其中这些芯片焊垫212是配置于芯片210的主动面210a上，且其可为接地焊垫、电源焊垫或信号焊垫。此外，芯片焊垫212通常是配置于芯片210的边缘处，以利于进行打线制程。
此导线架220包括一芯片座222、一绝缘层224、多个转接焊垫226以及多个内引脚228。此芯片210的背面210b可通过一黏着胶材260而固定于芯片座222的中央区域上。绝缘层224是配置于芯片210以外的芯片座222上，在此实施例中，绝缘层224是呈一环状结构，环绕于芯片210的***，且与芯片210间保持一距离，以作为现有的导线架中的汇流架来使用。而这些转接焊垫226是彼此分开地配置于绝缘层224上，以保持电性绝缘。此外，这些内引脚228是环绕于芯片座222的***。
这些第一焊线230分别连接这些芯片焊垫212与这些转接焊垫226，且这些第二焊线240分别连接这些转接焊垫226与这些内引脚228。这些第一焊线230与第二焊线240是利用打线制程而形成。此外，在此实施例中，芯片封装结构200还可选择性地形成一密封剂250。此密封剂250包覆住主动面210a、芯片座222、这些内引脚228、这些第一焊线230与这些第二焊线240，以防止上述元件受损或是受潮。
而除了图2A中所示的环状绝缘层224以外，请参考图3A所示，在此芯片封装结构200’中，绝缘层224’为两个彼此分离的条状结构，配置于芯片210以外的芯片座222上。此外，请参考图3B所示，此芯片封装结构200”中之绝缘层224”是呈一U型结构，配置于芯片210以外的芯片座222上。当然，除了图2A、3A及3B中所示的形状外，绝缘层也可具有其他型态，本发明对此不作任何限制。
第二实施例
图4是本发明第二实施例的一种芯片封装结构的上视示意图。请参考图4，此芯片封装结构200’”的结构大致上与图2A中所示的芯片封装结构200相同，而二者不同之处在于：此芯片封装结构200’”具有多个彼此分离的绝缘垫224’”，而转接焊垫226分别配置于绝缘垫224’”上。此芯片封装结构200’”的其他元件大致上与图2A中所示的芯片封装结构200相同，所以，在此不再重述。
在本发明的芯片封装结构中，是利用设置于芯片座上的绝缘层(或绝缘垫)以及转接焊垫，将现有导线架中的汇流架整合于芯片座上，以缩小芯片封装结构整体的体积。
此外，相较于现有的芯片封装结构，本发明的芯片焊垫分别通过第一焊线连接至转接焊垫，而转接焊垫再通过第二焊线连接至导线架的内引脚。换言之，这些转接焊垫分别作为这些芯片焊垫对应电性连接至这些内引脚的转接点。由于这些第一焊线与这些第二焊线的长度较短，因此，即可避免焊线在封胶制程中发生坍塌或被灌入的密封剂扯断而造成电性断路的情形发生，进而提升本发明的芯片封装结构的生产良率。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许更动与润饰，因此本发明的保护范围当以权利要求所界定的为准。

Claims (7)

1.一种芯片封装结构，包括：
一芯片，具有一主动面、一背面与多个芯片焊垫，其中该些芯片焊垫配置于该主动面上；
一导线架，包括：
一芯片座，该芯片的该背面是固着于该芯片座上；
一绝缘层，配置于该芯片以外的该芯片座上；
多个转接焊垫，配置于该绝缘层上；以及
多个内引脚；
多条第一焊线，分别连接该些芯片焊垫与该些转接焊垫；以及
多条第二焊线，分别连接该些转接焊垫与该些内引脚。
2.如权利要求1所述的芯片封装结构，其特征在于，该绝缘层为环状，配置于该芯片以外的该芯片座上。
3.如权利要求1所述的芯片封装结构，其特征在于，该绝缘层为条状，配置于该芯片以外的该芯片座上。
4.如权利要求1所述的芯片封装结构，其特征在于，该绝缘层是呈一U型结构，配置于该芯片以外的该芯片座上。
5.如权利要求1所述的芯片封装结构，其特征在于，还包括一密封剂，该密封剂包覆该主动面、该芯片座、该些内引脚、该些第一焊线与该些第二焊线。
6.一种芯片封装结构，包括：
一芯片，具有一主动面、一背面与多个芯片焊垫，其中该些芯片焊垫配置于该主动面上；
一导线架，包括：
一芯片座，该芯片的该背面是固着于该芯片座上；
多个彼此分离的绝缘垫，配置于该芯片以外的该芯片座上；
多个转接焊垫，分别配置于该些绝缘垫上；以及
多个内引脚；
多条第一焊线，分别连接该些芯片焊垫与该些转接焊垫；以及
多条第二焊线，分别连接该些转接焊垫与该些内引脚。
7.如权利要求6所述的芯片封装结构，其特征在于，还包括一密封剂，该密封剂包覆该主动面、该芯片座、该些内引脚、该些第一焊线与该些第二焊线。
CNA2006101728223A 2006-12-29 2006-12-29 芯片封装结构 Pending CN101211883A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CNA2006101728223A CN101211883A (zh) 2006-12-29 2006-12-29 芯片封装结构
US11/733,782 US20080157304A1 (en) 2006-12-29 2007-04-11 Chip package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA2006101728223A CN101211883A (zh) 2006-12-29 2006-12-29 芯片封装结构

Publications (1)

Publication Number Publication Date
CN101211883A true CN101211883A (zh) 2008-07-02

Family

ID=39582694

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006101728223A Pending CN101211883A (zh) 2006-12-29 2006-12-29 芯片封装结构

Country Status (2)

Country Link
US (1) US20080157304A1 (zh)
CN (1) CN101211883A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103828041A (zh) * 2011-09-29 2014-05-28 夏普株式会社 半导体装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI358815B (en) * 2006-09-12 2012-02-21 Chipmos Technologies Inc Stacked chip package structure with lead-frame hav

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3347651B2 (ja) * 1997-09-17 2002-11-20 株式会社巴川製紙所 電子部品用接着テープ
CN101241890B (zh) * 2007-02-06 2012-05-23 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103828041A (zh) * 2011-09-29 2014-05-28 夏普株式会社 半导体装置
CN103828041B (zh) * 2011-09-29 2016-07-06 夏普株式会社 半导体装置

Also Published As

Publication number Publication date
US20080157304A1 (en) 2008-07-03

Similar Documents

Publication Publication Date Title
CN101814480B (zh) 一种芯片封装结构及其封装方法
CN101114628B (zh) 半导体器件及其制造方法
CN100524739C (zh) 半导体器件及其制造方法
WO2007026392A1 (ja) 半導体装置およびその製造方法
CN101373761B (zh) 多芯片模块封装件
CN1574323B (zh) 半导体器件
CN102237343A (zh) 用连接片实现连接的半导体封装及其制造方法
CN102044449A (zh) 半导体封装和制造半导体封装的方法
CN103050467A (zh) 封装结构及其制造方法
CN103426837A (zh) 半导体封装及形成半导体封装的方法
TWI226122B (en) Multi-chip package with electrical interconnection
CN101131978A (zh) 集成电路封装构造及其使用的多层导线架
CN103337486B (zh) 半导体封装构造及其制造方法
CN101211883A (zh) 芯片封装结构
CN101266958A (zh) 晶片封装结构
US20080006917A1 (en) Chip package structure and fabricating method threrof
US20070267756A1 (en) Integrated circuit package and multi-layer lead frame utilized
CN101894830B (zh) 堆叠式封装构造及其制造方法
CN101127332A (zh) 晶片上引脚球格阵列封装构造
JP2007141947A (ja) 半導体装置およびその製造方法
CN100470782C (zh) 芯片封装结构
CN100463156C (zh) 晶片封装结构及其制造方法
US20080038872A1 (en) Method of manufacturing semiconductor device
CN100477198C (zh) 芯片封装结构及其制造方法
JP4658987B2 (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication