CN101266958A - 晶片封装结构 - Google Patents

晶片封装结构 Download PDF

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CN101266958A
CN101266958A CNA2007100876735A CN200710087673A CN101266958A CN 101266958 A CN101266958 A CN 101266958A CN A2007100876735 A CNA2007100876735 A CN A2007100876735A CN 200710087673 A CN200710087673 A CN 200710087673A CN 101266958 A CN101266958 A CN 101266958A
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package structure
substrate
chip package
conductive
wafer
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吴燕毅
乔永超
邱介宏
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
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Priority to US11/739,696 priority patent/US20080224284A1/en
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Abstract

本发明公开了一种晶片封装结构，其主要包括一基板、一晶片以及一导线架。此晶片是配置于基板上，且通过打线接合或是覆晶接合技术与基板电性连接。此晶片是且通过基板上的重配置线路层与导线架电性连接，如此，即可解决现有技术中当晶片尺寸缩小时，用以电性连接晶片与导线架的内引脚之间的打线导线的长度需要增长，所会遭遇到的打线导线易坍塌的问题，以提升其制作上的良率。

Description

晶片封装结构
技术领域
本发明是有关于一种半导体元件，且特别是有关于一种晶片封装结构。
背景技术
在半导体产业中，集成电路(integrated circuits，IC)的生产主要可分为三个阶段：集成电路的设计(IC design)、集成电路的制作(IC process)及集成电路的封装(IC package)。在集成电路的制作中，晶片(die)是经由晶圆(wafer)制作、形成集成电路以及切割晶圆(wafer sawing)等步骤而完成。晶圆具有一主动面(active surface)，其泛指晶圆的具有主动元件(activedevice)的表面。在晶圆的集成电路完成之后，晶圆的主动面更配置有多个接垫(bonding pad)，以使最终由晶圆切割所形成的晶片，可经由这些接垫而向外电性连接于一承载器(carrier)。承载器例如为一导线架(leadframe)或一封装基板(package substrate)，而晶片可以打线接合(wire bonding)或覆晶接合(flip chip bonding)的方式连接至承载器上，使得晶片的这些接垫可分别电性连接于承载器的多个接点，以构成一晶片封装体。
就打线接合技术(wire bonding technology)而言，以往对于较低脚数的IC封装，主要采用的都是以导线架为主体的封装。在经过晶圆切割、黏晶(diebonding)、打线接合、封胶(molding)与剪切成型(trimming/forming)等主要步骤后，传统以导线架为主体的晶片封装体即可大致完成。
在现今电子产品追求轻薄短小的趋势下，晶片的尺寸也需朝向小型化的方向发展。在晶片尺寸变小的状况下，若继续延用先前的导线架以进行晶片封装时，会发现晶片与导线架的内引脚之间的距离变长了，相对而言，用以电性连接晶片与导线架的内引脚之间的打线导线的长度需要随之增长。然而，当打线导线之长度加长及其弧度加大时，打线导线易因坍塌而造成电性短路，且容易在封胶时被灌入的胶体扯断而造成电性断路，如此，皆会降低晶片封装结构的良率。然而，若要重新开模以制作出适用于小型化晶片的导线架，则会增加整体的制作成本。
发明内容
本发明所要解决的问题是提供一种晶片封装结构，此封装结构是将一晶片配置于一基板上，且与基板电性连接。此基板上配置有一重配置线路层，使晶片可通过此重配置线路层而与一导线架电性连接，如此，以解决小型化晶片在利用导线架进行封装时，所遭遇到的良率降低或是制作成本增加的问题。
为解决上述问题，本发明提出一种晶片封装结构，包括一基板、一晶片、多条打线导线以及多个导线架引脚。基板的一表面具有一重配置线路层，且此重配置线路层具有多条重配置导电迹线。晶片具有一主动面、一背面与多个配置于主动面上的晶片焊垫，其中晶片的背面是固着于基板的表面上。这些打线导线分别电性连接上述的晶片焊垫与重配置导电迹线的一端。这些导线架引脚是配置于基板的表面上，且至少部分的导线架引脚与相对应的重配置导电迹线的另一端电性连接，使晶片的这些晶片焊垫通过打线导线以及重配置线路层而与导线架引脚电性连接。
在上述的晶片封装结构中，这些导线架引脚分别具有一内引脚，且这些内引脚是位于晶片的外侧。
在上述的晶片封装结构中，至少部分的内引脚分别与相对应的重配置导电迹线的另一端电性连接。
在上述的晶片封装结构中，重配置线路层还包括多个第一接垫与多个第二接垫，各第一接垫配置于相对应的重配置导电迹线的一端，而各第二接垫配置于相对应的重配置导电迹线的另一端。
在上述的晶片封装结构中，这些打线导线分别连接于上述晶片焊垫与第一接垫。
在上述的晶片封装结构中，基板还包括多个导电层，这些导电层分别配置于第二接垫上，使基板的重配置线路层通过这些导电层与这些内引脚电性连接。
在上述的晶片封装结构中，各导电层是由一导电胶或是一导电凸块所组成。
在上述的晶片封装结构中，此导电胶包括银胶、异方性导电胶、异方性导电膜或是导电型B阶胶。
在上述的晶片封装结构中，这些导电凸块的材料包括焊料、金、铜、铝、镍或是导电型B阶材质的凸块。
在上述的晶片封装结构中，此晶片封装结构还包括一胶体，此胶体包覆晶片、这些打线导线、导线架引脚以及部分的基板。
晶片除可通过打线方式与基板电性连接之外，其也可利用覆晶接合的方式与基板电性连接。由于其结构与上述的晶片封装结构相似，只是晶片与基板电性连接的方式稍有不同，所以，在此不再重述。
本发明的晶片封装结构是先将小型化的晶片配置于基板上，再通过基板上的重配置线路层与导线架电性连接。如此，即可避免现有技术中当晶片尺寸缩小时，用以电性连接晶片与导线架的内引脚之间的打线导线的长度需要随之增长，而衍生的打线导线易坍塌，或是在封胶时被灌入的胶体扯断而造成电性断路等问题，以提升其制作上的良率。此外，由于本发明是利用重配置线路层将接垫位置依据接合方式进行重配置，因此，可适用于高脚数的导线架。
附图说明
为让本发明的上述目的、特征和优点能更明显易懂，以下结合附图对本发明的具体实施方式作详细说明，其中：
图1A是根据本发明的第一实施例的一种晶片封装结构的俯视示意图。
图1B是沿着图1A中所示的晶片封装结构的I-I’剖面线的剖面示意图。
图2是根据本发明的另一实施例的一种晶片封装结构的剖面示意图。
具体实施方式
图1A是根据本发明的第一实施例的一种晶片封装结构的俯视示意图；图1B是沿着图1A中所示的晶片封装结构的I-I’剖面线的剖面示意图。请参考图1A及图1B，此晶片封装结构100主要包括一基板110、一晶片120、多条打线导线130以及多个导线架引脚140。基板110的上表面110a具有一重配置线路层112，此重配置线路层112具有多个第一接垫112a、多条重配置导电迹线112b以及多个第二接垫112c，且第一接垫112a与第二接垫112c分别配置于重配置导电迹线112b的两端。
晶片120具有一主动面120a、一背面120b与多个配置于主动面120a上的晶片焊垫122。此晶片120的背面120b可通过一粘着胶材(图中未示)而固着于基板10的上表面110a上。多条以打线接合技术形成的打线导线130分别电性连接晶片120上的晶片焊垫122与重配置线路层112的第一接垫112a，使晶片120通过这些打线导线130与基板110电性连接。
多个导线架引脚140配置于基板110的上表面110a上。此导线架引脚140具有多个环绕于晶片120外侧的内引脚142，且这些内引脚142分别与重配置线路层112的第二接垫112c电性连接，也就是说，在这些内引脚142中，可以是至少一部份内引脚分别与重配置线路层112的第二接垫112c电性连接。如此，晶片120的晶片焊垫122即可通过打线导线130以及重配置线路层112而与这些内引脚142电性连接。在此实施例中，导线架引脚140是通过配置于基板110的第二接垫112c上的导电层114而与第二接垫112c电性连接。更进一步而言，导电层114可为导电凸块、导电胶，或者是结合导电胶与导电凸块。其中，导电凸块的材质可为焊料、金、铜、镍、铝或者是导电型B阶材质的凸块。而导电胶可为银胶、异方性导电胶、异方性导电膜或导电型B阶胶等。然而，导线架引脚140也可通过其他方式与基板110电性连接，例如是打线导线等，本发明对此不作任何限制。
此外，晶片封装结构100还包括一胶体150，此胶体150覆盖晶片120、打线导线130、导线架引脚140以及至少一部分的基板110，以保护基板110、晶片120、打线导线130以及导线架引脚140免于受损及受潮。在其他(未绘示)的实施例当中，胶体150也能够完全覆盖基板110。
图2是根据本发明的另一实施例的一种晶片封装结构的剖面示意图。请参考图2，此晶片封装结构100’大致上与图1B中所示的晶片封装结构100相同，而二者不同之处在于：晶片120是通过覆晶接合技术与基板110电性连接，在此实施例中，晶片120是通过配置于第一接垫112a上的导电凸块116与基板110电性连接。本实施例的导电凸块116的材质例如可以是焊料、金、铜、镍、铝或者是导电型B阶材质的凸块。此晶片封装结构100’的其他元件与图1B中所示的元件相同，所以，在此不再重述。
综上所述，本发明的晶片封装结构是先将小型化的晶片配置于基板上，并与基板电性连接，之后，再通过基板上的重配置线路层与导线架电性连接。如此，即可避免现有技术中当晶片尺寸缩小时，用以电性连接晶片与导线架的内引脚之间的打线导线的长度需要随之增长，而衍生的打线导线易坍塌，或是在封胶时被灌入的胶体扯断而造成电性断路等问题，以提升其制作上的良率。此外，由于本发明是利用重配置线路层将接垫位置依据接合方式进行重配置，因此，可适用于高脚数的导线架。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当以所附的权利要求书所界定的为准。

Claims (14)

1. 一种晶片封装结构，其特征在于，包括：
一基板，该基板的一表面具有一重配置线路层，其中该重配置线路层具有多条重配置导电迹线；
一晶片，具有一主动面、一背面与多个配置于该主动面上的晶片焊垫，其中该晶片的背面固着于所述基板的表面上；
多条打线导线，分别电性连接所述晶片焊垫与所述重配置导电迹线的一端；以及
多个导线架引脚，配置于所述基板的表面上，其中至少部分的导线架引脚与相对应的所述重配置导电迹线的另一端电性连接。
2. 如权利要求1所述的晶片封装结构，其特征在于，所述导线架引脚分别具有一内引脚，且所述内引脚是位于所述晶片的外侧。
3. 如权利要求2所述的晶片封装结构，其特征在于，至少部分的所述内引脚分别与相对应的所述重配置导电迹线的另一端电性连接。
4. 如权利要求1所述的晶片封装结构，其特征在于，所述重配置线路层还包括多数个第一接垫与多数个第二接垫，各第一接垫配置于相对应的所述重配置导电迹线的一端，而各第二接垫配置于相对应的所述重配置导电迹线的另一端。
5. 如权利要求4所述的晶片封装结构，其特征在于，所述打线导线分别连接于所述晶片焊垫与所述第一接垫。
6. 如权利要求4所述的晶片封装结构，其特征在于，所述基板还包括多数个导电层，分别配置于所述第二接垫上，使所述基板的所述重配置线路层通过所述导电层与所述内引脚电性连接。
7. 如权利要求6所述的晶片封装结构，其特征在于，各所述导电层是由一导电胶或是一导电凸块所组成。
8. 如权利要求1所述的晶片封装结构，其特征在于，还包括一胶体，所述胶体覆盖所述晶片、所述打线导线、所述导线架引脚以及至少部份的所述基板。
9. 一种晶片封装结构，其特征在于，包括：
一基板，该基板的一表面具有一重配置线路层，其中该重配置线路层具有多条重配置导电迹线；
一晶片，具有一主动面、一背面与多个配置于该主动面上的导电凸块，其中所述导电凸块分别与所述重配置导电迹线的一端电性连接；以及
多个导线架引脚，配置于所述基板的所述表面上，其中各导线架引脚分别具有一内引脚，且所述内引脚分别与所述重配置导电迹线的另一端电性连接。
10. 如权利要求9所述的晶片封装结构，其特征在于，所述重配置线路层还包括多数个第一接垫与多数个第二接垫，各第一接垫配置于相对应的所述重配置导电迹线的一端，而各第二接垫配置于相对应的所述重配置导电迹线的另一端。
11. 如权利要求9所述的晶片封装结构，其特征在于，所述导电凸块是通过覆晶接合的方式分别与所述第一接垫电性连接。
12. 如权利要求9所述的晶片封装结构，其特征在于，所述基板还包括多数个导电层，分别配置于所述第二接垫上，使所述基板的所述重配置线路层通过所述导电层与所述内引脚电性连接。
13. 如权利要求12所述的晶片封装结构，其特征在于，各所述导电层为一导电胶或者是一导电凸块。
14. 如权利要求9所述的晶片封装结构，其特征在于，还包括一胶体，所述胶体包覆所述晶片、所述导线架以及至少部份的所述基板。
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CN103515328A (zh) * 2012-06-29 2014-01-15 三星电机株式会社 半导体封装件
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CN103178034B (zh) * 2011-12-21 2015-09-16 矽品精密工业股份有限公司 封装件结构、封装基板结构及其制法
CN103515328A (zh) * 2012-06-29 2014-01-15 三星电机株式会社 半导体封装件
CN105493279A (zh) * 2013-09-04 2016-04-13 奥斯兰姆施尔凡尼亚公司 用于将器件附接到柔性衬底的***
CN110993579A (zh) * 2019-11-25 2020-04-10 南京矽力杰半导体技术有限公司 电源模块的封装结构

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