CN103426837A - 半导体封装及形成半导体封装的方法 - Google Patents
半导体封装及形成半导体封装的方法 Download PDFInfo
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Abstract
本发明公开了一种半导体封装及形成半导体封装的方法。在一个实施方式中,一种半导体封装包括竖直半导体芯片,该竖直半导体芯片具有位于竖直半导体芯片的一侧上的第一主表面以及位于竖直半导体芯片的相对侧上的第二主表面。第一主表面包括第一接触区,并且第二主表面包括第二接触区。竖直半导体芯片构造为调节沿电流方向从第一接触区到第二接触区的电流。在第二主表面的第二接触区处设置有背面导体。半导体封装进一步包括第一密封剂,在该第一密封剂中设置有竖直半导体芯片和背面导体。
Description
技术领域
本发明总体上涉及半导体装置,更特别地,涉及半导体封装及形成半导体封装的方法。
背景技术
在许多电子和其他应用中使用半导体装置。其中,半导体装置包括集成电路或分立器件,这些集成电路或分立器件通过在半导体晶片之上沉积一种或多种类型的材料的薄膜并使该材料的薄膜图案化以形成集成电路而形成于半导体晶片上。
典型地,将半导体装置封装在陶瓷或塑料本体内,以保护半导体装置免受物理损坏或腐蚀。该封装还支撑将半导体装置(也被叫做晶粒(die,裸片)或芯片)与封装外部的其他装置连接所需的电接触件(contact)。根据半导体装置的类型和所封装的半导体装置的预期用途,可使用许多不同类型的封装。其中,典型的封装特征(例如,封装的尺寸,引脚数量,等等)可遵照电子元件工业联合会(JEDEC)的开放标准。封装还可被叫做半导体装置组件,或简单地叫做组件。
由于在保护这些电连接和下面的芯片或多个芯片的同时将多个电连接与外部衬垫连接的复杂性,因而封装可能是一个高成本的工序。
发明内容
通过以下讨论的本发明的说明性实施方式,总体上解决或规避这些和其他问题,并总体上实现技术优点。
根据本发明的一个实施方式,一种半导体封装包括竖直半导体芯片,该竖直半导体芯片具有位于竖直半导体芯片的一侧上的第一主表面以及位于竖直半导体芯片的相对侧上的第二主表面。第一主表面包括第一接触区,并且第二主表面包括第二接触区。竖直半导体芯片构造为调节沿电流方向从第一接触区到第二接触区的电流。在第二主表面的第二接触区处设置有背面导体。半导体封装进一步包括第一密封剂,在该第一密封剂中设置有竖直半导体芯片和背面导体。
根据本发明的一个实施方式,一种形成半导体封装的方法包括将竖直半导体芯片放置在载体上。该竖直半导体芯片具有位于竖直半导体芯片的正面上的有源区以及位于竖直半导体芯片的背面上的有源区。竖直半导体芯片的正面面向载体。将竖直半导体芯片构造为,调节从竖直半导体芯片的正面到竖直半导体芯片的背面的电流。该方法进一步包括通过在竖直半导体芯片和载体上施加第一密封剂来形成重组晶片。该重组晶片具有第一主表面,该第一主表面与竖直半导体芯片的正面共面。该方法进一步包括使重组晶片与载体分离,从而露出第一主表面,并使重组晶片从与第一主表面相对的一侧开始变薄,以形成重组晶片的第二主表面。使竖直半导体芯片相对于第一密封剂从第二主表面开始选择性地变薄,以露出位于至少一个竖直半导体芯片的背面上的有源区的表面。在位于竖直半导体芯片的背面上的有源区的露出表面上形成背面导体。该方法包括用第二密封剂封装第一密封剂、竖直半导体芯片和背面导体。
以上已经宽泛地略述了本发明的一个实施方式的各种特征,以便可更好地理解本发明的以下给出的详细描述。在下文中将描述本发明的各种实施方式的附加特征和优点,这些实施方式形成本发明的权利要求的主题。本领域的技术人员应理解的是,可容易地将所公开的概念和特定实施方式用作改进或设计用于执行本发明的相同目的的其他结构或工序的基础。本领域的技术人员还应认识到,这种等同结构没有背离如在下述权利要求中阐述的本发明的实质和范围。
附图说明
为了更全面地理解本发明及其优点,现在结合附图参考以下描述,其中:
图1(其包括图1A至图1C)示出了根据本发明的一个实施方式的半导体封装,其中,图1A示出了横截面图,图1B示出了顶部截面图,图1C示出了底视图;
图2示出了根据本发明的一个实施方式的在将切割的晶粒放置在载体上之后的制造过程中的半导体封装;
图3示出了根据本发明的一个实施方式的在形成重组晶片之后的制造过程中的半导体封装;
图4示出了根据本发明的一个实施方式的在使重组晶片与载体分离之后的制造过程中的半导体封装;
图5(其包括图5A至图5C)示出了根据本发明的一个实施方式的制造过程中的半导体封装的放大图,其示出了正面金属化,其中,图5A和图5C示出了横截面图,图5B示出了顶部截面图;
图6(其包括图6A和图6B)示出了根据本发明的一个实施方式的在形成正面重新分布层之后的制造过程中的半导体封装的放大图,其中,图6A示出了横截面图,图6B示出了顶部截面图;
图7(其包括图7A和图7B)示出了根据本发明的一个实施方式的在使重组晶片变薄之后的制造过程中的半导体封装的放大图,其中,图7A示出了横截面图,图7B示出了顶部截面图;
图8(其包括图8A至图8C)示出了根据本发明的一个实施方式的在使竖直半导体芯片进一步变薄之后的制造过程中的半导体封装的放大图,其中,图8A示出了横截面图,图8B示出了顶部截面图,图8C示出了一个可替代实施方式,其示出了另一放大的横截面图;
图9(其包括图9A和图9B)示出了根据本发明的一个实施方式的在竖直半导体芯片下方形成背面导体之后的制造过程中的半导体封装的放大图,其中,图9A示出了横截面图,图9B示出了顶部截面图;
图10(其包括图10A和图10B)示出了根据本发明的实施方式而形成的引线框架半导体封装;
图11至图12示出了半导体封装的一个可替代结构实施方式及其形成方法;
图13(其包括图13A至图13E)示出了一个可替代实施方式,其中,在变薄工艺之后形成前背面重新分布层;
图14(其包括图14A和图14B)示出了制造半导体封装的一个可替代实施方式,其中,在形成背面导体之前形成金属衬垫;
图15示出了根据本发明的一个可替代实施方式的将半导体封装安装在电路板上;
图16(其包括图16A和图16B)示出了根据本发明的一个实施方式的具有一个以上的竖直半导体芯片的半导体封装;
图17(其包括图17A和图17B)示出了根据本发明的一个实施方式的在一个芯片中具有一个以上的晶体管的半导体封装;
图18示出了根据本发明的一个实施方式的具有一个以上的竖直半导体装置和逻辑电路的半导体封装。
不同附图中的相应数字和符号通常指的是相应的部件,除非另有指明。将附图绘制为清楚地示出实施方式的相关方面,而并非必须按比例绘制。
具体实施方式
下面详细地讨论了各种实施方式的制造和使用。然而,应理解的是,本发明提供了可在许多上下文中体现的许多可应用的发明构思。所讨论的特定实施方式仅说明了制造和使用本发明的特殊方式,并不限制本发明的范围。
功率半导体晶粒具有特殊需求(例如,由于高电压和高发热的原因)并需要良好的热管理。因此,对功率半导体装置的封装在对制造成本非常敏感的同时具有增加的性能需求。如下面将描述的,本发明的各种实施方式使得能够以低成本形成具有改进性能的用于功率半导体封装的封装。
与传统的用于竖直半导体装置的封装相比,本发明的实施方式具有许多优点。例如,本发明的实施方式使得能够形成超薄芯片,例如,比大约60μm更薄的芯片,而没有机械稳定性问题。此外显著减小机械和热机械应力。本发明的实施方式有利地去耦了超薄芯片和壳体/密封剂之间的应力。本发明的实施方式提供了形成与超薄芯片的接触件和重新布线(例如,重新分布线路)而没有机械和其他问题的方法。本发明的实施方式减小了热阻和电阻,从而改进装置的性能。本发明的实施方式减小了制造工艺步骤的数量,从而降低了与封装相关的成本。类似地,在各种实施方式中并行地制造许多封装,这进一步降低了生产成本。
将利用图1描述本发明的结构实施方式。将利用图10、图12、图13、图14、图15、图16、图17和图18描述其他结构实施方式。将利用图2至图10描述一种形成半导体封装的方法。将利用图11至图12、图13和图14描述制造该封装的其他实施方式。
图1(其包括图1A至图1C)示出了根据本发明的一个实施方式的半导体封装,其中,图1A示出了横截面图,图1B示出了顶部截面图,图1C示出了底视图。
参考图1A,竖直半导体芯片20设置在密封剂50中。在各种实施方式中,竖直半导体芯片20由于竖直电流(例如,从顶部表面11到底部表面12)的原因而是竖直半导体装置。因此,竖直半导体芯片20具有位于顶部表面11和底部表面12上的接触区。
在各种实施方式中,竖直半导体芯片20可形成在硅衬底上。或者,在其他实施方式中,竖直半导体芯片20可以是形成于碳化硅(SiC)上的装置。在一个实施方式中,竖直半导体芯片20是至少部分地形成于氮化镓(GaN)上的装置。
在各种实施方式中,竖直半导体芯片20包括功率半导体装置,在一个实施方式中,该功率半导体装置可以是分立器件。在一个实施方式中,竖直半导体芯片20是两端装置,例如,PIN二极管或肖特基二极管。在一个或多个实施方式中,竖直半导体芯片20是三端装置,例如,功率金属绝缘体半导体场效应晶体管(MISFET)、结型场效应晶体管(JFET)、双极型晶体管(BJT)、绝缘栅双极型晶体管(IGBT)或晶闸管。
在各种实施方式中,竖直半导体芯片20构造为,在大约20V至大约1000V下工作。在一个实施方式中,竖直半导体芯片20构造为,在大约20V至大约100V下工作。在另一实施方式中,竖直半导体芯片20构造为,在大约100V至大约500V下工作。在又一实施方式中,竖直半导体芯片20构造为,在大约500V至大约1000V下工作。在一个实施方式中,竖直半导体芯片20是NPN晶体管。在另一实施方式中,竖直半导体芯片20是PNP晶体管。在又一实施方式中,竖直半导体芯片20是n沟道MISFET。在另一实施方式中,竖直半导体芯片20是p沟道MISFET。在一个或多个实施方式中,竖直半导体芯片20可包括多个装置,例如,竖直MISFET和二极管,或者,由绝缘区分开的两个MISFET装置。
在各种实施方式中,竖直半导体芯片20从顶部表面11到底部表面12的厚度可小于50μm。在各种实施方式中,竖直半导体芯片20从顶部表面11到底部表面12的厚度可小于20μm。在各种实施方式中,竖直半导体芯片20从顶部表面11到底部表面12的厚度可小于10μm。
在各种实施方式中,竖直半导体芯片20从顶部表面11到底部表面12的厚度可以是大约5μm至大约50μm。在一个实施方式中,竖直半导体芯片20从顶部表面11到底部表面12的厚度可以是大约1μm至大约10μm。在另一实施方式中,竖直半导体芯片20从顶部表面11到底部表面12的厚度可以是大约0.5μm至大约5μm。在又一实施方式中,竖直半导体芯片20从顶部表面11到底部表面12的厚度可以是大约1μm至大约2.5μm。小于10μm的厚度可有利地将电阻率减到最小并改进导热率,以在有效地去除在工作过程中在竖直半导体芯片20内产生的热的同时便于提高电性能。
在各种实施方式中,密封剂50包括介质材料,并且,在一个实施方式中,可包括模塑化合物。在其他实施方式中,密封剂50可包括以下材料中的一种或多种:聚合物、共聚物、生物聚合物、纤维浸渍聚合物(例如,树脂中的碳纤维或玻璃纤维)、颗粒填充聚合物以及其他有机材料。在一个或多个实施方式中,密封剂50包括并非用模塑化合物以及诸如环氧树脂和/或硅树脂的材料形成的密封剂。在各种实施方式中,密封剂50可由任何适当的硬质塑料、热塑性塑料、热固性材料或层压材料制成。在一些实施方式中,密封剂50的材料可包括填充材料。在一个实施方式中,密封剂50可包括环氧材料和填充材料,该填充材料包括玻璃或其他电绝缘矿物填充材料(例如氧化铝或有机填充材料)的小颗粒。
在一个或多个实施方式中,竖直半导体芯片20是分立的三端功率半导体装置。在一个实施方式中,竖直半导体芯片20是具有源极、栅极和漏极的三端晶体管。在一个实施方式中,源极和栅极形成在顶部表面11附近,而漏极形成在背面表面12附近。
在源极和栅极形成在顶部表面11附近并且漏极形成在背面表面12附近的实施方式中,顶部表面11具有源极接触区110和栅极接触区120,而背面表面12具有漏极接触区130。在一个实施方式中,源极接触区110、栅极接触区120和漏极接触区130可包括硅化物区。
如图1A和图1B所示,(通过栅极接触区120)与栅极耦接的栅极接触件220和(通过源极接触区110)与源极耦接的源极接触件210设置在竖直半导体芯片20的顶部表面之上。类似地,背面接触件320设置在竖直半导体芯片20的漏极上。在各种实施方式中,可通过设置于竖直半导体芯片20的顶部表面和底部表面上的硅化物区来使栅极接触件220、源极接触件210和背面接触件320耦接。
如图1B所示,源极接触件210通过多个导电线路250a与源极衬垫230耦接,并且栅极接触件230通过多个导电线路250b与栅极衬垫240耦接。因此,半导体封装是扇出封装,因为封装尺寸比竖直半导体芯片20的尺寸大。有利地,将衬垫放置在远离源极接触件210和栅极接触件220的地方避免了损坏竖直半导体芯片20,例如,在测试过程中。
如在图1A和图1B中进一步示出的,互连件280a和280b可使一个或多个正面接触衬垫与背面上的一个或多个接触衬垫耦接。在一个或多个实施方式中,可分别使用中间层265a和265b连接互连件280a和280b,所述中间层可以是用于焊接的层或导电粘合浆料。或者,可使用薄膜或带子。在各种实施方式中,互连件280a和280b可以是任何适当类型的互连件,并可包括夹具、焊线、夹子、条、带、电流带,等等。
如图1A和图1C所示,密封剂50设置在外密封剂450中。在一个实施方式中,密封剂50和外密封剂450包括相同的材料。在可替代实施方式中,密封剂50和外密封剂450包括不同的材料。在各种实施方式中,外密封剂450包括介质材料,并且,在一个实施方式中,可包括模塑化合物。在其他实施方式中,外密封剂450可包括以下材料中的一种或多种:聚合物、共聚物、生物聚合物、纤维浸渍聚合物(例如,树脂中的碳纤维或玻璃纤维)、颗粒填充聚合物以及其他有机材料。在一个或多个实施方式中,外密封剂450包括并非用模塑化合物以及诸如环氧树脂和/或硅树脂的材料形成的密封剂。在各种实施方式中,外密封剂50可由任何适当的硬质塑料、热塑性塑料、热固性材料或层压材料制成。在一些实施方式中,外密封剂450的材料可包括填充材料。在一个实施方式中,密封剂50可包括环氧材料和填充材料,该填充材料包括玻璃或其他电绝缘矿物填充材料(例如氧化铝或有机填充材料)的小颗粒。在各种实施方式中,即使密封剂50和外密封剂450包括相同的材料,它们也由于在不同的工艺步骤中形成而具有不同的界面。
参考图1C,半导体封装的表面可包括用于接触封装上的装置的衬垫或引线。如在图1C中的底视图中示出的,可焊的漏极衬垫260可形成在背面接触件320下方。源极输入/输出(I/O)290形成在封装的背面上,并与源极衬垫230耦接。类似地,栅极I/O270形成在封装的背面上并与栅极衬垫240耦接(也见图1A)。
图2至图10示出了根据本发明的实施方式的各种加工阶段过程中的半导体封装。
图2示出了根据本发明的一个实施方式的在将切割的晶粒放置在载体上之后的制造过程中的半导体封装。
参考图2,将多个竖直半导体芯片20放置在载体10之上。在各种实施方式中,将多个竖直半导体芯片20的具有有源区的表面放置在载体10之上,如图2所示。
多个竖直半导体芯片20可利用传统的加工形成,例如,在晶片内,进行切割以形成多个竖直半导体芯片20。如上所述,多个竖直半导体芯片20可形成在硅衬底(例如,大块硅衬底或绝缘体上硅(SOI)衬底)上。或者,竖直半导体芯片20可以是形成于碳化硅(SiC)上的装置。本发明的实施方式还可包括形成于化合物半导体衬底上的装置,并可包括异质外延衬底上的装置。在一个实施方式中,竖直半导体芯片20是至少部分地形成于氮化镓(GaN)上的装置,该氮化镓可以是蓝宝石或硅衬底上的GaN。
接下来,将多个竖直半导体芯片20附接至载体10,这在加工过程中提供机械支撑和稳定性。在各种实施方式中,载体10可以是由刚性材料(例如,诸如镍、钢或不锈钢的金属、层压材料,薄膜、或材料叠层)制成的板。载体10可具有至少一个平面,可将多个竖直半导体芯片20放置在该平面上。在一个或多个实施方式中,载体10可是圆形或方形形状,尽管在各种实施方式中载体10可是任何适当的形状。在各种实施方式中,载体10可具有任何适当的尺寸。在一些实施方式中,载体10可包括胶带,例如,层压在载体10上的双面胶带。载体10可包括框架,在一个实施方式中该框架是具有粘合箔的环形结构(环形)。在一个或多个实施方式中,可通过框架沿着外边缘支撑粘合箔。
在各种实施方式中,可使用粘合层30附接多个竖直半导体芯片20。在各种实施方式中,粘合层30可包括胶水或其他粘合类型的材料。在各种实施方式中,粘合层30可以是薄的,例如,在一个实施方式中小于大约100μm,在另一实施方式中处于1μm至大约50μm之间。
在各种实施方式中,多个竖直半导体芯片20可包括功率芯片,这些功率芯片例如吸取大电流(例如,大于30安培)。在各种实施方式中,多个竖直半导体芯片20可包括分立竖直器件,例如,两端或三端功率装置。竖直半导体芯片20的实例包括PIN或肖特基二极管、MISFET、JFET、BJT、IGBT或晶闸管。
图3示出了根据本发明的一个实施方式的在形成重组晶片之后的制造过程中的半导体封装。
如图3所示,在多个竖直半导体芯片20上方施加密封剂50,并且使该密封剂部分地包围多个竖直半导体芯片20。在一个实施方式中,使用压缩模塑工艺来施加密封剂50。在压缩模塑中,可将密封剂50放置在模塑腔体中,然后封闭模塑腔体以压缩密封剂50。当模塑单个图案时,可使用压缩模塑。在一个可替代实施方式中,使用传递模塑工艺来施加密封剂50。在其他实施方式中,可使用喷射模塑、粒化模塑、粉末模塑或液体模塑来施加密封剂50。或者,可使用印刷工艺(例如,孔版印刷或丝网印刷)来施加密封剂50。
在各种实施方式中,密封剂50包括介质材料,并且,在一个实施方式中,可包括模塑化合物。在其他实施方式中,密封剂50可包括以下材料中的一种或多种:聚合物、共聚物、生物聚合物、纤维浸渍聚合物(例如,树脂中的碳纤维或玻璃纤维)、颗粒填充聚合物以及其他有机材料。在一个或多个实施方式中,密封剂50包括并非用模塑化合物以及诸如环氧树脂和/或硅树脂的材料形成的密封剂。在各种实施方式中,密封剂50可由任何适当的硬质塑料、热塑性塑料、热固性材料或层压材料制成。在一些实施方式中,密封剂50的材料可包括填充材料。在一个实施方式中,密封剂50可包括环氧材料和填充材料,该填充材料包括玻璃或其他电绝缘矿物填充材料(例如氧化铝或有机填充材料)的小颗粒。可使密封剂50固化,即,经受热处理以***,从而形成保护多个半导体芯片20的气密密封。固化工艺使密封剂50***,从而形成保持多个竖直半导体芯片20的单个衬底。这种衬底被叫做重组晶片90。
图4示出了根据本发明的一个实施方式的在使重组晶片与载体分离之后的制造过程中的半导体封装。
参考图4,去除载体10以分离重组晶片90或人造晶片。嵌有多个竖直半导体芯片20的密封剂50在后续加工过程中提供机械和热稳定性。去除载体10还露出半导体芯片20的前部表面。在各种实施方式中,根据密封剂50的热稳定性,重组晶片90可经受高达300℃的温度。
图5(其包括图5A至图5C)示出了根据本发明的一个实施方式的制造过程中的半导体封装的放大图,其示出了正面金属化,其中,图5A和图5C示出了横截面图,图5B示出了顶部截面图。与图2至图4不同,图5示出了一个半导体封装的放大图。
参考图5A至图5C,竖直半导体芯片20包括正面金属化层100,该正面金属化层包括源极接触区110和栅极接触区120(也见图5B)。正面金属化层100形成在竖直半导体芯片20的顶部表面11之上。在各种实施方式中,正面金属化层100可在芯片切割之前形成。或者,在一些实施方式中,正面金属化层100可在此加工阶段形成。源极接触区100和栅极接触区120可包括多层。在一个实施方式中,硅化物区可覆盖竖直半导体芯片20的半导体材料。在后面是金属层的硅化物区上可形成阻挡层。在一个实施方式中,源极接触区110和栅极接触区120可包括铜。在另一实施方式中,源极接触区110和栅极接触区120可包括铝。在各种实施方式中,源极接触区110和栅极接触区120可包括钛、钽、钨及其氮化物。在正面金属化层100周围设置钝化层60。
图6(其包括图6A和图6B)示出了根据本发明的一个实施方式的在形成正面重新分布层之后的制造过程中的半导体封装的放大图,其中,图6A示出了横截面图,图6B示出了顶部截面图。
参考图6A,在正面金属化层100上形成重新分布层200。重新分布层200包括源极接触件210、源极衬垫230、栅极接触件220、栅极衬垫240以及多个导电线路250。可使用任何适当的技术形成重新分布层200。在一个实施方式中,可在重组晶片90的顶部表面上沉积晶种层。可在晶种层上沉积阻挡层,并使该阻挡层图案化以露出晶种层的一部分。可使用晶种层生长导电材料,例如,使用镀覆工艺(例如电镀或无电镀)。在一个实施方式中,生长的导电材料包括铜、银、金、镍、锌和/或铂。在一个可替代实施方式中,可使用去除工艺沉积并图案化导电材料。在另一实施方式中,例如,可使用孔版印刷或丝网印刷直接印刷重新分布层200。
图7(其包括图7A和图7B)示出了根据本发明的一个实施方式的在使重组晶片变薄之后的制造过程中的半导体封装的放大图,其中,图7A示出了横截面图,图7B示出了顶部截面图。
使重组晶片90从背面表面开始变薄,以露出竖直半导体芯片20的表面。在各种实施方式中,可化学地、机械地或化学机械地执行该变薄。在一个实施方式中,可使用磨具40使重组晶片90变薄。在变薄之后,重组晶片90具有第一高度H1。在各种实施方式中,第一高度H1可是大约50μm至大约500μm。在一个实施方式中,第一高度H1可以是大约10μm至大约50μm。在一个实施方式中,第一高度H1可以是大约10μm至大约100μm。在一个实施方式中,第一高度H1可以是大约100μm至大约400μm。在一个实施方式中,第一高度H1可小于大约50μm。在一个实施方式中,第一高度H1可小于大约100μm。在一个实施方式中,第一高度H1可小于大约200μm。在一个实施方式中,第一高度H1可小于大约500μm。
图8(其包括图8A至图8C)示出了根据本发明的一个实施方式的在使竖直半导体芯片进一步变薄之后的制造过程中的半导体封装的放大图,其中,图8A示出了横截面图,图8B示出了顶部截面图,图8C示出了一个可替代实施方式,其示出了另一放大的横截面图。
使竖直半导体芯片20的露出的背面表面变薄至第二高度H2,形成沟槽310。在各种实施方式中(在图11中示出了一个这种实施方式),沟槽310可包括侧壁。
在各种实施方式中,第二高度H2可以是大约0.5μm至大约10μm。在一个实施方式中,第二高度H2可以是大约0.5μm至大约2μm。在一个实施方式中,第二高度H2可以是大约1μm至大约2μm。在一个实施方式中,第二高度H2可以是大约2μm至大约5μm。在一个实施方式中,第二高度H2可以是大约3μm至大约4μm。
有利地,在各种实施方式中,使竖直半导体芯片20变薄至非常小的厚度。这有利地减小了装置在操作过程中的电阻,并改进了从装置带走的热的热传导。
在一个实施方式中,使用蚀刻工艺相对于密封剂50选择性地蚀刻竖直半导体芯片20。在一个实施方式中,蚀刻工艺可以是定时蚀刻。在另一实施方式中,将蚀刻化学选择为,在到达竖直半导体芯片20的掺杂区之后停止(减慢)。
在另一实施方式中,使用蚀刻停止层来停止蚀刻工艺。在一些实施方式中,如图8C所示,在变薄工艺的过程中,可改变包括竖直半导体芯片20的衬底的结构。图8C示出了在变薄之前和之后的竖直半导体芯片20的厚度。在变薄之前的竖直半导体芯片20包括第一层31和第二层32,第一层31包括有源区,第二层32包括与第一层31不同的材料。在一个实施方式中,当在绝缘体上硅衬底上制造竖直半导体芯片20时,第一层31包括硅,第二层32包括氧化层。在另一实施方式中,当在GaN/Si异质外延衬底上制造竖直半导体芯片20时,第一层31包括化合物半导体材料(例如GaN),第二层32包括硅。在变薄之前的竖直半导体芯片20的厚度是第一厚度H1,而在变薄之后是第二厚度H2。例如,当在绝缘体上硅衬底上形成竖直半导体芯片20时,可在去除绝缘层之后停止变薄工艺。类似地,在异质外延衬底(例如硅衬底上的GaN层)的情况中,可在去除硅衬底留下GaN层之后停止变薄工艺。或者,可留下小部分的硅衬底,然后可将其转换成硅化物。例如,这可用来形成竖直GaN粉末装置(或SiC粉末装置)。
图9(其包括图9A和图9B)示出了根据本发明的一个实施方式的在竖直半导体芯片下方形成背面导体之后的制造过程中的半导体封装的放大图,其中,图9A示出了横截面图,图9B示出了顶部截面图。
参考图9A,在竖直半导体芯片20的露出的背面表面下方形成背面接触件320。因此,在一个实施方式中,背面接触件320形成竖直半导体芯片20中的晶体管的漏极接触件的一部分。
与正面重新分布层200相似,可使用任何适当的技术形成背面接触件320。在一个实施方式中,可在重组晶片90的背面表面上沉积晶种层。可在晶种层上沉积阻挡层,并使该阻挡层图案化以露出晶种层的一部分。可使用晶种层生长导电材料,例如,使用镀覆工艺(例如电镀或无电镀)。在一个实施方式中,生长的导电材料包括铜、银、金、镍、锌和/或铂。在一个可替代实施方式中,可使用去除蚀刻工艺沉积并图案化导电材料。在另一实施方式中,例如,可使用孔版印刷或丝网印刷直接印刷重新分布层200。
在形成背面接触件320之后,对重组晶片90进行切割,以形成各个封装单元。
有利地,在各种实施方式中,背面接触件320是厚导电层,其形成于竖直半导体芯片20下方。填充重组晶片90的沟槽310的导电材料确保了远离半导体区的良好的热传导。
在一些实施方式中,可直接使用由此形成的半导体封装并将该半导体封装安装在电路板上。在其他实施方式中,可将半导体封装封装在引线框架、夹具框和其他适当的衬底上,以形成半导体封装。本发明的实施方式包括形成任何适当类型的封装,例如,符合JEDEC标准的。实例包括晶体管尺寸封装、小尺寸封装、薄型小尺寸封装、减薄紧缩型小尺寸封装、单列直插式封装,等等。
可在后续封装之前测试由此形成的半导体封装。例如,可在衬垫(例如,源极衬垫230和栅极衬垫240)上应用测试探针。然而,在各种实施方式中,竖直半导体芯片20非常薄,并且如果通过测试探针直接向下压,即,当直接在薄半导体层上方施加压力时,该竖直半导体芯片可能损坏。在各种实施方式中,有利地,由于这些衬垫的扇出性质的原因,避免了对变薄的竖直半导体芯片20的损坏。换句话说,衬垫由密封剂50机械地支撑,并且,放置测试探针不会损坏竖直半导体芯片20。此外,该设计不需要增加芯片面积。
图10(其包括图10A和图10B)示出了根据本发明的实施方式而形成的引线框架半导体封装。
参考图10A,将半导体封装(例如,如在图9中形成的)放置在引线框架410之上。可使用粘合层330(在一个实施方式中其可以是绝缘的)将半导体封装附接至引线框架410。在一些实施方式中,粘合层330可以是导电的,例如,可包括纳米导电浆料。在可替代实施方式中,可将背面接触件320焊接至引线框架410,使得粘合层330是可焊的材料。使用引线接合工艺利用焊线430将衬垫(例如,源极衬垫230和栅极衬垫240)与引线框架410耦接。将外密封剂450施加在半导体封装和引线框架410上。
在一个或多个实施方式中,可使用压缩模塑工艺来施加外密封剂450。在压缩模塑中,可将外密封剂450放置在模塑腔体中,然后封闭模塑腔体以压缩外密封剂450。当模塑单个图案时,可使用压缩模塑。在一个可替代实施方式中,使用传递模塑工艺来施加外密封剂450。在其他实施方式中,可使用喷射模塑、粒化模塑、粉末模塑或液体模塑来施加外密封剂450。或者,可使用印刷工艺(例如,孔版印刷或丝网印刷)来施加外密封剂450。可执行固化处理,以形成引线框架封装。
图10B示出了一个可替代实施方式,其显示出夹具状的互连件。例如,可利用焊接将夹具440或金属条带附接至中间层265。本发明的实施方式包括其他类型的适当的互连件。
图11至图12示出了半导体封装的一个可替代结构实施方式及其形成方法。
此实施方式可遵循图2至图7中描述的步骤。参考图11,可如在之前的实施方式中描述地形成沟槽310。作为另一例证,在一个实施方式中,沟槽310可包括梯形侧壁,该梯形侧壁具有凹表面。
参考图12,在竖直半导体芯片20的露出表面上施加粘合浆料321。将背板325放置在粘合浆料321之上。可使粘合浆料321固化,从而牢固地支持背板325。此实施方式避免了用于形成厚背面重新分布层的可能较长的电镀工艺。
图13(其包括图13A至图13E)示出了一个可替代实施方式,其中,在变薄工艺之后形成前背面重新分布层。
此实施方式可遵循图2至图7中描述的步骤。如图13A所示,在竖直半导体芯片20的背面上形成沟槽310之后,形成正面重新分布层200。在各种实施方式中,在形成沟槽310之前或之后,对重组晶片90(图7所示)进行切割(singulate)。还在封装的侧壁上形成正面重新分布层200,从而不需要分别形成互连件,例如焊线。例如,可沿着侧壁溅射金属,以形成互连件280。
参考图13B,如在之前的实施方式中描述的,在竖直半导体芯片20的背面上形成粘合浆料321。如图13C所示,如之前描述的,在粘合浆料321上形成背板325。参考图13D,将半导体封装放置在具有多个引线420的引线框架410上。因此,使用粘合层330将来自半导体封装的互连件280与多个引线420耦接。在一个实施方式中,粘合层330包括焊接材料。在其他实施方式中,粘合层330可包括导电浆料。
参考图13E,在半导体封装和引线框架410上形成外密封剂450。因此,在各种实施方式中,形成引线框架封装。
图14(其包括图14A和图14B)示出了一个制造半导体封装的可替代实施方式,其中,在形成背面导体之后形成金属衬垫。
此实施方式与图13类似。然而,如图14A所示,在形成粘合浆料321之前,在切割的重组晶片的背面表面上形成金属衬垫322。可使用金属衬垫322作为晶种层,并且,然后可使用该金属衬垫形成重新分布线路(例如,如图14B所示)。
图15示出了本发明的一个可替代实施方式,示出了将半导体封装直接安装在电路板上。在一个实施方式中,没有将半导体封装附接至引线框架410,而是将具有密封剂50的半导体封装放置在载体上,并使用外密封剂450封装,如在之前的实施方式中描述的。使由此形成的封装与载体分离,并可将该封装安装在电路板500上。
到目前为止,利用一个分立式晶体管描述了本发明的实施方式。然而,本发明的实施方式可用来形成多个晶体管。在图16和图17中提供了几个实例。
图16(其包括图16A和图16B)示出了根据本发明的一个实施方式的具有一个以上的竖直半导体装置的半导体封装。
如图16A和图16B所示,将两个分立式晶体管嵌在彼此附近。可根据需要使两个晶体管互连。本发明的实施方式可包括两个以上的晶体管。例如,在图16A中,将第一晶体管(左晶体管)的漏极与第二晶体管(右晶体管)的源极耦接。在此实施方式中,在形成重组晶片的同时,将至少两个分立的竖直半导体芯片20放置在彼此附近,由此将这些竖直半导体芯片嵌在密封剂50内。
图17(其包括图17A和图17B)示出了根据本发明的一个实施方式的在一个芯片中具有一个以上的晶体管的半导体封装。
与之前的实施方式不同,在此实施方式中,在相同的衬底内形成竖直半导体芯片20。在变薄工艺之后,仅通过隔离区550将相邻的晶体管隔开。因此,可便宜地将多个功率装置集成在一个封装内。而且,可根据需要使晶体管互连。例如,可将相邻晶体管的栅极衬垫240耦接在一起,同时通过背面接触件320将左晶体管的漏极与第二晶体管的源极耦接。在各种实施方式中,图10至图14也可类似地用来适应多个晶体管和/或芯片。
图18示出了根据本发明的一个实施方式的具有一个以上的竖直半导体装置和逻辑电路的半导体封装。
如图18所示,将两个分立式晶体管嵌在彼此附近。可根据需要使两个晶体管互连。本发明的实施方式可包括两个以上的晶体管。例如,在图18中,将第一晶体管(左晶体管)的漏极与第二晶体管(右晶体管)的源极耦接。在此实施方式中,在形成重组晶片的同时,将至少两个分立的竖直半导体芯片20和逻辑芯片21放置在彼此附近,由此将竖直半导体芯片和逻辑芯片嵌在密封剂50内。
与竖直功率半导体装置的传统封装相比,本发明的实施方式可提供优点。有利地,本发明的实施方式不需要在同样制造超薄芯片的同时处理超薄晶片。类似地,本发明的实施方式不需要对薄半导体芯片进行切割、焊接。本发明的实施方式允许背面加工达到便于形成其他层的高温,例如,高达280℃。不管前段技术(例如,SFET、IGBT、SiC、CMOS、双极,等等)如何,都可应用本发明的实施方式。可将本发明的实施方式加工为大晶片或大面板。本发明的实施方式由于良好的测试和牢固的装配过程而实现了更高的产量。
虽然已经参考说明性实施方式描述了本发明,但是本描述并非旨在以限制性的意思解释。对于本领域的技术人员来说,在参考本描述之后,说明性实施方式以及本发明的其他实施方式的各种修改和组合将是显而易见的。作为例证,在各种实施方式中可使图1至图18中描述的实施方式彼此组合。因此,旨在使所附权利要求包含任何这种修改或实施方式。
虽然已经详细地描述了本发明及其优点,但是,应理解的是,在不背离由所附权利要求定义的本发明的实质和范围的前提下,在此可作出各种改变、替代和更改。例如,本领域的技术人员将容易理解的是,在保持在本发明的范围内的同时,可改变在此描述的许多特征、功能、方法和材料。
此外,本发明的范围并非旨在限于在说明书中描述的工艺、机器、制造、物质成分、方式、方法和步骤的特殊实施方式。作为本领域的一个普通技术人员从本发明的公开内容中将容易理解的是,根据本发明,可利用目前存在或以后将开发的和在此描述的相应实施方式一样基本上执行相同功能或基本上达到相同效果的工艺、机器、制造、物质成分、方式、方法或步骤。因此,所附权利要求旨在将这种工艺、机器、制造、物质成分、方式、方法或步骤包括在其范围内。
Claims (45)
1.一种半导体封装,包括:
竖直半导体芯片,所述竖直半导体芯片具有位于所述竖直半导体芯片的一侧上的第一主表面以及位于所述竖直半导体芯片的相对侧上的第二主表面,其中,所述第一主表面包括第一接触区,并且所述第二主表面包括第二接触区,并且其中,所述竖直半导体芯片构造为调节沿电流方向从所述第一接触区到所述第二接触区的电流;
背面导体,所述背面导体设置在所述第二主表面的所述第二接触区处;以及
第一密封剂,在所述第一密封剂中设置有所述竖直半导体芯片和所述背面导体。
2.根据权利要求1所述的半导体封装,进一步包括:
第二竖直半导体芯片,所述第二竖直半导体芯片设置在所述第一密封剂中,所述第二竖直半导体芯片耦接至所述竖直半导体芯片;以及
逻辑芯片,所述逻辑芯片设置在所述第一密封剂中。
3.根据权利要求1所述的半导体封装,进一步包括:
第二密封剂,在所述第二密封剂中设置有所述第一密封剂、所述竖直半导体芯片和所述背面导体。
4.根据权利要求3所述的半导体封装,进一步包括:
多个接触衬垫,所述多个接触衬垫设置在所述第二密封剂的主表面中。
5.根据权利要求4所述的半导体封装,其中,所述多个接触衬垫包括第一接触衬垫,所述第一接触衬垫通过设置在所述第二密封剂中的互连件耦接至所述第一接触区。
6.根据权利要求5所述的半导体封装,其中,所述互连件是焊线、夹具、夹子、条、带和电互连件中的一个或多个。
7.根据权利要求5所述的半导体封装,其中,所述互连件设置在所述第一密封剂的侧壁上。
8.根据权利要求7所述的半导体封装,其中,所述互连件设置在所述第一密封剂与所述第二密封剂之间。
9.根据权利要求3所述的半导体封装,其中,所述第一密封剂和所述第二密封剂是相同的材料。
10.根据权利要求3所述的半导体封装,其中,所述第一密封剂和所述第二密封剂是不同的材料。
11.根据权利要求1所述的半导体封装,其中,所述背面导体通过粘合浆料、薄膜或带子附接至所述竖直半导体芯片。
12.根据权利要求11所述的半导体封装,其中,所述粘合浆料沉积在所述竖直半导体芯片的倾斜侧壁之上。
13.根据权利要求1所述的半导体封装,其中,所述竖直半导体芯片具有倾斜侧壁。
14.根据权利要求1所述的半导体封装,其中,所述竖直半导体芯片沿所述电流方向比所述第一密封剂薄。
15.根据权利要求1所述的半导体封装,其中,所述竖直半导体芯片沿所述电流方向的厚度小于大约50μm。
16.根据权利要求1所述的半导体封装,其中,所述竖直半导体芯片沿所述电流方向的厚度是大约5μm至大约25μm。
17.根据权利要求1所述的半导体封装,进一步包括:
第二竖直半导体芯片,所述第二竖直半导体芯片设置在所述第一密封剂中,其中,所述第二竖直半导体芯片具有位于所述第二竖直半导体芯片的一侧上的第一主表面以及位于所述第二竖直半导体芯片的相对侧上的第二主表面。
18.根据权利要求1所述的半导体封装,其中,所述竖直半导体芯片包括:
第一晶体管,所述第一晶体管具有第一接触区和第二接触区,以及
第二晶体管,所述第二晶体管具有位于所述第一主表面上的第三接触区以及位于所述第二主表面上的第四接触区,其中,所述第二晶体管构造为调节从所述第三接触区到所述第四接触区的电流,并且其中,所述第一晶体管与所述第二晶体管通过隔离区而分开。
19.根据权利要求1所述的半导体封装,其中,所述竖直半导体芯片包括硅衬底。
20.根据权利要求1所述的半导体封装,其中,所述竖直半导体芯片包括氮化镓。
21.根据权利要求1所述的半导体封装,其中,所述竖直半导体芯片包括碳化硅。
22.一种半导体封装,包括:
竖直半导体芯片,所述竖直半导体芯片具有位于所述竖直半导体芯片的一侧上的第一主表面以及位于所述竖直半导体芯片的相对侧上的第二主表面,其中,所述第一主表面包括第一接触区,并且所述第二主表面包括第二接触区,并且其中,所述竖直半导体芯片构造为调节沿电流方向从所述第一接触区到所述第二接触区的电流;
背面导体,所述背面导体设置在所述第二主表面的漏极接触区上;
第一密封剂,在所述第一密封剂中设置有所述竖直半导体芯片和所述背面导体;
第二密封剂,在所述第二密封剂中设置有所述第一密封剂、所述竖直半导体芯片和所述背面导体;
多个接触衬垫,所述多个接触衬垫设置在所述第二密封剂的主表面上;以及
互连件,所述互连件设置在所述第二密封剂中,所述互连件使所述第一接触区与所述多个接触衬垫中的衬垫耦接。
23.根据权利要求22所述的半导体封装,进一步包括:
第二竖直半导体芯片,所述第二竖直半导体芯片设置在所述第一密封剂中,其中,所述第二竖直半导体芯片具有位于所述第二竖直半导体芯片的一侧上的第一主表面以及位于所述第二竖直半导体芯片的相对侧上的第二主表面。
24.根据权利要求23所述的半导体封装,进一步包括设置在所述第一密封剂中的逻辑芯片。
25.根据权利要求22所述的半导体封装,其中,所述竖直半导体芯片包括:
第一晶体管,所述第一晶体管具有所述第一接触区和所述第二接触区,以及
第二晶体管,所述第二晶体管具有位于所述第一主表面上的第三接触区以及位于所述第二主表面上的第四接触区,其中,所述第二晶体管构造为调节从所述第三接触区到所述第四接触区的电流,并且其中,所述第一晶体管与所述第二晶体管通过隔离区而分开。
26.根据权利要求22所述的半导体封装,其中,所述竖直半导体芯片具有倾斜侧壁。
27.根据权利要求22所述的半导体封装,其中,所述竖直半导体芯片沿所述电流方向比所述第一密封剂薄。
28.根据权利要求22所述的半导体封装,其中,所述竖直半导体芯片沿所述电流方向的厚度小于大约50μm。
29.根据权利要求22所述的半导体封装,其中,所述竖直半导体芯片沿所述电流方向的厚度是大约1μm至大约100μm。
30.根据权利要求22所述的半导体封装,其中,所述互连件设置在所述第一密封剂的侧壁上。
31.根据权利要求30所述的半导体封装,其中,所述互连件设置在所述第一密封剂与所述第二密封剂之间。
32.一种形成半导体封装的方法,包括:
将竖直半导体芯片放置在载体上,其中,所述竖直半导体芯片具有位于所述竖直半导体芯片的正面上的有源区以及位于所述竖直半导体芯片的背面上的有源区,其中,所述竖直半导体芯片的所述正面面向所述载体,并且其中,将所述竖直半导体芯片构造为调节从所述竖直半导体芯片的所述正面到所述竖直半导体芯片的所述背面的电流;
通过在所述竖直半导体芯片和所述载体上施加第一密封剂而形成重组晶片,其中,所述重组晶片具有第一主表面,所述第一主表面与所述竖直半导体芯片的所述正面共面;
使所述重组晶片与所述载体分离,从而露出所述第一主表面;
使所述重组晶片从与所述第一主表面相对的一侧开始变薄,以形成所述重组晶片的第二主表面;
使所述竖直半导体芯片相对于所述第一密封剂从所述第二主表面开始选择性地变薄,以露出位于所述竖直半导体芯片的所述背面上的所述有源区的表面;
在位于所述竖直半导体芯片的所述背面上的所述有源区的露出表面上形成背面导体;以及
用第二密封剂封装所述第一密封剂、所述竖直半导体芯片和所述背面导体。
33.根据权利要求32所述的形成半导体封装的方法,其中,将竖直半导体芯片放置在载体上包括将多个竖直半导体芯片放置在所述载体上,并进一步包括对所述重组晶片进行切割。
34.根据权利要求33所述的形成半导体封装的方法,其中,在形成所述背面导体之后执行所述切割。
35.根据权利要求33所述的形成半导体封装的方法,其中,在形成所述背面导体之前执行所述切割。
36.根据权利要求32所述的形成半导体封装的方法,其中,形成所述背面导体包括使用导电浆料层来附接背板。
37.根据权利要求32所述的形成半导体封装的方法,其中,形成所述背面导体包括形成硅化物区。
38.根据权利要求32所述的形成半导体封装的方法,其中,形成所述背面导体包括:
形成晶种层;以及
使用镀覆工艺来用导电材料对所述晶种层进行镀覆。
39.根据权利要求32所述的形成半导体封装的方法,进一步包括:
在使所述竖直半导体芯片选择性地变薄之后在所述正面上形成正面重新分布线路。
40.根据权利要求39所述的形成半导体封装的方法,进一步包括:
在形成所述正面重新分布线路的同时形成侧壁重新分布线路。
41.根据权利要求39所述的形成半导体封装的方法,进一步包括:
在分离所述重组晶片之后在所述正面上形成正面重新分布线路。
42.根据权利要求41所述的形成半导体封装的方法,进一步包括:
将所述正面重新分布线路中的线路与位于所述第二密封剂的主表面上的衬垫耦接。
43.根据权利要求32所述的形成半导体封装的方法,其中,所述选择性地变薄包括:
蚀刻包括硅衬底和异质外延层的工件;以及
在蚀刻而穿过所述硅衬底之后停止所述蚀刻。
44.根据权利要求43所述的形成半导体封装的方法,其中,所述异质外延层包括氮化镓。
45.根据权利要求43所述的形成半导体封装的方法,其中,所述异质外延包括碳化硅。
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