CN101000755A - Multi-screen display splicing controller - Google Patents
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- 101100169873 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DCK1 gene Proteins 0.000 description 10
- 101000708009 Homo sapiens Sentrin-specific protease 8 Proteins 0.000 description 7
- 102100031407 Sentrin-specific protease 8 Human genes 0.000 description 7
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 description 6
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- 101100175003 Oryza sativa subsp. japonica RGB1 gene Proteins 0.000 description 5
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Abstract
A splicing controller of multi-screen display consists of high definition video signal source and decoder. It is featured as outputting signal to display sub-screen image data generation circuit formed by phase-locked loop, synchronous signal generator, buffer storage controller, buffer storage and internal circuit of display sub-screen.
Description
Technical field
The present invention relates to a kind of digital video signal processing apparatus, particularly a kind of multi-screen display splicing controller.
Background technology
Large screen display is widely used in traffic, aviation, water transport, telecommunication, public security, electric power, military commanding, scheduling and control center, and large screen display system usually adopts multi-screen splicing to form, and adopts the multi-screen splicing controller.Conventional multi-screen splicing controller is based on the traditional control system of " computing machine+integrated circuit board " mode of Windows operating system mostly, poor stability, and can not divorced from computer and independent operating.Particularly, when input high-definition video signal source, high-definition video signal need be converted to the form that calculates function identification, can increase the image noise in the transfer process, can not satisfy the high definition display requirement.
Summary of the invention
The purpose of this invention is to provide a kind of multi-screen display splicing controller, the technical matters that solve is to improve the antijamming capability and the stability of controller, makes picture material not be subjected to any infringement, and can appended drawings as noise.
The present invention is by the following technical solutions: a kind of multi-screen display splicing controller, comprise high-definition video signal source and demoder, and the signal of described demoder output to split-screen display view data produces circuit; The split-screen display view data produces circuit and comprises:
The line synchronizing signal of Rcv decoder output is used for phase-locked and frequency multiplication, and produces the phaselocked loop of the divided data clock signal of split-screen display view data;
Receive the divided data clock signal of phaselocked loop output and the field sync signal of demoder output, the branch synchronizing signal of output split-screen display view data and the synchronous generator of divided data useful signal;
The data that receive two groups of signals and control buffer write the cache controller with read operation, and described one group of signal is used to control the write operation of buffer from synchronizing signal, data useful signal and data clock signal that demoder produces; Another group signal is used to control the read operation of buffer from the divided data clock signal of phaselocked loop generation and the branch synchronizing signal and the divided data useful signal of synchronous generator generation; Branch synchronizing signal and divided data useful signal that the divided data clock signal that described phaselocked loop produces, synchronous generator produce also input to the split-screen display internal circuit;
The viewdata signal of described buffer Rcv decoder output is read the split screen viewdata signal and is delivered to corresponding split-screen display internal circuit under cache controller control.
The signal of demoder output of the present invention comprises field sync signal, line synchronizing signal, data useful signal, data clock signal and viewdata signal.
Synchronizing signal of the present invention comprises field sync signal and line synchronizing signal.
Display image data generating circuit of the present invention by the view data of 1 to 64 group of split-screen display produce circuit side by side and demoder connect to form.
When the region shape that each split-screen display of the present invention shows was identical with area, the view data of each split-screen display produced the shared phaselocked loop of circuit and a circuit for generating synchronous signals.
The clock frequency of divided data clock signal of the present invention is lower than the clock frequency of the data clock signal of demoder output; The frequency of described minute field sync signal is the integral multiple of the field sync signal of demoder output.
The synchronizing signal of of the present invention minute synchronizing signal and divided data useful signal and demoder output and data useful signal have the phase locking relation.
Phaselocked loop of the present invention adopts AD9883 or AV9173.
Synchronous generator of the present invention and cache controller adopt FPGA FPGA.
Buffer of the present invention adopts the synchronous DRAM special IC, or the Block Memory among the storage unit circuit EP2C8Q208 of FPGA inside.
The present invention compared with prior art, and is at first because main circuit, has the advantage that digital circuit is handled based on programmable logic device (PLD) FPGA and Embedded System Design, and promptly antijamming capability is strong, stable high; The second, serve as to handle unit with single pixel, to picture material without any infringement, can appended drawings as noise, satisfy the high definition display requirement fully; The 3rd, but divorced from computer and independent operating, start gets final product operate as normal, and speed is fast.
Description of drawings
Fig. 1 is a multi-screen display splicing controller embodiment schematic diagram of the present invention.
Fig. 2 is that the view data of No. 1 split-screen display among Fig. 1 produces circuit theory diagrams.
Fig. 3 is four screen video data distribution principle figure of the embodiment of the invention.
Fig. 4 is the branch multi-screen display splicing controller schematic diagrams such as n of the embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is done to describe further.
As shown in Figure 1, multi-screen display splicing controller of the present invention comprises: the high-definition video signal source 1 that produces high definition or ultrahigh resolution vision signal; The demoder 2 of high definition or ultrahigh resolution vision signal and output digital image sets of signals is used to decode; Be used to receive the display image data generating circuit 3 of data image signal group; Described display image data generating circuit 3 be by the view data that the view data of No. 1 split-screen display produces circuit, No. 2 split-screen displays produce circuit ... maximal value is that No. 64 split-screen display view data generation circuit are formed the signal of Rcv decoder output side by side.As most preferred embodiment, the YPbPr signal or the Video signal of high definition DVD player output adopted in the high-definition video signal source, and demoder adopts special IC SAA7114.
The course of work of multi-screen display splicing controller of the present invention: high-definition video signal source 1 produces high definition or ultrahigh resolution vision signal, output digital image sets of signals after demoder 2 decodings, described data image signal group comprises field sync signal Vsync, line synchronizing signal Hsync, data useful signal DEN, data clock signal DCLK and viewdata signal group RGB.
As shown in Figure 2, the view data of No. 1 split-screen display generation circuit comprises phaselocked loop 4, synchronous generator 5, cache controller 6 and buffer 7.
The line synchronizing signal Hsync that demoder 2 produces sends into phaselocked loop, carry out phase-locked and frequency multiplication, produce the divided data clock signal DCK1 of No. 1 split-screen display view data, the clock frequency of DCK1 is lower than the DCLK clock frequency of demoder 2 outputs, and the frequency of branch field sync signal Vsync1 is the integral multiple of the field sync signal Vsync of demoder 2 outputs; Phaselocked loop is special IC: AD9883 or AV9173.DCK1 is admitted to synchronous generator 5, field sync signal Vsync by demoder 2 outputs also is admitted to synchronous generator 5, under DCK1 and Vsync control, branch synchronizing signal Vsync1, Hsync1 and the divided data useful signal DEN1 of No. 1 split-screen display view data of synchronous generator 5 outputs, Vsync, Hsync, the DEN synchronizing signal of these signals and demoder output has the phase locking relation, be different from the synchronizing signal that demoder is exported, can guarantee the image stabilization of display screen; Cache controller 6 receives two groups of signals, one group of Vsync, Hsync, DEN, DCLK from demoder 2, and another group is from DCK1, Vsync1, the Hsync1 of synchronous generator 5, the DEN1 of phaselocked loop.Under these two groups of signal controlling, the data of cache controller 6 control buffers 7 write and read operation, and wherein, the write operation of sets of signals Vsync, Hsync, DEN, DCLK control buffer 6 is about to viewdata signal RGB and writes buffer 7; The read operation of sets of signals Vsync1, Hsync1, DEN1, DCK1 control buffer 6, promptly from buffer 7, read view data RGB1, input to the split-screen display internal circuit No. 1, under cache controller 6 controls, buffer 7 produces the viewdata signal RGB1 of No. 1 split-screen display.Under sets of signals Vsync1, Hsync1, DEN1, the DCK1 of phaselocked loop 4 and synchronous generator 5 outputs control, cache controller 6 sends " reading " command signal to buffer 7, from buffer 7, read corresponding viewdata signal RGB1, sets of signals Vsync1, Hsync1, DEN1, DCK1 and RGB1 are provided for corresponding No. 1 split-screen display internal circuit, make No. 1 split-screen display show the respective image content.
As most preferred embodiment, the synchronous generator 5 that the view data of No. 1 split-screen display produces circuit adopts FPGA FPGA, as EP2C8Q208, cache controller 6 adopts FPGA FPGA, as EP2C8Q208, buffer 7 adopt " writing " and " reading " but the synchronous DRAM special IC of independent operation, as IS42S32200B or K4S643232H, or the Block Memory among the storage unit circuit EP2C8Q208 of FPGA inside, divide panel type display to adopt the LED display screen, its processing to view data belongs to prior art.
As shown in Figure 3,2 * 2 multi-screen display splicings of forming with four screens are example, and cache controller data allocations in the course of the work is described.No. 1 split-screen display shows the capable C1 row of R1 in the upper left corner; No. 2 split-screen displays show the capable C2 row of R1 in the upper right corner; No. 3 split-screen displays show the capable C1 row of R2 in the lower left corner; No. 4 split-screen displays show the capable C2 row of R2 in the lower right corner.Sets of signals in demoder 2 outputs: under Vsync, Hsync, DEN, the DCLK control, cache controller 6 sends " writing " command signal to buffer 7.When the viewdata signal RGB of demoder 2 output was positioned at regional that No. 1 split-screen display shows, the cache controller in No. 1 split-screen display data generating circuit write the respective cache device with RGB; When the viewdata signal RGB of demoder 2 output was positioned at regional that No. 2 split-screen displays show, the cache controller in No. 2 split-screen display data generating circuits write the respective cache device with RGB; When the viewdata signal RGB of demoder 2 output was positioned at regional that No. 3 split-screen displays show, the cache controller in No. 3 split-screen display data generating circuits write the respective cache device with RGB; When the viewdata signal RGB of demoder 2 output was positioned at regional that No. 4 split-screen displays show, the cache controller in No. 4 split-screen display data generating circuits write buffer with RGB, only writes corresponding split-screen display in each buffer and wants content displayed.
Produce the phaselocked loop of circuit and the sets of signals of synchronous generator output at the split screen display image data: divide Vsync, divide Hsync, divide DEN, divide under the DCK control, the cache controller of this circuit sends " reading " command signal to buffer, reads corresponding sub image data RGB from buffer.These sets of signals: divide Vsync, divide Hsync, divide DEN, divide DCK and divide RGB to offer corresponding display screen internal circuit, make display screen show the respective image content.
As shown in Figure 4, when the region shape that shows when split-screen display was identical with area, the view data of each split-screen display produces circuit can a shared phaselocked loop and a circuit for generating synchronous signals, just simplification more of multi-screen display splicing controller like this.Control signal group Vsync, Hsync, DEN, the DCLK of demoder 2 outputs input to each cache controller in proper order, and the viewdata signal RGB of demoder 2 outputs inputs to each buffer simultaneously, controls the write operation of each buffer with this; Control signal group Vsync1, Hsync1, DEN1, the DCK1 of phaselocked loop and circuit for generating synchronous signals output input to each cache controller simultaneously, control the read operation of each buffer with this; Control signal group Vsync1, Hsync1, DEN1, DCK1 also input to each split-screen display internal circuit simultaneously, the viewdata signal RGB1 that each buffer is read ..., RGBn also inputs to corresponding split-screen display internal circuit.
Multi-screen display splicing controller of the present invention, high definition video signal is behind demoder output digital image signal, to treatment of picture is to be the digital processing process of unit with the pixel, to picture material without any infringement, can appended drawings as noise, picture quality depends on demoder fully, and demoder adopts the special IC of technology maturation.Make each split-screen display show respective image content, antijamming capability is strong, and stability is high, but divorced from computer and independent operating.
Claims (10)
1. a multi-screen display splicing controller comprises high-definition video signal source and demoder, it is characterized in that: the signal of described demoder output to split-screen display view data produces circuit; The split-screen display view data produces circuit and comprises:
The line synchronizing signal of Rcv decoder output is used for phase-locked and frequency multiplication, and produces the phaselocked loop of the divided data clock signal of split-screen display view data;
Receive the divided data clock signal of phaselocked loop output and the field sync signal of demoder output, the branch synchronizing signal of output split-screen display view data and the synchronous generator of divided data useful signal;
The data that receive two groups of signals and control buffer write the cache controller with read operation, and described one group of signal is used to control the write operation of buffer from synchronizing signal, data useful signal and data clock signal that demoder produces; Another group signal is used to control the read operation of buffer from the divided data clock signal of phaselocked loop generation and the branch synchronizing signal and the divided data useful signal of synchronous generator generation; Branch synchronizing signal and divided data useful signal that the divided data clock signal that described phaselocked loop produces, synchronous generator produce also input to the split-screen display internal circuit;
The viewdata signal of described buffer Rcv decoder output is read the split screen viewdata signal and is delivered to corresponding split-screen display internal circuit under cache controller control.
2. multi-screen display splicing controller according to claim 1 is characterized in that: the signal of described demoder output comprises field sync signal, line synchronizing signal, data useful signal, data clock signal and viewdata signal.
3. multi-screen display splicing controller according to claim 2 is characterized in that: described synchronizing signal comprises field sync signal and line synchronizing signal.
4. multi-screen display splicing controller according to claim 3 is characterized in that: described display image data generating circuit by the view data of 1 to 64 group of split-screen display produce circuit side by side and demoder connect to form.
5. multi-screen display splicing controller according to claim 2 is characterized in that: when the region shape that described each split-screen display shows was identical with area, the view data of each split-screen display produced the shared phaselocked loop of circuit and a circuit for generating synchronous signals.
6. according to claim 4 or 5 described multi-screen display splicing controllers, it is characterized in that: the clock frequency of described divided data clock signal is lower than the clock frequency of the data clock signal of demoder output; The frequency of described minute field sync signal is the integral multiple of the field sync signal of demoder output.
7. multi-screen display splicing controller according to claim 6 is characterized in that: the synchronizing signal and the data useful signal of described minute synchronizing signal and divided data useful signal and demoder output have the phase locking relation.
8. multi-screen display splicing controller according to claim 7 is characterized in that: described phaselocked loop adopts AD9883 or AV9173.
9. multi-screen display splicing controller according to claim 8 is characterized in that: described synchronous generator and cache controller adopt FPGA FPGA.
10. multi-screen display splicing controller according to claim 9 is characterized in that: described buffer adopts the synchronous DRAM special IC, or the Block Memory among the storage unit circuit EP2C8Q208 of FPGA inside.
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