CN103795979B - Method and device for synchronizing distributed image stitching - Google Patents
Method and device for synchronizing distributed image stitching Download PDFInfo
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Abstract
The invention provides a method and device for synchronizing distributed image stitching. The method and device for synchronizing distributed image stitching are applied to a video decoder in a distributed stitching control system. The method comprises the steps that the video decoder decodes video frames output by a stitching controller, and stores decoded video data in a video memory; when display output is interrupted, the theoretical display output time of the nth frame is worked out according to the formula Xn=(Tn-T1)+t1+d; whether the current preset time for displaying the nth frame is longer than or equal to Xn is judged; if yes, the nth frame data are output and are displayed by a sub-display screen corresponding to the decoder; if not, whether the nth frame is displayed or not is judged again in a next display interruption generation period. By the adoption of the method and device for synchronizing distributed image stitching, the time during which images on all output screens are not synchronous can be shortened, and the effect of displaying a stitched image is improved.
Description
Technical field
The present invention relates to field of video monitoring, more particularly to the method and apparatus that a kind of splicing of distributed image is synchronous.
Background technology
In order to meet the demand that user is watched giant-screen, large screen splicing technology is more and more applied to video monitoring neck
Domain.So-called large screen splicing technology, into many parts, is shown on different display devices by by a secondary complete image segmentation
Show and ensure image parts simultaneous display.At present, each producer is used mostly matrix device to realize large screen splicing, belongs to
The splicing equipment of integrated form, as depicted in figs. 1 and 2, Fig. 1 is simple matrix device to its common solution, does not support net
Network stream is input into, the tiled display to carry out network flow, and front end has to connect a Video Decoder for carrying out to network flow
Decoding, output video signal is to matrix device；Fig. 2 is integrated with decoder module, can simultaneously support network flow and video signal input.
For above two solution, poor expandability, what is transmitted between different display modules is original graph after decoding
Picture, data volume is big, and because using integrated form Splicing model, each split screen Image Sharing bandwidth is transmitted, and transmitting procedure can
The time that image reaches display module can be caused to produce certain difference, therefore when tiled display is exported, each display can be caused
Produce during module display splicing picture asynchronous.
The content of the invention
Based on the problems referred to above, the present invention proposes a kind of synchronous method of distributed image splicing, is applied to a kind of distributed
On Video Decoder in splicing control system, the distributed splicing control system includes splicing controller, some video solutions
Code device and some sub- display screens, wherein some Video Decoders are all connected to the splicing controller, each video solution
Code device connects one or more sub- display screens, and methods described includes：
Step A, the frame of video to splicing controller output are decoded, and decoded video data are stored in aobvious
In depositing；When in the display output pregnancy ceased is given birth to, when calculating the theoretical display output of n-th frame according to formula Xn=(Tn-T1)+t1+d
Between；Wherein Xn represents the theoretical display output time of calculated n-th frame；After t1 represents synchronous with other Video Decoders
First frame reaches the system time of video memory；The T1 and Tn represent respectively the timestamp carried in first frame and n-th frame；The d
The display buffer time is represented, the time is the integral multiple that display output interrupts the generation cycle；The n is the integer more than 1；
Wherein the decoder produces the time of display output interruption and other decoders produce the time synchronized that display outputs are interrupted；
Whether step B, the judgement current time for preparing to show n-th frame are more than or equal to the Xn；If so, then export this n-th
Frame data are shown by the corresponding sub- display screen of the decoder；Otherwise, hold again when next display output is interrupted and produced
Row step B.
Preferably, the Video Decoder is received and disappeared comprising the multicast for resetting order by what the splicing controller sent
Breath, and replacement order in the multicast message resets display output chip, with realize the display output break period and other
The synchronization of decoder.
Preferably, the Video Decoder receives the first query messages frame time of advent sent from the splicing controller
Afterwards, the time difference for receiving the system time with the system time of the first frame arrival video memory of record of the query messages is calculated, and will
The time difference is advertised to the splicing controller, so that the splicing controller can be according to the time difference and other video solutions
The time difference of code device notice carries out synchronous with other Video Decoders to the time that Video Decoder head frames reach video memory.
Preferably, the splicing controller is regarded according to the time difference of the time difference and other Video Decoder notices to this
Frequency decoder head frames reach time of video memory to carry out synchronously being specially with other Video Decoders：Splicing controller is with described logical
In the time difference of announcement on the basis of maximum time difference, to the Video Decoder send will record first frame reach time of video memory to
The instruction of front adjustment m milliseconds, wherein m=a-b, a are the maximum time difference, and b receives the inquiry and disappears for the Video Decoder
The system time of breath reaches the time difference of the system time of video memory with the first frame of record.
Preferably, when the time difference that arbitrary Video Decoder in each Video Decoder is calculated with it is described maximum when
Between difference between difference exceed the display buffer time when, splicing controller to the Video Decoder send comprising empty it is slow
The message of area's order is rushed, the Video Decoder is received after the message, and the order of the emptying buffer in the message is emptied
The data of screen buffer, return execution step A.
The present invention also proposes a kind of distributed image splicing synchronizer, and the device is applied to a kind of distributed splicing control
On Video Decoder in system, it is described it is distributed splicing control system also include splicing controller, some sub- display screens and
Other Video Decoders, wherein each Video Decoder is all connected to the splicing controller, each Video Decoder connection
One or more sub- display screens, the device includes：
Decoding computing module, for decoding to the frame of video that the splicing controller is exported, and regards decoded
Frequency evidence is stored in video memory, and when in the display output pregnancy ceased is given birth to, according to formula Xn=(Tn-T1)+t1+d n-th frame is calculated
The theoretical display output time；Wherein Xn represents the theoretical display output time of calculated n-th frame；T1 is represented and other videos
First frame after decoder synchronization reaches the system time of video memory；The T1 and Tn are represented respectively in first frame and n-th frame and carried
Timestamp；The d represents the display buffer time, and the time is the integral multiple that display output interrupts the generation cycle；The n
It is the integer more than 1；The decoder produces time and other decoders generation display outputs interruptions that display output is interrupted
Time synchronized；
Output control module, for judging whether the current time for preparing to show n-th frame is more than or equal to the Xn；If so,
Then export the n-th frame data to be shown by the corresponding sub- display screen of the decoder；Otherwise, pregnancy ceased in next display output is treated
Rejudge whether export the n-th frame when raw.
Preferably, the decoding computing module is further used for：Receive by the splicing controller send comprising replacement
The multicast message of order, and replacement order in the multicast message resets display output chip, to realize display output in
The disconnected time is synchronous with other decoders.
Preferably, the decoding computing module is further used for：When receiving the first frame that sends from the splicing controller
After the query messages of the time of advent, the system that calculating receives the system time of the query messages and the first frame arrival video memory of record
The time difference of time, and the time difference is advertised to into the splicing controller so that the splicing controller can according to this when
Between difference and the time difference of other Video Decoders notice the time that Video Decoder head frames reach video memory is carried out and other
The synchronization of Video Decoder.
Preferably, the splicing controller is regarded according to the time difference of the time difference and other Video Decoder notices to this
Frequency decoder head frames reach time of video memory to carry out synchronously being specially with other Video Decoders：Splicing controller is with described logical
In the time difference of announcement on the basis of maximum time difference, to the Video Decoder send will record first frame reach time of video memory to
The instruction of front adjustment m milliseconds, wherein m=a-b, a are the maximum time difference, and b receives the inquiry and disappears for the Video Decoder
The system time of breath reaches the time difference of the system time of video memory with the first frame of record.
Preferably, when the time difference that arbitrary Video Decoder in each Video Decoder is calculated with it is described maximum when
Between difference between difference exceed the display buffer time when, splicing controller to the Video Decoder send comprising empty it is slow
The message of area's order is rushed, the output control module is further used for：After receiving the message, according to the clearing buffers in the message
The order in area empties the data of screen buffer.
The present invention program by proposing a kind of distributed decoding tiled display scheme, strictly control by the timestamp in code stream
On display opportunity of the system per two field picture, so as to reduce each cutout screen picture nonsynchronous time, lift stitching image display effect.
Description of the drawings
Fig. 1 is large screen splicing solution schematic diagram in a kind of prior art；
Fig. 2 is large screen splicing solution schematic diagram in another kind of prior art；
Fig. 3 is a kind of tiled display schematic flow sheet of distributed splicing control system proposed by the present invention；
Fig. 4 is the synchronous method flow diagram of a kind of distributed image splicing in one embodiment of the present invention；
Fig. 5 is the schematic diagram that the first frame time of advent is selected in one embodiment of the present invention；
Fig. 6 is to carry out the first synchronization frame time of advent to the display prot of each sub- display screen in one embodiment of the present invention
Schematic diagram；
Fig. 7 is to carry out the flow chart of display control according to timestamp in one embodiment of the present invention；
Fig. 8 is the logic device that a kind of distributed image splices synchronizer in one embodiment of the present invention.
Specific embodiment
For the technical problem proposed in background technology, the present invention program proposes a kind of distributed splicing control system, please
Referring to Fig. 3, from unlike the integrated form Splicing model adopted in prior art, the distributed splicing control system includes one
Splicing control device, some Video Decoders and some sub- display screens, wherein some Video Decoders are all connected to institute
Splicing controller is stated, each Video Decoder connects one or more sub- display screens.In specific implementation process, by splicing control
Code stream is replicated and is distributed on multiple Video Decoders by equipment according to splicing business, and each Video Decoder is decoded to code stream
Afterwards, according to splicing business, a portion picture of an output image.Certainly, if Video Decoder supports multipath decoding output,
Then the Video Decoder can be responsible for exporting some of picture, the Video Decoder 1 in such as Fig. 4.It is easy for description, herein
The frame of the Video Decoder output being related to each means the part picture of the frame that the Video Decoder correspondence need to be exported.Such as,
The description of the 1st frame of the output of decoder 2 in Fig. 3 actually refers to the part 2 picture of the 1st frame that decoder 2 is exported.
For the distributed splicing control system, it is the problem that cannot avoid that the splicing of image is synchronous.The present invention proposes one
Plant suitable for the synchronous method and apparatus of the image mosaic of the distributed splicing control system.It is detailed below in conjunction with specific embodiment
Explanation.
Fig. 4 is referred to, the method performs following steps：
S401, the frame of video to splicing controller output are decoded, and decoded video data are stored in aobvious
In depositing；When in the display output pregnancy ceased is given birth to, when calculating the theoretical display output of n-th frame according to formula Xn=(Tn-T1)+t1+d
Between；
Wherein, Xn represents the theoretical display output time of calculated n-th frame；T1 represents same with other Video Decoders
First frame after step reaches the system time of video memory；The T1 and Tn represent respectively the timestamp carried in first frame and n-th frame；
The d represents the display buffer time, and the time is the integral multiple that display output interrupts the generation cycle；The n is more than 1
Integer；The time that the time and other decoders that wherein decoder generation display output is interrupted produces display outputs interruption is same
Step；
Whether S402, the judgement current time for preparing to show n-th frame are more than or equal to the Xn；If so, the n-th frame is then exported
Data are shown by the corresponding sub- display screen of the decoder；Otherwise, re-execute when next display output is interrupted and produced
Step S402.
In the display output stage, the display output chip of each Video Decoder often shows and all can produce after a two field picture one
Display output is interrupted for being configured to next two field picture.However, in the system of the distributed splicing, due to each video solution
The display output chip of code device produces that the opportunity that display output interrupts is inconsistent, and can cause that image shows is asynchronous.
Therefore, in the present embodiment, need in advance to produce the display output chip of each Video Decoder and show what is interrupted
Time synchronizes.The mistake that the time that the display output that the display output chip of each Video Decoder is produced is interrupted is synchronized
Journey, is specifically performed by splicing controller.In actual utilization, splicing controller can be simultaneously heavy by each Video Decoder of control
Put display output chip to ensure that the time that each Video Decoder generation display output is interrupted is synchronization.A kind of preferred
Mode in, because splicing controller in actual applications is located in same LAN with each Video Decoder, therefore splice control
Device processed can send one comprising the multicast message for resetting order, after each Video Decoder receives the multicast message in the network,
Replacement order in the multicast message resets to display output chip, to realize the same of display output break period
Step.Because splicing controller is located at same LAN with each Video Decoder, therefore the real-time of multicast message can be at utmost
The all of display output chip of guarantee all receive the multicast message simultaneously, interrupt so as to realize that each decoder produces display output
Opportunity it is consistent.
In the present embodiment, each Video Decoder is received after the frame of video of splicing controller output, is by periodic
Call formula Xn=(Tn-T1)+t1+d to calculate and control display and the output time of n-th frame, the wherein formula is called
Cycle is that Video Decoder produces the cycle that display output is interrupted.In the formula, Tn and T1 be video data in carry when
Between stab.Because timestamp and parameter d are fixed value, therefore in the present embodiment, Xn-t1 is really existing with a fixed value
Relatively.If the time t1 that the first frame of i.e. each Video Decoder record reaches video memory is identical, according to the formula, then calculate
The theoretical display output time of n-th frame is necessarily identical.So as in order to the video memory for ensureing each Video Decoder receives the time of first frame
T1 is identical, and the time t1 for also needing the video memory for reaching each Video Decoder to the first frame is synchronized.
Splicing controller is reached to the first frame recorded in each Video Decoder referring to the drawings and with reference to concrete instance
The process that the time of video memory synchronizes is further described：
In the present embodiment, the first frame of the record reach the video memory of each Video Decoder time it is concrete headed by frame reach
After video memory, the next display output of record interrupts the system time for producing.6 are referred to, because display output interrupts what is produced
Time has carried out in advance synchronization, and the time that each Video Decoder video memory receives first frame there may be difference, therefore in order to
Ensure that the time of the first frame arrival video memory of each Video Decoder record is identical as far as possible, it is recordable when first frame is actually reached video memory
Afterwards, next display output interrupts the time that the system time for producing reaches video memory as the first frame.V01 in such as Fig. 5 and
Although V02, the actual time that first frame is reached differs, but if selecting head frames reaches the next display output recorded after video memory
Interrupt the time of the time as the first frame to video memory of generation, the time t1 all same of final V01 and V02 records.
But many times, first frame reaches the time difference of different video decoders and is likely larger than a display output interruption
Cycle, institute's method described above can not be fully solved problem.The embodiment of the present invention based on the above method, further according to
In the following manner is operated.
When the time t1 for reaching video memory in the first frame recorded to each Video Decoder is synchronized, splicing controller can pass through
A multicast message is sent to each decoder to inquire about and determine in each Video Decoder that first frame reaches earliest the video solution of video memory
Code device, and Video Decoder head frames are reached the time of video memory as reference value, with this to other each Video Decoder head frames
The time for reaching video memory is corrected.
However, because the system time of each decoder is possibly different from, the first frame of each Video Decoder record reaches aobvious
The system time deposited is possibly different from, therefore in the present embodiment, splicing controller is received by inquiring about each Video Decoder
The first frame of time and record to query messages reaches the time difference between the system time of video memory to determine each video decoding
First frame reaches earliest the Video Decoder of video memory in device.For example, splicing controller can send a multicast to the unification of each decoder
Used as query messages, each decoder is received after the query messages message, calculates the system time and note for receiving the query messages
The first frame of record is reached after the time difference of the time of video memory, and the time difference is returned to into splicing controller as Query Result.In order to
Ensure the reliability of Query Result, splicing controller can be by repeatedly inquiring about to ensure Query Result.It is real-time due to multicast message
Property, each decoder receives the time of query messages it is believed that identical, therefore returns when splicing controller receives each Video Decoder
The time difference after, during the time difference that can be calculated according to different video decoders is to judge each Video Decoder
First frame reaches earliest the Video Decoder of video memory, that is, frame is arrived earliest headed by the maximum Video Decoder of the time difference for calculating
Up to the Video Decoder of video memory.
After confirming that first frame reaches earliest the Video Decoder of video memory, splicing controller is calculated with the Video Decoder
Time difference on the basis of be worth, the time that video memory is reached to the first frame of other Video Decoders record is corrected.Specially：Xiang Qi
His each Video Decoder sends the instruction for the time of the first frame arrival video memory that will be recorded adjusting m milliseconds forward, wherein m=a-b, a
For the maximum time difference calculated in each Video Decoder, b receives the query messages for each Video Decoder
System time with record first frame reach video memory system time time difference.For example：Fig. 3 and Fig. 6 is referred to, to inquire about three
As a example by secondary, after splicing controller is inquired about by three times, the time difference returned by each Video Decoder is finally confirmed to regard
The time difference that frequency decoder 1 is calculated is maximum, i.e., frame reaches earliest the Video Decoder of video memory headed by Video Decoder 1, then with
The time difference that Video Decoder 1 is returned carries out school as reference value to the time of the first frame arrival video memory of the record of Video Decoder 2
Just.Splicing controller is sent out by the further calculating difference of the time difference returned to Video Decoder 1 and Video Decoder 2
The generation week that existing Video Decoder 2 two display outputs more late than the time that the first frame that Video Decoder 1 is recorded reaches video memory are interrupted
Phase, therefore splicing controller adjusts forward the instruction in 2 cycles to the time that Video Decoder 2 sends first frame arrival video memory, depending on
Frequency decoder 2 is received after the instruction, will deduct the time that two display outputs interrupt the generation cycle the first frame time of advent of record,
So as to the described first frame for ensureing Video Decoder 1 and the record of Video Decoder 2 reaches the time consistency of video memory.
Wherein, in the present embodiment, arbitrary Video Decoder is calculated in splicing controller finds each Video Decoder
The time difference, the difference between the time difference that the Video Decoder for reaching video memory earliest with the first frame is calculated,
Beyond the display buffer time of each Video Decoder when, it is unified to send one comprising emptying buffer order to each Video Decoder
Message；Each Video Decoder is received after the message, after emptying the data of respective screen buffer, is re-executed the above and is respectively walked
Suddenly.In the present embodiment, the display buffer time all same of each Video Decoder, while remembering to each Video Decoder for convenience
The first frame time of record is adjusted, and the display buffer time is the integral multiple that each decoder display output interrupts the generation cycle.
By to description more than the present embodiment, if the time t1 of each Video Decoder video memory of first frame arrival is identical,
During the theoretical display output of each Video Decoder n-th frame that each Video Decoder is calculated according to formula Xn=(Tn-T1)+t1+d
Between it is inevitable identical.Therefore for a Video Decoder, in the display output stage of video, can be according to n-th for calculating
The theoretical display output time of frame is shown and output control to n-th frame.Such as when Video Decoder prepares to carry out n-th frame
When showing and exporting, can be prepared to show the time of n-th frame and the Xn whether further confirming that by comparing current system
Show the n-th frame.Refer to Fig. 7, in the figure 7 tn represent current system prepare show n-th frame when system time.Video is decoded
Device is obtained after n-th frame data from decoded video relief area, and when system prepares to show n-th frame, Video Decoder is by comparing
The tn and Xn that calculated by above-mentioned formula is determining whether to show the n-th frame；If the tn is more than or equal to Xn, and the frame is defeated
Go out and shown to corresponding sub- display screen；If display output is interrupted produce once (when 60fps is exported) per 16.7ms, therefore
Tn is being increased with the gradient of 16.7ms, and when first fit conditions above, then export the frame is carried out to corresponding sub- display screen
Show, now tn is more than or equal to Xn, less than Xn+16.7ms, therefore can be by nonsynchronous time control of frame of video at one
Display output was interrupted within the generation cycle.In addition, if the tn is less than Xn, then the frame is not processed, treat next display output
Carry out again interrupt cycle judging whether to show the frame.
Certainly, in the present embodiment, splicing controller can be periodically using said method to carrying out to each Video Decoder
The synchronization that display output is interrupted, and reach time of the video memory of each Video Decoder to the first frame and synchronize, it is concrete real
Apply step identical with the present embodiment above description, will not be described here.
By the present embodiment above description, would know that in the present invention program, splicing controller can be periodically to each
The time of the video memory that the first frame on opportunity and output that Video Decoder produces display output interruption reaches each Video Decoder enters
Row is synchronous, so as at utmost avoid due to each Video Decoder produce opportunity that display output interrupts it is different and cause when
Between error.In the present invention, splicing controller actually only make use of each Video Decoder receive the system time of query messages with
The first frame of record reaches the time of video memory, and to the time of the first frame arrival video memory of each Video Decoder synchronization has been carried out, and is not required to
The system time of different video decoders is synchronized, therefore synchronous effect is more effective.
Fig. 8 is refer to, the present invention also proposes a kind of distributed image splicing synchronizer 80, and the device is applied to a kind of point
On Video Decoder in cloth splicing control system, the distributed splicing control system also includes splicing controller, some
Sub- display screen and other Video Decoders, wherein each Video Decoder is all connected to the splicing controller, each is regarded
Frequency decoder connects one or more sub- display screens, and the device includes：
Decoding computing module 81, for decoding to the frame of video that the splicing controller is exported, and will be decoded
Video data is stored in video memory, and when in the display output pregnancy ceased is given birth to, according to formula Xn=(Tn-T1)+t1+d n-th frame is calculated
The theoretical display output time；
Wherein, Xn represents the theoretical display output time of calculated n-th frame；T1 represents same with other Video Decoders
First frame after step reaches the system time of video memory；The T1 and Tn represent respectively the timestamp carried in first frame and n-th frame；
The d represents the display buffer time, and the time is the integral multiple that display output interrupts the generation cycle；The n is more than 1
Integer；The decoder produces the time of display output interruption and other decoders produce the time synchronized that display outputs are interrupted；
Output control module 82, for judging whether the current time for preparing to show n-th frame is more than or equal to the Xn；If
It is then to export the n-th frame data to be shown by the corresponding sub- display screen of the decoder；Otherwise, in treating next display output
Pregnancy ceased rejudges whether export the n-th frame when giving birth to.
In the present embodiment, the decoding computing module is further used for：The bag that reception is sent by the splicing controller
Containing the multicast message for resetting order, and the replacement order in the multicast message resets display output chip, to realize showing
The output break period is synchronous with other decoders.
In the present embodiment, the decoding computing module is further used for：Send from the splicing controller when receiving
The first frame time of advent query messages after, calculating receives the system time of the query messages and reaches video memory with the first frame of record
System time time difference, and the time difference is advertised to into the splicing controller, so that the splicing controller can root
The time that Video Decoder head frames reach video memory is carried out according to the time difference and the time difference of other Video Decoder notices
It is synchronous with other Video Decoders.
In the present embodiment, the splicing controller is according to the time difference and the time difference of other Video Decoder notices
The time that Video Decoder head frames reach video memory is carried out synchronously to be specially with other Video Decoders：Splicing controller with
In the time difference of the notice on the basis of maximum time difference, send to the Video Decoder and the first frame of record is reached into video memory
Time adjusts forward the instruction of m milliseconds, wherein m=a-b, and a is the maximum time difference, and b receives described for the Video Decoder
The system time of query messages reaches the time difference of the system time of video memory with the first frame of record.
In the present embodiment, the time difference for calculating when arbitrary Video Decoder in each Video Decoder with it is described most
When difference between big time difference exceeds the display buffer time, splicing controller sends to the Video Decoder and includes
The message of emptying buffer order, the output control module is further used for：It is clear in the message after receiving the message
The order of buffer empty empties the data of screen buffer.
Presently preferred embodiments of the present invention is the foregoing is only, not to limit the present invention, all essences in the present invention
Within god and principle, any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (10)
1. a kind of synchronous method of distributed image splicing, is applied to a kind of distributed Video Decoder spliced in control system
On, it is characterised in that the distributed splicing control system includes that splicing controller, some Video Decoders and some sons are aobvious
Display screen, wherein some Video Decoders are all connected to the splicing controller, each Video Decoder connects one or many
Individual sub- display screen, methods described includes：
Step A, the frame of video to splicing controller output decode, and decoded video data are stored in into video memory
In；When in the display output pregnancy ceased is given birth to, when calculating the theoretical display output of n-th frame according to formula Xn=(Tn-T1)+t1+d
Between；Wherein Xn represents the theoretical display output time of calculated n-th frame；After t1 represents synchronous with other Video Decoders
First frame reaches the system time of video memory；The T1 and Tn represent respectively the timestamp carried in first frame and n-th frame；The d
The display buffer time is represented, the time is the integral multiple that display output interrupts the generation cycle；The n is the integer more than 1；
Wherein the decoder produces the time of display output interruption and other decoders produce the time synchronized that display outputs are interrupted；It is described
Frame is reached after video memory headed by the system time of first frame arrival video memory, when the next display output of record interrupts the system for producing
Between；
Whether step B, the judgement current time for preparing to show n-th frame are more than or equal to the Xn；If so, the n-th frame number is then exported
According to being shown by the corresponding sub- display screen of the decoder；Otherwise, step is re-executed when next display output is interrupted and produced
Rapid B.
2. the method for claim 1, it is characterised in that the Video Decoder is received and sent by the splicing controller
Comprising the multicast message for resetting order, and replacement order in the multicast message resets display output chip, to realize
The display output break period is synchronous with other decoders.
3. method as claimed in claim 2, it is characterised in that the Video Decoder is received to be sent out from the splicing controller
After the first query messages frame time of advent for going out, the first frame of system time and record that calculating receives the query messages reaches video memory
System time time difference, and the time difference is advertised to into the splicing controller, so that the splicing controller can root
The time that Video Decoder head frames reach video memory is carried out according to the time difference and the time difference of other Video Decoder notices
It is synchronous with other Video Decoders.
4. method as claimed in claim 3, it is characterised in that the splicing controller is according to the time difference and other videos
The time difference of decoder notice carries out synchronous with other Video Decoders to the time that Video Decoder head frames reach video memory
Specially：On the basis of time difference maximum in the time difference of the notice, sending to the Video Decoder will for splicing controller
The first frame of record reaches the instruction for the time of video memory adjusting m milliseconds forward, and wherein m=a-b, a is the maximum time difference, and b is
The first frame of system time and record that the Video Decoder receives the query messages reaches the time difference of the system time of video memory.
5. method as claimed in claim 4, it is characterised in that when arbitrary Video Decoder in each Video Decoder is calculated
When difference between the time difference and the maximum time difference exceeds the display buffer time, splicing controller is to described
Video Decoder sends the message comprising emptying buffer order, and the Video Decoder is received after the message, according to the message
In the order of emptying buffer empty the data of screen buffer, return execution step A.
6. a kind of distributed image splices synchronizer, and the device is applied to the video solution in a kind of distributed splicing control system
Code device on, it is characterised in that it is described it is distributed splicing control system also include splicing controller, some sub- display screens and other
Video Decoder, wherein each Video Decoder is all connected to the splicing controller, each Video Decoder connects one
Or many sub- display screens, the device includes：
Decoding computing module, for decoding to the frame of video that the splicing controller is exported, and by decoded video counts
According to being stored in video memory, and when in the display output pregnancy ceased is given birth to, the theory of n-th frame is calculated according to formula Xn=(Tn-T1)+t1+d
The display output time；Wherein Xn represents the theoretical display output time of calculated n-th frame；T1 is represented and other video decodings
First frame after device synchronization reaches the system time of video memory；The T1 and Tn represent respectively in first frame and n-th frame carry when
Between stab；The d represents the display buffer time, and the time is the integral multiple that display output interrupts the generation cycle；The n is big
In 1 integer；The decoder produces the time of display output interruption and other decoders produce the time that display outputs are interrupted
It is synchronous；Frame is reached after video memory headed by the system time of the first frame arrival video memory, and the next display output of record interrupts generation
System time；
Output control module, for judging whether the current time for preparing to show n-th frame is more than or equal to the Xn；If so, it is then defeated
Go out the n-th frame data to be shown by the corresponding sub- display screen of the decoder；Otherwise, when next display output is interrupted and produced
Rejudge and whether export the n-th frame.
7. device as claimed in claim 6, it is characterised in that the decoding computing module is further used for：Receive by described
The multicast message comprising replacement order that splicing controller sends, and the replacement order replacement in the multicast message shows defeated
Go out chip, it is synchronous with other decoders to realize the display output break period.
8. device as claimed in claim 7, it is characterised in that the decoding computing module is further used for：When receive from
After the query messages of the first frame time of advent that the splicing controller sends, calculating receive the system time of the query messages with
The first frame of record reaches the time difference of the system time of video memory, and the time difference is advertised to into the splicing controller, so that
The splicing controller can be according to the time difference and the time difference of other Video Decoder notices to Video Decoder head frames
The time of arrival video memory carries out synchronous with other Video Decoders.
9. device as claimed in claim 8, it is characterised in that the splicing controller is according to the time difference and other videos
The time difference of decoder notice carries out synchronous with other Video Decoders to the time that Video Decoder head frames reach video memory
Specially：On the basis of time difference maximum in the time difference of the notice, sending to the Video Decoder will for splicing controller
The first frame of record reaches the instruction for the time of video memory adjusting m milliseconds forward, and wherein m=a-b, a is the maximum time difference, and b is
The first frame of system time and record that the Video Decoder receives the query messages reaches the time difference of the system time of video memory.
10. device as claimed in claim 9, it is characterised in that when arbitrary Video Decoder is calculated in each Video Decoder
The time difference and the maximum time difference between difference when exceeding the display buffer time, splicing controller is to institute
State Video Decoder and send the message comprising emptying buffer order, the output control module is further used for：Receive this to disappear
After breath, the order of the emptying buffer in the message empties the data of screen buffer.
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