CN100590600C - Computer system booting earlier stage debugging device - Google Patents
Computer system booting earlier stage debugging device Download PDFInfo
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- CN100590600C CN100590600C CN200410027243A CN200410027243A CN100590600C CN 100590600 C CN100590600 C CN 100590600C CN 200410027243 A CN200410027243 A CN 200410027243A CN 200410027243 A CN200410027243 A CN 200410027243A CN 100590600 C CN100590600 C CN 100590600C
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Abstract
The invention discloses a debugging device and its method before the computer system started which adopts accelerating collectrator structure. It comprises a computer system with PCI bus to debug before the computer started which has PIC surface interface, programmable integrated chip, BIOS register and LED display, wherein PIC surface interface is connected with a testing computer system's PIC interface; programmable integrated chip is connected with PIC surface interface, which has the same address with BIOS of testing computer system and can controls the replaced testing computer system's BISO operation by control program to achieve computer system auto testing and analyzes the malfunction of testing computer system; it displays the malfunction code at LED display and storages the control program into BIOS register.
Description
Technical field
The present invention relates to a kind of debuggers of computer system, particularly a kind of startup of computer system debugging equipment in early stage.
Background technology
Generally speaking, computer system architecture comprises central processing unit, input media, output unit, storer etc., and these assemblies all are to reach by bus to connect and functions such as data transmission, control.
In above-mentioned computer system architecture,, all might carry out the misarrangement function to computer system no matter in the development of computer main board or in the maintenance stage.Because the running in this computer system relates to quite complicated function command, by the assistance of debugging routine, the computer engineer just can analyze the reason that computer system makes a mistake.But general debugging routine after needs computer to be measured is finished normal startup, could be carried out the misarrangement function.May 30 calendar year 2001, disclosed application number was that 99124820.1 Chinese patent has proposed a kind ofly can't start or carrying out under the operating system under the situation of debugging routine at computer, the debugging equipment and the method thereof in launch computer early stage.Because this patent can only be applicable to that traditional employing comprises PCI (PerpheralComponent Interconnect, peripheral parts interconnected) in the computer system architecture of bus and ISA (Industry StandardArchitecture) bus, have certain use limitation.
Development along with computer technology, the up-to-date chipset (chip set) that Intel Company releases is made up of three chip blocks, be respectively MCH (Memory Controller Hub, internal memory and image controller), ICH (I/OController Hub, the I/O controller) and FWH (Fireware Hub, basic input and output are similar to BIOS).Because this new chipset has used special bus, be commonly referred to as and quicken hub architecture (AHA, Acclerated Hub Architechure).And used this chipset computer the system architecture synoptic diagram as shown in Figure 1.Wherein, central processing unit 110 is used for the data of the high-speed transfer in the disposal system, and internal memory and image controller 120 connect also control display card 121 and storer 122; I/O controller 130 connects internal memory and image controller 120, and connects and control hard disk 133, pci bus controller 131 and voice controller 150, and pci bus controller 131 is connected with pci interface 132, is used to expand the function of computer system; And the BIOS of basic input and output 140 similar and former computers, the store electricity brain system starts the program of self check in early stage and the self check of controlling computer system; I/O device controller 160 is connected with keyboard 161, mouse 162 and other serial line interface, parallel interface etc., the part work of sharing I/O controller 130 come and I/O equipment between the data of acceptance/transmission.
Therefore, for the computer system that adopts said structure, because in the past startup card or fault analysis card are not supported this computer system structure, when system can't start or during other fault, adopts in the past startup card or fault analysis card can not analyze and find out the system failure.And, for adopting the computer system of quickening hub architecture, when if computer system breaks down, general computer engineer can start computer system and enter the self-misarrangement of carrying out system after the operating system, thereby the computer engineer can find out the fault of system simply and easily; But can't finish when computer system and to start and when entering the operating system of self-misarrangement, the computer engineer just need come the analysis of failure place to the inspection that whole computer system is carried out gigantic project, this method takes time and effort, and it is lower to analyze out of order efficiency ratio, is unfavorable for computer system is carried out failure analysis.
Summary of the invention
In order to address the above problem, the present invention is based on the computer system of quickening hub architecture, a kind of fail analysis device that starts early stage that solves has been proposed.
The startup device in early stage of realizing computer system of the present invention has adopted following technical scheme: a kind of startup debugging equipment in early stage of computer system, be used for a computer system to be measured is carried out misarrangement, what this computer system adopted is to quicken hub architecture and comprise a pci bus, this debugging equipment comprises: a PCI interface, be used to connect the pci interface of a computer system to be measured, make to send/take orders between this computer system to be measured and this debugging equipment and data etc.; One integrated chip able to programme, be used to connect the PCI interface, its address is identical with the address of the BIOS of computer system to be measured, can control its BIOS that replaces computer system to be measured running by control program, realize the self check of computer system to be measured, and analyze the fault of computer system to be measured; And a BIOS storer, be used to store the control program of integrated chip able to programme; One light-emitting diode display is connected with integrated chip able to programme, is used to the reveal codes that shows that integrated chip able to programme provides.
This debugging equipment also comprises a gauge tap, and this gauge tap is connected between PCI interface and the integrated chip able to programme, is used to connect/disconnect the clock signal of integrated chip able to programme; Described control program is consistent with the bios program of computer system to be measured; Described integrated chip able to programme also comprises a write data latch circuit, can be in this circuit with the data latching on the pci bus interface, and be written to the BIOS storer.
Owing to adopted technique scheme, the present invention can be effectively to adopting the computer system of quickening hub architecture to carry out misarrangement, assist self check, and the failure code of demonstration computer system, can analyze the fault of computer system accurately according to this failure code, therefore, the present invention effectively improves the failure analysis ability to the computer system that has fault; Simultaneously, owing to can refresh the control program of debugging equipment very easily, therefore, this debugging equipment can adapt to the computer system that hub architecture is quickened in various employings.
Figure of description
Fig. 1 is the configuration diagram that adopts the computer system of quickening hub architecture.
Fig. 2 is the system architecture synoptic diagram of the startup debugging equipment in early stage of computer system of the present invention.
Fig. 3 is startup debugging equipment principle of work in the early stage synoptic diagram of computer system of the present invention.
Fig. 4 is the schematic flow sheet that adopts debugging equipment of the present invention to carry out misarrangement.
Embodiment
The startup debugging equipment in early stage of computer system of the present invention is applied to the computer system of acceleration hub architecture as shown in Figure 1, the present invention is described in further detail below in conjunction with Fig. 1, because basic input and output 140 function classes are similar to the BIOS of computer system in the past among Fig. 1, therefore in describing below, the BIOS of computer system 10 to be measured promptly refers to the basic input and output 140 among Fig. 1, or is expressed as BIOS.
Be illustrated in figure 2 as the system architecture synoptic diagram of the startup debugging equipment 20 in early stage of computer system of the present invention.This debugging equipment 20 comprises a PCI interface 210, integrated chip able to programme 220, BIOS storer and light-emitting diode display 230.Wherein PCI interface 210 is used to connect the pci interface 132 of a computer system 10 to be measured, makes can send/take orders between this computer system 10 to be measured and this debugging equipment 20 and data etc.; Integrated chip 220 able to programme, be used to connect PCI interface 210, its address is identical with the address of the BIOS of computer system 10 to be measured, can control its BIOS that replaces computer system 10 to be measured running by control program, realize the self check of computer system 10 to be measured, and analyze the fault of computer system 10 to be measured; And the BIOS storer, be used to store the control program of integrated chip 220 able to programme; With light-emitting diode display 230, it is connected with integrated chip 220 able to programme, is used to the reveal codes that shows that integrated chip 220 able to programme provides.This debugging equipment 20 also comprises a gauge tap 250, and this gauge tap 250 is connected PCI interface 210 and integrated chip 220 able to programme, is used to connect/disconnect the clock signal of integrated chip 220 able to programme.And the control program of integrated chip 220 able to programme is consistent with the bios program of computer system to be measured.
For adopting the computer system 10 of quickening hub architecture, its start-up course is roughly as follows: after opening the power switch of computer system 10, central processing unit 110 sends reset signal, makes system reset, simultaneously, central processing unit 110 control clock generators are sent clock signal to each electronic chip; Simultaneously, central processing unit 110 sends the system start-up address, the address of this address pointing system BIOS storer, this address converts the first address of corresponding basic input and output 140 to by the pci bus interface, and from basic input and output 140, read the start-up control program, this control procedure controlling computer system 10 detects one by one and comprises keyboard, mouse, serial line interface, parallel interface etc. and finish self check, starts the operating system of computer system 10 then.But, for the computer system 10 that has fault,, can find out guilty culprit by the help of debugging equipment 20 so, or finish the self check of system and start its operating system if it can not finish self check automatically.
Simultaneously, in conjunction with the principle of work synoptic diagram of debugging equipment shown in Figure 3 20 describe debugging equipment 20 specifically how to assist to exist fault computer system 10 startup and find out fault.In Fig. 3, circuit shown in the frame of broken lines is the internal circuit of integrated chip 220 able to programme.Behind computer system 10 power switches, 32 system start-up addresses that central processing unit 110 sends are latched this 32 system start-up addresses by after the PCI interface 210 by FRAME# in the pci bus and IRTY# signal controlling address latch circuit 221; Then, by address decoding circuitry 222 with this address decoding to BIOS interface circuit 225, and point to the address of the control program in the BIOS storer 240; Then, control circuit 224 can send the logic control signal that reads the control program in the BIOS storer 240, and control program is latched in the read data latch cicuit 226 by behind the BIOS interface circuit 225; And read data latch cicuit 226 is by after the PCI interface 210, control program is outputed to the pci bus interface, reach central processing unit 110 behind I/O controller 130 by computer system 10 and internal memory and the image controller 120 afterwards, central processing unit 110 instructs the self check of control system according to this control program; After so reading control program in the BIOS storer 240 through some this, system finishes self check.Wherein, address decoding circuitry 222 with the system start-up address decoding time the BIOS interface circuit 225, also output in the display circuit 223, after certain logical operation is carried out in the address of 223 pairs of decodings of this display circuit, be presented on the connected light-emitting diode display 230 in the mode of code; And control circuit 224 provides the control signal sequential of connected each circuit unit according to certain time sequence, guaranteeing in the cycle of same reading control program, and the work that each circuit unit in the integrated chip 220 able to programme can united and coordinating.
Wherein, the scope of system start-up address be FFFE0000 to FFFFFFFF, promptly the storage size of the BIOS storer 240 of debugging equipment 20 is 4M.When address latch cicuit 221 whenever reads the primary system enabling address, the address code after the corresponding decoding all can be presented on the light-emitting diode display 230.
Adopt schematic flow sheet that debugging equipment 20 of the present invention carries out misarrangement as shown in Figure 4.Behind the bios version consistent with the bios version of this debugging equipment 20 (promptly guaranteeing both content unanimities) of determining computer system 10 to be measured, adopt following steps to realize the startup misarrangement in early stage of computer system 10:
The step 302 of debugging equipment 20 is installed earlier, and the PCI interface part 210 that is about to debugging equipment 20 is inserted in the pci interface 132 of computer system 10 to be measured; Then, start the step 303 of dress debugging equipment 20, promptly connect the gauge tap 250 of dress debugging equipment 20; Opening computer 10 power supplys to be measured, the step 304 of beginning self check, at this moment, computer system 10 begins computer system 10 conscientious self checks according to the principle of work of above-mentioned debugging equipment 20; If self check is finished, computer system 10 enters DOS environment (step 306) so, if computer system 10 can not be finished self check, the light-emitting diode display 230 of debugging equipment 20 shows failure codes (step 307) so, then according to the interpretation of result fault (step 308) of step 306 and 307.
And, if computer system 10 can be finished self check, i.e. step 306, so, the code that this moment, light-emitting diode display 230 showed is FFFFFFFF; If computer system 10 can not be finished self check, i.e. step 307, so, the code that this moment, light-emitting diode display 230 showed is failure code for the address code when wrong occurring;
Simultaneously, Organization Chart in conjunction with computer to be measured 10 shown in Figure 1, specific as follows according to step 306 and 307 analysis of failure (step 308): when step 306 occurring, the fault that shows computer system is: the online fault of physics between I/O controller 130 and the basic input and output 140, or the program error in the basic input and output 140, the physics program online or that refresh in the basic input and output 140 that promptly can seek and reclose between I/O controller 130 and the basic input and output 140 is repaired computer system 10; If step is 307, at this moment, can be by reading the code on the light-emitting diode display 230 on the debugging equipment 20, this code is failure code, and this code and BIOS control program are compared, and just can judge the location of fault place accurately.
Certainly, if the bios version of the control program of debugging equipment 20 and computer system to be tested 10 is inconsistent, can refresh the control program of debugging equipment 20 so by following method, make its both unanimities: select a function good and have a computer system 10 that needs bios version, debugging equipment 20 after gauge tap 250 disconnections is inserted in the pci interface 132 of computer system 10, open the power supply of computer system 10, after entering operating system, this moment closed gauge tap 250 and move the BIOS refurbishing procedure; At this moment, BIOS data in the computer system 10 are widely read the pci bus interface by the control of BIOS refresh process, and by behind the pci interface circuit, be written in the write data latch circuit 227 in the integrated chip 220 able to programme, clock signal in the same one-period that provides according to control circuit 224 and, after the operation of BIOS refurbishing procedure finishes, promptly finish refreshing to the control program in the BIOS storer 240 of debugging equipment 20 by writing data into behind the BIOS interface circuit 225 in the BIOS storer 240.BIOS storer 240 can certainly be taken off, be loaded on the special-purpose BIOS CD writers, it is carried out refreshing of version.
Owing to adopted technique scheme, the present invention can be effectively to adopting the computer system of quickening hub architecture to carry out misarrangement, assist self check, and the failure code of demonstration computer system, can analyze the fault of computer system accurately according to this failure code, therefore, the present invention effectively improves the failure analysis ability to the computer system that has fault; Simultaneously, owing to can refresh the control program of debugging equipment very easily, therefore, this debugging equipment can adapt to the computer system that hub architecture is quickened in various employings.
Claims (12)
1. the startup of computer system debugging equipment in early stage is used for a computer system to be measured is carried out misarrangement, and this computer system comprises a pci bus, it is characterized in that, this debugging equipment comprises:
One PCI interface is used to connect the pci interface of a computer system to be measured, makes can send/take orders between this computer system to be measured and this debugging equipment and data etc.;
One integrated chip able to programme, be used to connect the PCI interface, its address is identical with the address of the BIOS of computer system to be measured, can control its BIOS that replaces computer system to be measured running by control program, realize the self check of computer system to be measured, and analyze the fault of computer system to be measured; And
One BIOS storer is used to store the control program of integrated chip able to programme;
One light-emitting diode display is connected with integrated chip able to programme, is used to the reveal codes that shows that integrated chip able to programme provides.
The startup of computer system as claimed in claim 1 early stage debugging equipment, it is characterized in that: this debugging equipment also comprises a gauge tap, this gauge tap is connected between PCI interface and the integrated chip able to programme, is used to connect/disconnect the clock signal of integrated chip able to programme.
The startup of computer system as claimed in claim 1 early stage debugging equipment, it is characterized in that: described control program is consistent with the bios program of computer system to be measured.
The startup of computer system as claimed in claim 1 early stage debugging equipment, it is characterized in that: comprise a display circuit in the described integrated chip able to programme, this display circuit can carry out logical operation, and central processing unit is shown on the light-emitting diode display the self-detection result of the computer system method with code.
The startup of computer system as claimed in claim 2 early stage debugging equipment, it is characterized in that: when described gauge tap is closed, computer system to be measured will be finished self check by debugging equipment and the control program that reads the BIOS storer, and the failure code of central processing unit to computer system is shown on the light-emitting diode display.
The startup of computer system as claimed in claim 1 early stage debugging equipment, it is characterized in that: described integrated chip able to programme comprises a BIOS interface circuit, it links to each other with the BIOS storer.
The startup of computer system as claimed in claim 1 early stage debugging equipment, it is characterized in that: described integrated chip able to programme comprises an address latch circuit, and it is in order to the enabling address of latched system.
8. as the startup of claim 1 or 6 described computer systems debugging equipment in early stage, it is characterized in that: described integrated chip able to programme comprises an address decoding circuitry, its in order to address decoding to the BIOS interface circuit, and point to control program address in the BIOS storer.
The startup of computer system as claimed in claim 1 early stage debugging equipment, it is characterized in that: described integrated chip able to programme comprises a write data latch circuit, it in this circuit, and is written to the BIOS storer with the data latching on the pci bus interface.
The startup of computer system as claimed in claim 1 early stage debugging equipment, it is characterized in that: described computer system is to adopt to quicken hub architecture.
11. the startup of computer system as claimed in claim 1 debugging equipment in early stage, it is characterized in that: described integrated chip able to programme comprises a read data latch cicuit, and it outputs to the pci bus interface with control program.
12. the startup of computer system as claimed in claim 1 debugging equipment in early stage, it is characterized in that: described integrated chip able to programme comprises a control circuit, and it is in order to send the logic control signal that reads control program in the BIOS storer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200410027243A CN100590600C (en) | 2004-05-20 | 2004-05-20 | Computer system booting earlier stage debugging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200410027243A CN100590600C (en) | 2004-05-20 | 2004-05-20 | Computer system booting earlier stage debugging device |
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| Publication Number | Publication Date |
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| CN1700182A CN1700182A (en) | 2005-11-23 |
| CN100590600C true CN100590600C (en) | 2010-02-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200410027243A Expired - Fee Related CN100590600C (en) | 2004-05-20 | 2004-05-20 | Computer system booting earlier stage debugging device |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102081562A (en) | 2009-11-30 | 2011-06-01 | 华为技术有限公司 | Equipment diagnosis method and system |
| CN111289885B (en) * | 2020-03-06 | 2022-06-03 | 湖南国科微电子股份有限公司 | Debugging system and method for power-on and power-off of chip |
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| CN1700182A (en) | 2005-11-23 |
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Granted publication date: 20100217 Termination date: 20120520 |