CN112861458A - Chip low-power consumption verification method - Google Patents
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- CN112861458A CN112861458A CN202110244312.7A CN202110244312A CN112861458A CN 112861458 A CN112861458 A CN 112861458A CN 202110244312 A CN202110244312 A CN 202110244312A CN 112861458 A CN112861458 A CN 112861458A
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- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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Abstract
The invention provides a chip low-power consumption verification method, which comprises the following steps: simulating the initial power-down state of the chip; simulating power-on reset of the chip; reading a boot mode and a starting address, reading a CPU instruction, carrying out case configuration according to a low-power-consumption scene of a chip, and carrying out CPU configuration standby; the subsystem configured with the deep sleep scene is in a power-down state, and can be directly recovered to a power-on state from the power-down state after being awakened, and the awakening mode needs to be subjected to traversal test; the subsystem configured with the light sleep scene is in a standby state without power failure, and is directly recovered to a working state from the standby state after awakening to come. The low-power-consumption case adopts SVA assertion to monitor the power-down and power-on time sequence in real time, reduces the workload of manual check of verification and greatly improves the working efficiency.
Description
Technical Field
The invention relates to a chip verification method, in particular to a chip low-power consumption verification method.
Background
With the increasingly complex application scenes of the chip and the increasingly high requirements for the power consumption of the chip, the low-power-consumption design of the chip becomes a critical performance index of the chip, and the low-power-consumption verification of the chip becomes an independent verification direction.
The currently generally adopted low-power-consumption verification is mainly performed in a PG netlist stage, the verification method mainly determines whether the power-off state can be awakened normally or not and whether the CPU can work normally or not after awakening from a waveform, and after a full-chip power-on time sequence and isolation enabling before the power-off state take effect, signal isolation value checking lacks of a system and comprehensive verification.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a chip low-power consumption verification method, which solves the low-power consumption case verification blind spot by automatically generating SVA assertion and compiling an automatic script.
The invention is realized by the following technical scheme:
a chip low-power consumption verification method comprises the following verification processes:
step 1, simulating an initial power-down state of a chip;
step 2, simulating power-on reset of the chip;
step 3, reading a boot mode and a starting address, reading a CPU instruction, carrying out case configuration according to a low-power-consumption scene of a chip, and carrying out CPU configuration standby;
step 4, if the case configuration scene is in the deep sleep mode, performing step 5, and if the case configuration scene is in the light sleep mode, performing step 6;
step 5, in the deep sleep mode, the subsystem enters a power-down state; the verification platform generates wake-up excitation in a simulated mode, after the state machine of the power management module receives the wake-up excitation, the power management module outputs a control signal to the chip simulation part, the chip simulation part provides power for the subsystem, and the subsystem jumps to a power-on state from a power-off state; or the power management module directly supplies power to the subsystem, and the subsystem jumps from a power-down state to a power-up state; after the subsystem is electrified again, the CPU is recovered to a normal state from a standby state, and boot is carried out again or the CPU is executed from an instruction pointer stored before standby; SVA assertion is added in the verification platform and is used for checking the time sequence of a state machine output control signal of the power management module and the power supply time sequence provided by the chip simulation part to the subsystem;
step 6, in the light sleep mode, the verification platform generates wake-up excitation in a simulation mode, and after the state machine of the power management module receives the wake-up excitation, the state machine of the power management module jumps to the wake-up state from the light sleep state; and the CPU is recovered to a normal state from a standby state, continues to read the instruction from the instruction address before the sleep, and executes subsequent operation.
Preferably, verification is performed at both the RTL simulation and PG netlist stages.
Further, in the RTL simulation stage, the CPF file is added in the simulation parameters and the CPF simulation parameters are set to perform low-power-consumption simulation; the CPF file is used for defining power domains, power-down conditions of all the power domains, isolation enabling effective conditions and signal isolation values.
Preferably, before step 1, writing an automation script, extracting a model containing an initial statement, adding the extracted model into the CPF file, and initializing the model after each power-on through parameter option setting.
Preferably, in step 5, before the power down of the power domain corresponding to the subsystem, the isolation enable takes effect, the SVA is adopted to assert whether the isolation value of the detection signal is correct, if not, the error reason is printed, and the simulation is stopped.
Further, the automatic SVA assertion generating process comprises: and extracting the signal isolation value defined when the isolation enable takes effect according to the CPF file isolation value definition and the isolation generating condition, and automatically generating SVA assertion.
Compared with the prior art, the invention has the following beneficial technical effects:
the low-power-consumption case adopts SVA assertion to monitor the power-down and power-on time sequence in real time, reduces the workload of manual check of verification and greatly improves the working efficiency. The low-power-consumption case scene is awakened by sleeping for multiple times in the same case, the awakening mode is completely covered, and the instruction reading mode after the CPU is awakened is traversed.
Furthermore, the invention carries out low power consumption verification in both the RTL simulation stage and the PG netlist verification stage, and finds the problem as early as possible.
Furthermore, in an RTL simulation stage, an automatic script is compiled, a model containing initial initialization operation is extracted, the model is added into a CPF file, and through parameter option configuration, the initialization statement can be executed again after the model is powered on every time, so that the simulation problem that the model cannot normally work due to the fact that signals inside the model are not initialized after the model is powered off and powered on for many times when the model is powered on and the initialization statement is executed only when the model is powered on for the first time is solved.
Furthermore, the isolation value is checked by adopting SVA assertion in the low-power-consumption case, so that the workload of manual checking for verification is reduced, and the working efficiency is greatly improved.
Drawings
FIG. 1 is a flow chart of low power verification for a specific chip of the present invention;
FIG. 2 is a flow chart of the automated generation isolation check of the present invention.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
The low-power consumption verification method of the chip comprises two stages of verification:
the first stage, RTL simulation (preceding stage simulation) stage, the verification process is as follows:
1. and modifying the verification platform to enable the low-power-consumption verification platform to simulate the chip to work in a charged mode. The common pre-stage simulation verification platform does not have a power-on process, the common pre-stage simulation verification platform directly works after the simulation starts, the low-power consumption verification is that the whole chip is shut down when the simulation starts, all force signals of the simulation verification platform are modified, and the configuration is carried out after the chip is powered on;
2. adding CPF related options to the simulation parameter options, wherein the CPF related options comprise loading CPF files (power domains are mainly defined, power failure conditions of all power domains, isolation enabling effective conditions and signal isolation values), and CPF simulation parameters;
3. modifying a CPF file, wherein the preceding-stage simulation comprises a plurality of models (ram, memory and the like), the v file comprises initial functions, initialization is carried out at the simulation time 0, low-power-consumption verification is carried out at the simulation time 0, the initialization work is not effective, after a chip is powered on, a control signal in the model can be in an x state to cause the x state to cause simulation abnormity (memory or ram data read-write failure and the like occur), in order to solve the problems, a python automatic script is written, the model containing the initial statements is extracted, the CPF file is modified, and the model is initialized again after being powered on through parameter option configuration (the extracted model is added by a set _ sim _ control command);
4. low power consumption use case scenario design
The chip power domain is divided into a normally open area and a power failure area, the normally open area indicates that the chip is always in a power-on state after being powered on, the power failure area indicates that the chip can be in a power failure state through different modes after being powered on, and the power failure area has two modes after being powered off: one is power-up of the register configuration. For a power failure area of a register for controlling power-on, power-on configuration needs to be added in a case main.c function, and whether the corresponding power failure area is powered on or not after CPU configuration is completed is confirmed from a simulation waveform; the other is that the state machine of the PMU module (power management module) in the normally-open area outputs a control signal to the full-chip analog part, the analog part carries out power-on operation on the power-off area of the digital part of the chip, the power-on time sequence needs to be checked according to the power-on time sequence (SVA assertion) of the chip, the time sequence of the control signal of the state machine is checked, and after the control signal is checked to be effective, whether the power-on of the corresponding power-off area is successful is judged.
The low-power-consumption scene configuration mainly comprises two scenes, namely a deep sleep scene and a light sleep scene. When a deep sleep scene is configured, the subsystem is in a power-down state, and can be directly recovered to a power-on state from the power-down state after being awakened. The wake-up mode requires a traversal test (e.g., timing wake-up, external pin edge triggered wake-up, etc.), and the modes of CPU (processor) reading instructions after wake-up are also different, and generally divided into a latency mode (after CPU recovers from the standby state, it continues to execute from a general instruction register stored before deep sleep) and a boot mode (after recovering from the standby state, it re-executes instructions according to the configured start address). The subsystem configured with the light sleep scene is in a standby state without power failure, and is directly recovered to a working state from the standby state after awakening to come. In the light sleep scene, the CPU is generally in a standby state, and after waking up, the CPU jumps to an instruction register pointer stored before the light sleep to continue executing.
As in fig. 2, the isolation value is checked. After a deep sleep scene is configured, the subsystem can enter a power-down state, and before power failure, if a key signal is not isolated to a certain fixed value, an X-state signal is contained, and if the X-state signal is used as an incoming signal of other power-on subsystems, the subsystem can be caused to process abnormity. Isolation value checking is one process that must be verified for low power consumption verification. Before the power failure, the isolation enabling can be pulled up firstly, then the power failure is carried out, after the isolation enabling is effective, a large number of signal isolation values need to be checked, the case is awakened after the power failure for many times, the workload of manual checking can be large, aiming at the problem, an automatic tool (python) is designed, the signal isolation values are extracted according to the CPF file isolation value definition and the isolation generating conditions, SVA assertion is automatically generated, the SVA assertion mainly checks that the isolation value enabling is pulled up, whether the signals are isolated to the corresponding values or not, if the corresponding values are not isolated, the SVA assertion fails, the printing failure reason is caused, and the simulation is stopped.
And in the second stage, verifying the PG netlist, wherein the verification process is as follows:
1. and modifying the code of the verification platform and simulating the chip power-on process. The verification platform simulates a chip power-on button (rising edge excitation) and a chip system clock, a simulation part (a chip simulation part model written by verilog) generates VDD | VSS and is connected to a digital end of a PG netlist after receiving a power-on control signal, and subsequent low-power-consumption scene simulation can be performed after the digital part normally supplies power;
2. and (3) continuing to use the first-stage simulation case, parallelly transplanting the case to a PG netlist for verification, wherein under a normal condition, except for time delay, the waveform of the PG netlist is consistent with the RTL simulation waveform, and after all the simulation cases pass, completing netlist verification.
Specifically, as shown in fig. 1, the chip low power consumption verification method of the present invention includes the following verification processes:
step 1, simulating an initial power-down state of a chip;
step 2, simulating power-on reset of the chip;
step 3, reading a boot mode and a starting address, reading a CPU instruction, carrying out case configuration according to a low-power-consumption scene of a chip, and carrying out CPU configuration standby;
step 4, if the case configuration scene is in the deep sleep mode, performing step 5, otherwise, performing step 6;
step 5, in the deep sleep mode, the subsystem enters a power-down state; the verification platform simulates to generate a wake-up excitation signal, after the state machine of the power management module (PMU) receives the wake-up excitation signal, the power management module control subsystem skips from a power failure state to a power-on state, and the subsystem can be controlled to recover from the power failure state in two ways: the first is that the power management module outputs control signals to the chip analog part, and the chip analog part provides power for the subsystem; the other is that the PMU module outputs a subsystem power signal (e.g. pwr signal) to directly control the subsystem power. And after the subsystem is powered on again, the CPU is recovered to a normal state from a standby state, and the instruction is executed again from the boot or from a sleep position.
Step 6, in a subsystem light sleep mode, a verification platform simulates and generates a wake-up stimulus, and a PMU (power management unit) jumps to a wake-up state from a light sleep state after receiving the wake-up stimulus; and the CPU is recovered to a normal state from a standby state, continues to read the instruction from the instruction address before the sleep, and executes subsequent operation.
And 5, before the power failure of the subsystem in the deep sleep mode, enabling the isolation to take effect, adopting the automatically generated SVA to assert whether the isolation value of the detection signal is correct or not, printing an error reason if the isolation value is incorrect, and stopping simulation. The automatic SVA assertion generation process comprises the following steps: providing an ISO _ EN and an ISO _ EN effective isolation value table file, reading table contents row by Python, extracting an isolation enabling value according to keyword matching and a signal isolation value when the isolation is effective, generating an SVA assertion for each signal isolation value, adopting an implication statement at each clock rising edge, if the isolation enabling is effective, defining an isolation value in the file at the current clock edge, asserting identification printing error information, printing the error signal isolation value and stopping simulation; and adding support SVA options into the simulation parameters, automatically generating SVA assertions and adding the SVA assertions into a use case SV file.
Claims (6)
1. A chip low-power consumption verification method is characterized by comprising the following verification processes:
step 1, simulating an initial power-down state of a chip;
step 2, simulating power-on reset of the chip;
step 3, reading a boot mode and a starting address, reading a CPU instruction, carrying out case configuration according to a low-power-consumption scene of a chip, and carrying out CPU configuration standby;
step 4, if the case configuration scene is in the deep sleep mode, performing step 5, and if the case configuration scene is in the light sleep mode, performing step 6;
step 5, in the deep sleep mode, the subsystem enters a power-down state; the verification platform generates wake-up excitation in a simulated mode, after the state machine of the power management module receives the wake-up excitation, the power management module outputs a control signal to the chip simulation part, the chip simulation part provides power for the subsystem, and the subsystem jumps to a power-on state from a power-off state; or the power management module directly supplies power to the subsystem, and the subsystem jumps from a power-down state to a power-up state; after the subsystem is electrified again, the CPU is recovered to a normal state from a standby state, and boot is carried out again or the CPU is executed from an instruction pointer stored before standby; SVA assertion is added in the verification platform and is used for checking the time sequence of a state machine output control signal of the power management module and the power supply time sequence provided by the chip simulation part to the subsystem;
step 6, in the light sleep mode, the verification platform generates wake-up excitation in a simulation mode, and after the state machine of the power management module receives the wake-up excitation, the state machine of the power management module jumps to the wake-up state from the light sleep state; and the CPU is recovered to a normal state from a standby state, continues to read the instruction from the instruction address before the sleep, and executes subsequent operation.
2. The method for verifying low power consumption of a chip as claimed in claim 1, wherein the low power consumption verification of the chip is performed in both stages of RTL simulation and PG netlist.
3. The chip low power consumption verification method according to claim 2, wherein in the RTL simulation stage, the low power consumption simulation is performed by adding a CPF file in the simulation parameters and setting the CPF simulation parameters; the CPF file is used for defining power domains, power-down conditions of all the power domains, isolation enabling effective conditions and signal isolation values.
4. The method for verifying the low power consumption of the chip as claimed in claim 1, wherein before step 1, an automation script is written, a model containing an initial statement is extracted, the extracted model is added to the CPF file, and the model is initialized again after being powered on every time through parameter option setting.
5. The method for verifying low power consumption of a chip according to claim 1, wherein in step 5, before a power domain corresponding to the subsystem is powered down, the isolation enable is enabled to take effect, SVA is adopted to assert whether an isolation value of the detection signal is correct or not, if not, a cause of error is printed, and simulation is stopped.
6. The chip low power consumption verification method according to claim 5, wherein the SVA assertion automatic generation process is: and extracting the signal isolation value defined when the isolation enable takes effect according to the CPF file isolation value definition and the isolation generating condition, and automatically generating SVA assertion.
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