CN110853695A

CN110853695A - Method for testing NVRAM storage performance

Info

Publication number: CN110853695A
Application number: CN201910986606.XA
Authority: CN
Inventors: 朱姝
Original assignee: Luoyang Institute of Electro Optical Equipment AVIC
Current assignee: Luoyang Institute of Electro Optical Equipment AVIC
Priority date: 2019-10-17
Filing date: 2019-10-17
Publication date: 2020-02-28

Abstract

The invention belongs to the technical field of electronics, and relates to a comprehensive test method for NVRAM (non-volatile random access memory) storage performance. The hardware resources required by the test method are a self-made test device and a tested object NVRAM, and the required software is a self-programming test program solidified in a memory of the self-test device. After the test device is powered on and started, the performance of the test device can be diagnosed, after the performance of the test device is confirmed to be normal, the test device starts to carry out online constant value, online variable value and offline storage performance test operation on the Nvram, and feeds back a test result. The problems of incompleteness and incapability of detecting the boundary of the conventional test are solved, and the complete test of NVRAM full storage space and synchronous detection of the upper network and the lower network is realized. The test method has the advantages of low cost, high reliability and easy realization.

Description

Method for testing NVRAM storage performance

Technical Field

The invention belongs to the technical field of electronics, and relates to a comprehensive testing method for NVRAM (non-volatile random access memory) storage performance.

Background

NVRAM (non-volatile random access memory) refers to semiconductor memory in which data is retained after power is removed. NVRAM is one of the most important storage devices in the present and future due to its good random addressing capability, and with the rapid development of mobile devices, portable devices and wireless devices, NVRAM has also met with unprecedented opportunities and has rapidly developed. The NVRAM has physical advantages of DRAM and SRAM, a fast transmission speed, a large monolithic capacity, and a long-term storage characteristic of a hard disk, and thus is widely applied to an automobile system, a communication system, a computer system, an industrial system, and the like.

And is also widely applied to onboard electronic equipment. The NVRAM used in the plug-in system outer hanging article management processor causes a NVRAN (RAM with a battery) to frequently break down due to the complexity of an onboard environment, the current testing method is simple, and at the present stage, a method for electrifying and testing a fixed space is generally adopted for testing a nonvolatile RAM, namely, a certain unit or a plurality of units of a storage space are subjected to read-write comparison to judge whether the storage is normal, but according to the display of the conventional fault data, the test is very unreliable, and the misjudgment rate is very high. The test method can not identify the failure of some memory units of the NVRAM, and can not effectively find the function of losing data after the power failure of the equipment caused by the failure of the self-contained battery, thereby causing the misjudgment of the equipment detection and influencing the normal training of troops. An efficient complete detection approach involving boundary testing is urgently needed to solve this problem.

Disclosure of Invention

The invention provides a comprehensive test method for NVRAM (non-volatile random access memory) storage performance, which solves the technical problems that the existing test method cannot identify the storage function failure of certain storage units of the NVRAM and cannot effectively find the function of losing data after the equipment is powered off due to the failure of a self-contained battery, thereby causing misjudgment on equipment detection and influencing the normal training of troops.

The technical scheme of the invention is as follows:

a method of testing NVRAM storage performance, comprising the steps of:

1) writing data 0x03 into all storage spaces of the NVRAM, reading the data of each storage space and comparing one by one to obtain comparison information whether the data are consistent with the written data; repeating the above process for multiple times and feeding back address information of the memory space with inconsistent comparison;

2) writing data 0xcc into all storage spaces of the NVRAM, reading the data of each storage space and comparing one by one to obtain comparison information whether the data are consistent with the written data; repeating the process and feeding back the address information of the storage space with inconsistent comparison;

3) writing data into the whole memory space of the NVRAM, writing starting data 0x01 from a memory cell corresponding to a starting address 0x0, and adding 1 to the data along with adding 1 to the address of the memory cell until 0xff is written into the memory cell with the address of 0x000000 fe; then, the memory cell with the address of 0x000000ff rewrites the initial data 0x01, the next memory cell writes the data from 0x01 again after the data is written to 0xff until the whole memory space of the NVRAM is fully written, and then the data is read one by one, and whether the data is consistent with the written variable value data is compared, and the address information and the input data information of the memory space with the inconsistent comparison are fed back;

4) and repeating the step 3) for multiple times and feeding back the address information and the input data information of the storage space with inconsistent comparison obtained in each comparison process.

Preferably: the number of repetitions of the write-compare-feedback process in step 1 is 20.

Preferably: the number of repetitions of the write-compare-feedback process in step 2) is 20.

Preferably: the number of repetitions of the write-compare-feedback process in step 4) is 20.

To obtain the best test results: the method for testing the NVRAM storage performance further comprises the step 5): and (4) according to the actual application and the performance index of the NVRAM, the NVRAM equipment is disconnected and stands still for a period of time, the NVRAM is reconnected, then the stored data of each storage unit is read again and compared with the written data, and the address information of the storage space with inconsistent comparison is fed back.

To obtain the best test results: the step 5) further comprises an environment simulation process, which specifically comprises the following steps: and (4) according to the actual application and the performance index of the NVRAM, the NVRAM equipment is disconnected from the network to simulate the external environment for a period of time, the NVRAM is reconnected, the stored data of each storage unit is read again and compared with the written data, and the address information of the storage space with inconsistent comparison is fed back.

To feed back the final overall test results: the method for testing the NVRAM storage performance further comprises the following step 6): and feeding back the position information of the storage space which is compared and consistent after the steps 1), 2), 3), 4) and 5) to a detection device for detecting the storage performance of the NVRAM, and calculating to obtain the storage performance information of the NVRAM.

To avoid test errors: the method for testing the storage performance of the NVRAM further comprises a test self-diagnosis step for completing the diagnosis of the operation module, the power supply, the controller and the excitation signal before the step 1).

THE ADVANTAGES OF THE PRESENT INVENTION

The test of the NVRAM storage performance of the invention has the following main advantages:

1) the problems of incompleteness and incapability of detecting boundaries of the conventional test are solved, the test of the full storage space is realized, and the NVRAM is completely tested;

2) the power-on work test is carried out again after the network is disconnected, the situation that the preloaded data cannot be read due to internal performance attenuation although the online normal reading can be carried out is avoided, and the full work cycle performance test of the NVRAM, particularly in the military field, is completed;

3) by utilizing the write variable value data, misjudgment caused by disconnection or adhesion of a certain address line can be avoided, and misjudgment caused by reading and writing in a low-order memory cell all the time due to the fault of a high-order address line can be effectively avoided by starting from 0x01 and adding 1 to write in data along with adding 1 to the address;

4) the test method is simple, easy, high in cost, comprehensive in test, high in accuracy, high in running speed, easy to realize, and applicable to other NVRAM chips, and only needs to change the address.

Drawings

FIG. 1 is a schematic structural diagram of a homemade test device for testing the performance of an NVRAM memory according to the present invention;

FIG. 2 is a schematic flow chart of a test method of the present invention;

FIG. 3 is a schematic diagram of a test procedure provided by an embodiment of the present invention;

fig. 4 is a schematic diagram of the circuit composition of an embodiment of the present invention.

Detailed Description

The invention will now be further described with reference to the accompanying drawings and specific embodiments thereof:

a method for testing the storage performance of an NVRAM comprises a built hardware circuit and a written test program. The hardware resources required by the test method are a self-made test device and a tested object NVRAM, and the required software is a self-programming test program solidified in a memory of the self-test device.

The self-made test device comprises an operation module, a storage module, a controller module, a bottom layer driving module, an application program module, a self-diagnosis module and a test interface, and is shown in detail in figure 1.

The operation module is a processing unit of the testing device and is mainly used for carrying out operation processing on various data and executing various instructions;

the controller module is a key control part for the coordination work among all the modules, and is used for transferring all the modules to carry out various works in order after logic operation according to an instruction sent by the processing module;

the storage module is mainly used for storing various operation data;

the bottom layer driving module is an operating system for ensuring the running of the testing device and is a program for managing hardware and software resources of the testing device;

the application program module is a main operation program for testing the NVRAM, and performs read-write operation on a test object according to the application program;

the self-diagnosis module mainly performs self-detection on the testing device before working so as to ensure normal working of the testing device, and then performs testing judgment on a testing object so as to avoid deviation of a testing result caused by abnormality of testing equipment.

The test program is an important component of the test method, and the test program can be used for detecting the whole storage space of the NVRAM. The test method mainly comprises three test units, wherein one test unit is an online fixed value test, the other test unit is an online variable value test, and the other test unit is a power-on work test after the network is disconnected.

1) On-line fixed value test, namely writing and fixing all storage spaces of the NVRAM through an operation module, reading data one by one unit, comparing whether the data is consistent with the written data or not, testing all the spaces for 20 times, and stopping testing and reporting fault information when the data of the existing storage units are inconsistent;

2) on-line variable value test, that is, when data is written into the storage space, the data is not all the same, and 0x01 is set to be written from the initial address, 1 is added to the data along with the address until the whole space is full, then the data is read one by one unit and compared whether the data is consistent with the written variable value data, the whole space is tested for 20 times, and when the data of the existing storage unit is inconsistent, the test is stopped and fault information is reported.

3) And (3) powering on again to perform work test after off-line, namely after the on-line test program is tested, writing data into the NVRAM storage space, placing for a period of time according to the actual application condition and the performance index of the object to be tested, then performing on-line work again, directly reading the data from the storage units one by one to compare with the pre-written data value, and stopping the test and reporting fault information when the data are inconsistent. And testing all the spaces for 20 times, and judging that the NVRAM is in failure after being off-line as long as inconsistent units exist, otherwise, testing the NVRAM normally.

When the online test program fails, the NVRAM can be judged to be in fault, and the NVRAM is not powered on again for testing after being disconnected from the network; and when the online test process is normal, performing online test after the second step of network disconnection, and if the test is normal, judging that the NVRAM storage performance is normal. The full-space coverage test is to perform writing and reading operations on all storage spaces of the NVRAM, and simultaneously, the written data is changed into a variable value, so that misjudgment caused by the fact that the fault of a certain unit happens to be consistent with the written data or the short circuit of an address line and a data line in a chip is avoided; after the NVRAM is written with data, the NVRAM is powered down and stored for a certain time according to actual application and performance indexes of the object to be tested, and then whether the internal data is stored normally is tested, so as to avoid the situation that although the data can be read normally on line, the NVRAM cannot store data when being powered up again due to internal battery failure, which is detailed in fig. 2.

The following is further illustrated with the test object as DS1744W and the storage space as 32 Kx 8 as an example:

the present invention includes both hardware and software components.

The self-diagnosis of the test device is completed by an excitation signal test, a power module test, a controller module test and an operation module test, and whether the test device works normally is judged by using the test output signals.

The excitation signal test is to introduce a 40M signal of excitation output into an auxiliary circuit, divide the frequency by two and send the signal into a resettable steady-state trigger circuit, when the excitation signal input is normal, the output of the steady-state trigger circuit is 1, and once no excitation signal is input, the output of the trigger circuit changes from high to low. Outputting the result, and testing the auxiliary circuit as the figure;

the power module test is to introduce power voltage (3.3V) into a threshold comparison circuit on an auxiliary circuit board, wherein the circuit mainly comprises two comparators, and the compared threshold voltages are respectively 3V and 3.6V. When the voltage is between 3V and 3.6V, the comparators N3 and N4 output 0, the triode is not conducted, and the output is 1; when the power supply voltage is greater than 3.6V, the comparator N3 outputs 5V, and the conduction output of the triode is 0; when the power supply voltage is less than 3V, the comparator N4 outputs 5V, and the triode is conducted and outputs 0V; when the power supply is normal, the output is 1, the fault output is 0, the result is output, and the test auxiliary circuit is as shown in the figure;

the controller module test is that when the controller module is normally started, a BG signal is output outwards, and a test auxiliary circuit is shown in the figure according to whether a state signal output when the controller module is judged to normally work is normal or not;

the operation module test is that when the operation module processor is normally started, BR signals are output outwards, the result is output according to whether the state signals output when the operation module processor is normally operated or not, and the test auxiliary circuit is as shown in the figure.

The test program is an important component of the test method, by which the detection of the entire memory space of the NVRAM is achieved. The test method mainly comprises three test units, wherein one test unit is used for online fixed value tests of 0x03 and 0xcc, the other test unit is used for online variable value tests, and the other test unit is used for power-on work tests after network disconnection.

1) In the online fixed value writing unit 1, the CPU is controlled to write data 0x03 into all storage spaces of the NVRAM, then the data are read one by one and compared to determine whether the data are consistent with the written data 0x03, all the spaces are tested for 20 times, and when the data of the existing storage units are inconsistent, the test is stopped and fault information is reported;

2) the online fixed value writing unit 2 writes data 0xcc to all storage spaces of the NVRAM from the control CPU, then reads the data one by one and compares whether the data is consistent with the written data 0xcc, all the spaces are tested for 20 times, and when the data of the existing storage units are inconsistent, the test is stopped and fault information is reported;

3) when the data is written into the memory space, the data is not all the same, 0x01 is written from a starting address 0x0 to a corresponding data unit, the data is written with 1 plus 1 along with the address until 0xff is written into the memory unit 0x000000fe, then the data 0x01 is rewritten into the memory unit 0x000000ff, the next memory unit is written into the memory unit from 0x01 again after the data is written into the memory unit 0xff until the whole space is full, the data is read from the unit by unit and is compared whether the data is consistent with the written variable value data, the test is carried out for 20 times in the whole space, and when the data of the existing memory unit is inconsistent, the test is stopped and the fault information is reported.

4) The re-electrifying work test after off-line is that after the on-line test program is tested, the NVRAM storage space is written with data, the external power supply is disconnected, the NVRAM is electrified after being placed for a period of time, the data are directly read from the storage units one by one and compared with the data value written in advance, and the test is stopped and the fault information is reported when the data are inconsistent. And testing the whole space for 20 times, judging that the NVRAM is in power-off storage failure as long as inconsistent units exist, and otherwise, testing the NVRAM normally.

The NVRAM adopted by the embodiment is DS1744, the method for testing the NVRAM storage performance is also applicable to testing other NVRAM chips, only correct connection is needed, and the test address space is changed.

Claims

1. A method of testing NVRAM storage performance, comprising the steps of:

2. The method of testing NVRAM storage performance of claim 1, wherein: the number of repetitions of the write-compare-feedback process in step 1 is 20.

3. The method of testing NVRAM storage performance of claim 2, wherein: the number of repetitions of the write-compare-feedback process in step 2) is 20.

4. A method of testing NVRAM storage performance according to claim 3, characterised in that: the number of repetitions of the write-compare-feedback process in step 4) is 20.

5. The method of testing NVRAM storage performance of claim 1, wherein: the method for testing the NVRAM storage performance further comprises the step 5): and (4) according to the actual application and the performance index of the NVRAM, the NVRAM equipment is disconnected and stands still for a period of time, the NVRAM is reconnected, then the stored data of each storage unit is read again and compared with the written data, and the address information of the storage space with inconsistent comparison is fed back.

6. The method of claim 5, wherein the testing of the NVRAM storage performance comprises: the step 5) further comprises an environment simulation process, which specifically comprises the following steps: and (4) according to the actual application and the performance index of the NVRAM, the NVRAM equipment is disconnected from the network to simulate the external environment for a period of time, the NVRAM is reconnected, the stored data of each storage unit is read again and compared with the written data, and the address information of the storage space with inconsistent comparison is fed back.

7. The method of claim 6, wherein the testing of the NVRAM storage performance comprises: the method for testing the NVRAM storage performance further comprises the following step 6): and feeding back the position information of the storage space which is compared and consistent after the steps 1), 2), 3), 4) and 5) to a detection device for detecting the storage performance of the NVRAM, and calculating to obtain the storage performance information of the NVRAM.

8. The method of testing NVRAM storage performance of claim 1, wherein: the method for testing the storage performance of the NVRAM further comprises a test self-diagnosis step for completing the diagnosis of the operation module, the power supply, the controller and the excitation signal before the step 1).