CN100458798C - 检查电路的方法 - Google Patents
检查电路的方法 Download PDFInfo
- Publication number
- CN100458798C CN100458798C CNB2004800264146A CN200480026414A CN100458798C CN 100458798 C CN100458798 C CN 100458798C CN B2004800264146 A CNB2004800264146 A CN B2004800264146A CN 200480026414 A CN200480026414 A CN 200480026414A CN 100458798 C CN100458798 C CN 100458798C
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- circuit
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000012360 testing method Methods 0.000 title abstract description 5
- 238000012545 processing Methods 0.000 claims description 25
- 239000013078 crystal Substances 0.000 claims description 3
- 230000008676 import Effects 0.000 claims description 2
- 238000009434 installation Methods 0.000 claims 18
- 230000001915 proofreading effect Effects 0.000 claims 1
- 238000007689 inspection Methods 0.000 description 17
- 230000005669 field effect Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 230000001419 dependent effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000005284 excitation Effects 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 101500027295 Homo sapiens Sperm histone HP3 Proteins 0.000 description 3
- 102400000926 Sperm histone HP3 Human genes 0.000 description 3
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- 239000004065 semiconductor Substances 0.000 description 2
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- 230000001052 transient effect Effects 0.000 description 1
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Images
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
Claims (26)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10343344A DE10343344B4 (de) | 2003-09-12 | 2003-09-12 | Verfahren zum Prüfen einer elektrischen Schaltung |
DE10343344.9 | 2003-09-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1849609A CN1849609A (zh) | 2006-10-18 |
CN100458798C true CN100458798C (zh) | 2009-02-04 |
Family
ID=34305903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004800264146A Expired - Fee Related CN100458798C (zh) | 2003-09-12 | 2004-08-31 | 检查电路的方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7636903B2 (zh) |
EP (1) | EP1665104A2 (zh) |
JP (1) | JP2007505295A (zh) |
CN (1) | CN100458798C (zh) |
DE (1) | DE10343344B4 (zh) |
WO (1) | WO2005026994A2 (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100688525B1 (ko) * | 2005-01-26 | 2007-03-02 | 삼성전자주식회사 | 이벤트 구동 스위치 레벨 시뮬레이션 방법 및 시뮬레이터 |
US7581199B1 (en) * | 2005-08-08 | 2009-08-25 | National Semiconductor Corporation | Use of state nodes for efficient simulation of large digital circuits at the transistor level |
TWI448711B (zh) * | 2012-01-13 | 2014-08-11 | Realtek Semiconductor Corp | 產生積體電路模型的方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3851161A (en) * | 1973-05-07 | 1974-11-26 | Burroughs Corp | Continuity network testing and fault isolating |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4907180A (en) | 1987-05-04 | 1990-03-06 | Hewlett-Packard Company | Hardware switch level simulator for MOS circuits |
JPH0652253A (ja) | 1992-07-27 | 1994-02-25 | Hitachi Ltd | 回路のシミュレーション方法及びその装置 |
JPH11186398A (ja) | 1997-12-19 | 1999-07-09 | Sharp Corp | 半導体集積回路の回路シミュレーションを行うためのデータ作成方法及びデータ作成システム |
US6055366A (en) * | 1998-02-23 | 2000-04-25 | Advanced Micro Devices, Inc. | Methods and apparatus to perform high voltage electrical rule check of MOS circuit design |
US6117179A (en) * | 1998-02-23 | 2000-09-12 | Advanced Micro Devices, Inc. | High voltage electrical rule check program |
US6499129B1 (en) * | 1998-07-22 | 2002-12-24 | Circuit Semantics, Inc. | Method of estimating performance of integrated circuit designs |
WO2000057317A1 (en) * | 1999-03-19 | 2000-09-28 | Moscape, Inc. | System and method for performing assertion-based analysis of circuit designs |
US6389578B1 (en) * | 1999-05-26 | 2002-05-14 | Hewlett-Packard Company | Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit |
JP2001014368A (ja) | 1999-06-30 | 2001-01-19 | Mitsubishi Electric Corp | クロック解析装置およびクロック解析方法 |
DE10106247A1 (de) * | 2000-09-29 | 2002-10-31 | Continental Teves Ag & Co Ohg | Verfahren und System zur numerischen Simulation von elektrischen Netzwerken |
US6898546B2 (en) * | 2001-10-31 | 2005-05-24 | Infineon Technologies Ag | Method for processing data representing parameters relating to a plurality of components of an electrical circuit, computer readable storage medium and data processing system containing computer-executable instructions for performing the method |
US20030093504A1 (en) * | 2001-10-31 | 2003-05-15 | Tilmann Neunhoeffer | Method for processing data containing information about an electronic circuit having a plurality of hierarchically organized networks, computer readable storage medium and data processing system containing computer-executable instructions for performing the method |
US7240316B2 (en) * | 2002-04-16 | 2007-07-03 | Micron Technology, Inc. | Apparatus and method to facilitate hierarchical netlist checking |
DE10343346B4 (de) * | 2003-09-12 | 2011-01-27 | Qimonda Ag | Verfahren zum Prüfen einer elektrischen Schaltung und Einrichtung zur Durchführung des Verfahrens |
-
2003
- 2003-09-12 DE DE10343344A patent/DE10343344B4/de not_active Expired - Fee Related
-
2004
- 2004-08-31 CN CNB2004800264146A patent/CN100458798C/zh not_active Expired - Fee Related
- 2004-08-31 EP EP04762738A patent/EP1665104A2/de not_active Withdrawn
- 2004-08-31 WO PCT/DE2004/001951 patent/WO2005026994A2/de active Search and Examination
- 2004-08-31 JP JP2006525617A patent/JP2007505295A/ja active Pending
-
2006
- 2006-03-10 US US11/372,754 patent/US7636903B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3851161A (en) * | 1973-05-07 | 1974-11-26 | Burroughs Corp | Continuity network testing and fault isolating |
Non-Patent Citations (4)
Title |
---|
Electrical debugging of synchronous MOSVLSIcircuitsexploiting analysis of the intended logicbehaviour*. I.Bolsens,W.De Rammelaere,L.Claesen,H.De Man.proceedings of the 26th ACM/IEEE Design Automation Conference. 1989 |
Electrical debugging of synchronous MOSVLSIcircuitsexploiting analysis of the intended logicbehaviour*. I.Bolsens,W.De Rammelaere,L.Claesen,H.De Man.proceedings of the 26th ACM/IEEE Design Automation Conference. 1989 * |
Transistor-Level Estimation of Worst-Case Delays inMOS VLSI Circuits. Michel R.Dagenais,Serge Gaiotti,Nicholas C.Rumin.IEEE Transactions on Computed-aided Design of Integrated Circuits and Systems,Vol.11 No.3. 1992 |
Transistor-Level Estimation of Worst-Case Delays inMOS VLSI Circuits. Michel R.Dagenais,Serge Gaiotti,Nicholas C.Rumin.IEEE Transactions on Computed-aided Design of Integrated Circuits and Systems,Vol.11 No.3. 1992 * |
Also Published As
Publication number | Publication date |
---|---|
WO2005026994A2 (de) | 2005-03-24 |
DE10343344B4 (de) | 2006-04-20 |
JP2007505295A (ja) | 2007-03-08 |
US7636903B2 (en) | 2009-12-22 |
US20060230372A1 (en) | 2006-10-12 |
WO2005026994A3 (de) | 2005-09-01 |
CN1849609A (zh) | 2006-10-18 |
DE10343344A1 (de) | 2005-05-04 |
EP1665104A2 (de) | 2006-06-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
C56 | Change in the name or address of the patentee | ||
CP01 | Change in the name or title of a patent holder |
Address after: Munich, Germany Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: Infineon Technologies AG |
|
TR01 | Transfer of patent right |
Effective date of registration: 20120920 Address after: Munich, Germany Patentee after: QIMONDA AG Address before: Munich, Germany Patentee before: Infineon Technologies AG |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20151230 Address after: German Berg, Laura Ibiza Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: QIMONDA AG |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090204 Termination date: 20160831 |