CA1310710C - Process and arrangement for the monitoring of a clock signal - Google Patents
Process and arrangement for the monitoring of a clock signalInfo
- Publication number
- CA1310710C CA1310710C CA000594886A CA594886A CA1310710C CA 1310710 C CA1310710 C CA 1310710C CA 000594886 A CA000594886 A CA 000594886A CA 594886 A CA594886 A CA 594886A CA 1310710 C CA1310710 C CA 1310710C
- Authority
- CA
- Canada
- Prior art keywords
- flop
- output
- input
- signal
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
- G01R23/15—Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements (indicating that pulse width is above or below a certain limit)
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Heidelberger Druckmaschinen Aktiengesellschaft Abstract In a process for the monitoring of a clock signal, a bistable element is brought to a first state by pulses of the clock signal. On the occurrence of pulses of a reference signal, the frequency of said reference signal being lower than the frequency of the clock signal, the state of the bistable element is scanned and is outputted as an output signal. After such scanning, the bistable element is set to a second state.
Description
1 3 1 07 1 o Heidelberger Druckmaschinen Aktiengesellschaft Process and arrangement for the monitoring of a clock signal The invention relates to a process and an arrangement for the monitoring of a clock signal.
The functioning of electronic control apparatuses frequently depends on the presence of a clock signal.
If, because of a fault in the clock-signal generator, there is no clock signal, this may result in malfunctions tha~ may lead to serious damage in certain individual cases.
The object of the present invention is to indicate a process for the monitoring of a clock signal, said process being able to be implemented with little outlay on circuitry.
The process according to the invention is characterized in that a bistable element is brought to a first state by pulses of the clock signal, in that, on the occurrence of pulses of a reference signal, the frequency of said reference signal being lower than the frequency of the clock signal, the state of the bistable element is scanned and is outputted as an output signal and ;n that, after such scanning, the bistable element is set to a second state.
Preferably, at specified edges of the clock signal and of the reference signal, the b;stable element is brought ~31()710 to the first state and the state of the bistable element is scanned.
A further development of the process according to the invention consists in that the reference signal is derived from the mains voltage. This results in a particularly s1mple and reliable method of producing the reference signal.
An advantageous arrangement for the implementation of the process according to the invention is characterized in that the clock signal can be ~upplied to the clock input of a first delay flip-flop, the D input of said first delay flip-flop being connected to a fixed logic level and its output being connected to the D input of a second delay flip-flop, in that the reference signal can be supplied to the clock inputs of the second delay flip-flop and of a monostable multivibrator, in that an output of th~ second delay flip-flop forms the output of the arrangement and in that an output of the monostable multivibrator is connected to the reset input of the first delay flip-flop.
In a further development of the arrangement according to the invention, it is provided that a turn-on reset signal can be supplied to the set inputs of the delay flip-flops and to the reset input of the monostable multivibrator. In control apparatuses that, after turning-on, are brought anyway to an initial state by a turn-on reset signal, this further development makes it possible without any additional effort for the arrangement according to the invention to commence the monitoring of the clock signal immediately after turning-on.
In a further development of the arrangement according to the invention, a simple method of producing the reference signal is provided in that a threshold-value circuit is provided for the derivation of the reference signal from the mains voltage.
A specimen embodiment of the invention is explained in greater detail in the following description and is represented in the drawings with reference to several Figures, in which:
Fig. 1 shows a block diagram of the specimen embodiment;
and Fig. 2 shows timing diagrams of the signals occurring in the arrangement according to Fig. 1.
The arrangement shown in Fig. t consists of two delay flip-flops 1, 2 and of a monostable multivibrator 3.
The clock signal T that is to be monitored is supplied to the clock input of the delay flip-flop 1 via an input 4. The D input of the delay flip-flop is connected to the operating voltage Vcc. The output Q of the delay flip-flop 1 is connected to the D input of the delay flip-flop 2, while the output Q of the delay flip-flop 2 forms the output 5 of the arrangement. The reference signal SYN is supplied to the clock inputs of the delay flip-flop 2 and of the monostable multivibrator 3. The s;gnal at the output Q of the monostable multivibrator 3 is used for resetting the delay flip-flop l and is sent for this purpose to a dynamic reset input of the delay flip-flop 1. A turn-on reset signal supplied at 7 sets the two delay flip-flops 1, 2 and is additionally fed to a reset input of the monostable multivibrator 3.
1 3 1 07 1 ~
The reference signal SYN is derived from the mains voltage by a threshold~value circuit 8, for which purpose an input g is supplied with an alternating-current voltage that is drawn from the secondary winding (not shown) of a mains transformer.
The operating principle of the arrangement according to Fig. 1 and the process accor~ing to the invention are explained in the following with reference to Fig. 2.
The signal shown in line a) in Fig. 2 is a wave-form signal obtained from the mains voltage. With regard to the clock signal T shown in line b), it is assumed that there are two pulses and that there is then no clock signal.
Line c) represents the output signal of the delay flip-flop 1. It is brought to the value 1 with the leading edge of the clock signal T. On arrival of the leading edge of the reference signal SYN, the value of the output signal S1 of the delay flip-flop 1 is transferred to the delay flip-flop 2, whereupon the output signal S2 (line d)) of the delay flip-flop 2 likewise assumes the value 1. At the same time, the monostable multivibrator 3 (Fig. 1), whose output signal is shown in line e), is clocked. The delay flip-flop 1 is reset with the leading edge of the output signal M.
This is repeated as long as the clock signal T is present. If, however, it fails to appear, the output signal S1 of the delay flip-flop 1 is not set to the value 1, with the result that a 1 cannot be transferred to the delay flip-flop 2. The output 5 therefore switches to O, which may be indicated by a suitable indication device. Depending on the particular requirements, it is also possible for other measures to be taken, such as the automatic stopping of a machine.
The functioning of electronic control apparatuses frequently depends on the presence of a clock signal.
If, because of a fault in the clock-signal generator, there is no clock signal, this may result in malfunctions tha~ may lead to serious damage in certain individual cases.
The object of the present invention is to indicate a process for the monitoring of a clock signal, said process being able to be implemented with little outlay on circuitry.
The process according to the invention is characterized in that a bistable element is brought to a first state by pulses of the clock signal, in that, on the occurrence of pulses of a reference signal, the frequency of said reference signal being lower than the frequency of the clock signal, the state of the bistable element is scanned and is outputted as an output signal and ;n that, after such scanning, the bistable element is set to a second state.
Preferably, at specified edges of the clock signal and of the reference signal, the b;stable element is brought ~31()710 to the first state and the state of the bistable element is scanned.
A further development of the process according to the invention consists in that the reference signal is derived from the mains voltage. This results in a particularly s1mple and reliable method of producing the reference signal.
An advantageous arrangement for the implementation of the process according to the invention is characterized in that the clock signal can be ~upplied to the clock input of a first delay flip-flop, the D input of said first delay flip-flop being connected to a fixed logic level and its output being connected to the D input of a second delay flip-flop, in that the reference signal can be supplied to the clock inputs of the second delay flip-flop and of a monostable multivibrator, in that an output of th~ second delay flip-flop forms the output of the arrangement and in that an output of the monostable multivibrator is connected to the reset input of the first delay flip-flop.
In a further development of the arrangement according to the invention, it is provided that a turn-on reset signal can be supplied to the set inputs of the delay flip-flops and to the reset input of the monostable multivibrator. In control apparatuses that, after turning-on, are brought anyway to an initial state by a turn-on reset signal, this further development makes it possible without any additional effort for the arrangement according to the invention to commence the monitoring of the clock signal immediately after turning-on.
In a further development of the arrangement according to the invention, a simple method of producing the reference signal is provided in that a threshold-value circuit is provided for the derivation of the reference signal from the mains voltage.
A specimen embodiment of the invention is explained in greater detail in the following description and is represented in the drawings with reference to several Figures, in which:
Fig. 1 shows a block diagram of the specimen embodiment;
and Fig. 2 shows timing diagrams of the signals occurring in the arrangement according to Fig. 1.
The arrangement shown in Fig. t consists of two delay flip-flops 1, 2 and of a monostable multivibrator 3.
The clock signal T that is to be monitored is supplied to the clock input of the delay flip-flop 1 via an input 4. The D input of the delay flip-flop is connected to the operating voltage Vcc. The output Q of the delay flip-flop 1 is connected to the D input of the delay flip-flop 2, while the output Q of the delay flip-flop 2 forms the output 5 of the arrangement. The reference signal SYN is supplied to the clock inputs of the delay flip-flop 2 and of the monostable multivibrator 3. The s;gnal at the output Q of the monostable multivibrator 3 is used for resetting the delay flip-flop l and is sent for this purpose to a dynamic reset input of the delay flip-flop 1. A turn-on reset signal supplied at 7 sets the two delay flip-flops 1, 2 and is additionally fed to a reset input of the monostable multivibrator 3.
1 3 1 07 1 ~
The reference signal SYN is derived from the mains voltage by a threshold~value circuit 8, for which purpose an input g is supplied with an alternating-current voltage that is drawn from the secondary winding (not shown) of a mains transformer.
The operating principle of the arrangement according to Fig. 1 and the process accor~ing to the invention are explained in the following with reference to Fig. 2.
The signal shown in line a) in Fig. 2 is a wave-form signal obtained from the mains voltage. With regard to the clock signal T shown in line b), it is assumed that there are two pulses and that there is then no clock signal.
Line c) represents the output signal of the delay flip-flop 1. It is brought to the value 1 with the leading edge of the clock signal T. On arrival of the leading edge of the reference signal SYN, the value of the output signal S1 of the delay flip-flop 1 is transferred to the delay flip-flop 2, whereupon the output signal S2 (line d)) of the delay flip-flop 2 likewise assumes the value 1. At the same time, the monostable multivibrator 3 (Fig. 1), whose output signal is shown in line e), is clocked. The delay flip-flop 1 is reset with the leading edge of the output signal M.
This is repeated as long as the clock signal T is present. If, however, it fails to appear, the output signal S1 of the delay flip-flop 1 is not set to the value 1, with the result that a 1 cannot be transferred to the delay flip-flop 2. The output 5 therefore switches to O, which may be indicated by a suitable indication device. Depending on the particular requirements, it is also possible for other measures to be taken, such as the automatic stopping of a machine.
Claims (9)
1. Process for the monitoring of a clock signal, characterized in that a bistable element is brought to a first state by pulses of the clock signal, in that, on the occurrence of pulses of a reference signal, the frequency of said reference signal being lower than the frequency of the clock signal, the state of the bistable element is scanned and is outputted as an output signal, in that, after such scanning, the bistable element is set to a second state, and in that the reference signal is derived from the mains voltage.
2. Process according to claim 1, characterized in that, at specified edges of the clock signal and of the reference signal, the bistable element is brought to the first state and the state of the bistable element is scanned.
3. Arrangement for the implementation for the process according to claim 1, characterized in that the clock signal is supplied to the clock input of a first delay flip-flop (1), the D input of said first delay flip-flop (1) is connected to a fixed logic level and its output is connected to the D input of a second delay flip-flop (2), in that the reference signal is supplied to the clock inputs of the second delay flip-flop and of a monostable multivibrator (3), in that an output of the second delay flip-flop (2) forms the output (5) of the arrangement, and in that an output of the monostable multivibrator (3) is connected to the reset input of the first delay flip-flop (1).
4. In a process for the monitoring of a clock signal, characterized in that a bistable element is brought to a first state by pulses of the clock signal, in that, on the occurrence of pulses of a reference signal, the frequency of said reference signal being lower than the frequency of the clock signal, the state of the bistable element is scanned and is outputted as an output signal, and in that, after such scanning, the bistable element is set to a second state, an arrangement for implementing the process characterized in that the clock signal is supplied to the clock input of a first delay flip-flop (1), the D input of said first delay flip-flop (1) is connected to a fixed logic level and its output is connected to the D input of a second delay flip-flop (2), in that the reference signal is supplied to the clock inputs of the second delay flip-flop and of a monostable multivibrator (3), in that an output of the second delay flip-flop (2) forms the output (5) of the arrangement, and in that an output of the monostable multivibrator (3) is connected to the reset input of the first delay flip-flop (1).
5. Arrangement according to claim 3, characterized in that a turn-on reset signal is supplied to the set inputs of the delay flip flops (1, 2) and to the reset input of the monostable multivibrator (3).
6. Arrangement according to claim 3, characterized in that said arrangement includes a threshold-value circuit (8) for the derivation of the reference signal from the mains voltage.
7. In a process according to claim 4, including providing a turn-on reset signal supplied to the set inputs of the delay flip-flops (1, 2) and to the reset input of the monostable multivibrator (3).
8. In a process according to claim 4, wherein said arrangement includes a threshold-value circuit (8) for derivation of the reference signal from the mains voltage.
9. Device for performing a method of monitoring a clock signal, comprising a first D-flip-flop having a clock input for receiving a clock signal, an input connected to a fixed logic level, and an output; a second D-flip-flop having an input connected to said output of said first D-flip-flop, and having a clock input;
a monostable multivibrator having a clock input and output; and means for supplying a reference signal to said clock inputs of said second D-flip-flop and said monostable multivibrator, said output of said second D-flip-flop forming the output of the device, and said first D-flip-flop having a reset input to which said output of said monostable multivibrator is connected;
wherein said means for supplying a reference signal comprise a threshold-value circuit connected to AC-main voltage for deriving said reference signal from the AC-main voltage.
a monostable multivibrator having a clock input and output; and means for supplying a reference signal to said clock inputs of said second D-flip-flop and said monostable multivibrator, said output of said second D-flip-flop forming the output of the device, and said first D-flip-flop having a reset input to which said output of said monostable multivibrator is connected;
wherein said means for supplying a reference signal comprise a threshold-value circuit connected to AC-main voltage for deriving said reference signal from the AC-main voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3815531.1 | 1988-05-06 | ||
| DE3815531A DE3815531A1 (en) | 1988-05-06 | 1988-05-06 | METHOD AND ARRANGEMENT FOR MONITORING A CLOCK SIGNAL |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1310710C true CA1310710C (en) | 1992-11-24 |
Family
ID=6353834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000594886A Expired - Lifetime CA1310710C (en) | 1988-05-06 | 1989-03-28 | Process and arrangement for the monitoring of a clock signal |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5028813A (en) |
| EP (1) | EP0340479B1 (en) |
| JP (1) | JPH01318427A (en) |
| AU (1) | AU616258B2 (en) |
| CA (1) | CA1310710C (en) |
| DE (2) | DE3815531A1 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2923929B2 (en) * | 1990-09-14 | 1999-07-26 | 安藤電気株式会社 | Start match circuit for asynchronous signal |
| US6060879A (en) * | 1995-09-07 | 2000-05-09 | Core Engineering Inc. | Current magnitude sensing circuit |
| US5787114A (en) * | 1996-01-17 | 1998-07-28 | Lsi Logic Corporation | Loop-back test system and method |
| US5781544A (en) * | 1996-01-17 | 1998-07-14 | Lsi Logic Corporation | Method for interleaving network traffic over serial lines |
| US5956370A (en) * | 1996-01-17 | 1999-09-21 | Lsi Logic Corporation | Wrap-back test system and method |
| US5781038A (en) * | 1996-02-05 | 1998-07-14 | Lsi Logic Corporation | High speed phase locked loop test method and means |
| US5896426A (en) * | 1996-02-05 | 1999-04-20 | Lsi Logic Corporation | Programmable synchronization character |
| US6208621B1 (en) | 1997-12-16 | 2001-03-27 | Lsi Logic Corporation | Apparatus and method for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency |
| US6341142B2 (en) | 1997-12-16 | 2002-01-22 | Lsi Logic Corporation | Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method |
| US6331999B1 (en) | 1998-01-15 | 2001-12-18 | Lsi Logic Corporation | Serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream |
| US9568520B2 (en) * | 2014-05-16 | 2017-02-14 | Hamilton Sundstrand Corporation | Frequency detection circuits |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2634867A (en) * | 1968-08-26 | 1970-03-26 | Electric Control & Engineering Limited | Improvements in sensing, latching and initiation circuits |
| AU407236B2 (en) * | 1969-01-20 | 1970-10-12 | The Bunker Ramo Corporation | Flipflop circuit |
| AU485452B2 (en) * | 1974-09-13 | 1976-03-18 | Iwatani & Co., Ltd | an ELECTRONIC TIMER SWITCH PREVENTING THERE-STARTING OFA UNIT WITHIN ACERTAIN TIMED INTERVAL |
| JPS5235009U (en) * | 1975-09-02 | 1977-03-12 | ||
| DE2644646C2 (en) * | 1976-10-02 | 1983-04-07 | Robert Bosch Gmbh, 7000 Stuttgart | Device for detecting one or more missing pulses in an otherwise regular pulse train |
| DE2848641C2 (en) * | 1978-11-09 | 1982-08-19 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Circuit arrangement for signal-technically safe monitoring of a pulse train |
| US4380815A (en) * | 1981-02-25 | 1983-04-19 | Rockwell International Corporation | Simplified NRZ data phase detector with expanded measuring interval |
| US4467285A (en) * | 1981-12-21 | 1984-08-21 | Gte Automatic Electric Labs Inc. | Pulse monitor circuit |
| JPS5917893A (en) * | 1982-07-16 | 1984-01-30 | Mitsubishi Electric Corp | Control device for motor |
| JPS5941925A (en) * | 1982-08-31 | 1984-03-08 | Fujitsu Ltd | Clock selecting circuit |
| JPS6037815A (en) * | 1983-08-09 | 1985-02-27 | Nec Corp | Clock detecting circuit |
| US4583013A (en) * | 1984-02-13 | 1986-04-15 | Rockwell International Corporation | Oscillator signal detect circuit |
| US4628269A (en) * | 1984-05-23 | 1986-12-09 | Motorola, Inc. | Pulse detector for missing or extra pulses |
| JPH0634296B2 (en) * | 1985-05-27 | 1994-05-02 | キヤノン株式会社 | Dropout detection device |
| DE3632840A1 (en) * | 1986-09-26 | 1988-04-07 | Endress Hauser Gmbh Co | METHOD AND ARRANGEMENT FOR TRANSMITTING BINARY CODED INFORMATION IN A MEASURING ARRANGEMENT |
-
1988
- 1988-05-06 DE DE3815531A patent/DE3815531A1/en active Granted
-
1989
- 1989-03-28 CA CA000594886A patent/CA1310710C/en not_active Expired - Lifetime
- 1989-04-10 DE DE8989106289T patent/DE58904858D1/en not_active Revoked
- 1989-04-10 EP EP89106289A patent/EP0340479B1/en not_active Revoked
- 1989-04-20 AU AU33208/89A patent/AU616258B2/en not_active Ceased
- 1989-05-02 JP JP1112286A patent/JPH01318427A/en active Pending
- 1989-05-08 US US07/348,972 patent/US5028813A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE3815531C2 (en) | 1990-08-16 |
| JPH01318427A (en) | 1989-12-22 |
| EP0340479A2 (en) | 1989-11-08 |
| EP0340479A3 (en) | 1990-11-07 |
| DE3815531A1 (en) | 1989-11-23 |
| EP0340479B1 (en) | 1993-07-07 |
| US5028813A (en) | 1991-07-02 |
| DE58904858D1 (en) | 1993-08-12 |
| AU616258B2 (en) | 1991-10-24 |
| AU3320889A (en) | 1989-11-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |