EP0340479B1 - Arrangement for monitoring a time base signal - Google Patents

Arrangement for monitoring a time base signal Download PDF

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Publication number
EP0340479B1
EP0340479B1 EP89106289A EP89106289A EP0340479B1 EP 0340479 B1 EP0340479 B1 EP 0340479B1 EP 89106289 A EP89106289 A EP 89106289A EP 89106289 A EP89106289 A EP 89106289A EP 0340479 B1 EP0340479 B1 EP 0340479B1
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EP
European Patent Office
Prior art keywords
flipflop
signal
monitoring
input
flip
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Revoked
Application number
EP89106289A
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German (de)
French (fr)
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EP0340479A2 (en
EP0340479A3 (en
Inventor
Dieter Hauck
Karl-Heinz May
Hans Müller
Jürgen Rehberger
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Heidelberger Druckmaschinen AG
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Heidelberger Druckmaschinen AG
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Application filed by Heidelberger Druckmaschinen AG filed Critical Heidelberger Druckmaschinen AG
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Publication of EP0340479A3 publication Critical patent/EP0340479A3/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G01R23/15—Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements (indicating that pulse width is above or below a certain limit)

Definitions

  • the invention relates to an arrangement for monitoring a clock signal.
  • US Pat. No. 4,467,285 describes a clock signal detection circuit which contains a monitoring circuit and a memory circuit.
  • the monitoring circuit detects the failure of the clock signal and is periodically reset by an external pulse train.
  • the memory circuit is clocked by the external pulse train and stores the output signal of the monitoring circuit.
  • the memory circuit can be reset by an external signal or by an edge of the clock signal to be monitored.
  • the frequency of the external pulse train which clocks the memory circuit should be less than half the frequency of the clock signal to be monitored.
  • JK flip-flops are used as the monitoring and storage circuit, the clock signal to be monitored being fed via a gate to the clock input of the monitoring flip-flop and between the output of this flip-flop and the I input of the memory flip-flop a switch is provided.
  • a disadvantage of this solution is that the external pulse train for periodic resetting of the monitoring flip-flop must be generated by an external pulse source, the frequency of which must meet the above-mentioned condition.
  • the query for the presence of the Monitoring clock signal made at relatively large intervals, that is, the monitoring circuit between two edges of the pulse train is inactive, so that the circuit does not work reliably at all times.
  • the object of the present invention is to develop an arrangement for monitoring a clock signal which has little circuit complexity and which improves the reliability in the monitoring.
  • a switch-on reset signal can be fed to the set inputs of the D flip-flops and the reset input of the monostable multivibrator.
  • a simple generation of the comparison signal is provided in that a threshold circuit is provided to derive the comparison signal from the mains voltage.
  • the arrangement shown in FIG. 1 consists of two D-flip-flops 1, 2 and a monostable multivibrator 3.
  • the clock signal T to be monitored is fed to the clock input of the D-flip-flop 1 via an input 4.
  • the D input of the D flip-flop 1 is connected to the operating voltage Vcc.
  • the output Q of the D flip-flop 1 is connected to the D input of the D flip-flop 2, while the output Q of the D flip-flop 2 forms the output 5 of the arrangement.
  • a comparison signal SYN is fed to the clock inputs of the D flip-flop 2 and the monostable multivibrator 3.
  • the signal at the output Q of the monostable multivibrator 3 is used to reset the D flip-flop 1 and for this purpose is led to a dynamically acting reset input of the D flip-flop 1.
  • a switch-on reset signal supplied at 7 sets the two D flip-flops 1, 2 and is also fed to a reset input of the monostable multivibrator 3.
  • the comparison signal SYN is derived from the mains voltage by a threshold circuit 8, for which an AC voltage is supplied to an input 9, which the secondary winding, not shown, of a mains transformer is removed.
  • the signal shown in line a) of FIG. 2 is a meandering signal obtained from the mains voltage.
  • the clock signal T shown in line b) assumes that two pulses are present and that the clock signal then fails.
  • Line c) represents the output signal of the D flip-flop 1. It is brought to the value 1 with the leading edge of the clock signal T.
  • the value of the output signal S1 of the D flip-flop 1 is transferred to the D flip-flop 2, whereupon the output signal S2 (line d)) of the D flip-flop 2 also has the value 1 assumes.
  • the monostable multivibrator 3 (FIG. 1) is clocked, whose output signal is shown in line e).
  • the D flip-flop 1 is reset with the leading edge of the output signal M.
  • the output signal S1 of the D flip-flop 1 is not set to the value 1, so that no 1 can be accepted by the D flip-flop 2.
  • the output 5 thus goes to 0, which can be indicated by a suitable display device.
  • other measures can also be taken, such as automatically stopping a machine.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

Die Erfindung betrifft eine Anordnung zur Überwachung eines Taktsignals.The invention relates to an arrangement for monitoring a clock signal.

Die Funktion von elektronischen Steuer- und Regeleinrichtungen hängt häufig vom Vorhandensein eines Taktsignals ab. Bleibt ein Taktsignal wegen eines Fehlers des Taktsignalgenerators aus, so können Fehlfunktionen auftreten, die im Einzelfall ernsthafte Schäden nach sich ziehen können.The function of electronic control and regulating devices often depends on the presence of a clock signal. If a clock signal fails to appear due to a fault in the clock signal generator, malfunctions can occur which in individual cases can result in serious damage.

In der Patentschrift US 44 67 285 ist eine Taktsignalerkennungsschaltung beschrieben, die eine Überwachungsschaltung und eine Speicherschaltung enthält. Die Überwachungsschaltung erkennt den Ausfall des Taktsignals und wird periodisch von einem externen Impulszug zurückgesetzt. Die Speicherschaltung wird durch den externen Impulszug getaktet und speichert das Ausgangssignal der Überwachungsschaltung. Die Speicherschaltung kann von einem externen Signal oder von einer Flanke des zu überwachenden Taktsignals zurückgesetzt werden. Die Frequenz des externen Impulszuges, welcher die Speicherschaltung taktet, soll weniger als die Hälfte der Frequenz des zu überwachenden Taktsignals betragen. Als Überwachungs- und Speicherschaltung werden JK-Flip-Flops verwendet, wobei das zu überwachende Taktsignal über ein Gatter dem Takteingang des Überwachungs-Flip-Flops zugeführt wird und zwischen dem Ausgang dieses Flip-Flops und dem I-Eingang des Speicher-Flip-Flops ein Schalter vorgesehen ist.US Pat. No. 4,467,285 describes a clock signal detection circuit which contains a monitoring circuit and a memory circuit. The monitoring circuit detects the failure of the clock signal and is periodically reset by an external pulse train. The memory circuit is clocked by the external pulse train and stores the output signal of the monitoring circuit. The memory circuit can be reset by an external signal or by an edge of the clock signal to be monitored. The frequency of the external pulse train which clocks the memory circuit should be less than half the frequency of the clock signal to be monitored. JK flip-flops are used as the monitoring and storage circuit, the clock signal to be monitored being fed via a gate to the clock input of the monitoring flip-flop and between the output of this flip-flop and the I input of the memory flip-flop a switch is provided.

Nachteilig bei dieser Lösung ist, daß der externe Impulszug zum periodischen Zurücksetzen des Überwachungs-Flip-Flops von einer externen Impulsquelle erzeugt werden muß, deren Frequenz o.g. Bedingung erfüllen muß. Bei niedrigen Frequenzen wird die Abfrage auf das Vorhandensein des zu überwachenden Taktsignals in relativ großen Zeitabständen vorgenommen, daß heißt, daß die Überwachungsschaltung zwischen zwei Flanken des Impulszuges inaktiv ist, so daß die Schaltung nicht zu jedem Zeitpunkt zuverlässig arbeitet.A disadvantage of this solution is that the external pulse train for periodic resetting of the monitoring flip-flop must be generated by an external pulse source, the frequency of which must meet the above-mentioned condition. At low frequencies, the query for the presence of the Monitoring clock signal made at relatively large intervals, that is, the monitoring circuit between two edges of the pulse train is inactive, so that the circuit does not work reliably at all times.

Aufgabe der vorliegenden Erfindung ist es, eine Anordnung zur Überwachung eines Taktsignals zu entwickeln, welche einen geringen Schaltungsaufwand hat und welche die Zuverlässigkeit bei der Überwachung verbessert.The object of the present invention is to develop an arrangement for monitoring a clock signal which has little circuit complexity and which improves the reliability in the monitoring.

Die Aufgabe wird erfindungsgemäß mit dem Merkmalen des Anspruchs 1 gelöst.The object is achieved with the features of claim 1.

Bei einer Weiterbildung der erfindungsgemäßen Anordnung ist vorgesehen, daß ein Einschalt-Rücksetzsignal den Setzeingängen der D-Flip-Flops und dem Rücksetzeingang des monostabilen Multivibrators zuführbar ist. Bei Steuer- bzw. Regeleinrichtungen, welche nach dem Einschalten ohnehin durch ein Einschalt-Rücksetzsignal in einen Anfangszustand gebracht werden, wird durch diese Weiterbildung ohne zusätzlichen Aufwand ermöglicht, daß die erfindungsgemäße Anordnung unmittelbar nach dem Einschalten die Überwachung des Taktsignals aufnimmt.In a further development of the arrangement according to the invention, it is provided that a switch-on reset signal can be fed to the set inputs of the D flip-flops and the reset input of the monostable multivibrator. In the case of control or regulating devices which are brought into an initial state anyway by a switch-on reset signal after switching on, this development enables the arrangement according to the invention to monitor the clock signal immediately after switching on without additional effort.

Bei einer anderen Weiterbildung der erfindungsgemäßen Anordnung ist eine einfache Erzeugung des Vergleichssignals dadurch vorgesehen, daß zur Ableitung des Vergleichssignals aus der Netzspannung eine Schwellwertschaltung vorgesehen ist.In another development of the arrangement according to the invention, a simple generation of the comparison signal is provided in that a threshold circuit is provided to derive the comparison signal from the mains voltage.

Ein Ausführungsbeispiel der Erfindung ist in der Zeichnung anhand mehrerer Figuren dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigt:

Fig. 1
ein Blockschaltbild des Ausführungsbeispiels und
Fig. 2
Zeitdiagramme der bei der Anordnung nach Fig. 1 auftretenden Signale.
An embodiment of the invention is shown in the drawing using several figures and explained in more detail in the following description. It shows:
Fig. 1
a block diagram of the embodiment and
Fig. 2
Time diagrams of the signals occurring in the arrangement according to FIG. 1.

Die in Fig. 1 dargestellte Anordnung besteht aus zwei D-Flip-Flops 1, 2 und einem monostabilen Multivibrator 3. Über einen Eingang 4 wird dem Takteingang des D-Flip-Flops 1 das zu überwachende Taktsignal T zugeführt. Der D-Eingang des D-Flip-Flops 1 liegt an der Betriebsspannung Vcc. Der Ausgang Q des D-Flip-Flops 1 ist mit dem D-Eingang des D-Flip-Flops 2 verbunden, während der Ausgang Q des D-Flip-Flops 2 den Ausgang 5 der Anordnung bildet. Ein Vergleichssignal SYN wird den Takteingängen des D-Flip-Flops 2 und des monostabilen Multivibrators 3 zugeführt. Das Signal am Ausgang Q des monostabilen Multivibrators 3 dient zum Rücksetzen des D-Flip-Flops 1 und wird dazu an einen dynamisch wirkenden Reset-Eingang des D-Flip-Flops 1 geführt. Ein bei 7 zugeführtes Einschalt-Rücksetzsignal setzt die beiden D-Flip-Flops 1, 2 und wird außerdem einem Rücksetz-Eingang des monostabilen Multivibrators 3 zugeleitet.The arrangement shown in FIG. 1 consists of two D-flip-flops 1, 2 and a monostable multivibrator 3. The clock signal T to be monitored is fed to the clock input of the D-flip-flop 1 via an input 4. The D input of the D flip-flop 1 is connected to the operating voltage Vcc. The output Q of the D flip-flop 1 is connected to the D input of the D flip-flop 2, while the output Q of the D flip-flop 2 forms the output 5 of the arrangement. A comparison signal SYN is fed to the clock inputs of the D flip-flop 2 and the monostable multivibrator 3. The signal at the output Q of the monostable multivibrator 3 is used to reset the D flip-flop 1 and for this purpose is led to a dynamically acting reset input of the D flip-flop 1. A switch-on reset signal supplied at 7 sets the two D flip-flops 1, 2 and is also fed to a reset input of the monostable multivibrator 3.

Das Vergleichssignal SYN wird durch eine Schwellwertschaltung 8 aus der Netzspannung abgeleitet, wozu einem Eingang 9 eine Wechselspannung zugeführt ist, welche der nicht dargestellten Sekundärwicklung eines Netztransformators entnommen wird.The comparison signal SYN is derived from the mains voltage by a threshold circuit 8, for which an AC voltage is supplied to an input 9, which the secondary winding, not shown, of a mains transformer is removed.

Die Funktion der Anordnung nach Fig. 1 und das erfindungsgemäße Verfahren werden im folgenden anhand von Fig. 2 erläutert. Das in Zeile a) der Fig. 2 dargestellte Signal ist ein aus der Netzspannung gewonnenes mäanderförmiges Signal. Bei dem in Zeile b) dargestellten Taktsignal T wird angenommen, daß zwei Impulse vorhanden sind und daß danach das Taktsignal ausfällt.The function of the arrangement according to FIG. 1 and the method according to the invention are explained below with reference to FIG. 2. The signal shown in line a) of FIG. 2 is a meandering signal obtained from the mains voltage. The clock signal T shown in line b) assumes that two pulses are present and that the clock signal then fails.

Zeile c) stellt das Ausgangssignal des D-Flip-Flops 1 dar. Es wird mit der Vorderflanke des Taktsignals T auf den Wert 1 gebracht. Bei Eintreffen der Vorderflanke des Vergleichssignals SYN wird der Wert des Ausgangssignals S1 des D-Flip-Flops 1 in das D-Flip-Flop 2 übernommen, worauf das Ausgangssignal S2 (Zeile d)) des D-Flip-Flops 2 ebenfalls den Wert 1 annimmt. Gleichzeitig wird der monostabile Multivibrator 3 (Fig. 1) getaktet, dessen Ausgangssignal in Zeile e) dargestellt ist. Mit der Vorderflanke des Ausgangssignals M wird das D-Flip-Flop 1 rückgesetzt.Line c) represents the output signal of the D flip-flop 1. It is brought to the value 1 with the leading edge of the clock signal T. When the leading edge of the comparison signal SYN arrives, the value of the output signal S1 of the D flip-flop 1 is transferred to the D flip-flop 2, whereupon the output signal S2 (line d)) of the D flip-flop 2 also has the value 1 assumes. At the same time, the monostable multivibrator 3 (FIG. 1) is clocked, whose output signal is shown in line e). The D flip-flop 1 is reset with the leading edge of the output signal M.

Dieses wiederholt sich solange, wie das Taktsignal T vorhanden ist. Bleibt es jedoch aus, so wird das Ausgangssignal S1 des D-Flip-Flops 1 nicht auf den Wert 1 gesetzt, so daß durch das D-Flip-Flop 2 keine 1 übernommen werden kann. Der Ausgang 5 geht somit auf 0, was durch eine geeignete Anzeigervorrichtung angezeigt werden kann. Je nach Anforderungen im Einzelfall können auch andere Maßnahmen ergriffen werden, wie beispielsweise das automatische Anhalten einer Maschine.This is repeated as long as the clock signal T is present. However, if there is no signal, the output signal S1 of the D flip-flop 1 is not set to the value 1, so that no 1 can be accepted by the D flip-flop 2. The output 5 thus goes to 0, which can be indicated by a suitable display device. Depending on the requirements in individual cases, other measures can also be taken, such as automatically stopping a machine.

Claims (3)

  1. Arrangement for monitoring a clock signal, consisting of two flipflop circuits (1, 2), the clock input of the first flipflop circuit (1) being connected to a clock signal source, the clock input of the second flipflop circuit (2) furthermore being connected to a reference signal source, and a monitoring signal being extractable at the output of the second flipflop circuit (2) if the clock signal fails, characterised in that D-type flipflops (1,2) are provided as flipflop circuits, the D input of the first flipflop (1) being connected to a fixed logic level (Vcc) and the output of the first D-type flipflop (1) being connected to the D input of the second D-type flipflop (2), in that the reference signal source is connected to the clock inputs of the second D-type flipflop (2) and of a monostable multivibrator (3), and in that an output of the monostable multivibrator (3) is connected to the reset input of the first D-type flipflop (1).
  2. Arrangement according to Claim 1, characterised in that a switching-on/reset signal can be supplied to the set inputs of the D-type flipflops (1, 2) and to the reset input of the monostable multivibrator (3).
  3. Arrangement according to Claim 1, characterised in that a threshold circuit (8) is provided for deriving the reference signal from the mains voltage.
EP89106289A 1988-05-06 1989-04-10 Arrangement for monitoring a time base signal Revoked EP0340479B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3815531A DE3815531A1 (en) 1988-05-06 1988-05-06 METHOD AND ARRANGEMENT FOR MONITORING A CLOCK SIGNAL
DE3815531 1988-05-06

Publications (3)

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EP0340479A2 EP0340479A2 (en) 1989-11-08
EP0340479A3 EP0340479A3 (en) 1990-11-07
EP0340479B1 true EP0340479B1 (en) 1993-07-07

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EP89106289A Revoked EP0340479B1 (en) 1988-05-06 1989-04-10 Arrangement for monitoring a time base signal

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US (1) US5028813A (en)
EP (1) EP0340479B1 (en)
JP (1) JPH01318427A (en)
AU (1) AU616258B2 (en)
CA (1) CA1310710C (en)
DE (2) DE3815531A1 (en)

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US5781038A (en) * 1996-02-05 1998-07-14 Lsi Logic Corporation High speed phase locked loop test method and means
US5896426A (en) * 1996-02-05 1999-04-20 Lsi Logic Corporation Programmable synchronization character
US6208621B1 (en) 1997-12-16 2001-03-27 Lsi Logic Corporation Apparatus and method for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency
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US6331999B1 (en) 1998-01-15 2001-12-18 Lsi Logic Corporation Serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream
US9568520B2 (en) * 2014-05-16 2017-02-14 Hamilton Sundstrand Corporation Frequency detection circuits

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Also Published As

Publication number Publication date
DE3815531C2 (en) 1990-08-16
CA1310710C (en) 1992-11-24
JPH01318427A (en) 1989-12-22
EP0340479A2 (en) 1989-11-08
EP0340479A3 (en) 1990-11-07
DE3815531A1 (en) 1989-11-23
US5028813A (en) 1991-07-02
DE58904858D1 (en) 1993-08-12
AU616258B2 (en) 1991-10-24
AU3320889A (en) 1989-11-09

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