ATE514135T1 - Vefahren und apparat zur bit-serialer verbindung von hochparallelen prozessormatrizen mit speichermatrizen - Google Patents
Vefahren und apparat zur bit-serialer verbindung von hochparallelen prozessormatrizen mit speichermatrizenInfo
- Publication number
- ATE514135T1 ATE514135T1 AT01968297T AT01968297T ATE514135T1 AT E514135 T1 ATE514135 T1 AT E514135T1 AT 01968297 T AT01968297 T AT 01968297T AT 01968297 T AT01968297 T AT 01968297T AT E514135 T1 ATE514135 T1 AT E514135T1
- Authority
- AT
- Austria
- Prior art keywords
- memory
- bits
- data
- matrices
- mode
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Image Processing (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/652,003 US6912626B1 (en) | 2000-08-31 | 2000-08-31 | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner |
PCT/US2001/027047 WO2002019129A2 (en) | 2000-08-31 | 2001-08-31 | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE514135T1 true ATE514135T1 (de) | 2011-07-15 |
Family
ID=24615128
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT01968297T ATE514135T1 (de) | 2000-08-31 | 2001-08-31 | Vefahren und apparat zur bit-serialer verbindung von hochparallelen prozessormatrizen mit speichermatrizen |
Country Status (7)
Country | Link |
---|---|
US (2) | US6912626B1 (de) |
EP (1) | EP1314099B1 (de) |
JP (1) | JP4860891B2 (de) |
KR (1) | KR100772287B1 (de) |
AT (1) | ATE514135T1 (de) |
AU (1) | AU2001288553A1 (de) |
WO (1) | WO2002019129A2 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7937557B2 (en) * | 2004-03-16 | 2011-05-03 | Vns Portfolio Llc | System and method for intercommunication between computers in an array |
US7904695B2 (en) * | 2006-02-16 | 2011-03-08 | Vns Portfolio Llc | Asynchronous power saving computer |
US7913069B2 (en) * | 2006-02-16 | 2011-03-22 | Vns Portfolio Llc | Processor and method for executing a program loop within an instruction word |
US7966481B2 (en) | 2006-02-16 | 2011-06-21 | Vns Portfolio Llc | Computer system and method for executing port communications without interrupting the receiving computer |
US7904615B2 (en) | 2006-02-16 | 2011-03-08 | Vns Portfolio Llc | Asynchronous computer communication |
KR100834412B1 (ko) * | 2007-05-23 | 2008-06-04 | 한국전자통신연구원 | 모바일 멀티미디어 연산의 효율적인 처리를 위한 병렬 프로세서 |
JP5089776B2 (ja) * | 2007-09-11 | 2012-12-05 | コア ロジック,インコーポレイテッド | 浮動小数点演算のための再構成アレイプロセッサ |
US8243543B2 (en) | 2008-02-29 | 2012-08-14 | Hynix Semiconductor Inc. | Semiconductor memory device for high-speed data input/output |
KR100929832B1 (ko) * | 2008-02-29 | 2009-12-07 | 주식회사 하이닉스반도체 | 고속의 데이터 입출력을 위한 반도체 메모리 장치 |
KR101565172B1 (ko) * | 2010-01-15 | 2015-11-02 | 삼성전자주식회사 | 대규모 병렬 프로세서 어레이 시스템의 데이터 처리 장치 및 방법 |
US10318153B2 (en) * | 2014-12-19 | 2019-06-11 | Advanced Micro Devices, Inc. | Techniques for changing management modes of multilevel memory hierarchy |
CN107408076B (zh) * | 2015-04-08 | 2020-12-11 | 国立大学法人奈良先端科学技术大学院大学 | 数据处理装置 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4321694A (en) | 1978-05-12 | 1982-03-23 | Burroughs Corporation | Charge coupled device memory with enhanced access features |
US4380046A (en) * | 1979-05-21 | 1983-04-12 | Nasa | Massively parallel processor computer |
US5038386A (en) * | 1986-08-29 | 1991-08-06 | International Business Machines Corporation | Polymorphic mesh network image processing system |
US5148547A (en) * | 1988-04-08 | 1992-09-15 | Thinking Machines Corporation | Method and apparatus for interfacing bit-serial parallel processors to a coprocessor |
JPH03266084A (ja) * | 1990-03-16 | 1991-11-27 | Fujitsu Ltd | 配線処理の後方探索処理方法 |
US5247613A (en) * | 1990-05-08 | 1993-09-21 | Thinking Machines Corporation | Massively parallel processor including transpose arrangement for serially transmitting bits of data words stored in parallel |
US5157785A (en) * | 1990-05-29 | 1992-10-20 | Wavetracer, Inc. | Process cell for an n-dimensional processor array having a single input element with 2n data inputs, memory, and full function arithmetic logic unit |
US5963746A (en) | 1990-11-13 | 1999-10-05 | International Business Machines Corporation | Fully distributed processing memory element |
DE4105193A1 (de) * | 1991-02-20 | 1992-08-27 | Bodenseewerk Geraetetech | Datenschnittstelle zur ein- und ausgabe von daten bei parallelrechnern |
US5243699A (en) * | 1991-12-06 | 1993-09-07 | Maspar Computer Corporation | Input/output system for parallel processing arrays |
US5581773A (en) | 1992-05-12 | 1996-12-03 | Glover; Michael A. | Massively parallel SIMD processor which selectively transfers individual contiguously disposed serial memory elements |
JPH06275069A (ja) | 1993-03-20 | 1994-09-30 | Hitachi Ltd | シリアルメモリ |
CA2129882A1 (en) * | 1993-08-12 | 1995-02-13 | Soheil Shams | Dynamically reconfigurable interprocessor communication network for simd multiprocessors and apparatus implementing same |
US5557734A (en) * | 1994-06-17 | 1996-09-17 | Applied Intelligent Systems, Inc. | Cache burst architecture for parallel processing, such as for image processing |
JP3013714B2 (ja) | 1994-09-28 | 2000-02-28 | 日本電気株式会社 | 半導体記憶装置 |
US5638533A (en) | 1995-10-12 | 1997-06-10 | Lsi Logic Corporation | Method and apparatus for providing data to a parallel processing array |
US5727229A (en) | 1996-02-05 | 1998-03-10 | Motorola, Inc. | Method and apparatus for moving data in a parallel processor |
DE19634031A1 (de) | 1996-08-23 | 1998-02-26 | Siemens Ag | Prozessor mit Pipelining-Aufbau |
DE102010023793A1 (de) * | 2010-06-15 | 2011-12-15 | J. F. Knauer Industrie-Elektronik Gmbh | Vorrichtung und Verfahren zum Einmischen von Konditioniermittel, insbesondere Flockmittel, in Schlämme |
-
2000
- 2000-08-31 US US09/652,003 patent/US6912626B1/en not_active Expired - Lifetime
-
2001
- 2001-08-31 EP EP01968297A patent/EP1314099B1/de not_active Expired - Lifetime
- 2001-08-31 JP JP2002523172A patent/JP4860891B2/ja not_active Expired - Lifetime
- 2001-08-31 WO PCT/US2001/027047 patent/WO2002019129A2/en active Application Filing
- 2001-08-31 KR KR1020037002937A patent/KR100772287B1/ko active IP Right Grant
- 2001-08-31 AT AT01968297T patent/ATE514135T1/de not_active IP Right Cessation
- 2001-08-31 AU AU2001288553A patent/AU2001288553A1/en not_active Abandoned
-
2005
- 2005-05-04 US US11/121,172 patent/US7386689B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
AU2001288553A1 (en) | 2002-03-13 |
US20050262288A1 (en) | 2005-11-24 |
WO2002019129A3 (en) | 2003-03-13 |
EP1314099B1 (de) | 2011-06-22 |
US7386689B2 (en) | 2008-06-10 |
WO2002019129A2 (en) | 2002-03-07 |
JP2004507836A (ja) | 2004-03-11 |
EP1314099A2 (de) | 2003-05-28 |
KR20030064391A (ko) | 2003-07-31 |
JP4860891B2 (ja) | 2012-01-25 |
US6912626B1 (en) | 2005-06-28 |
KR100772287B1 (ko) | 2007-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR960700476A (ko) | 프레임 버퍼용 출력 스위칭 회로의 구조(architecture of output switching circuitry for frame buffer) | |
JP2003241957A5 (de) | ||
JP5261803B2 (ja) | 不揮発性メモリ用の高速ファンアウトシステムアーキテクチャおよび入出力回路 | |
US20140281284A1 (en) | Multi-read port memory | |
JPS62264357A (ja) | 並列プロセツサ・アレイにおけるプロセツサ付加のシミユレ−シヨン方法 | |
ATE514135T1 (de) | Vefahren und apparat zur bit-serialer verbindung von hochparallelen prozessormatrizen mit speichermatrizen | |
GB1118070A (en) | Data processing systems | |
KR960012002A (ko) | 반도체 메모리와 그 사용방법, 컬럼 디코더 및 화상 프로세서 | |
JP2011510426A (ja) | タイミング制約が緩和されるnandフラッシュメモリアクセス | |
KR890002782A (ko) | 데이타 처리 회로용 교차 메모리 | |
JP2000260181A5 (de) | ||
JP2001273774A5 (de) | ||
KR950704744A (ko) | 프레임 버퍼내에 고속 멀티-컬러 저장장소를 제공하기 위한 방법 및 장치(method and apparatus for providing fast multi-color storage in a frame buffer) | |
KR970003208A (ko) | 고속동작을 위한 회로 배치 구조를 가지는 반도체 메모리 장치 | |
KR910008566A (ko) | 동기 벡터 프로세서용 제2 인접 통신 네트워크, 시스템 및 방법 | |
JP2008077768A5 (de) | ||
US6359827B1 (en) | Method of constructing a very wide, very fast distributed memory | |
KR950704769A (ko) | 윈도우 운영용으로 설계된 프레임버퍼 시스템에서 스크롤링 속도를 증가시키는 방법 및 장치(method and apparatus for increasing the rate of scrolling in a frame buffer system designed for windowing operations) | |
JP2003124319A (ja) | 半導体装置 | |
JP4723334B2 (ja) | Dma転送システム | |
KR100558485B1 (ko) | 메모리 모듈 및 이 모듈의 테스트 방법 | |
US20070244948A1 (en) | Memory transfer with early access to critical portion | |
US11791823B2 (en) | FPGA inter-tile control signal sharing | |
JP2950427B2 (ja) | レジスタバンク回路 | |
JPH03204753A (ja) | Dma制御装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |