ATE491222T1 - Verfahren zur herstellung von relaxierten schichten - Google Patents
Verfahren zur herstellung von relaxierten schichtenInfo
- Publication number
- ATE491222T1 ATE491222T1 AT06123069T AT06123069T ATE491222T1 AT E491222 T1 ATE491222 T1 AT E491222T1 AT 06123069 T AT06123069 T AT 06123069T AT 06123069 T AT06123069 T AT 06123069T AT E491222 T1 ATE491222 T1 AT E491222T1
- Authority
- AT
- Austria
- Prior art keywords
- layer
- layers
- crystalline
- elastically
- strained
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000203 mixture Substances 0.000 abstract 5
- 239000002178 crystalline material Substances 0.000 abstract 4
- 239000000463 material Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 230000006835 compression Effects 0.000 abstract 2
- 238000007906 compression Methods 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000012777 electrically insulating material Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02513—Microstructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Physical Vapour Deposition (AREA)
- Chemical Vapour Deposition (AREA)
- Magnetic Heads (AREA)
- Materials For Medical Uses (AREA)
- Lubricants (AREA)
- Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0511040A FR2892733B1 (fr) | 2005-10-28 | 2005-10-28 | Relaxation de couches |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE491222T1 true ATE491222T1 (de) | 2010-12-15 |
Family
ID=36591270
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT06123069T ATE491222T1 (de) | 2005-10-28 | 2006-10-27 | Verfahren zur herstellung von relaxierten schichten |
Country Status (10)
Country | Link |
---|---|
US (1) | US7452792B2 (de) |
EP (1) | EP1786025B1 (de) |
JP (1) | JP4926652B2 (de) |
KR (1) | KR100921837B1 (de) |
CN (1) | CN1971850A (de) |
AT (1) | ATE491222T1 (de) |
DE (1) | DE602006018696D1 (de) |
FR (1) | FR2892733B1 (de) |
SG (1) | SG131912A1 (de) |
TW (1) | TWI325153B (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5548351B2 (ja) * | 2007-11-01 | 2014-07-16 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
DE102010046215B4 (de) | 2010-09-21 | 2019-01-03 | Infineon Technologies Austria Ag | Halbleiterkörper mit verspanntem Bereich, Elektronisches Bauelement und ein Verfahren zum Erzeugen des Halbleiterkörpers. |
FR3064398B1 (fr) * | 2017-03-21 | 2019-06-07 | Soitec | Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure |
JP7094082B2 (ja) * | 2017-06-14 | 2022-07-01 | 日本ルメンタム株式会社 | 光半導体素子、光サブアセンブリ、及び光モジュール |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3024258B2 (ja) | 1991-05-22 | 2000-03-21 | 松下電器産業株式会社 | 化合物半導体装置の製造方法 |
US5461243A (en) * | 1993-10-29 | 1995-10-24 | International Business Machines Corporation | Substrate for tensilely strained semiconductor |
EP1295319A2 (de) * | 2000-06-22 | 2003-03-26 | Massachusetts Institute Of Technology | Ätzstopp-schichtzusammensetzung für sige-halbleiteranordnungen |
JP2004507084A (ja) * | 2000-08-16 | 2004-03-04 | マサチューセッツ インスティテュート オブ テクノロジー | グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス |
US6524935B1 (en) * | 2000-09-29 | 2003-02-25 | International Business Machines Corporation | Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique |
US6515335B1 (en) * | 2002-01-04 | 2003-02-04 | International Business Machines Corporation | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
US6805962B2 (en) * | 2002-01-23 | 2004-10-19 | International Business Machines Corporation | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications |
FR2842349B1 (fr) * | 2002-07-09 | 2005-02-18 | Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon | |
FR2842350B1 (fr) * | 2002-07-09 | 2005-05-13 | Procede de transfert d'une couche de materiau semiconducteur contraint | |
JP3837527B2 (ja) * | 2002-12-06 | 2006-10-25 | 国立大学法人東北大学 | 歪み半導体単結晶の作製方法 |
JP3967695B2 (ja) * | 2003-08-27 | 2007-08-29 | 株式会社東芝 | 歪み緩和SiGe基板の製造方法 |
US7247534B2 (en) * | 2003-11-19 | 2007-07-24 | International Business Machines Corporation | Silicon device on Si:C-OI and SGOI and method of manufacture |
WO2005112129A1 (ja) * | 2004-05-13 | 2005-11-24 | Fujitsu Limited | 半導体装置およびその製造方法、半導体基板の製造方法 |
US7217949B2 (en) * | 2004-07-01 | 2007-05-15 | International Business Machines Corporation | Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) |
US7585792B2 (en) * | 2005-02-09 | 2009-09-08 | S.O.I.Tec Silicon On Insulator Technologies | Relaxation of a strained layer using a molten layer |
US7265004B2 (en) * | 2005-11-14 | 2007-09-04 | Freescale Semiconductor, Inc. | Electronic devices including a semiconductor layer and a process for forming the same |
-
2005
- 2005-10-28 FR FR0511040A patent/FR2892733B1/fr active Active
-
2006
- 2006-01-19 US US11/337,267 patent/US7452792B2/en active Active
- 2006-10-27 SG SG200607480-1A patent/SG131912A1/en unknown
- 2006-10-27 TW TW095139733A patent/TWI325153B/zh active
- 2006-10-27 EP EP06123069A patent/EP1786025B1/de active Active
- 2006-10-27 AT AT06123069T patent/ATE491222T1/de not_active IP Right Cessation
- 2006-10-27 DE DE602006018696T patent/DE602006018696D1/de active Active
- 2006-10-27 KR KR1020060104823A patent/KR100921837B1/ko active IP Right Grant
- 2006-10-27 CN CNA2006101639198A patent/CN1971850A/zh active Pending
- 2006-10-30 JP JP2006294710A patent/JP4926652B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
EP1786025A1 (de) | 2007-05-16 |
CN1971850A (zh) | 2007-05-30 |
JP4926652B2 (ja) | 2012-05-09 |
US20070099399A1 (en) | 2007-05-03 |
US7452792B2 (en) | 2008-11-18 |
TWI325153B (en) | 2010-05-21 |
FR2892733B1 (fr) | 2008-02-01 |
JP2007197818A (ja) | 2007-08-09 |
FR2892733A1 (fr) | 2007-05-04 |
DE602006018696D1 (de) | 2011-01-20 |
KR20070045983A (ko) | 2007-05-02 |
KR100921837B1 (ko) | 2009-10-13 |
SG131912A1 (en) | 2007-05-28 |
EP1786025B1 (de) | 2010-12-08 |
TW200729295A (en) | 2007-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE602005024611D1 (de) | Verfahren zur Herstellung dual verspannter SOI Substrate | |
ATE358889T1 (de) | Verfahren zur herstellung einer plattenförmigen struktur insbesondere aus silizium, verwendung des verfahrens und der so hergestellten plattenförmigen struktur insbesondere aus silizium | |
ATE515794T1 (de) | Verfahren zur herstellung eines geoi-wafers (germanium on insulator) | |
ATE491222T1 (de) | Verfahren zur herstellung von relaxierten schichten | |
SG134290A1 (en) | Semiconductor layer structure and method for fabricating a semiconductor layer structure | |
ATE521085T1 (de) | Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur | |
DE60219321D1 (de) | Einzelketten vhh antikörper aus kamelen, verfahren zur deren herstellung in einem saugetier und deren verwendungen | |
TW200625531A (en) | Strained semiconductor-on-insulator structures and methods for making strained semiconductor-on-insulator structures | |
ATE425848T1 (de) | Lamelle zur fensterabdeckung und herstellungsverfahren | |
ATE344307T1 (de) | Gegenstände mit guter rollenstabilität, die eine trennlage mit hohem reibungskoeffizienten umfassen, sowie verfahren zur herstellung dieser gegenstände | |
JP2007324589A5 (de) | ||
TW200629352A (en) | Hetero-integrated strained silicon n- and p- MOSFETS | |
TW200802720A (en) | Engineering strain in thick strained-SOI substrates | |
DE502005000995D1 (de) | Dämmstoffplatte aus einem Holzwerkstoff-Bindemittelfaser-Gemisch und Verfahren zu ihrer Herstellung | |
ATE384098T1 (de) | Verfahren zur herstellung einer zusammensetzung und nanokomposite daraus | |
ATE502394T1 (de) | Verfahren zur herstellung von abtrennbaren substraten | |
TW200612204A (en) | Silicon rich dielectric antireflective coating | |
TW200520096A (en) | Film forming method and heat treatment equipment | |
ATE482082T1 (de) | Vorrichtung und verfahren zur herstellung von verbundwerkstoffen | |
ATE503981T1 (de) | Verfahren zur herstellung einer verbundpanzerungsplatte | |
ATE290430T1 (de) | Verfahren zur herstellung eines oxids | |
ATE552213T1 (de) | Verfahren zur herstellung von einem verbundwerkstoff | |
DE59700285D1 (de) | Verfahren zur herstellung eines flächenelementes mit unterbrochenen multifilamenten | |
US20050170577A1 (en) | Strained silicon layer fabrication with reduced dislocation defect density | |
WO2006057645A8 (en) | Enhancement of electron and hole mobilities in 110 under biaxial compressive strain |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |