Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Power Engineering (AREA)
• Recrystallisation Techniques (AREA)
• Formation Of Insulating Films (AREA)
• Chemical Vapour Deposition (AREA)
• Crystals, And After-Treatments Of Crystals (AREA)
• Inorganic Insulating Materials (AREA)

Applications Claiming Priority (1)

Publications (1)

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Family Applications (2)

Family Applications Before (1)

Country Status (9)

Families Citing this family (35)

Family Cites Families (4)

• 2004
  • 2004-11-19 EP EP08007334A patent/EP1973155B1/de active Active
  • 2004-11-19 DE DE602004013163T patent/DE602004013163T2/de active Active
  • 2004-11-19 EP EP04292742A patent/EP1659623B1/de active Active
  • 2004-11-19 AT AT04292742T patent/ATE392712T1/de not_active IP Right Cessation
  • 2004-11-19 AT AT08007334T patent/ATE515794T1/de not_active IP Right Cessation
• 2005
  • 2005-01-04 US US11/029,808 patent/US7229898B2/en active Active
  • 2005-08-31 TW TW094129940A patent/TWI297171B/zh active
  • 2005-09-16 JP JP2005270906A patent/JP4173884B2/ja active Active
  • 2005-11-01 KR KR1020050103864A patent/KR100734239B1/ko active IP Right Grant
  • 2005-11-18 SG SG200507154A patent/SG122908A1/en unknown
  • 2005-11-18 CN CNB2005101236830A patent/CN100472709C/zh active Active

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