ATE389937T1 - Schnelles programmier- und programmierverifikationsverfahren - Google Patents

Schnelles programmier- und programmierverifikationsverfahren

Info

Publication number
ATE389937T1
ATE389937T1 AT01480133T AT01480133T ATE389937T1 AT E389937 T1 ATE389937 T1 AT E389937T1 AT 01480133 T AT01480133 T AT 01480133T AT 01480133 T AT01480133 T AT 01480133T AT E389937 T1 ATE389937 T1 AT E389937T1
Authority
AT
Austria
Prior art keywords
programming
program
control gate
fast
verification procedure
Prior art date
Application number
AT01480133T
Other languages
English (en)
Inventor
Seiki Ogura
Tomoko Ogura
Nori Ogura
Original Assignee
Halo Lsi Design & Device Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Halo Lsi Design & Device Tech filed Critical Halo Lsi Design & Device Tech
Application granted granted Critical
Publication of ATE389937T1 publication Critical patent/ATE389937T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459Circuits or methods to verify correct programming of nonvolatile memory cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/12Programming voltage switching circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Circuits Of Receivers In General (AREA)
  • Debugging And Monitoring (AREA)
  • Storage Device Security (AREA)
AT01480133T 2000-12-15 2001-12-14 Schnelles programmier- und programmierverifikationsverfahren ATE389937T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US25582400P 2000-12-15 2000-12-15

Publications (1)

Publication Number Publication Date
ATE389937T1 true ATE389937T1 (de) 2008-04-15

Family

ID=22970026

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01480133T ATE389937T1 (de) 2000-12-15 2001-12-14 Schnelles programmier- und programmierverifikationsverfahren

Country Status (7)

Country Link
US (8) US6549463B2 (de)
EP (1) EP1215680B1 (de)
JP (1) JP4050048B2 (de)
KR (1) KR100880547B1 (de)
AT (1) ATE389937T1 (de)
DE (1) DE60133259D1 (de)
TW (1) TW577082B (de)

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CN101986389B (zh) * 2010-10-12 2015-06-24 上海华虹宏力半导体制造有限公司 闪存单元、闪存装置及其编程方法
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CN113129940A (zh) * 2019-12-30 2021-07-16 北京兆易创新科技股份有限公司 一种闪存及其制造方法

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Also Published As

Publication number Publication date
US20030123291A1 (en) 2003-07-03
JP4050048B2 (ja) 2008-02-20
EP1215680B1 (de) 2008-03-19
US20030123293A1 (en) 2003-07-03
EP1215680A2 (de) 2002-06-19
US20030128588A1 (en) 2003-07-10
US20030123308A1 (en) 2003-07-03
US6807105B2 (en) 2004-10-19
US6628546B2 (en) 2003-09-30
US6856545B2 (en) 2005-02-15
US7046553B2 (en) 2006-05-16
US6636439B1 (en) 2003-10-21
DE60133259D1 (de) 2008-04-30
US20030185053A1 (en) 2003-10-02
TW577082B (en) 2004-02-21
US6628547B2 (en) 2003-09-30
US6549463B2 (en) 2003-04-15
EP1215680A3 (de) 2004-01-21
US20030123292A1 (en) 2003-07-03
US6611461B2 (en) 2003-08-26
KR20020071442A (ko) 2002-09-12
JP2002230988A (ja) 2002-08-16
US20030123290A1 (en) 2003-07-03
US20020075725A1 (en) 2002-06-20
KR100880547B1 (ko) 2009-01-30

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