ATE284075T1 - Halbleiter verarbeitungverfahren mit der herstellung von einer sperrschicht - Google Patents
Halbleiter verarbeitungverfahren mit der herstellung von einer sperrschichtInfo
- Publication number
- ATE284075T1 ATE284075T1 AT98964820T AT98964820T ATE284075T1 AT E284075 T1 ATE284075 T1 AT E284075T1 AT 98964820 T AT98964820 T AT 98964820T AT 98964820 T AT98964820 T AT 98964820T AT E284075 T1 ATE284075 T1 AT E284075T1
- Authority
- AT
- Austria
- Prior art keywords
- barrier layer
- formed over
- regions
- processing method
- semiconductor processing
- Prior art date
Links
- 230000004888 barrier function Effects 0.000 title abstract 4
- 238000003672 processing method Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000000463 material Substances 0.000 abstract 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000003990 capacitor Substances 0.000 abstract 2
- 239000004020 conductor Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- 239000002019 doping agent Substances 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Weting (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/994,054 US6165833A (en) | 1997-12-19 | 1997-12-19 | Semiconductor processing method of forming a capacitor |
PCT/US1998/027106 WO1999033098A1 (en) | 1997-12-19 | 1998-12-18 | Semiconductor processing method comprising the fabrication of a barrier layer |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE284075T1 true ATE284075T1 (de) | 2004-12-15 |
Family
ID=25540242
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT98964820T ATE284075T1 (de) | 1997-12-19 | 1998-12-18 | Halbleiter verarbeitungverfahren mit der herstellung von einer sperrschicht |
Country Status (8)
Country | Link |
---|---|
US (2) | US6165833A (de) |
EP (2) | EP1042802B1 (de) |
JP (1) | JP3663128B2 (de) |
KR (1) | KR100455799B1 (de) |
AT (1) | ATE284075T1 (de) |
AU (1) | AU2005999A (de) |
DE (1) | DE69827974T2 (de) |
WO (1) | WO1999033098A1 (de) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5910880A (en) | 1997-08-20 | 1999-06-08 | Micron Technology, Inc. | Semiconductor circuit components and capacitors |
US6911371B2 (en) * | 1997-12-19 | 2005-06-28 | Micron Technology, Inc. | Capacitor forming methods with barrier layers to threshold voltage shift inducing material |
US6191443B1 (en) | 1998-02-28 | 2001-02-20 | Micron Technology, Inc. | Capacitors, methods of forming capacitors, and DRAM memory cells |
GB2358284B (en) * | 1999-07-02 | 2004-07-14 | Hyundai Electronics Ind | Method of manufacturing capacitor for semiconductor memory device |
EP1071130A3 (de) * | 1999-07-14 | 2005-09-07 | Matsushita Electric Industrial Co., Ltd. | Verbindungsleiterstruktur für Halbleitervorrichtung mit zusätzlichen Kapazitäten |
KR100359246B1 (ko) * | 1999-09-29 | 2002-11-04 | 동부전자 주식회사 | 적층형 캐패시터를 갖는 반도체 장치 제조 방법 |
US6947324B1 (en) | 2000-06-28 | 2005-09-20 | Marvell International Ltd. | Logic process DRAM |
US7184290B1 (en) | 2000-06-28 | 2007-02-27 | Marvell International Ltd. | Logic process DRAM |
US6570781B1 (en) * | 2000-06-28 | 2003-05-27 | Marvell International Ltd. | Logic process DRAM |
DE10042235A1 (de) * | 2000-08-28 | 2002-04-18 | Infineon Technologies Ag | Verfahren zur Herstellung einer elektrisch leitenden Verbindung |
US6734071B1 (en) * | 2000-08-30 | 2004-05-11 | Micron Technology, Inc. | Methods of forming insulative material against conductive structures |
US6545904B2 (en) | 2001-03-16 | 2003-04-08 | Micron Technology, Inc. | 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array |
US6411555B1 (en) | 2001-03-19 | 2002-06-25 | Micron Technology, Inc. | Reference charge generator, a method for providing a reference charge from a reference charge generator, a method of operating a reference charge generator and a dram memory circuit formed using memory cells having an area of 6f2 |
US6872320B2 (en) * | 2001-04-19 | 2005-03-29 | Xerox Corporation | Method for printing etch masks using phase-change materials |
US6670717B2 (en) * | 2001-10-15 | 2003-12-30 | International Business Machines Corporation | Structure and method for charge sensitive electrical devices |
US6551893B1 (en) * | 2001-11-27 | 2003-04-22 | Micron Technology, Inc. | Atomic layer deposition of capacitor dielectric |
US7165393B2 (en) | 2001-12-03 | 2007-01-23 | Catalytica Energy Systems, Inc. | System and methods for improved emission control of internal combustion engines |
KR20040043378A (ko) * | 2002-11-18 | 2004-05-24 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
KR100536030B1 (ko) * | 2003-02-25 | 2005-12-12 | 삼성전자주식회사 | 반도체 장치의 커패시터 형성 방법 |
KR100665396B1 (ko) * | 2004-01-09 | 2007-01-04 | 에스티마이크로일렉트로닉스 엔.브이. | 플래쉬 메모리 소자의 제조 방법 |
US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
US7858458B2 (en) | 2005-06-14 | 2010-12-28 | Micron Technology, Inc. | CMOS fabrication |
US7541632B2 (en) * | 2005-06-14 | 2009-06-02 | Micron Technology, Inc. | Relaxed-pitch method of aligning active area to digit line |
US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
US7687342B2 (en) | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
US7557032B2 (en) | 2005-09-01 | 2009-07-07 | Micron Technology, Inc. | Silicided recessed silicon |
US7416943B2 (en) | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US20090250793A1 (en) * | 2008-04-08 | 2009-10-08 | Yuri Sokolov | Bpsg film deposition with undoped capping |
US10840249B2 (en) * | 2018-08-23 | 2020-11-17 | Micron Technology, Inc. | Integrated circuitry constructions |
US11049864B2 (en) | 2019-05-17 | 2021-06-29 | Micron Technology, Inc. | Apparatuses including capacitor structures, and related memory devices, electronic systems, and methods |
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GB1165575A (en) * | 1966-01-03 | 1969-10-01 | Texas Instruments Inc | Semiconductor Device Stabilization. |
JPS5253666A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Method of preventing impurity diffusion from doped oxide |
JPS5253679A (en) | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Productin of semiconductor device |
US4464701A (en) * | 1983-08-29 | 1984-08-07 | International Business Machines Corporation | Process for making high dielectric constant nitride based materials and devices using the same |
KR940006682B1 (ko) * | 1991-10-17 | 1994-07-25 | 삼성전자 주식회사 | 반도체 메모리장치의 제조방법 |
US5313089A (en) * | 1992-05-26 | 1994-05-17 | Motorola, Inc. | Capacitor and a memory cell formed therefrom |
JP3141553B2 (ja) * | 1992-08-06 | 2001-03-05 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2786071B2 (ja) * | 1993-02-17 | 1998-08-13 | 日本電気株式会社 | 半導体装置の製造方法 |
US5471364A (en) * | 1993-03-31 | 1995-11-28 | Texas Instruments Incorporated | Electrode interface for high-dielectric-constant materials |
JPH0730077A (ja) * | 1993-06-23 | 1995-01-31 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5504041A (en) * | 1994-08-01 | 1996-04-02 | Texas Instruments Incorporated | Conductive exotic-nitride barrier layer for high-dielectric-constant materials |
US5488011A (en) * | 1994-11-08 | 1996-01-30 | Micron Technology, Inc. | Method of forming contact areas between vertical conductors |
JP2636755B2 (ja) * | 1994-11-09 | 1997-07-30 | 日本電気株式会社 | 半導体装置および半導体装置の製造方法 |
JP2827958B2 (ja) * | 1995-04-27 | 1998-11-25 | 日本電気株式会社 | 半導体記憶装置の容量素子の製造方法 |
US5654222A (en) * | 1995-05-17 | 1997-08-05 | Micron Technology, Inc. | Method for forming a capacitor with electrically interconnected construction |
US5663088A (en) * | 1995-05-19 | 1997-09-02 | Micron Technology, Inc. | Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a Ta2 O5 dielectric layer and amorphous diffusion barrier layer |
KR0168338B1 (ko) * | 1995-05-31 | 1998-12-15 | 김광호 | 랜딩 패드를 갖는 반도체 메모리 장치의 제조방법 |
US5597756A (en) * | 1995-06-21 | 1997-01-28 | Micron Technology, Inc. | Process for fabricating a cup-shaped DRAM capacitor using a multi-layer partly-sacrificial stack |
US5866453A (en) * | 1995-09-14 | 1999-02-02 | Micron Technology, Inc. | Etch process for aligning a capacitor structure and an adjacent contact corridor |
US5793076A (en) * | 1995-09-21 | 1998-08-11 | Micron Technology, Inc. | Scalable high dielectric constant capacitor |
US5786248A (en) | 1995-10-12 | 1998-07-28 | Micron Technology, Inc. | Semiconductor processing method of forming a tantalum oxide containing capacitor |
US5608249A (en) | 1995-11-16 | 1997-03-04 | Micron Technology, Inc. | Reduced area storage node junction |
KR100200299B1 (ko) * | 1995-11-30 | 1999-06-15 | 김영환 | 반도체 소자 캐패시터 형성방법 |
KR0170308B1 (ko) * | 1995-12-05 | 1999-02-01 | 김광호 | 강유전체 캐패시터의 제조방법 |
KR100253270B1 (ko) * | 1995-12-30 | 2000-04-15 | 김영환 | 반도체소자의 자기정합 스택캐패시터 형성방법 |
US5843830A (en) | 1996-06-26 | 1998-12-01 | Micron Technology, Inc. | Capacitor, and methods for forming a capacitor |
JPH1022476A (ja) * | 1996-07-02 | 1998-01-23 | Sony Corp | 容量素子 |
KR100246989B1 (ko) * | 1996-09-09 | 2000-03-15 | 김영환 | 반도체소자의 캐패시터 형성방법 |
US6251720B1 (en) | 1996-09-27 | 2001-06-26 | Randhir P. S. Thakur | High pressure reoxidation/anneal of high dielectric constant materials |
US5783462A (en) | 1997-01-22 | 1998-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making an external contact to a MOSFET drain for testing of stacked-capacitor DRAMS |
US6218260B1 (en) * | 1997-04-22 | 2001-04-17 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby |
US5910880A (en) | 1997-08-20 | 1999-06-08 | Micron Technology, Inc. | Semiconductor circuit components and capacitors |
-
1997
- 1997-12-19 US US08/994,054 patent/US6165833A/en not_active Expired - Fee Related
-
1998
- 1998-12-18 EP EP98964820A patent/EP1042802B1/de not_active Expired - Lifetime
- 1998-12-18 EP EP04028239A patent/EP1508914A3/de not_active Withdrawn
- 1998-12-18 AU AU20059/99A patent/AU2005999A/en not_active Abandoned
- 1998-12-18 KR KR10-2000-7006569A patent/KR100455799B1/ko not_active IP Right Cessation
- 1998-12-18 WO PCT/US1998/027106 patent/WO1999033098A1/en active IP Right Grant
- 1998-12-18 DE DE69827974T patent/DE69827974T2/de not_active Expired - Lifetime
- 1998-12-18 AT AT98964820T patent/ATE284075T1/de not_active IP Right Cessation
- 1998-12-18 JP JP2000525914A patent/JP3663128B2/ja not_active Expired - Fee Related
-
2000
- 2000-11-08 US US09/710,546 patent/US6593183B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6593183B1 (en) | 2003-07-15 |
EP1042802A1 (de) | 2000-10-11 |
DE69827974T2 (de) | 2005-11-24 |
WO1999033098A1 (en) | 1999-07-01 |
DE69827974D1 (de) | 2005-01-05 |
JP3663128B2 (ja) | 2005-06-22 |
KR100455799B1 (ko) | 2004-11-08 |
JP2002512435A (ja) | 2002-04-23 |
EP1042802B1 (de) | 2004-12-01 |
AU2005999A (en) | 1999-07-12 |
US6165833A (en) | 2000-12-26 |
EP1508914A2 (de) | 2005-02-23 |
EP1508914A3 (de) | 2005-05-25 |
KR20010033186A (ko) | 2001-04-25 |
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