ATE208953T1 - Verfahren und vorrichtung zum prüfen integrierter schaltkreischips in einem integrierten schaltkreismodul - Google Patents
Verfahren und vorrichtung zum prüfen integrierter schaltkreischips in einem integrierten schaltkreismodulInfo
- Publication number
- ATE208953T1 ATE208953T1 AT97938416T AT97938416T ATE208953T1 AT E208953 T1 ATE208953 T1 AT E208953T1 AT 97938416 T AT97938416 T AT 97938416T AT 97938416 T AT97938416 T AT 97938416T AT E208953 T1 ATE208953 T1 AT E208953T1
- Authority
- AT
- Austria
- Prior art keywords
- dice
- test mode
- testing
- mcm
- response signals
- Prior art date
Links
- 238000012360 testing method Methods 0.000 title abstract 13
- 238000000034 method Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000013102 re-test Methods 0.000 abstract 1
- 230000008439 repair process Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0062—Testing
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/718,173 US5796746A (en) | 1995-12-22 | 1996-09-19 | Device and method for testing integrated circuit dice in an integrated circuit module |
PCT/US1997/014564 WO1998012706A1 (en) | 1996-09-19 | 1997-08-20 | Device and method for testing integrated circuit dice in an integrated circuit module |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE208953T1 true ATE208953T1 (de) | 2001-11-15 |
Family
ID=24885103
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT97938416T ATE208953T1 (de) | 1996-09-19 | 1997-08-20 | Verfahren und vorrichtung zum prüfen integrierter schaltkreischips in einem integrierten schaltkreismodul |
Country Status (9)
Country | Link |
---|---|
US (1) | US5796746A (de) |
EP (1) | EP0928486B1 (de) |
JP (1) | JP3705443B2 (de) |
KR (1) | KR100400952B1 (de) |
AT (1) | ATE208953T1 (de) |
AU (1) | AU4074397A (de) |
DE (1) | DE69708314T2 (de) |
TW (1) | TW356576B (de) |
WO (1) | WO1998012706A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117434428A (zh) * | 2023-12-18 | 2024-01-23 | 杭州晶华微电子股份有限公司 | 芯片校准***、芯片校准模式进入方法及芯片 |
Families Citing this family (41)
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US6240535B1 (en) * | 1995-12-22 | 2001-05-29 | Micron Technology, Inc. | Device and method for testing integrated circuit dice in an integrated circuit module |
US5905401A (en) | 1996-09-09 | 1999-05-18 | Micron Technology, Inc. | Device and method for limiting the extent to which circuits in integrated circuit dice electrically load bond pads and other circuit nodes in the dice |
US6258609B1 (en) | 1996-09-30 | 2001-07-10 | Micron Technology, Inc. | Method and system for making known good semiconductor dice |
US5859768A (en) * | 1997-06-04 | 1999-01-12 | Motorola, Inc. | Power conversion integrated circuit and method for programming |
US6238942B1 (en) * | 1998-04-07 | 2001-05-29 | Micron Technology, Inc. | Method of wire-bonding a repair die in a multi-chip module using a repair solution generated during testing of the module |
DE19819264A1 (de) * | 1998-04-30 | 1999-11-25 | Micronas Intermetall Gmbh | Verfahren zum Testen einer integrierten Schaltungsanordnung und integrierte Schaltungsanordnung hierfür |
US6324485B1 (en) * | 1999-01-26 | 2001-11-27 | Newmillennia Solutions, Inc. | Application specific automated test equipment system for testing integrated circuit devices in a native environment |
US6288436B1 (en) * | 1999-07-27 | 2001-09-11 | International Business Machines Corporation | Mixed fuse technologies |
US6777785B1 (en) * | 1999-08-25 | 2004-08-17 | Winbond Electronics Corp. | Lead frame containing a master and a slave IC chips and a testing circuit embedded within the master IC chip |
US6392428B1 (en) * | 1999-11-16 | 2002-05-21 | Eaglestone Partners I, Llc | Wafer level interposer |
DE19964003A1 (de) * | 1999-12-30 | 2001-07-12 | Micronas Gmbh | Schaltungsanordnung und Verfahren zur Erzeugung und zum Auslesen von Ersatzdaten |
DE10004649A1 (de) * | 2000-02-03 | 2001-08-09 | Infineon Technologies Ag | Verfahren und Vorrichtung zur Anpassung/Abstimmung von Signallaufzeiten auf Leitungssystemen oder Netzen zwischen integrierten Schaltungen |
US7012811B1 (en) * | 2000-05-10 | 2006-03-14 | Micron Technology, Inc. | Method of tuning a multi-path circuit |
DE10029835C1 (de) | 2000-06-16 | 2001-10-25 | Infineon Technologies Ag | Integrierte Schaltung mit Testbetrieb und Testanordnung zum Testen einer integrierten Schaltung |
US6812048B1 (en) * | 2000-07-31 | 2004-11-02 | Eaglestone Partners I, Llc | Method for manufacturing a wafer-interposer assembly |
US6537831B1 (en) | 2000-07-31 | 2003-03-25 | Eaglestone Partners I, Llc | Method for selecting components for a matched set using a multi wafer interposer |
US6483330B1 (en) | 2000-09-11 | 2002-11-19 | Eaglestone Partners I, Llc | Method for selecting components for a matched set using wafer interposers |
US6815712B1 (en) | 2000-10-02 | 2004-11-09 | Eaglestone Partners I, Llc | Method for selecting components for a matched set from a wafer-interposer assembly |
US6686657B1 (en) | 2000-11-07 | 2004-02-03 | Eaglestone Partners I, Llc | Interposer for improved handling of semiconductor wafers and method of use of same |
US6577156B2 (en) * | 2000-12-05 | 2003-06-10 | International Business Machines Corporation | Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox |
US6524885B2 (en) * | 2000-12-15 | 2003-02-25 | Eaglestone Partners I, Llc | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
US6529022B2 (en) * | 2000-12-15 | 2003-03-04 | Eaglestone Pareners I, Llc | Wafer testing interposer for a conventional package |
US20020076854A1 (en) * | 2000-12-15 | 2002-06-20 | Pierce John L. | System, method and apparatus for constructing a semiconductor wafer-interposer using B-Stage laminates |
US20020078401A1 (en) * | 2000-12-15 | 2002-06-20 | Fry Michael Andrew | Test coverage analysis system |
US6834323B2 (en) | 2000-12-26 | 2004-12-21 | Intel Corporation | Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory |
US6732306B2 (en) * | 2000-12-26 | 2004-05-04 | Intel Corporation | Special programming mode with hashing |
US7007131B2 (en) * | 2000-12-27 | 2006-02-28 | Intel Corporation | Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory |
US6673653B2 (en) * | 2001-02-23 | 2004-01-06 | Eaglestone Partners I, Llc | Wafer-interposer using a ceramic substrate |
US6599764B1 (en) * | 2001-05-30 | 2003-07-29 | Altera Corporation | Isolation testing scheme for multi-die packages |
US7064447B2 (en) | 2001-08-10 | 2006-06-20 | Micron Technology, Inc. | Bond pad structure comprising multiple bond pads with metal overlap |
JP2003187596A (ja) * | 2001-12-14 | 2003-07-04 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6618304B2 (en) * | 2001-12-21 | 2003-09-09 | Micron Technology, Inc. | Memory module with test mode |
US6780762B2 (en) | 2002-08-29 | 2004-08-24 | Micron Technology, Inc. | Self-aligned, integrated circuit contact and formation method |
US6813748B2 (en) * | 2002-09-24 | 2004-11-02 | Infineon Technologies Ag | System and method for enabling a vendor mode on an integrated circuit |
DE10258199B4 (de) * | 2002-12-12 | 2005-03-10 | Infineon Technologies Ag | Schaltungsanordnung mit einer Anzahl von integrierten Schaltungsbauelementen auf einem Trägersubstrat und Verfahren zum Test einer derartigen Schaltungsanordnung |
JP2005277338A (ja) * | 2004-03-26 | 2005-10-06 | Nec Electronics Corp | 半導体装置及びその検査方法 |
US7308624B2 (en) * | 2005-04-28 | 2007-12-11 | Infineon Technologies North America Corp. | Voltage monitoring test mode and test adapter |
US20100067203A1 (en) * | 2008-07-08 | 2010-03-18 | T-Ray Science Inc. | Apparatus for carrying photoconductive integrated circuits |
US7958283B2 (en) * | 2008-08-13 | 2011-06-07 | Intel Corporation | Observing an internal link via a second link |
US8977788B2 (en) * | 2008-08-13 | 2015-03-10 | Intel Corporation | Observing an internal link via an existing port for system on chip devices |
US8563336B2 (en) * | 2008-12-23 | 2013-10-22 | International Business Machines Corporation | Method for forming thin film resistor and terminal bond pad simultaneously |
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EP0218852A1 (de) * | 1985-09-13 | 1987-04-22 | Siemens Aktiengesellschaft | Integrierter Schaltkreis mit NC-Pins und Verfahren zu seinem Betreiben |
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-
1996
- 1996-09-19 US US08/718,173 patent/US5796746A/en not_active Expired - Lifetime
-
1997
- 1997-08-20 AT AT97938416T patent/ATE208953T1/de not_active IP Right Cessation
- 1997-08-20 AU AU40743/97A patent/AU4074397A/en not_active Abandoned
- 1997-08-20 KR KR10-1999-7002370A patent/KR100400952B1/ko not_active IP Right Cessation
- 1997-08-20 JP JP51466998A patent/JP3705443B2/ja not_active Expired - Fee Related
- 1997-08-20 WO PCT/US1997/014564 patent/WO1998012706A1/en active IP Right Grant
- 1997-08-20 EP EP97938416A patent/EP0928486B1/de not_active Expired - Lifetime
- 1997-08-20 DE DE69708314T patent/DE69708314T2/de not_active Expired - Lifetime
- 1997-08-26 TW TW086112230A patent/TW356576B/zh not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117434428A (zh) * | 2023-12-18 | 2024-01-23 | 杭州晶华微电子股份有限公司 | 芯片校准***、芯片校准模式进入方法及芯片 |
Also Published As
Publication number | Publication date |
---|---|
US5796746A (en) | 1998-08-18 |
KR100400952B1 (ko) | 2003-10-10 |
KR20000048488A (ko) | 2000-07-25 |
JP2001500659A (ja) | 2001-01-16 |
EP0928486B1 (de) | 2001-11-14 |
DE69708314D1 (de) | 2001-12-20 |
JP3705443B2 (ja) | 2005-10-12 |
EP0928486A1 (de) | 1999-07-14 |
WO1998012706A1 (en) | 1998-03-26 |
TW356576B (en) | 1999-04-21 |
AU4074397A (en) | 1998-04-14 |
DE69708314T2 (de) | 2002-07-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |