WO2024108830A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2024108830A1
WO2024108830A1 PCT/CN2023/082799 CN2023082799W WO2024108830A1 WO 2024108830 A1 WO2024108830 A1 WO 2024108830A1 CN 2023082799 W CN2023082799 W CN 2023082799W WO 2024108830 A1 WO2024108830 A1 WO 2024108830A1
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WIPO (PCT)
Prior art keywords
buffer block
word line
isolation structure
buffer
filling layer
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PCT/CN2023/082799
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English (en)
French (fr)
Inventor
梅晓波
邓放心
周震
吕嘉伟
Original Assignee
长鑫存储技术有限公司
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Publication of WO2024108830A1 publication Critical patent/WO2024108830A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a method for manufacturing the same.
  • DRAM dynamic random access memory
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising a plurality of discrete active areas and an isolation structure located between adjacent active areas, the substrate comprising a word line area extending along a first direction; forming a buffer block and a filling layer, wherein the buffer block is located on a portion of the isolation structure between adjacent active areas of the word line area, and the buffer block is spaced apart from adjacent active areas, and the filling layer is located on the substrate and fills the area between adjacent buffer blocks; using a dry etching process to etch the filling layer, the buffer block, the isolation structure and the active area of the word line area to form a word line groove, wherein, in the word line area, a surface of the isolation structure facing the filling layer is exposed to the environment of the dry etching process before a surface of the isolation structure facing the buffer layer; forming a word line structure filling the word line groove.
  • the dry etching process has an etching rate on the buffer block that is lower than an etching rate on the filling layer.
  • the method of forming the buffer block and the filling layer includes: forming the buffer block first, and then forming the filling layer.
  • the step of forming the filling layer includes: forming a filling film on the substrate, the filling film filling the area between adjacent buffer blocks and also covering the top surface of the buffer block; planarizing the filling film, and the remaining filling film serves as the filling layer.
  • the stop position of the planarization process is the top surface of the buffer block, and the top surface of the formed filling layer is flush with the top surface of the buffer block.
  • the process steps of forming the buffer block include: forming a buffer layer on the substrate to cover the entire surface of the substrate; and patterning the buffer layer to form the buffer block.
  • a ratio of the depth of the opening to the thickness of the filling layer is in the range of 0.5-1.
  • the total width of the second buffer block is greater than or equal to the total width of the first buffer block; wherein the total width of the second buffer block is greater than 0; and the total width of the first buffer block is greater than or equal to 0.
  • the first buffer block is located in a central area of the first isolation structure; and/or the second buffer block is located in a central area of the second isolation structure.
  • the buffer block crosses the word line region along the second direction and is also located in the second direction. A region adjacent to the word line region on the substrate, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction.
  • the buffer block spans across at least two of the word line regions.
  • the thickness of the buffer block in a direction perpendicular to the surface of the substrate, is 2 nm to 4 nm.
  • the material of the buffer block includes nitride or oxynitride; the material of the filling layer includes oxide; and the material of the isolation structure includes oxide.
  • the present disclosure further provides a semiconductor structure on the other hand, comprising: a substrate, the substrate comprising a plurality of discrete active regions and an isolation structure located between adjacent active regions, the substrate comprising a word line region extending along a first direction; a word line structure, the word line structure being located within the word line region, the word line structure spanning the active regions and the isolation structure, wherein, in the first direction, the word line structure within the isolation structure located between adjacent active regions has at least two recesses.
  • the word line structure includes: a first word line portion, the first word line portion is located in a first isolation structure, the first isolation structure is located between a pair of adjacent active regions, and the first word line portion has at least two recessed portions; a second word line portion, the second word line portion is located in a second isolation structure, the second isolation structure is located between another pair of adjacent active regions, the second word line portion has at least two recessed portions, and along the first direction, the width of the second isolation structure is greater than the width of the first isolation structure.
  • the method for forming a semiconductor structure first provides a substrate, the substrate including a plurality of discrete active areas and an isolation structure located between adjacent active areas, the substrate including a word line area extending along a first direction; then a buffer block and a filling layer are formed, the buffer block is located on a portion of the isolation structure between adjacent active areas in the word line area, and the buffer block is spaced apart from the adjacent active areas, the filling layer is located on the substrate, and fills the area between adjacent buffer blocks; a dry etching process is used to etch the filling layer, the buffer block, the isolation structure and the active area in the word line area to form a word line groove, wherein, in the word line area, a surface of the isolation structure facing the filling layer is exposed to the dry etching process environment before a surface of the isolation structure facing the buffer layer; finally, a word line structure filling the word line groove is formed.
  • the depth of the word line structure facing the center area of the isolation layer will be greater than the depth of the word line structure facing the edge area of the isolation layer.
  • the word line structure located in the isolation structure presents a U-shaped structure, and the two side walls of the U-shaped word line structure are far away from the active area, which will result in the word line having a lower control ability over the channel of the active area.
  • the buffer block since a buffer block is formed on the surface of the isolation structure, when etching to form a word line groove, the buffer block causes different areas of the surface of the isolation structure to be in contact with the etching environment for different times, and the center of the isolation structure facing the buffer block is The surface of the area is exposed to the etching environment later.
  • the buffer block can delay the etching of the central area of the isolation structure by the etching environment, so that the etching progress of the central area of the isolation structure and the etching progress of the edge of the isolation structure are balanced to a certain extent.
  • the area of the isolation structure etched by the etching process will extend to both sides, so that the two side walls of the word line structure finally etched are closer to the active area, which can effectively improve the control ability of the word line over the channel in the active area.
  • 1 to 18 are schematic structural diagrams of various steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 19 is a schematic diagram of a cross-sectional structure of a semiconductor structure provided in accordance with an embodiment of the present disclosure.
  • the semiconductor structure manufactured by the current semiconductor structure manufacturing method has the problem that the word line has poor channel control capability over the active region.
  • the disclosed embodiment provides a method for manufacturing a semiconductor structure, first providing a substrate, the substrate including a plurality of discrete active areas and an isolation structure located between the active areas, the substrate including a word line area extending along a first direction; forming a buffer block and a filling layer, the buffer block being located on a portion of the isolation structure between adjacent active areas of the word line area, and the buffer block being spaced apart from the adjacent active areas, the filling layer being located on the substrate and filling the area between the adjacent buffer blocks.
  • a dry etching process is used to etch the word line groove, the filling layer, the buffer block, the isolation structure and the active area of the word line area, in the word line area, the surface of the isolation structure facing the isolation layer is exposed to the dry etching process before the surface of the isolation structure facing the buffer layer, and finally a word line structure filling the word line groove is formed. In this way, the control capability of the word line over the channel of the active area can be improved.
  • FIG. 1 to 18 are schematic structural diagrams of the steps of the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.
  • Fig. 1 is a schematic cross-sectional view of a step of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
  • Fig. 2 is a schematic top view of Fig. 1 , and the cross-sectional view direction of Fig. 1 is the X direction.
  • a substrate 100 is provided.
  • the substrate 100 includes a plurality of discrete active regions 110 and an isolation structure 120 located between adjacent active regions 110 .
  • the substrate 100 includes a word line region 130 extending along a first direction X.
  • a plurality of discrete active regions 110 are arranged in an array on the substrate 100, and the isolation structure 120 surrounds the active region 110, and there is an isolation structure 120 between every two adjacent active regions 110.
  • the width of the isolation structure 120 between every two adjacent active regions 110 is inconsistent, the width of the isolation structure 120 between some adjacent active regions 110 is narrower, and the width of the isolation structure 120 between other adjacent active regions 110 is wider.
  • the material of the active region 110 may include silicon, and the active region 110 is used to form a transistor in a semiconductor structure in a subsequent step.
  • the material of the isolation structure 120 may include silicon oxide, and the isolation structure 120 is used to isolate different active regions 110.
  • the word line region 130 is used to form a word line structure in a subsequent step.
  • the word line structure contacts the plurality of active regions 110 and constitutes a part of the finally formed semiconductor structure.
  • a buffer block 140 and a filling layer 150 are formed, wherein the buffer block 140 is located on a portion of the isolation structure 120 between adjacent active areas 110 of the word line area 130, and the buffer block 140 is spaced apart from the adjacent active areas 110, and the filling layer 150 is located on the substrate 100 and fills the area between adjacent buffer blocks 140.
  • the buffer block 140 can ensure that different areas of the surface of the isolation structure 120 where the word line grooves are to be formed are exposed to the etching environment for different times when the semiconductor structure is subsequently subjected to the process step of etching the word line grooves. This can change the morphology of the etched word line grooves, which is beneficial for widening the width of the word line grooves in the isolation structure 120, reducing the distance between the word line grooves and the active areas 110 on both sides of the isolation structure 120, and improving the control ability of the word line over the channel of the active area 110.
  • the surface of the substrate 100 may be thinned, and the surface to be thinned is the surface of the side of the substrate 100 where the word line structure is to be formed.
  • the thinning process allows the surface of each active area 110 and the surface of the isolation structure 120 to be exposed on the surface of the substrate 100, so as to form the buffer block 140 and the filling layer 150 in the subsequent steps.
  • the process method for thinning the surface of the substrate 100 may be chemical mechanical polishing (CMP).
  • buffer block 140 and the filling layer 150 There are multiple methods for forming the buffer block 140 and the filling layer 150 , and there are multiple sizes and positions of the buffer block 140 and the filling layer 150 , which will be described in detail below.
  • the method of forming the buffer block 140 and the filling layer 150 may include: first forming the buffer block 140, and then forming the filling layer 150. The following will take the method of first forming the buffer block 140 and then forming the filling layer 150 as an example. Describe the example.
  • the process steps of forming the buffer block 140 may include: forming a buffer layer 141 on the substrate 100 to cover the entire surface of the substrate 100 ; and then patterning the buffer layer 141 to form the buffer block 140 .
  • the buffer layer 141 may cover the surfaces of all active regions 110 on the surface of the substrate 100 and the surface of the isolation structure 120.
  • the process step of forming the buffer layer 141 may be a deposition process. Forming the buffer layer 141 first may reduce the process difficulty of manufacturing the buffer block 140.
  • the buffer layer 141 (refer to FIG4 ) is patterned to form a buffer block 140.
  • the patterning process may be an etching process.
  • the patterned buffer layer 141 is located on the surface of the isolation structure 120, and can adjust the contact time between the etching environment and each region of the isolation structure 120 when etching the word line grooves in the subsequent process, so that the width of the etched word line grooves becomes wider.
  • the step of forming a filling layer 150 may include: forming a filling film 151 on the substrate 100, the filling film 151 filling the area between adjacent buffer blocks 140 and also covering the top surface of the buffer block 140; planarizing the filling film 151, and the remaining filling film 151 serves as the filling layer 150.
  • a filling film 151 is first formed on the substrate 100, and the height of the filling film 151 is greater than the height of the buffer block 140 formed in the aforementioned step, that is, the filling film 151 completely covers the buffer block 140.
  • the process method for forming the filling film 151 may include a deposition method. Since the portion of the filling film 151 that exceeds the height of the buffer block 140 has the same etching rate in the same etching environment, in the subsequent step of etching the word line groove, the etching starting position is the upper surface of the semiconductor structure away from the substrate 100, and the portion of the filling film 151 that exceeds the height of the buffer block 140 has no obvious beneficial effect on the subsequently formed word line groove.
  • the filling film 151 can be thinned, that is, the filling film 151 can be flattened to reduce the time used for etching in the subsequent etching process.
  • the process method for the flattening treatment can be a chemical mechanical polishing process.
  • FIG 7 is a schematic diagram of a structure after a filling film 151 is planarized to form a filling layer 150.
  • the stop position of the planarization process can be higher than the top surface of the buffer block 140, and the formed filling layer 150 can also cover the top surface of the buffer block 140. In this way, it can be ensured that the size of the buffer block 140 will not be changed during the planarization process, and the complete buffer block 140 can be retained without weakening the buffering effect of the buffer block 140 on etching the word line groove in the subsequent process steps, and the size of the filling layer 150 can be reduced as much as possible, reducing the process time of the subsequent etching process.
  • FIG8 is a schematic diagram of the structure of another filling film 151 (refer to FIG7) after being planarized to form a filling layer 150.
  • the stop position of the planarization process may be the top surface of the buffer block 140, and the formed The top surface of the filling layer 150 can be flush with the top surface of the buffer block 140. In this way, unnecessary consumption in the subsequent etching process can be reduced to the greatest extent, and the process time, process energy consumption, process raw materials, etc. of the etching process can be reduced, which can effectively improve the manufacturing efficiency of the semiconductor structure.
  • the above is a method for forming the buffer block 140 and the filling layer 150 , in which the buffer block 140 is formed first and then the filling layer 150 is formed.
  • the buffer block 140 and the filling layer 150 may be formed by first forming the filling layer 150 and then forming the buffer block 140.
  • the filling layer 150 may be formed first, and the filling layer 150 has an opening 152 extending from the top surface to the bottom surface; and the buffer block 140 is formed to fill the opening 152.
  • the following description is based on the example of first forming the filling layer 150 and then forming the buffer block 140.
  • a filling layer 150 is first formed, and a plurality of openings 152 are provided in the filling layer 150.
  • the openings 152 are used to form buffer blocks 140 in subsequent steps.
  • the positions of the openings 152 are positions where the buffer blocks 140 need to be formed later.
  • the width of the openings along the first direction X is the width of the buffer blocks 140 needed to be formed later.
  • the height of the openings 152 can be equal to the height of the buffer blocks 140 needed to be formed later.
  • the process steps for forming the filling layer 150 may include: first forming a whole layer of filling film on the surface of the substrate 100, the filling film covering all active areas 110 and isolation structures 120 on the surface of the substrate 100; and then patterning the whole layer of filling film to form the filling layer 150 having the openings 152.
  • the ratio of the depth of the opening 152 to the thickness of the filling layer 150 is in the range of 0.5-1.
  • the ratio of the depth of the opening 152 to the thickness of the filling layer 150 may be 0.5, 0.6, 0.68, 0.72, 0.83, 0.96, 1, etc. It is understandable that the depth of the opening 152 is the height of the buffer block 140 to be formed later.
  • the ratio of the depth of the opening 152 to the thickness of the filling layer 150 is greater than or equal to 0.5 and less than 1, the opening 152 does not penetrate the filling layer 150; when the ratio of the depth of the opening 152 to the thickness of the filling layer 150 is 1, the opening 152 penetrates the filling layer 150.
  • the buffer block 140 may not penetrate the filling layer 150, or the buffer block 140 may also penetrate the filling layer 150.
  • the ratio of the depth of the opening 152 to the thickness of the filling layer 150 also needs to be greater than or equal to 0.5 and less than 1, that is, the ratio of the height of the buffer block 140 to the height of the filling layer 150 also needs to be greater than 0.5 and less than 1, and the thickness of the buffer block 140 still needs to retain a certain value.
  • the buffer block 140 can still have a better buffering effect, can effectively adjust the contact time between the etching environment and the surface areas of the isolation structure 120, and adjust the distance between the sidewall of the word line structure and the active areas 110 on both sides.
  • the process steps of forming the buffer block 140 may include: referring to FIG. 10 , forming a buffer layer 141, wherein the buffer layer 141 fills the opening 152 and is also located on the top surface of the filling layer 150; referring to FIG. 11 , removing the buffer layer 141 above the top surface of the filling layer 150, and the remaining buffer layer 141 serves as the buffer block 140.
  • the buffer block 140 can be formed.
  • the opening 152 is completely filled with the buffer block 140 , and there is no gap or blank in the opening 152 .
  • the buffer block 140 can more effectively exert its buffering effect in subsequent steps.
  • the process step of forming the buffer block 140 may also be to directly form the buffer block 140 that fills the opening 152 , which can make the manufacturing process of the semiconductor structure more concise.
  • the process steps for forming the buffer block 140 may also be: first forming a buffer layer 141 that fills the opening 152 and is also located on the top surface of the filling layer 150, without processing the buffer layer 141, directly using the buffer layer 141 as the buffer block 140, and performing subsequent steps.
  • the width of the buffer layer 141 as the buffer block 140 in the first direction X is relatively large, but it does not affect the improvement of the morphology of the word line groove formed subsequently by the buffer block 140.
  • the above is a method for forming the filling layer 150 first and then forming the buffer block 140.
  • the buffer block 140 and the filling layer 150 may also have different sizes and positions, which will be described in detail below.
  • the method for forming the buffer block 140 may further include: forming a first buffer block 142, the first buffer block 142 being located on a portion of the first isolation structure 121, the first isolation structure 121 being located between a pair of active regions 110 adjacent to each other in the first direction; forming a second buffer block 143, the second buffer block 143 being located on a portion of the second isolation structure 122, the second isolation structure 122 being located between another pair of active regions 110 adjacent to each other in the first direction, and the width of the second isolation structure 122 being greater than the width of the first isolation structure 121 along the first direction X.
  • the isolation structure 120 exposed on the surface of the substrate 100 has different widths
  • the width of the second isolation structure 122 is greater than the width of the first isolation structure 121
  • the buffer blocks 140 formed on the first isolation structure 121 and the second isolation structure 122 may also be different
  • the buffer blocks 140 formed on the surfaces of the first isolation structure 121 and the second isolation structure 122 may be the first buffer block 142 and the second buffer block 143, respectively.
  • the total width of the second buffer block 143 may be greater than or equal to the total width of the first buffer block 142.
  • the total width of the second buffer block 143 may be greater than 0; the total width of the first buffer block 142 may be greater than or equal to 0. That is, the width of the second buffer block 143 on the wider second isolation structure 122 is wider, and the width of the first buffer block 142 on the narrower first isolation structure 121 is narrower.
  • the wider second isolation structure 122 when etching to form a word line groove, the distance between the word line groove and the active areas 110 on both sides is farther, and the control effect of the word line structure formed in the wider isolation structure 120 on the active area 110 is weaker than that of the word line structure formed in the narrower isolation structure 120 on the active area 110, and it is more necessary to set a buffer block 140 on the isolation structure 120 for adjustment.
  • the wider second buffer block 143 can further enhance the control of the subsequently formed word line structure over the channel of the active area 110 . Therefore, forming the wider second buffer block 143 on the surface of the wider second isolation structure 122 can better enhance the control of the word line over the active area 110 .
  • the width of the first buffer block 143 may be equal to 0. That is, only the surface of the second isolation structure 122 has the second buffer block 143, and the surface of the first isolation structure 121 may not have the first buffer block 142 (refer to FIG. 12 ).
  • the buffer block 140 configured in this way can also enhance the control effect of the word line at the wider second isolation structure 122 on the active area 110, and since the number of buffer blocks 140 is reduced, the process flow can be simplified and the process difficulty can be reduced.
  • the second buffer block 143 may include at least two separate sub-buffer blocks 1431.
  • the first buffer block 142 may be located in the central region of the first isolation structure 121, and/or the second buffer block 143 may be located in the central region of the second isolation structure 122. Being located in the central region means that the position of the first buffer block 142 or the second buffer block 143 on the surface of the first isolation structure 121 or the second isolation structure 122 may be located in the central region of the corresponding isolation structure along the first direction X, and the position of the first buffer block 142 or the second buffer block 143 on the surface of the first isolation structure 121 or the second isolation structure 122 may be located in the central region of the corresponding isolation structure along a direction perpendicular to the first direction X.
  • the buffer block 140 can change the contact time between the etching environment and the central region and the edge region of the isolation structure, thereby changing the etching depth of the etching environment to the central region and the edge region of the isolation structure 120, and changing the morphology of the etched word line groove.
  • the time for the center area of the isolation structure 120 to contact the etching environment can be appropriately delayed, which can achieve a better effect of improving the word line groove morphology.
  • the position of the buffer block 140 on the surface of the isolation structure 120 can also be offset relative to the center area.
  • first buffer block 142 and the second buffer block 143 may both be located in the central area of the first isolation structure 121 and the second isolation structure 122, or the first buffer block 142 may be located in the central area of the first isolation structure 121 and the second buffer block 143 may not be located in the central area of the second isolation structure 122, or the first buffer block 142 may not be located in the central area of the first isolation structure 121 and the second buffer block 143 may be located in the central area of the second isolation structure 122.
  • FIG. 15 is a schematic diagram of a top view of a step in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. It should be noted that, for the sake of illustration, the figure does not show all structures in the semiconductor structure.
  • the buffer block 140 may cross the word line region 130 along the second direction Y, and is also located in an area adjacent to the word line region 130 in the second direction Y, wherein the second direction Y is parallel to the surface of the substrate 100 and perpendicular to the first direction X.
  • the buffer block 140 is located in the first direction Y.
  • the length in the second direction Y there are many situations for the length in the second direction Y: for example, the first sub-buffer block 1401 spans across multiple word line regions 130 along the second direction Y, and the first sub-buffer block 1401 covers multiple first isolation structures 121 and second isolation structures 122; for another example, the length of the second sub-buffer block 1402 in the second direction Y can be greater than the length of the word line region 130 in the second direction Y, and such a second sub-buffer block 1402 can be located on the surface of the first isolation structure 121 or the surface of the second isolation structure 122; for another example, the length of the third sub-buffer block 1403 in the second direction Y can also be less than the length of the word line region 130 in the second direction Y, and such a third sub-buffer block 1403 can also be located on the surface of the first isolation structure 121 or the surface of the second isolation structure 122.
  • the size of the buffer block 140 along the second direction Y is larger as shown in FIG. 15, and in the actual production process, it can reduce the process difficulty of making the buffer block 140 to a certain extent, which is conducive to improving the production efficiency.
  • the buffer block 140 is not etched in the area outside the word line area 130.
  • the etching environment can only act on the word line area 130, which can simplify the process flow and reduce the process difficulty while ensuring that a suitable word line groove is etched.
  • the buffer block 140 may span across at least two word line regions 130.
  • the buffer block 140 may span across multiple word line regions 130 along the second direction Y, and multiple word line regions 130 share the same buffer block 140.
  • the buffer block 140 configured in this way has a larger size in the second direction Y, which can further reduce the process difficulty of manufacturing the buffer block 140 in the actual production process, and because the number of buffer blocks 140 is reduced, the process flow can also be simplified, which is conducive to improving production efficiency.
  • the thickness of the buffer block 140 in the direction perpendicular to the surface of the substrate 100, may be 2nm to 4nm.
  • the thickness of the buffer block 140 in the direction perpendicular to the surface of the substrate 100, may be 2nm, 2.8nm, 3nm, 3.3nm, 4nm, etc.
  • the thickness of the buffer block 140 will affect the degree of change of the morphology of the word line groove formed subsequently by the buffer block 140, and will affect the improvement of the control ability of the word line over the channel of the active area 110.
  • the thickness of the buffer block 140 is too thick in the direction perpendicular to the surface of the substrate 100, it may cause a certain waste, and the bottom surface of the word line groove facing the central area of the isolation structure 120 may be too high relative to the bottom surface of the word line groove facing the edge area of the isolation structure 120. If the thickness of the buffer block 140 is too thin in the direction perpendicular to the surface of the substrate 100, it may not play a better role in improving the morphology of the word line groove, and it may not effectively improve the control ability of the word line over the channel of the active area 110. Therefore, the thickness of the buffer block 140 needs to be selected within a suitable range. When the thickness of the buffer block 140 is 2 nm to 4 nm, the subsequently formed word line can have a stronger control capability over the active area 110 without causing a waste of materials.
  • the material of the buffer block 140 may include nitride or oxynitride, for example, the material of the buffer block 140 may include silicon nitride or silicon oxynitride, etc.
  • the material of the filling layer 150 may include oxide, for example, the material of the filling layer 150 may include silicon oxide, etc.
  • the material of the isolation structure 120 may include oxide, for example, the material of the isolation structure 120 may include silicon oxide, etc.
  • a dry etching process is adopted to etch the filling layer 150 (refer to Figure 14), the buffer block 140, the isolation structure 120 and the active area 110 of the word line area 130 to form a word line groove 160, wherein, in the word line area 130, the surface of the isolation structure 120 facing the filling layer 150 is exposed to the dry etching process environment before the surface of the isolation structure 120 facing the buffer layer 141.
  • the word line groove 160 etched at this time is used to form a word line structure in subsequent steps.
  • the morphology of the word line groove 160 is the morphology of the word line structure. The closer the distance between the two side walls of the word line groove 160 in the first direction X and the active area 110 is, the stronger the control ability of the word line structure over the active area 110 is.
  • the etching rate of the buffer block 140 by the dry etching process may be lower than the etching rate of the filling layer 150.
  • the word line groove 160 is etched by the dry etching process along the second direction Y toward the substrate 100, the buffer block 140 located in the central area of the isolation structure 120 and the filling layer 150 located in the edge area of the isolation structure 120 are in contact with the dry etching environment at the same time, and the thickness of the buffer block 140 and the filling layer 150 in the direction perpendicular to the substrate surface is consistent.
  • the isolation structure 120 directly facing the buffer block 140 will be exposed later than the isolation structure 120 directly facing the filling layer 150, thereby improving the morphology of the word line groove 160, so that the distance between the two side walls of the word line groove 160 along the second direction Y and the active area 110 is smaller.
  • the central area of the bottom surface can protrude in the direction away from the substrate 100 relative to the edge area.
  • FIG. 17 is a schematic cross-sectional structural diagram of a step of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure
  • FIG. 18 is a schematic top structural diagram of FIG. 17 .
  • a word line structure 170 filling the word line groove 160 is formed.
  • the process method for forming the word line structure 170 may be a deposition method, and the word line structure may include a dielectric layer and a conductive layer.
  • the morphology of the word line structure 170 is the same as the morphology of the word line groove 160.
  • the two side walls of the word line structure 170 along the first direction X are close to the active area 110, and the word line structure 170 has a strong control capability over the channel of the active area 110, thereby improving the performance of the semiconductor structure.
  • a word line capping layer 180 may be further formed.
  • the word line capping layer 180 is located on a surface of the word line structure 170 away from the substrate 100 .
  • the word line structure 170 and the word line capping layer 180 together fill the word line groove 160 .
  • the present disclosure provides a method for manufacturing a semiconductor structure.
  • a substrate 100 is provided.
  • the substrate 100 has a plurality of active regions 110 and an isolation structure 120 located between the active regions 110.
  • the substrate 100 also includes a word line region 130 extending along a first direction X.
  • a buffer block 140 and a filling layer 150 are formed.
  • the buffer block 140 is located adjacent to the word line region 130.
  • the filling layer 150 is located on the substrate 100, and fills between the adjacent buffer blocks 140; wherein the size, position and formation method of the buffer block 140 can have many variations; a dry etching process is used to etch the word line groove 160 in the word line area 130, and the surface of the isolation structure 120 facing the filling layer 150 is exposed to the dry etching process environment before the surface of the isolation structure 120 facing the buffer block 140; finally, a word line structure 170 is formed that fills the word line groove 160. In this way, the control ability of the word line structure 170 on the channel of the active area 110 can be improved.
  • another embodiment of the present disclosure further provides a semiconductor structure, which is manufactured by the manufacturing method of the above-mentioned semiconductor structure.
  • the semiconductor structure provided by another embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. For the parts that are the same or corresponding to the previous embodiment, reference can be made to the corresponding description of the previous embodiment, and will not be described in detail below.
  • FIG. 19 is a schematic diagram of a cross-sectional structure of a semiconductor structure provided in accordance with an embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 100, the substrate 100 includes a plurality of discrete active regions 110 and an isolation structure 120 located between adjacent active regions 110, the substrate 100 includes a word line region 130 extending along a first direction X (refer to Figure 2); a word line structure 170, the word line structure 170 is located in the word line region 130, the word line structure 170 spans the active region 110 and the isolation structure 120, wherein, in the first direction X, the word line structure 170 in the isolation structure 120 located between adjacent active regions 110 has at least two recesses 171.
  • the substrate 100 includes an active region 110 and an isolation structure 120.
  • a plurality of discrete active regions 110 are arranged in an array on the substrate 100, and the isolation structure 120 is located between adjacent active regions 110.
  • the material of the active region 110 may include silicon.
  • the material of the isolation structure 120 may include silicon oxide.
  • the active region 110 is a transistor in a semiconductor structure, and the substrate 100 includes a plurality of transistors arranged in an array, and the word line structure 170 is connected to the gate of the transistor, that is, the word line structure 170 is in contact with the active region 110.
  • the word line structure 170 has at least two recessed portions 171, that is, a word line structure 170 is located on the bottom surface inside the substrate 100, and has at least two regions with depths greater than the depths of other regions. According to the above-mentioned semiconductor structure manufacturing method embodiment, among the word line structures 170 located in the isolation structure 120 between adjacent active regions 110, the word line structures 170 located in the center region of the isolation structure 120 along the first direction X have a smaller bottom surface depth, and the word line structures 170 located in the edge region of the isolation structure 120 along the first direction X have a larger bottom surface depth.
  • the word line structure 170 further includes: a first word line portion 172, the first word line portion 172 is located in the first isolation structure 121, the first isolation structure 121 is located between a pair of adjacent active regions 110, and the first word line portion 172 has at least two recessed portions 171; a second word line portion 173, the second word line portion 173 is located in the second isolation structure 122, and the second isolation structure 121 is located between a pair of adjacent active regions 110.
  • the word line structure 170 is located between another pair of adjacent active regions 110, the second word line portion 173 has at least two recessed portions 171, and the width of the second isolation structure 122 is greater than the width of the first isolation structure 121 along the first direction X.
  • the second word line portion 173 is inside the second isolation structure 122 with a wider width, and the first word line portion 172 is inside the first isolation structure 121 with a narrower width.
  • Both the first word line portion 172 and the second word line portion 173 may include at least two recessed portions 171.
  • Such a word line structure 170 has a smaller distance between the two side walls in the first direction X and the active region 110, and the word line structure 170 has a stronger ability to control the channel of the active region 110.
  • the semiconductor structure may further include a word line capping layer 180 .
  • the word line capping layer 180 is located on a surface of the word line structure 170 away from the substrate 100 .
  • the word line structure 170 and the word line capping layer 180 together fill the word line groove 160 .
  • the embodiment of the present disclosure provides a semiconductor structure, including: a substrate 100, the substrate 100 includes a plurality of discrete active regions 110 and an isolation structure 120 located between adjacent active regions 110, the substrate 100 includes a word line region 130 extending along a first direction X; a word line structure 170, the word line structure 170 is located in the word line region 130, the word line structure 170 spans the active region 110 and the isolation structure 120, and the word line structure 170 in the isolation structure 120 between adjacent active regions 110 in the first direction X has at least two recessed portions 171. In this way, the word line structure 170 has a stronger control effect on the channel of the active region 110.

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Abstract

公开了一种半导体结构及其制造方法。制造方法包括：提供包括多个有源区、隔离结构且具有字线区的基底；形成缓冲块以及填充层，缓冲块位于字线区的部分隔离结构上，填充层位于基底上，且填充相邻缓冲块之间的区域；干法刻蚀字线区的填充层、缓冲块、隔离结构以及有源区，形成字线凹槽，字线区中，与填充层正对的隔离结构表面先于与缓冲层正对的隔离结构表面暴露在干法刻蚀工艺的环境中；形成字线结构。

Description

半导体结构及其制造方法
交叉引用
本公开要求于2022年11月24日递交的名称为“半导体结构及其制造方法”、申请号为202211486292.5的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及其制造方法。
背景技术
随着半导体器件密度的增加，动态随机存储器(Dynamic Random Access Memory，简称：DRAM)的特征尺寸逐渐缩小。对于50nm及以下制程的DRAM，为了减少栅极占用晶体管的面积，DRAM的字线广泛使用埋入式字线(Buried Wordline)，埋入式字线的使用极大减少了字线对有源区的占用面积(相对于非埋入式字线，埋入式字线对有源区面积的占用减少40％～60％)。
然而，目前具有埋入式字线的半导体结构的制造方法还存在一定的问题。
发明内容
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制造方法，包括：提供基底，所述基底包括多个分立的有源区以及位于相邻所述有源区之间的隔离结构，所述基底包括沿第一方向延伸的字线区；形成缓冲块以及填充层，其中，所述缓冲块位于所述字线区的相邻的所述有源区之间的部分所述隔离结构上，且所述缓冲块与相邻的所述有源区相间隔，所述填充层位于所述基底上，且填充相邻所述缓冲块之间的区域；采用干法刻蚀工艺，刻蚀所述字线区的所述填充层、所述缓冲块、所述隔离结构以及所述有源区，以形成字线凹槽，其中，所述字线区中，与所述填充层正对的隔离结构表面先于与所述缓冲层正对的所述隔离结构表面暴露在所述干法刻蚀工艺的环境中；形成填充所述字线凹槽的字线结构。
在一些实施例中，所述干法刻蚀工艺对所述缓冲块的刻蚀速率小于对所述填充层的刻蚀速率。
在一些实施例中，形成所述缓冲块以及所述填充层的方法包括：先形成所述缓冲块，后形成所述填充层。
在一些实施例中，形成所述填充层的步骤包括：在所述基底上形成填充膜，所述填充膜填充满相邻所述缓冲块之间的区域，且还覆盖所述缓冲块顶面；对所述填充膜进行平坦化处理，剩余所述填充膜作为所述填充层。
在一些实施例中，所述平坦化处理的停止位置高于所述缓冲块顶面，形成的所述填充层还覆盖所述缓冲块顶面。
在一些实施例中，所述平坦化处理的停止位置为所述缓冲块顶面，形成的所述填充层顶面与所述缓冲块顶面齐平。
在一些实施例中，形成所述缓冲块的工艺步骤包括：在所述基底上形成覆盖所述基底整个表面的缓冲层；对所述缓冲层进行图形化处理，以形成所述缓冲块。
在一些实施例中，形成所述缓冲块以及所述填充层的方法包括：先形成所述填充层，且所述填充层内具有自顶面向底面延伸的开口；形成填充满所述开口的所述缓冲块。
在一些实施例中，所述开口的深度与所述填充层的厚度的比值在0.5-1范围内。
在一些实施例中，形成所述缓冲块的工艺步骤包括：形成缓冲层，所述缓冲层填充满所述开口且还位于所述填充层顶面；去除高于所述填充层顶面的所述缓冲层，剩余所述缓冲层作为所述缓冲块。
在一些实施例中，形成所述缓冲块的方法还包括：形成第一缓冲块，所述第一缓冲块位于部分第一隔离结构上，所述第一隔离结构位于在所述第一方向上相邻的一对所述有源区之间；形成第二缓冲块，所述第二缓冲块位于部分第二隔离结构上，所述第二隔离结构位于在所述第一方向上相邻的另一对所述有源区之间，且在沿所述第一方向上，所述第二隔离结构的宽度大于所述第一隔离结构的宽度。
在一些实施例中，在沿所述第一方向上，所述第二缓冲块的总宽度大于或等于所述第一缓冲块的总宽度；其中，所述第二缓冲块的总宽度大于0；所述第一缓冲块的总宽度大于或等于0。
在一些实施例中，同一所述第二隔离结构上，所述第二缓冲块包括至少2个相分立的子缓冲块。
在一些实施例中，所述第一缓冲块位于所述第一隔离结构的中心区域；和/或，所述第二缓冲块位于所述第二隔离结构的中心区域。
在一些实施例中，所述缓冲块沿第二方向横跨所述字线区，且还位于在所述第二方向 上与所述字线区相邻的区域，其中，所述第二方向平行于所述基底表面且垂直于所述第一方向。
在一些实施例中，所述缓冲块横跨至少两个所述字线区。
在一些实施例中，在垂直于所述基底表面的方向上，所述缓冲块的厚度为2nm～4nm。
在一些实施例中，所述缓冲块的材料包括氮化物或者氮氧化物；所述填充层的材料包括氧化物；所述隔离结构的材料包括氧化物。
根据本公开一些实施例，本公开另一方面还提供一种半导体结构，包括：基底，所述基底包括多个分立的有源区以及位于相邻所述有源区之间的隔离结构，所述基底包括沿第一方向延伸的字线区；字线结构，所述字线结构位于所述字线区内，所述字线结构横跨所述有源区以及所述隔离结构，其中，在所述第一方向上，位于相邻的所述有源区之间的所述隔离结构内的所述字线结构具有至少两个凹陷部。
在一些实施例中，所述字线结构包括：第一字线部，所述第一字线部位于第一隔离结构内，所述第一隔离结构位于一对相邻所述有源区之间，所述第一字线部具有至少两个凹陷部；第二字线部，所述第二字线部位于第二隔离结构内，所述第二隔离结构位于另一对相邻所述有源区之间，所述第二字线部具有至少两个凹陷部，且在沿所述第一方向上，所述第二隔离结构的宽度大于所述第一隔离结构的宽度。
本公开实施例提供的技术方案至少具有以下优点：
本公开实施例提供的半导体结构的形成方法，首先提供基底，基底包括多个分立的有源区以及位于相邻有源区之间的隔离结构，基底包括沿第一方向延伸的字线区；接着形成缓冲块以及填充层，缓冲块位于字线区的相邻的有源区之间的部分隔离结构上，且缓冲块与相邻的有源区相间隔，填充层位于基底上，并且填充相邻缓冲块之间的区域；采用干法刻蚀工艺刻蚀字线区的填充层、缓冲块、隔离结构以及有源区，以形成字线凹槽，其中，字线区中，与填充层正对的隔离结构表面先于与缓冲层正对的隔离结构表面暴露在干法刻蚀工艺环境中；最后形成填充字线凹槽的字线结构。在相关技术中，对隔离层进行刻蚀形成埋入式字线时，由于刻蚀工艺的特性，与隔离层中心区域正对的字线结构的深度会大于与隔离层边缘区域正对的字线结构的深度，位于隔离结构内的字线结构呈现U型结构，并且，U型字线结构的两侧壁距离有源区的距离较远，这会导致字线对有源区的沟道的控制能力较低。本公开实施例提供的半导体结构的制造方法中，由于隔离结构表面形成了缓冲块，刻蚀形成字线凹槽时，缓冲块使得隔离结构表面各区域与刻蚀环境接触的时间不同，隔离结构中心处与缓冲块正对 的区域的表面与刻蚀环境接触的时间较晚。缓冲块能够延缓刻蚀环境对隔离结构中心区域的刻蚀，使得隔离结构的中心区域的刻蚀进度与隔离结构边缘的刻蚀进度得到一定程度的平衡，刻蚀工艺刻蚀的隔离结构的区域范围会向两侧延伸，使得最终刻蚀出的字线结构的两侧壁与有源区的距离较近，能够有效得提高字线对有源区内沟道的控制能力。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1至图18为本公开一实施例提供的一种半导体结构的制造方法的各步骤的结构示意图；
图19为本公开一实施例提供的一种半导体结构的剖面结构示意图。
具体实施方式
由背景技术可知，目前的半导体结构的制造方法制造出的半导体结构存在字线对有源区的沟道控制能力较差的问题。
本公开实施例提供一种半导体结构的制造方法，首先提供基底，基底包括多个分立的有源区以及位于有源区之间的隔离结构，基底包括沿第一方向延伸的字线区；形成缓冲块以及填充层，缓冲块位于字线区的相邻有源区之间的部分隔离结构上，且缓冲块与相邻有源区相间隔，填充层位于基底上，并填充相邻缓冲块之间的区域。接着采用干法刻蚀工艺刻蚀字线凹槽，刻蚀字线区的填充层、缓冲块、隔离结构以及有源区，在字线区中，与隔离层正对的隔离结构表面先于与缓冲层正对的隔离结构的表面暴露在干法刻蚀的工艺中，最后形成填充字线凹槽的字线结构。如此，能够提高字线对有源区的沟道的控制能力。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图1至图18为本公开实施例提供的半导体结构的制造方法的各步骤的结构示意图。 图1为本公开一实施例提供的半导体结构制造方法的一步骤的剖面结构示意图。图2为图1的俯视结构示意图，图1的剖视方向为X方向。
参考图1至图2，提供基底100，基底100包括多个分立的有源区110以及位于相邻有源区110之间的隔离结构120，基底100包括沿第一方向X延伸的字线区130。
其中，多个分立的有源区110在基底100上呈阵列式排布，且隔离结构120环绕于有源区110的周围，每两个相邻有源区110之间均具有隔离结构120。在沿第一方向X上，每两个相邻有源区110之间的隔离结构120的宽度不一致，一些相邻有源区110之间的隔离结构120的宽度较窄，另一些相邻有源区110之间的隔离结构120的宽度较宽。有源区110的材料可以包括硅，有源区110用于在后续步骤中形成半导体结构中的晶体管。隔离结构120的材料可以包括氧化硅，隔离结构120用于隔离不同的有源区110。
字线区130在后续步骤中用于形成字线结构，字线结构与多个有源区110相接触构成最终形成的半导体结构的一部分。
参考图3至图15，形成缓冲块140以及填充层150，其中，缓冲块140位于字线区130的相邻的有源区110之间的部分隔离结构120上，且缓冲块140与相邻的有源区110相间隔，填充层150位于基底100上，且填充相邻缓冲块140之间的区域。
缓冲块140可以使得半导体结构在后续进行刻蚀字线凹槽的工艺步骤时，需形成字线凹槽的隔离结构120表面的不同区域接触到刻蚀环境的时间不同，能够改变刻蚀出的字线凹槽的形貌，有利于使得隔离结构120内的字线凹槽的宽度变宽，字线凹槽距离隔离结构120两侧有源区110的距离变小，字线对有源区110沟道的控制能力得到提高。
参考图3，在形成缓冲块140以及填充层150之前，可以先对基底100的表面进行减薄处理，需减薄的表面为基底100中需形成字线结构的一侧表面。减薄处理使得基底100的表面上能够露出每一有源区110的表面以及隔离结构120的表面，以便在后续步骤中形成缓冲块140以及填充层150。对基底100表面进行减薄处理的工艺方法可以为化学机械抛光技术(Chemical Mechanical Polishing，CMP)。
形成缓冲块140与填充层150的方法可以包括多种，形成的缓冲块140以及填充层150的尺寸以及位置也可以包括多种，以下将分别进行详细描述。
参考图4至图8，在一些实施例中，形成缓冲块140以及填充层150的方法可以包括：先形成缓冲块140，后形成填充层150。以下将以现在先形成缓冲块140再形成填充层150为 例进行描述。
参考图4至图5，在一些实施例中，形成缓冲块140的工艺步骤可以包括：在基底100上形成覆盖基底100整个表面的缓冲层141；再对缓冲层141进行图形化处理，以形成缓冲块140。
具体地，参考图4，缓冲层141可以覆盖基底100表面的所有有源区110的表面以及隔离结构120的表面。形成缓冲层141的工艺步骤可以为沉积工艺。这样先形成缓冲层141的方式可以降低制造缓冲块140的工艺难度。
参考图5，对缓冲层141(参考图4)进行图形化处理形成缓冲块140。进行图形化处理的工艺可以为刻蚀工艺。图形化处理后的缓冲层141位于隔离结构120表面，可以起到调整后续刻蚀字线凹槽时刻蚀环境与隔离结构120各个区域的接触的时间的作用，使得刻蚀出的字线凹槽宽度变宽。
参考图6至图8，在一些实施例中，形成填充层150的步骤可以包括：在基底100上形成填充膜151，填充膜151填充满相邻缓冲块140之间的区域，且还覆盖缓冲块140顶面；对填充膜151进行平坦化处理，剩余填充膜151作为填充层150。
具体地，参考图6，首先在基底100上形成填充膜151，填充膜151的高度大于前述步骤中形成的缓冲块140的高度，也就是说，填充膜151完全覆盖缓冲块140。形成填充膜151的工艺方法可以包括沉积方法。由于填充膜151超出缓冲块140高度的部分在相同的刻蚀环境中具有相同的刻蚀速率，在后续的刻蚀字线凹槽的步骤中，刻蚀起始位置为半导体结构中远离基底100的上表面，填充膜151超出缓冲块140高度的部分对后续形成的字线凹槽无明显有益影响。因此，可以将填充膜151进行减薄处理，即可把填充膜151进行平坦化处理以减小后续刻蚀工艺中用于刻蚀的时间。其中，平坦化处理的工艺方法可以为化学机械抛光工艺。
参考图7，图7为一种填充膜151进行平坦化处理后形成填充层150后的结构示意图。在一些实施例中，平坦化处理的停止位置可以高于缓冲块140顶面，形成的填充层150还可以覆盖缓冲块140顶面。如此，能够保证平坦化处理的过程不会改变缓冲块140的尺寸，既能够保留完整的缓冲块140，不削弱缓冲块140对后续工艺步骤中刻蚀字线凹槽的缓冲作用，又能尽可能减小填充层150的尺寸，减小后续刻蚀工艺的工艺时间。
参考图8，图8为另一种填充膜151(参考图7)进行平坦化处理后形成填充层150后的结构示意图。在一些实施例中，平坦化处理的停止位置可以为缓冲块140顶面，形成的 填充层150顶面与缓冲块140顶面可以齐平。如此，能够最大程度地减少后续刻蚀工艺中的不必要消耗，刻蚀工艺的工艺时间，工艺耗能、工艺原料等都能得到减小，能够有效地提高半导体结构的制造效率。
以上为形成缓冲块140以及填充层150中先形成缓冲块140再形成填充层150的形成方法。
参考图9至图11，在一些实施例中，形成缓冲块140以及填充层150还可以先形成填充层150再形成缓冲块140。可以先形成填充层150，且填充层150内具有自顶面向底面延伸的开口152；形成填充满开口152的缓冲块140。以下以先形成填充层150，再形成缓冲块140为例进行描述。
参考图9，首先形成填充层150，填充层150中具有多个开口152，开口152用于在后续步骤中形成缓冲块140，开口152的位置即为后续需形成缓冲块140的位置，开口沿第一方向X的宽度即为后续需形成的缓冲块140的宽度，开口152的高度可以等于后续需形成的缓冲块140的高度。其中，形成填充层150的工艺步骤可以包括：先在基底100表面形成一整层填充膜，填充膜覆盖基底100表面的全部有源区110以及隔离结构120；再对一整层填充膜进行图形化形成具有开口152的填充层150。
在一些实施例中，开口152的深度与填充层150的厚度的比值在0.5-1范围内。例如，开口152的深度与填充层150的厚度的比值可以为0.5、0.6、0.68、0.72、0.83、0.96、1等。可以理解的是，开口152的深度即为后续需形成的缓冲块140的高度。开口152的深度与填充层150的厚度的比值大于或等于0.5且小于1时，开口152并不贯穿填充层150；开口152的深度与填充层150的厚度的比值为1时，开口152贯穿填充层150。即缓冲块140可以不贯穿填充层150，或者，缓冲块140也可以贯穿填充层150。当缓冲块140不贯穿填充层150时，开口152的深度与填充层150厚度的比值也需要大于或等于0.5且小于1，即缓冲块140的高度与填充层150高度的比值也需要大于0.5且小于1，缓冲块140的厚度仍需保留一定的值。如此，在后续步骤中刻蚀字线凹槽时，缓冲块140仍然能够具有较佳的缓冲效果，能够有效调整刻蚀环境与隔离结构120的表面各区域接触的时间，调整字线结构的侧壁与两侧有源区110之间的距离。
参考图10至图11，在一些实施例中，形成缓冲块140的工艺步骤可以包括：参考图10，形成缓冲层141，缓冲层141填充满开口152且还位于填充层150顶面；参考图11，去除高于填充层150顶面的缓冲层141，剩余缓冲层141作为缓冲块140。如此可以使得缓冲块 140完全填充满开口，开口152中不具有缝隙以及空白，缓冲块140能够在后续步骤中更加有效地发挥其缓冲效果。
在另一些实施例中，形成缓冲块140的工艺步骤也可以为直接形成填满开口152的缓冲块140，可以使得半导体结构的制造工艺更加简洁。
在另一些实施例中，形成缓冲块140的工艺步骤还可以为：先形成填充满开口152且还位于填充层150顶面的缓冲层141，不对缓冲层141进行处理，直接将缓冲层141作为缓冲块140，进行后续步骤。此时作为缓冲块140的缓冲层141在第一方向X上的宽度较大，但并不影响缓冲块140对后续形成的字线凹槽形貌的改善。
以上为先形成填充层150再形成缓冲块140的形成方法。同样地，形成的缓冲块140以及填充层150也可以具有不同的尺寸以及位置，以下将进行详细描述。
参考图12，在一些实施例中，形成缓冲块140的方法还可以包括：形成第一缓冲块142，第一缓冲块142位于部分第一隔离结构121上，第一隔离结构121位于在第一方向上相邻的一对有源区110之间；形成第二缓冲块143，第二缓冲块143位于部分第二隔离结构122上，第二隔离结构122位于在第一方向上相邻的另一对有源区110之间，且在沿第一方向X上，第二隔离结构122的宽度大于第一隔离结构121的宽度。即对于基底100上的隔离结构120而言，基底100表面露出的隔离结构120具有不同的宽度，第二隔离结构122的宽度大于第一隔离结构121的宽度，第一隔离结构121与第二隔离结构122上形成的缓冲块140也可以不同，第一隔离结构121与第二隔离结构122表面形成的缓冲块140可以分别为第一缓冲块142和第二缓冲块143。
参考图12至图13，在一些实施例中，在沿第一方向X上，第二缓冲块143的总宽度可以大于或等于第一缓冲块142的总宽度。其中，第二缓冲块143的总宽度可以大于0；第一缓冲块142的总宽度可以大于或等于0。也就是说，在较宽的第二隔离结构122上的第二缓冲块143的宽度较宽，在较窄的第一隔离结构121上的第一缓冲块142的宽度较窄。这是由于较宽的第二隔离结构122中，在刻蚀形成字线凹槽时，字线凹槽距离两侧有源区110的距离较远，在较宽的隔离结构120中形成的字线结构对于有源区110的控制作用相较于较窄的隔离结构120中形成的字线结构对于有源区110的控制作用更弱，更需要在隔离结构120上设置缓冲块140进行调节。而较宽的第二缓冲块143对于后续形成的字线结构对有源区110的沟道的控制作用的提升会更大，因此，在较宽的第二隔离结构122表面形成较宽的第二缓冲块143能够更好地提升字线对有源区110的控制作用。
参考图13，第一缓冲块143的宽度可以等于0。也就是说，只有第二隔离结构122的表面上具有第二缓冲块143，第一隔离结构121表面可以不具有第一缓冲块142(参考图12)。如此设置的缓冲块140也能够提升较宽的第二隔离结构122处字线对有源区110的控制作用，并且，由于缓冲块140的数量变少，能够简化工艺流程、降低工艺难度。
参考图14，在一些实施例中，同一第二隔离结构122上，第二缓冲块143可以包括至少2个相分立的子缓冲块1431。在一较宽的第二隔离结构122表面，可以具有多个缓冲块，多个缓冲块在第一方向X上所占的总宽度较宽。使得第二隔离结构122上方的缓冲块在进行后续的字线凹槽刻蚀时，调节第二隔离结构122不同区域接触刻蚀环境的时间的能力较强，能够更好地提升字线对有源区110的控制效果。
在一些实施例中，第一缓冲块142可以位于第一隔离结构121的中心区域，和/或，第二缓冲块143可以位于第二隔离结构122的中心区域。位于中心区域是指第一缓冲块142或第二缓冲块143在第一隔离结构121或第二隔离结构122表面上的位置可以位于相应的隔离结构沿第一方向X的中心区域，第一缓冲块142或第二缓冲块143在第一隔离结构121或第二隔离结构122表面上的位置可以位于相应的隔离结构沿垂直于第一方向X的方向上的中心区域。这是由于在对隔离结构120进行刻蚀时，若不设置缓冲块140，刻蚀环境对隔离结构120的中心区域刻蚀的深度最深，刻蚀环境对隔离结构120的边缘区域刻蚀的深度最浅。缓冲块140可以改变刻蚀环境与隔离结构中心区域以及边缘区域的接触时间，从而改变刻蚀环境对隔离结构120中心区域以及边缘区域刻蚀的深度，改变刻蚀出的字线凹槽的形貌。缓冲块140位于隔离结构120中心区域时，可以适当延迟隔离结构120中心区域与刻蚀环境接触的时间，能够达到较佳的改善字线凹槽形貌的作用。在另一些实施例中，缓冲块140在隔离结构120表面的位置相对中心区域也可以有一定偏移。
另外，第一缓冲块142与第二缓冲块143在第一隔离结构121与第二隔离结构122表面的位置可以具有多种可能，第一缓冲块142与第二缓冲块143可以均位于第一隔离结构121与第二隔离结构122的中心区域，或第一缓冲块142位于第一隔离结构121的中心区域，第二缓冲块143不位于第二隔离结构122的中心区域，又或者，第一缓冲块142不位于第一隔离结构121的中心区域，第二缓冲块143位于第二隔离结构122的中心区域。
参考图15，图15为本公开实施例提供的半导体结构的制造方法中一步骤的俯视结构示意图。需要说明的是，为便于图示，图中并未示出半导体结构内的全部结构。在一些实施例中，缓冲块140沿第二方向Y可以横跨字线区130，且还位于在第二方向Y上与字线区130相邻的区域，其中，第二方向Y平行于基底100表面且垂直于第一方向X。缓冲块140在第 二方向Y上的长度存在多种情况：例如，第一子缓冲块1401在沿第二方向Y上横跨多个字线区130，此时第一子缓冲块1401覆盖多个第一隔离结构121以及第二隔离结构122；又例如，第二子缓冲块1402在第二方向Y上的长度可以大于字线区130在第二方向Y上的长度，这种第二子缓冲块1402可以位于第一隔离结构121表面，也可以位于第二隔离结构122表面；再例如，第三子缓冲块1403在第二方向Y上的长度还可以小于字线区130在第二方向Y上的长度，这种第三子缓冲块1403同样既可以位于第一隔离结构121表面，也可以位于第二隔离结构122表面。如图15中所示的第一子缓冲块1401以及第二子缓冲块1402这样设置的缓冲块140沿第二方向Y的尺寸较大，在实际的生产过程中，能够在一定程度上降低制作缓冲块140的工艺难度，有利于生产效率的提升。其中，在后续的干法刻蚀工艺过程中，缓冲块140位于字线区130以外的区域的部分未被刻蚀。刻蚀环境可以仅作用于字线区130，能够在保证刻蚀出合适的字线凹槽的同时，尽量简化工艺流程，降低工艺难度。
在一些实施例中，缓冲块140可以横跨至少两个字线区130。缓冲块140沿第二方向Y可以横跨多个字线区130，此时多个字线区130共用同一缓冲块140。这样设置的缓冲块140在第二方向Y上的尺寸较大，在实际生产过程中，能够进一步降低制作缓冲块140的工艺难度，并且，由于缓冲块140的数量减少，还能够简化工艺流程，有利于提升生产效率。
在一些实施例中，在垂直于基底100表面的方向上，缓冲块140的厚度可以为2nm～4nm。例如，在垂直于基底100表面的方向上，缓冲块140的厚度可以为2nm、2.8nm、3nm、3.3nm、4nm等。缓冲块140的厚度会影响到缓冲块140对后续形成的字线凹槽的形貌的改变程度，会影响字线对有源区110的沟道的控制能力的改善情况。若在垂直于基底100表面的方向上，缓冲块140的厚度过厚，则可能会造成一定的浪费，并且，与隔离结构120中心区域正对的字线凹槽的底面相对于与隔离结构120边缘区域正对的字线凹槽的底面可能过高。若在垂直于基底100表面的方向上，缓冲块140的厚度过薄，则可能无法起到较佳的改善字线凹槽形貌的作用，并且无法有效地改善字线对有源区110的沟道的控制能力。因此，缓冲块140的厚度需要选择合适的范围，缓冲块140的厚度为2nm～4nm时，能够使得后续形成的字线对有源区110的控制能力较强的同时，不造成材料的浪费。
在一些实施例中，缓冲块140的材料可以包括氮化物或者氮氧化物，例如，缓冲块140的材料可以包括氮化硅或氮氧化硅等。填充层150的材料可以包括氧化物，例如，填充层150的材料可以包括氧化硅等。隔离结构120的材料可以包括氧化物，例如，隔离结构120的材料可以包括氧化硅等。如此，能够使得在后续进行刻蚀字线凹槽的工艺步骤时，同一刻蚀环境对缓冲块140的刻蚀速率小于对填充层150以及隔离结构120的刻蚀速率，使得缓冲 块140能够起到改变字线凹槽的形貌的作用。
参考图16，采用干法刻蚀工艺，刻蚀字线区130的填充层150(参考图14)、缓冲块140、隔离结构120以及有源区110，以形成字线凹槽160，其中，字线区130中，与填充层150正对的隔离结构120表面先于与缓冲层141正对的隔离结构120表面暴露在干法刻蚀工艺的环境中。
此时刻蚀出的字线凹槽160用于在后续步骤中形成字线结构，字线凹槽160的形貌即为字线结构的形貌，字线凹槽160在第一方向X上的两侧壁与有源区110的距离越近，字线结构对有源区110的控制能力越强。
在一些实施例中，干法刻蚀工艺对缓冲块140的刻蚀速率可以小于对填充层150的刻蚀速率。在干法刻蚀工艺沿第二方向Y朝向基底100方向刻蚀字线凹槽160时，位于隔离结构120中心区域的缓冲块140与位于隔离结构120边缘区域的填充层150同时与干法刻蚀环境相接触，且缓冲块140与填充层150在垂直于基底表面的方向上的厚度一致。由于干法刻蚀工艺对缓冲块140的刻蚀速率小于对填充层150的刻蚀速率，与缓冲块140正对的隔离结构120会晚于与填充层150正对的隔离结构120被暴露出，从而改善字线凹槽160的形貌，使得字线凹槽160沿第二方向Y的两侧壁与有源区110的距离更小。而对于刻蚀出的字线凹槽160的底面，底面的中心区域可以相对于边缘区域朝向远离基底100的方向突出。
图17为本公开一实施例提供的半导体结构的制造方法的一步骤的剖面结构示意图，图18为图17的俯视结构示意图。
参考图17至图18，形成填充字线凹槽160的字线结构170。
在一些实施例中，形成字线结构170的工艺方法可以为沉积方法，字线结构可以包括介质层和导电层。字线结构170的形貌与字线凹槽160的形貌相同。字线结构170沿第一方向X的两侧壁距离有源区110的距离较近，字线结构170对有源区110的沟道的控制能力较强，提高了半导体结构的性能。
参考图19，还可以形成字线盖层180，字线盖层180位于字线结构170远离基底100的表面上，字线结构170和字线盖层180共同填充满字线凹槽160。
本公开实施例提供一种半导体结构的制造方法，首先提供基底100，基底100上具有多个有源区110以及位于有源区110之间的隔离结构120，基底100中还包括沿第一方向X延伸的字线区130；接着形成缓冲块140以及填充层150，缓冲块140位于字线区130的相邻 有源区110之间的部分隔离结构120上，且缓冲块140与相邻有源区110相间隔，填充层150位于基底100上，且填充相邻缓冲块140之间；其中，缓冲块140的尺寸、位置以及形成方式可以具有诸多变形；采用干法刻蚀工艺在字线区130中刻蚀字线凹槽160，与填充层150正对的隔离结构120表面先于与缓冲块140正对的隔离结构120表面暴露在干法刻蚀工艺的环境中；最后形成填充满字线凹槽160的字线结构170。如此，能够提高字线结构170对有源区110的沟道的控制能力。
相应的，本公开另一实施例还提供一种半导体结构，这一半导体结构由上述半导体结构的制造方法制造得出。以下将结合附图对本公开另一实施例提供的半导体结构进行详细说明，与前一实施例相同或者相应的部分，可参考前述实施例的相应说明，以下将不做详细赘述。
图19为本公开一实施例提供的一种半导体结构的剖面结构示意图。
参考图19，半导体结构包括：基底100，基底100包括多个分立的有源区110以及位于相邻有源区110之间的隔离结构120，基底100包括沿第一方向X延伸的字线区130(参考图2)；字线结构170，字线结构170位于字线区130内，字线结构170横跨有源区110以及隔离结构120，其中，在第一方向X上，位于相邻的有源区110之间的隔离结构120内的字线结构170具有至少两个凹陷部171。
基底100中包括有源区110以及隔离结构120。多个分立的有源区110在基底100上阵列排布，隔离结构120位于相邻有源区110之间。有源区110的材料可以包括硅。隔离结构120的材料可以包括氧化硅。有源区110在半导体结构中即为晶体管，在基底100中包括多个阵列排布的晶体管，字线结构170与晶体管的栅极相连接，即字线结构170与有源区110相接触。
字线结构170具有至少两个凹陷部171，即，一字线结构170位于基底100内部的底面上，至少具有两个区域的深度大于其他区域的深度。根据上述半导体结构的制造方法实施例可知，位于相邻有源区110之间的隔离结构120内的字线结构170中，位于隔离结构120沿第一方向X中心区域的字线结构170的底面深度较小，位于隔离结构120沿第一方向X边缘区域的字线结构170的底面深度较大。
在一些实施例中，字线结构170还包括：第一字线部172，第一字线部172位于第一隔离结构121内，第一隔离结构121位于一对相邻有源区110之间，第一字线部172具有至少两个凹陷部171；第二字线部173，第二字线部173位于第二隔离结构122内，第二隔离结 构122位于另一对相邻有源区110之间，第二字线部173具有至少两个凹陷部171，且在沿第一方向X上，第二隔离结构122的宽度大于第一隔离结构121的宽度。即，在沿第一方向X上，宽度较宽的第二隔离结构122内为第二字线部173，宽度较窄的第一隔离结构121内为第一字线部172。第一字线部172与第二字线部173均可以包括至少两个凹陷部171。这样的字线结构170在第一方向X上的两侧壁与有源区110的距离较小，字线结构170对有源区110的沟道的控制能力较强。
在一些实施例中，半导体结构还可以包括字线盖层180，字线盖层180位于字线结构170远离基底100的表面上，字线结构170和字线盖层180共同填充满字线凹槽160。
本公开实施例提供一种半导体结构，包括：基底100，基底100上包括多个分立的有源区110以及位于相邻有源区110之间的隔离结构120，基底100包括沿第一方向X延伸的字线区130；字线结构170，字线结构170位于字线区130内，字线结构170横跨有源区110以及隔离结构120，并且，在第一方向X上，相邻有源区110之间的隔离结构120内的字线结构170至少具有两个凹陷部171。如此，字线结构170对有源区110的沟道的控制作用较强。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自更动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种半导体结构的制造方法，包括：
    提供基底(100)，所述基底(100)包括多个分立的有源区(110)以及位于相邻所述有源区(110)之间的隔离结构(120)，所述基底(100)包括沿第一方向(X)延伸的字线区(130)；
    形成缓冲块(140)以及填充层(150)，其中，所述缓冲块(140)位于所述字线区(130)的相邻的所述有源区(110)之间的部分所述隔离结构(120)上，且所述缓冲块(140)与相邻的所述有源区(110)相间隔，所述填充层(150)位于所述基底(100)上，且填充相邻所述缓冲块(140)之间的区域；
    采用干法刻蚀工艺，刻蚀所述字线区(130)的所述填充层(150)、所述缓冲块(140)、所述隔离结构(120)以及所述有源区(110)，以形成字线凹槽(160)，其中，所述字线区(130)中，与所述填充层(150)正对的隔离结构(120)表面先于与所述缓冲层(141)正对的所述隔离结构(120)表面暴露在所述干法刻蚀工艺的环境中；
    形成填充所述字线凹槽(160)的字线结构(170)。
  2. 如权利要求1所述的制造方法，其中，所述干法刻蚀工艺对所述缓冲块(140)的刻蚀速率小于对所述填充层(150)的刻蚀速率。
  3. 如权利要求1所述的制造方法，其中，形成所述缓冲块(140)以及所述填充层(150)的方法包括：
    先形成所述缓冲块(140)，后形成所述填充层(150)。
  4. 如权利要求3所述的制造方法，其中，形成所述填充层(150)的步骤包括：
    在所述基底(100)上形成填充膜(151)，所述填充膜(151)填充满相邻所述缓冲块(140)之间的区域，且还覆盖所述缓冲块(140)顶面；
    对所述填充膜(151)进行平坦化处理，剩余所述填充膜(151)作为所述填充层(150)。
  5. 如权利要求4所述的制造方法，其中，所述平坦化处理的停止位置高于所述缓冲块(140)顶面，形成的所述填充层(150)还覆盖所述缓冲块(140)顶面。
  6. 如权利要求4所述的制造方法，其中，所述平坦化处理的停止位置为所述缓冲块(140)顶面，形成的所述填充层(150)顶面与所述缓冲块(140)顶面齐平。
  7. 如权利要求3所述的制造方法，其中，形成所述缓冲块(140)的工艺步骤包括：
    在所述基底(100)上形成覆盖所述基底(100)整个表面的缓冲层(141)；
    对所述缓冲层(141)进行图形化处理，以形成所述缓冲块(140)。
  8. 如权利要求1所述的制造方法，其中，形成所述缓冲块(140)以及所述填充层(150)的方法包括：
    先形成所述填充层(150)，且所述填充层(150)内具有自顶面向底面延伸的开口(152)；
    形成填充满所述开口(152)的所述缓冲块(140)。
  9. 如权利要求8所述的制造方法，其中，所述开口(152)的深度与所述填充层(150)的厚度的比值在0.5-1范围内。
  10. 如权利要求8所述的制造方法，其中，形成所述缓冲块(140)的工艺步骤包括：
    形成缓冲层(141)，所述缓冲层(141)填充满所述开口(152)且还位于所述填充层(150)顶面；
    去除高于所述填充层(150)顶面的所述缓冲层(141)，剩余所述缓冲层(141)作为所述缓冲块(140)。
  11. 如权利要求1所述的制造方法，其中，形成所述缓冲块(140)的方法还包括：
    形成第一缓冲块(142)，所述第一缓冲块(142)位于部分第一隔离结构(121)上，所述第一隔离结构(121)位于在所述第一方向(X)上相邻的一对所述有源区(110)之间；
    形成第二缓冲块(143)，所述第二缓冲块(143)位于部分第二隔离结构(122)上，所述第二隔离结构(122)位于在所述第一方向(X)上相邻的另一对所述有源区(110)之间，且在沿所述第一方向(X)上，所述第二隔离结构(122)的宽度大于所述第一隔离结构(121)的宽度。
  12. 如权利要求11所述的制造方法，其中，在沿所述第一方向(X)上，所述第二缓冲块(143)的总宽度大于或等于所述第一缓冲块(142)的总宽度；其中，所述第二缓冲块(143)的总宽度大于0；所述第一缓冲块(142)的总宽度大于或等于0。
  13. 如权利要求12所述的制造方法，其中，同一所述第二隔离结构(122)上，所述第二缓冲块(143)包括至少2个相分立的子缓冲块(1431)。
  14. 如权利要求11所述的制造方法，其中，所述第一缓冲块(142)位于所述第一隔离结构(121)的中心区域；和/或，所述第二缓冲块(143)位于所述第二隔离结构(122)的中心 区域。
  15. 如权利要求1所述的制造方法，其中，所述缓冲块(140)沿第二方向(Y)横跨所述字线区(130)，且还位于在所述第二方向(Y)上与所述字线区(130)相邻的区域，其中，所述第二方向(Y)平行于所述基底(100)表面且垂直于所述第一方向(X)。
  16. 如权利要求15所述的制造方法，其中，所述缓冲块(140)横跨至少两个所述字线区(130)。
  17. 如权利要求1所述的制造方法，其中，在垂直于所述基底(100)表面的方向上，所述缓冲块(140)的厚度为2nm～4nm。
  18. 如权利要求1所述的制造方法，其中，所述缓冲块(140)的材料包括氮化物或者氮氧化物；所述填充层(150)的材料包括氧化物；所述隔离结构(120)的材料包括氧化物。
  19. 一种半导体结构，包括：
    基底(100)，所述基底(100)包括多个分立的有源区(110)以及位于相邻所述有源区(110)之间的隔离结构，所述基底(100)包括沿第一方向(X)延伸的字线区(130)；
    字线结构(170)，所述字线结构(170)位于所述字线区(130)内，所述字线结构(170)横跨所述有源区(110)以及所述隔离结构(120)，其中，在所述第一方向(X)上，位于相邻的所述有源区(110)之间的所述隔离结构(120)内的所述字线结构(170)具有至少两个凹陷部(171)。
  20. 如权利要求19所述的半导体结构，其中，所述字线结构(170)包括：
    第一字线部(172)，所述第一字线部(172)位于第一隔离结构(121)内，所述第一隔离结构(121)位于一对相邻所述有源区(110)之间，所述第一字线部(172)具有至少两个凹陷部(171)；
    第二字线部(173)，所述第二字线部(173)位于第二隔离结构(122)内，所述第二隔离结构122位于另一对相邻所述有源区(110)之间，所述第二字线部173具有至少两个凹陷部(171)，且在沿所述第一方向(X)上，所述第二隔离结构(122)的宽度大于所述第一隔离结构(121)的宽度。
PCT/CN2023/082799 2022-11-24 2023-03-21 半导体结构及其制造方法 WO2024108830A1 (zh)

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