WO2024092961A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
WO2024092961A1
WO2024092961A1 PCT/CN2022/137471 CN2022137471W WO2024092961A1 WO 2024092961 A1 WO2024092961 A1 WO 2024092961A1 CN 2022137471 W CN2022137471 W CN 2022137471W WO 2024092961 A1 WO2024092961 A1 WO 2024092961A1
Authority
WO
WIPO (PCT)
Prior art keywords
ion
layer
region
ion implantation
doping
Prior art date
Application number
PCT/CN2022/137471
Other languages
English (en)
French (fr)
Inventor
魏丹清
罗清威
Original Assignee
武汉新芯集成电路制造有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉新芯集成电路制造有限公司 filed Critical 武汉新芯集成电路制造有限公司
Publication of WO2024092961A1 publication Critical patent/WO2024092961A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table

Definitions

  • the present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof.
  • Avalanche photodiode is a P-N junction type light detection diode, which uses the avalanche multiplication effect of carriers to amplify the photoelectric signal to improve the sensitivity of detection.
  • the avalanche photodiode structures currently used are guard ring type and pull-through (also known as pass) type.
  • the former is a ring-shaped isolation structure deposited on the basis of the latter to prevent avalanche breakdown at the edge of the P-N junction under high reverse voltage.
  • the currently commonly used pull-through avalanche photodiode read-through APD, also known as RAPD
  • read-through APD also known as RAPD
  • Read diode structure i.e., N+PIP+ type structure
  • I is a low-doped area close to the intrinsic, where most of the incident photons are absorbed and generate photogenerated carriers; the multiplied high electric field area is concentrated in a narrow area near the P-N+ junction; N+ and P+ are highly doped and low-resistance, which are used to reduce the contact resistance to facilitate connection with the electrode.
  • FIG. 1a and FIG. 1b it is a P-N junction structure, and its P-type material is composed of three parts.
  • the material absorbs the light energy and generates primary electron-hole pairs.
  • the photoelectrons are accelerated by the weaker electric field of the depletion layer in the I layer 12, and move to the P-N junction composed of the P layer 13 and the N+ layer 14.
  • the avalanche collision effect occurs under the acceleration of the strong electric field.
  • the photoelectrons that have obtained avalanche multiplication reach the N+ layer 14, and the holes are absorbed by the P+ layer 11.
  • the above semiconductor device has the following problems: 1) When a reverse bias voltage is applied to the avalanche photodiode, the potential difference between the P+ layer 11 and the N+ layer 14 is only in the vertical direction, and the carriers outside the width of the multiplication region 15 in the horizontal direction cannot reach the multiplication region 15, which leads to low detection efficiency; 2) In order to improve the detection efficiency, it is usually chosen to increase the width of the multiplication region 15 in the horizontal direction by increasing the width of the N+ layer 14, but this will cause the defects and damage caused by the shallow trench and/or deep trench etching on the periphery of the avalanche photodiode to directly contact the multiplication region 15, which will cause the dark count rate to increase and reduce the device performance; 3) In order to improve the semiconductor device, the potential difference between the P+ layer 11 and the N+ layer 14 is only in the vertical direction, and the carriers outside the width of the multiplication region 15 in the horizontal direction cannot reach the multiplication region 15, which leads to low detection efficiency; 4) In order to improve the detection efficiency, the
  • the object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the detection efficiency of the semiconductor device.
  • the present invention provides a semiconductor device, comprising:
  • a substrate having a first surface and a second surface opposite to each other;
  • a first ion doping region and a second ion doping region of opposite doping types wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from a side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in a direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction.
  • the substrate includes a base and an intrinsic doping layer formed on the base, and the first ion doping region and the second ion doping region are formed in the intrinsic doping layer.
  • the doping type of the substrate is P type
  • the doping type of the first ion doping region is N type
  • the doping type of the second ion doping region is P type
  • the ion implantation regions of each layer are stacked layer by layer.
  • the ion implantation region far away from the first ion doping region wraps the ion implantation region close to the first ion doping region.
  • a width of a contact area between the second ion-doped region and the first ion-doped region in a direction parallel to the first surface is smaller than a width of the first ion-doped region in a direction parallel to the first surface.
  • the semiconductor device further includes:
  • a guard ring is formed at the periphery of the first ion-doped region.
  • the present invention also provides a method for manufacturing a semiconductor device, comprising:
  • a first ion doping region and a second ion doping region of opposite doping types are formed, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from a side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, wherein the ion doping concentration of each layer of the ion implantation regions increases layer by layer in a direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in a direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction.
  • the ion implantation regions of each layer are stacked layer by layer.
  • the ion implantation region far away from the first ion doping region wraps the ion implantation region close to the first ion doping region.
  • the method for manufacturing the semiconductor device further includes:
  • a guard ring is formed at the periphery of the first ion doped region.
  • the semiconductor device of the present invention comprises a first ion doping region and a second ion doping region of opposite doping types, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from a side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in the direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction, thereby improving the detection efficiency of the semiconductor device.
  • the manufacturing method of the semiconductor device of the present invention forms a first ion doping region and a second ion doping region of opposite doping types, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from the side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in the direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction, thereby improving the detection efficiency of the semiconductor device.
  • FIG. 1a is a schematic diagram of a semiconductor device
  • FIG. 1b is a schematic diagram of carrier diffusion of the semiconductor device shown in FIG. 1a ;
  • FIG. 2a is a schematic diagram of a semiconductor device according to an embodiment of the present invention.
  • FIG2b is a schematic diagram of carrier diffusion of the semiconductor device shown in FIG2a;
  • FIG. 3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • An embodiment of the present invention provides a semiconductor device, comprising: a substrate, the substrate having a first surface and a second surface opposite to each other; a first ion doping region and a second ion doping region of opposite doping types, the first ion doping region extending from the first surface into the substrate, the second ion doping region extending from a side of the first ion doping region away from the first surface toward the second surface, the second ion doping region comprising at least two layers of ion implantation regions, the ion doping concentration of each layer of the ion implantation regions increasing layer by layer in a direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in a direction parallel to the first surface increasing layer by layer, so that the first ion doping region and the second ion doping region form a graded junction.
  • the semiconductor device provided in this embodiment is described in detail below with reference to FIG. 2a and FIG. 2b.
  • the substrate includes a base 21 and an intrinsic doping layer 211 formed on the base 21, wherein the intrinsic doping layer 211 is an epitaxial layer formed on the base 21 by an epitaxial process, and the substrate has a first surface and a second surface opposite to each other, wherein the side of the intrinsic doping layer 211 away from the base 21 is the first surface, and the side of the base 21 away from the intrinsic doping layer 211 is the second surface.
  • the intrinsic doping layer 211 has a very low doping level (e.g., less than 5 ⁇ 10 14 atoms/cm 3 ).
  • the intrinsic doping layer 211 may be an unintentionally doped semiconductor substrate, i.e., a substrate having P- or N-type doping caused only by accidental contamination by impurities during its manufacture.
  • the intrinsic doping layer 211 may also be a semiconductor substrate with a higher doping level.
  • the doping types of the substrate 21 and the intrinsic doping layer 211 may be the same or different.
  • the doping type of the substrate 21 is P-type, and the doping type of the intrinsic doping layer 211 may be N-type or P-type; the doping type of the substrate 21 is N-type, and the doping type of the intrinsic doping layer 211 may be N-type or P-type.
  • the substrate 21 is P+ type, the intrinsic doping layer 211 is P- type, and the doping concentration of the substrate 21 is greater than the doping concentration of the intrinsic doping layer 211.
  • the material of the substrate can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs) or indium phosphide (InP), etc.
  • the first ion doping region 22 and the second ion doping region 23 are formed in the substrate, that is, the first ion doping region 22 extends from the first surface of the substrate into the substrate, and the second ion doping region 23 extends from the side of the first ion doping region 22 away from the first surface toward the second surface.
  • the first ion doping region 22 and the second ion doping region 23 can be formed in the intrinsic doping layer 211. Since the ion doping concentration of the intrinsic doping layer 211 is very low, which is much smaller than the ion doping concentration of the first ion doping region 22 and the second ion doping region 23, the intrinsic doping layer 211 can be used as a neutral region.
  • the first ion-doped region 22 and the second ion-doped region 23 have opposite doping types, and the second ion-doped region 23, the substrate 21 and the intrinsic doping layer 211 have the same doping type.
  • the first ion-doped region 22 has an N-type doping type
  • the second ion-doped region 23, the substrate 21 and the intrinsic doping layer 211 have a P-type doping type, so that a P-N junction is formed between the first ion-doped region 22 and the second ion-doped region 23.
  • the second ion doping region 23 includes at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation region increases layer by layer in the direction from the first surface to the second surface, and the width of each layer of the ion implantation region in the direction parallel to the first surface increases layer by layer, so that the first ion doping region 22 and the second ion doping region 23 form a graded junction.
  • the cross-sectional shape of each layer of the ion implantation region can be a circle, a square, a diamond or other suitable shapes.
  • the ion doping concentration of each layer of the ion implantation region can be greater than, equal to or less than the ion doping concentration of the substrate 21.
  • a multiplication region 27 is formed between the ion implantation region closest to the first ion doping region 22 and the first ion doping region 22.
  • each layer of the ion implantation area increases layer by layer in the direction from the first surface to the second surface
  • a vertical built-in electric field perpendicular to the first surface is formed between adjacent ion implantation areas, and the direction of the vertical built-in electric field is the same as the direction of the electric field generated by applying a reverse bias voltage to the photodiode in the working state, thereby increasing the diffusion speed of carriers to the multiplication zone 27, thereby reducing the carrier loss in the diffusion process, increasing the probability of avalanche occurrence, and thus improving the detection efficiency of the semiconductor device.
  • the thickness of the substrate is designed to be very large (usually above 7.5 ⁇ m) in order to improve the absorption efficiency of semiconductor devices for near-infrared light (905 nm to 940 nm)
  • the thickness of the intrinsic doping layer 211 is very large, while the thickness of the multiplication zone 27 is relatively small, resulting in the need for carriers to pass through a long distance of the depletion zone (from the P-N junction to the range where the intrinsic doping layer 211 and the substrate 21 are connected) to produce an avalanche.
  • a vertical built-in electric field is formed to increase the diffusion speed of the carriers, thereby reducing the energy consumption of the carriers in the depletion zone, and more carriers can diffuse into the multiplication zone 27, thereby increasing the probability of avalanche occurrence.
  • the width of each layer of the ion implantation region in the direction parallel to the first surface increases layer by layer from the first surface toward the second surface, so that the built-in electric field formed between adjacent ion implantation regions includes not only a vertical built-in electric field perpendicular to the first surface but also a curved built-in electric field that is non-parallel to the vertical built-in electric field.
  • the curved built-in electric field can diffuse the carriers in the edge area outside the width range of the ion implantation region in the intrinsic doping layer 211 into the multiplication region 27 under the action of the curved built-in electric field (as shown by the curved arrow in FIG. 2b ), thereby improving the utilization rate of the carriers and further improving the detection efficiency of the semiconductor device.
  • the orthographic projection of the vertical built-in electric field on the first surface overlaps with the orthographic projection of the ion implantation region closest to the first ion doping region 22 on the first surface; the curved built-in electric field is located outside the vertical built-in electric field and its orthographic projection on the first surface overlaps or intersects with the orthographic projection of the ion implantation region farthest from the first ion doping region 22 on the first surface.
  • Each layer of the ion implantation region may include but is not limited to being wrapped layer by layer or stacked layer by layer, and is arranged as required.
  • the doping depth of each layer of the ion implantation region in the direction perpendicular to the first surface extends from the interface between the first ion doping region 22 and the second ion doping region 23 toward the second surface, that is, in the adjacent ion implantation regions, the ion implantation region far away from the first ion doping region 22 is not only located at the bottom surface of the ion implantation region close to the first ion doping region 22, but also located at the side surface of the ion implantation region close to the first ion doping region 22, that is, the ion implantation region far away from the first ion doping region 22 wraps the ion implantation region close to the first ion doping region 22 in a groove shape.
  • the doping depth of each layer of the ion implantation regions in the direction perpendicular to the first surface extends from the interface of the adjacent ion implantation regions toward the second surface, and is distributed in a step-like manner similar to a hemisphere, that is, in the adjacent ion implantation regions, the ion implantation regions far away from the first ion doping region 22 are only located on the bottom surface of the ion implantation regions close to the first ion doping region 22, and not on the side surface of the ion implantation regions close to the first ion doping region 22.
  • the ion implantation regions of each layer may share the same axis; in the adjacent ion implantation regions, the doping depth of each layer of the ion implantation regions in the direction perpendicular to the first surface may be the same or different.
  • the width of the first ion doping region 22 in the direction parallel to the first surface may be between the maximum width and the minimum width of the ion implantation regions of each layer in the direction parallel to the first surface; or, the width of the first ion doping region 22 in the direction parallel to the first surface may be greater than the maximum width of the ion implantation regions of each layer in the direction parallel to the first surface; or, the width of the first ion doping region 22 in the direction parallel to the first surface may be less than the minimum width of the ion implantation regions of each layer in the direction parallel to the first surface.
  • the width of the contact area between the second ion doping area 23 and the first ion doping area 22 in a direction parallel to the first surface is smaller than the width of the first ion doping area 22 in a direction parallel to the first surface, so as to avoid lateral edge breakdown of the photodiode; wherein, when the ion implantation areas of each layer are stacked layer by layer, the width of the contact area between the second ion doping area 23 and the first ion doping area 22 in a direction parallel to the first surface is the width of the ion implantation area closest to the first ion doping area 22 in a direction parallel to the first surface, then, the width of the ion implantation area closest to the first ion doping area 22 in a direction parallel to the first surface is smaller than the width of the first ion doping area 22 in a direction parallel to the first surface; when the ion implantation areas of each layer are wrapped layer by layer, the width of the contact area between the second ion doping area 22
  • the second ion doping region 23 comprises four layers of ion implantation regions stacked in a direction from the first surface toward the second surface, namely, a first ion implantation region 231, a second ion implantation region 232, a third ion implantation region 233 and a fourth ion implantation region 234 stacked in layers, the ion doping concentration of the first ion implantation region 231 to the fourth ion implantation region 234 gradually increases, and the width of the first ion implantation region 231 to the fourth ion implantation region 234 in a direction parallel to the first surface gradually increases.
  • the number of ion implantation region layers in the second ion doping region 23 is not specifically limited and can be set as needed.
  • the semiconductor device further includes: an ion heavily doped region 221 formed on the surface of the first ion doped region 22 , and the ion heavily doped region 221 has the same doping type as the first ion doped region 22 .
  • the semiconductor device further includes a guard ring 24 formed at the periphery of the first ion doping region 22.
  • the guard ring 24 surrounds the first ion doping region 22, and the substrate is spaced between the guard ring 24 and the first ion doping region 22.
  • the depth of the guard ring 24 is not less than the depth of the first ion-doped region 22 .
  • the guard ring 24 may be a shallow trench isolation structure or an ion-doped ring. If the guard ring 24 is an ion-doped ring, the doping type of the ion-doped ring may be N-type or P-type.
  • the semiconductor device further includes: an annular deep trench isolation structure (not shown) formed in the substrate outside the guard ring 24, the deep trench isolation structure and the guard ring 24 being separated by the substrate, and the deep trench isolation structure is used to achieve isolation between adjacent photodiodes to avoid crosstalk.
  • annular deep trench isolation structure (not shown) formed in the substrate outside the guard ring 24, the deep trench isolation structure and the guard ring 24 being separated by the substrate, and the deep trench isolation structure is used to achieve isolation between adjacent photodiodes to avoid crosstalk.
  • the depth of the deep trench isolation structure is not less than the depth of the first ion doping region 22 .
  • the deep trench isolation structure is formed in an annular trench (not shown) in the substrate, and includes an insulating material layer (not shown) covering the inner surface of the annular trench and a conductive layer (not shown) filling the annular trench.
  • the width of the multiplication region 27 since in an embodiment of the present invention, there is no need to increase the width of the multiplication region 27 by increasing the width of the first ion doping region 22 in a direction parallel to the first surface, it is avoided that the width of the multiplication region 27 is too large, which causes the defects and damages generated by etching the grooves when forming the shallow trench isolation structure and the deep trench isolation structure to directly contact the multiplication region 27, thereby avoiding causing the dark count rate to increase and reduce the device performance.
  • the semiconductor device also includes: a first electrode 25 and a second electrode 26, the first electrode 25 is formed on the ion heavily doped region 221, and the second electrode 26 is formed on the first surface or the second surface of the substrate.
  • the second electrode 26 is formed on the second surface of the substrate; the ion heavily doped region 221 is used to connect the first ion doped region 22, so that when a voltage is applied to the first ion doped region 22 through the first electrode 25, the contact resistance is reduced; and a reverse bias voltage is applied to the photodiode through the first electrode 25 and the second electrode 26.
  • the semiconductor device comprises: a substrate having a first surface and a second surface facing each other; a first ion doping region and a second ion doping region of opposite doping types, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from the side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation region increases layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation region in the direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction.
  • the semiconductor device of the present invention can improve the detection efficiency of the semiconductor device.
  • FIG. 3 is a flow chart of the method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • the method for manufacturing a semiconductor device includes:
  • Step S1 providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other;
  • Step S2 forming a first ion-doped region and a second ion-doped region of opposite doping types, wherein the first ion-doped region extends from the first surface into the substrate, and the second ion-doped region extends from a side of the first ion-doped region away from the first surface toward the second surface, and the second ion-doped region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in a direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in a direction parallel to the first surface increases layer by layer, so that the first ion-doped region and the second ion-doped region form a graded junction.
  • a substrate is provided, wherein the substrate has a first surface and a second surface opposite to each other.
  • the substrate includes a base 21 and an intrinsic doping layer 211 formed on the base 21, the intrinsic doping layer 211 is an epitaxial layer formed on the base 21 by an epitaxial process, the side of the intrinsic doping layer 211 away from the base 21 is the first surface, and the side of the base 21 away from the intrinsic doping layer 211 is the second surface.
  • the doping types of the substrate 21 and the intrinsic doping layer 211 may be the same or different.
  • the doping type of the substrate 21 is P-type, and the doping type of the intrinsic doping layer 211 may be N-type or P-type; the doping type of the substrate 21 is N-type, and the doping type of the intrinsic doping layer 211 may be N-type or P-type.
  • the substrate 21 is P+ type, the intrinsic doping layer 211 is P- type, and the doping concentration of the substrate 21 is greater than the doping concentration of the intrinsic doping layer 211.
  • the material of the substrate can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs) or indium phosphide (InP), etc.
  • a first ion doping region 22 and a second ion doping region 23 of opposite doping types are formed, and the first ion doping region 22 and the second ion doping region 23 are formed in the substrate, that is, the first ion doping region 22 extends from the first surface of the substrate into the substrate, and the second ion doping region 23 extends from the side of the first ion doping region 22 away from the first surface toward the second surface.
  • the first ion doping region 22 and the second ion doping region 23 can be formed in the intrinsic doping layer 211. Since the ion doping concentration of the intrinsic doping layer 211 is very low, which is much smaller than the ion doping concentration of the first ion doping region 22 and the second ion doping region 23, the intrinsic doping layer 211 can be used as a neutral region.
  • the doping types of the first ion doping region 22 and the second ion doping region 23 are opposite, and the doping types of the second ion doping region 23, the substrate 21 and the intrinsic doping layer 211 are the same.
  • the doping type of the first ion doping region 22 is N-type
  • the doping type of the second ion doping region 23, the substrate 21 and the intrinsic doping layer 211 are P-type, so that a P-N junction is formed between the first ion doping region 22 and the second ion doping region 23.
  • the second ion doping region 23 includes at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in the direction from the first surface to the second surface, and the width of each layer of the ion implantation regions in the direction parallel to the first surface increases layer by layer, so that the first ion doping region 22 and the second ion doping region 23 form a graded junction.
  • a multiplication region 27 is formed between the ion implantation region closest to the first ion doping region 22 and the first ion doping region 22.
  • each layer of the ion implantation area increases layer by layer in the direction from the first surface to the second surface
  • a vertical built-in electric field perpendicular to the first surface is formed between adjacent ion implantation areas, and the direction of the vertical built-in electric field is the same as the direction of the electric field generated by applying a reverse bias voltage to the photodiode in the working state, thereby increasing the diffusion speed of carriers to the multiplication zone 27, thereby reducing the carrier loss in the diffusion process, increasing the probability of avalanche occurrence, and thus improving the detection efficiency of the semiconductor device.
  • the width of each layer of the ion implantation region in the direction parallel to the first surface increases layer by layer in the direction from the first surface to the second surface, so that the built-in electric field formed between adjacent ion implantation regions includes not only a vertical built-in electric field perpendicular to the first surface but also a curved built-in electric field that is non-parallel to the vertical built-in electric field.
  • the curved built-in electric field can diffuse the carriers in the edge area outside the width range of the ion implantation region in the intrinsic doping layer 211 into the multiplication region 27 under the action of the curved built-in electric field (as shown by the curved arrow in FIG. 2b ), thereby improving the utilization rate of the carriers and further improving the detection efficiency of the semiconductor device.
  • Each layer of the ion implantation region may include but is not limited to being wrapped layer by layer or stacked layer by layer, and is arranged as required.
  • the doping depth of each layer of the ion implantation region in the direction perpendicular to the first surface extends from the interface between the first ion doping region 22 and the second ion doping region 23 toward the second surface, that is, in the adjacent ion implantation regions, the ion implantation region far away from the first ion doping region 22 is not only located at the bottom surface of the ion implantation region close to the first ion doping region 22, but also located at the side surface of the ion implantation region close to the first ion doping region 22, that is, the ion implantation region far away from the first ion doping region 22 wraps the ion implantation region close to the first ion doping region 22 in a groove shape.
  • the doping depth of each layer of the ion implantation regions in the direction perpendicular to the first surface extends from the interface of the adjacent ion implantation regions toward the second surface, and is distributed in a step-like manner similar to a hemisphere, that is, in the adjacent ion implantation regions, the ion implantation regions far away from the first ion doping region 22 are only located at the bottom surface of the ion implantation regions close to the first ion doping region 22, and not at the side surface of the ion implantation regions close to the first ion doping region 22.
  • the ion implantation regions of each layer may share the same axis; in the adjacent ion implantation regions, the doping depth of each layer of the ion implantation regions in the direction perpendicular to the first surface may be the same or different.
  • the width of the first ion doping region 22 in the direction parallel to the first surface may be between the maximum width and the minimum width of the ion implantation regions of each layer in the direction parallel to the first surface; or, the width of the first ion doping region 22 in the direction parallel to the first surface may be greater than the maximum width of the ion implantation regions of each layer in the direction parallel to the first surface; or, the width of the first ion doping region 22 in the direction parallel to the first surface may be less than the minimum width of the ion implantation regions of each layer in the direction parallel to the first surface.
  • the width of the contact area between the second ion doping area 23 and the first ion doping area 22 in a direction parallel to the first surface is smaller than the width of the first ion doping area 22 in a direction parallel to the first surface, so as to avoid lateral edge breakdown of the photodiode; wherein, when the ion implantation areas of each layer are stacked layer by layer, the width of the contact area between the second ion doping area 23 and the first ion doping area 22 in a direction parallel to the first surface is the width of the ion implantation area closest to the first ion doping area 22 in a direction parallel to the first surface, then, the width of the ion implantation area closest to the first ion doping area 22 in a direction parallel to the first surface is smaller than the width of the first ion doping area 22 in a direction parallel to the first surface; when the ion implantation areas of each layer are wrapped layer by layer, the width of the contact area between the second ion doping area 22
  • the second ion doping region 23 comprises four ion implantation regions stacked in layers from the first surface toward the second surface, namely, the first ion implantation region 231, the second ion implantation region 232, the third ion implantation region 233 and the fourth ion implantation region 234 stacked in layers, the ion doping concentration of the first ion implantation region 231 to the fourth ion implantation region 234 gradually increases, and the width of the first ion implantation region 231 to the fourth ion implantation region 234 in the direction parallel to the first surface gradually increases.
  • the number of ion implantation region layers in the second ion doping region 23 is not specifically limited and can be set as needed.
  • An ion implantation process may be used to first form the first ion doping region 22 and then form the second ion doping region 23 , or to first form the second ion doping region 23 and then form the first ion doping region 22 .
  • the step of forming the second ion doping region 23 may include: first, forming a patterned mask layer (not shown) on the first surface of the substrate, the patterned mask layer having an opening for ion implantation into the substrate; then, when the layers of the ion implantation region are formed in sequence along the direction from the first surface to the second surface, the width of the opening can be adjusted to become larger by replacing the mask for multiple times, and after each adjustment of the width of the opening, the patterned mask layer with the opening of the adjusted width is used as a mask to perform ion implantation into the substrate, and the energy and dose of the ion implantation gradually increase with each increase in the width of the opening, so that a layer of ion implantation region with a predetermined depth and width is formed after each ion implantation; when the layers of the ion implantation region are formed in sequence along the direction from the second surface to the first surface, the width of the opening can be adjusted to
  • the mask is used to perform ion implantation into the substrate, wherein the energy and dosage of the ion implantation are gradually reduced as the width of the opening is adjusted each time, so that a layer of ion implantation region with a predetermined depth and width is formed after each ion implantation.
  • the substrate needs to be annealed to remove the breakage or damage of the semiconductor lattice caused by ion collision.
  • the method for manufacturing the semiconductor device further includes: forming an ion heavily doped region 221 on the surface of the first ion doped region 22 by an ion implantation process, wherein the ion heavily doped region 221 has the same doping type as the first ion doped region 22 .
  • the method for manufacturing the semiconductor device further includes: forming a guard ring 24 on the periphery of the first ion-doped region 22 , wherein the guard ring 24 surrounds the first ion-doped region 22 , and the substrate is spaced between the guard ring 24 and the first ion-doped region 22 .
  • the depth of the guard ring 24 is not less than the depth of the first ion-doped region 22 .
  • the guard ring 24 may be a shallow trench isolation structure or an ion-doped ring. If the guard ring 24 is an ion-doped ring, the doping type of the ion-doped ring may be N-type or P-type.
  • the manufacturing method of the semiconductor device also includes: forming an annular deep trench isolation structure (not shown) in the substrate outside the guard ring 24, the deep trench isolation structure and the guard ring 24 are separated by the substrate, and the deep trench isolation structure is used to achieve isolation between adjacent photodiodes to avoid crosstalk.
  • the depth of the deep trench isolation structure is not less than the depth of the first ion doping region 22 .
  • the deep trench isolation structure is formed in an annular trench (not shown) in the substrate, and includes an insulating material layer (not shown) covering the inner surface of the annular trench and a conductive layer (not shown) filling the annular trench.
  • the width of the multiplication region 27 since in an embodiment of the present invention, there is no need to increase the width of the multiplication region 27 by increasing the width of the first ion doping region 22 in a direction parallel to the first surface, it is avoided that the width of the multiplication region 27 is too large, which causes the defects and damage caused by etching the groove when forming the shallow trench isolation structure and the deep trench isolation structure to directly contact the multiplication region 27, thereby avoiding causing the dark count rate to increase and reduce the device performance.
  • the manufacturing method of the semiconductor device also includes: forming a first electrode 25 on the heavily ion-doped region 221, and forming a second electrode 26 on the first surface or the second surface of the substrate.
  • the second electrode 26 is formed on the second surface of the substrate; the heavily ion-doped region 221 is used to connect the first ion-doped region 22, so that when a voltage is applied to the first ion-doped region 22 through the first electrode 25, the contact resistance is reduced; and a reverse bias voltage is applied to the photodiode through the first electrode 25 and the second electrode 26.
  • the manufacturing method of the semiconductor device includes: providing a substrate, the substrate having a first surface and a second surface opposite to each other; forming a first ion doping region and a second ion doping region of opposite doping types, the first ion doping region extending from the first surface into the substrate, the second ion doping region extending from the side of the first ion doping region away from the first surface toward the second surface, the second ion doping region comprising at least two layers of ion implantation regions, the ion doping concentration of each layer of the ion implantation region increasing layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation region in the direction parallel to the first surface increasing layer by layer, so that the first ion doping region and the second ion doping region form a graded junction.
  • the manufacturing method of the semiconductor device of the present invention can improve the detection efficiency of the semiconductor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Light Receiving Elements (AREA)

Abstract

本发明提供了一种半导体器件及其制造方法，所述半导体器件包括：衬底，所述衬底具有相背的第一表面和第二表面；掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、且各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结。本发明的技术方案能够提高半导体器件的探测效率。

Description

半导体器件及其制造方法 技术领域
本发明涉及半导体集成电路制造领域，特别涉及一种半导体器件及其制造方法。
背景技术
雪崩光电二极管是一种P-N结型的光检测二极管，其中利用了载流子的雪崩倍增效应来放大光电信号以提高检测的灵敏度。目前使用的雪崩光电二极管结构形式有保护环型和拉通(又称通达)型，前者是在后者的基础上淀积一层环形的隔离结构，以防止在高反压时使P-N结边缘产生雪崩击穿。目前普遍使用的拉通型雪崩光电二极管(read-through APD，又称RAPD)，其基本结构常常采用容易产生雪崩倍增效应的Read二极管结构(即N+PIP+型结构)，其中，P+一面接收光；I为接近本征的低掺杂区，大部分入射光子在此被吸收并产生光生载流子；倍增的高电场区集中在P-N+结附近的窄区；N+、P+为高掺杂低阻压，用于减小接触电阻以利于与电极相连。
参阅图1a和图1b所示的一种半导体器件，是一个P-N结的结构形式，其P型材料由三部分构成，光子从P+层11射入，进入本征掺杂I(p)层12后，在这里，材料吸收了光能并产生了初级电子-空穴对。这时，光电子在I层12被耗尽层的较弱的电场加速，移向由P层13与N+层14构成的P-N结，受到强电场的加速作用出现雪崩碰撞效应，最后，获得雪崩倍增后的光电子到达N+层14，空穴被P+层11吸收。其耗尽区从P-N结区一直拉通到I层12与P+层11相接的范围内，其倍增区15位于P层13与N+层14构成的P-N结之间。耗尽区在整个范围内电场增加较小，当耗尽区中的场强达到足够大(～3*10^5V/cm)时，光生载流子将被加速到很高的速度，在运动过程中与晶格中的原子碰撞时会使之电离，产生额外的电子-空穴对。这些新生电子和空穴也被加速，发生新的碰撞和电离，产生更多的电子-空穴对，这个物理过程称为雪崩效应，它倍增了一次光电流，使之得到放大。
但是，上述半导体器件存在如下问题：1)当向雪崩光电二极管施加反向 偏置电压时，P+层11与N+层14之间的电势差只在垂直方向，水平方向上倍增区15宽度范围外的载流子无法到达倍增区15，进而导致探测效率低；2)为了提高探测效率，通常选择在水平方向上通过增加N+层14的宽度来使得倍增区15的宽度增大，但是会导致雪崩光电二极管***的浅沟槽和/或深沟槽刻蚀产生的缺陷、损伤等直接与倍增区15接触，进而导致引起暗计数率增加，降低器件性能；3)为了提升半导体器件对近红外光(905nm～940nm)的吸收效率，需要半导体器件的厚度很大(通常在7.5μm以上)，而在垂直方向上倍增区15的厚度较小，导致载流子需要通过扩散的方式经过P+层11与倍增区15之间的耗尽区内的很长一段距离的本征掺杂层12之后才能产生雪崩，且扩散过程中存在能量消耗，导致只有很少部分的载流子能产生雪崩，进而降低探测效率，且扩散时间较长也影响了半导体器件的灵敏度。
因此，如何提升探测效率是目前亟需解决的问题。
发明内容
本发明的目的在于提供一种半导体器件及其制造方法，能够提高半导体器件的探测效率。
为实现上述目的，本发明提供了一种半导体器件，包括：
衬底，所述衬底具有相背的第一表面和第二表面；
掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、且各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结。
可选地，所述衬底包括基底和形成于所述基底上的本征掺杂层，所述第一离子掺杂区与所述第二离子掺杂区形成于所述本征掺杂层中。
可选地，所述基底的掺杂类型为P型，所述第一离子掺杂区的掺杂类型 为N型，所述第二离子掺杂区的掺杂类型为P型。
可选地，各层所述离子注入区层层堆叠。
可选地，在相邻的所述离子注入区中，远离所述第一离子掺杂区的所述离子注入区包裹靠近所述第一离子掺杂区的所述离子注入区。
可选地，所述第二离子掺杂区与所述第一离子掺杂区的接触区域在平行于所述第一表面的方向上的宽度小于所述第一离子掺杂区在平行于所述第一表面的方向上的宽度。
可选地，所述半导体器件还包括：
保护环，形成于所述第一离子掺杂区的***。
本发明还提供一种半导体器件的制造方法，包括：
提供一衬底，所述衬底具有相背的第一表面和第二表面；
形成掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、且各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结。
可选地，各层所述离子注入区层层堆叠。
可选地，在相邻的所述离子注入区中，远离所述第一离子掺杂区的所述离子注入区包裹靠近所述第一离子掺杂区的所述离子注入区。
可选地，所述半导体器件的制造方法还包括：
形成保护环于所述第一离子掺杂区的***。
与现有技术相比，本发明的技术方案具有以下有益效果：
1、本发明的半导体器件，由于包括掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第 一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、且各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结，进而使得能够提高半导体器件的探测效率。
2、本发明的半导体器件的制造方法，通过形成掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、且各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结，进而使得能够提高半导体器件的探测效率。
附图说明
图1a是一种半导体器件的示意图；
图1b是图1a所示的半导体器件的载流子扩散示意图；
图2a是本发明一实施例的半导体器件的示意图；
图2b是图2a所示的半导体器件的载流子扩散示意图；
图3是本发明一实施例的半导体器件的制造方法的流程图。
其中，附图1a～图3的附图标记说明如下：
11-P型基底；12-本征掺杂层；13-P型阱区；14-N型阱区；15-倍增区；21-基底；211-本征掺杂层；22-第一离子掺杂区；221-离子重掺杂区；23-第二离子掺杂区；231-第一离子注入区；232-第二离子注入区；233-第三离子注入区；234-第四离子注入区；24-保护环；25-第一电极；26-第二电极；27-倍增区。
具体实施方式
为使本发明的目的、优点和特征更加清楚，以下对本发明提出的半导体 器件及其制造方法作进一步详细说明。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明一实施例提供了一种半导体器件，所述半导体器件包括：衬底，所述衬底具有相背的第一表面和第二表面；掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结。
下面参阅图2a～图2b详细描述本实施例提供的半导体器件。
所述衬底包括基底21和形成于所述基底21上的本征掺杂层211，所述本征掺杂层211为通过外延工艺形成于所述基底21上的外延层，所述衬底具有相背的第一表面和第二表面，所述本征掺杂层211远离所述基底21的一侧为所述第一表面，所述基底21远离所述本征掺杂层211的一侧为所述第二表面。
所述本征掺杂层211具有非常低(例如，低于5×10 14原子/cm 3)的掺杂水平，作为示例，所述本征掺杂层211可以是非故意掺杂的半导体衬底，即，具有仅由杂质在其制造时的偶然污染引起的P-or N-型掺杂的衬底；作为变型，所述本征掺杂层211还可以是具有较高掺杂水平的半导体衬底。
其中，所述基底21与所述本征掺杂层211掺杂类型可以相同也可以不同，例如，所述基底21的掺杂类型为P型，所述本征掺杂层211的掺杂类型可以为N型或P型；所述基底21的掺杂类型为N型，所述本征掺杂层211的掺杂类型可以为N型或P型。优选的，所述基底21为P+型，所述本征掺杂层211为P-型，且所述基底21掺杂浓度大于所述本征掺杂层211掺杂浓度。
所述衬底的材质可以为本领域技术人员熟知的任意合适的底材，例如可以是以下所提到的材料中的至少一种：硅(Si)、锗(Ge)、锗硅(SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)或磷化铟(InP)等。
所述第一离子掺杂区22和所述第二离子掺杂区23形成于所述衬底中，即所述第一离子掺杂区22从所述衬底的第一表面延伸至所述衬底中，所述第二离子掺杂区23从所述第一离子掺杂区22远离所述第一表面的一侧朝向所述第二表面延伸。
其中，所述第一离子掺杂区22与所述第二离子掺杂区23可以形成于所述本征掺杂层211中，由于所述本征掺杂层211的离子掺杂浓度很低，远小于所述第一离子掺杂区22与所述第二离子掺杂区23的离子掺杂浓度，因此，所述本征掺杂层211可以作为中性区域。
所述第一离子掺杂区22和所述第二离子掺杂区23掺杂类型相反，所述第二离子掺杂区23、所述基底21和所述本征掺杂层211掺杂类型相同，优选的，所述第一离子掺杂区22掺杂类型为N型，所述第二离子掺杂区23、所述基底21、所述本征掺杂层211掺杂类型为P型，使得所述第一离子掺杂区22和所述第二离子掺杂区23之间形成P-N结。
所述第二离子掺杂区23包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区22与所述第二离子掺杂区23构成缓变结。在平行于所述第一表面截面上，各层所述离子注入区截面形状可以是圆形、方形、菱形等其他合适的形状。各层所述离子注入区的离子掺杂浓度可以大于、等于或小于所述基底21的离子掺杂浓度。最靠近所述第一离子掺杂区22的所述离子注入区与所述第一离子掺杂区22之间形成倍增区27。
其中，由于从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大，使得相邻的所述离子注入区之间构成垂直于所述第一表面的垂直内建电场，且所述垂直内建电场的方向与工作状态下向光电二极管中施加反向偏置电压所产生的电场方向相同，进而使得载流子向所述倍增区27的扩散速度得到提高，从而减少了扩散过程中的载流子损失，提高了雪崩发生的概率，从而提高半导体器件的探测效率。
尤其当为了提升半导体器件对近红外光(905nm～940nm)的吸收效率而 将所述衬底的厚度设计的很大(通常在7.5μm以上)时，导致所述本征掺杂层211的厚度很大，而所述倍增区27的厚度较小，从而导致载流子需要经过很长一段距离的耗尽区(从P-N结区一直到所述本征掺杂层211与基底21相接的范围内)才能产生雪崩，本实施例中通过形成垂直内建电场使得载流子的扩散速度得到提高，进而使得载流子在耗尽区能量消耗减少，更多的载流子能够扩散到所述倍增区27中，从而提高了雪崩发生的概率。
其中，从所述第一表面朝向所述第二表面的方向上各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，使得在相邻的所述离子注入区之间形成的内建电场中，不仅包含垂直于所述第一表面的垂直内建电场还包含与所述垂直内建电场非平行的弯曲内建电场。所述弯曲内建电场能够将位于所述本征掺杂层211中所述离子注入区的宽度范围外的边缘区域的载流子在弯曲内建电场的作用下扩散到所述倍增区27中(如图2b中的弯曲的箭头)，提高载流子的利用率，进而提高半导体器件的探测效率。
所述垂直内建电场在所述第一表面上的正投影与最靠近所述第一离子掺杂区22的离子注入区在所述第一表面上的正投影重叠；所述弯曲内建电场位于所述垂直内建电场***且在所述第一表面上的正投影与最远离所述第一离子掺杂区22的离子注入区在所述第一表面上的正投影重叠或相交。
各层所述离子注入区可以包括但不限于层层包裹或者层层堆叠，根据需要进行设置。当各层所述离子注入区层层包裹时，各层所述离子注入区在垂直于所述第一表面的方向上的掺杂深度从所述第一离子掺杂区22与所述第二离子掺杂区23界面朝向所述第二表面延伸，即在相邻的所述离子注入区中，远离所述第一离子掺杂区22的所述离子注入区不仅位于靠近所述第一离子掺杂区22的所述离子注入区的底面，且还位于靠近所述第一离子掺杂区22的所述离子注入区的侧面，即远离所述第一离子掺杂区22的所述离子注入区呈凹槽形包裹靠近所述第一离子掺杂区22的所述离子注入区。当各层所述离子注入区层层堆叠时，各层所述离子注入区在垂直于所述第一表面的方向上的掺杂深度从相邻所述离子注入区界面朝向所述第二表面延伸，呈台阶状分布类似半球形，即在相邻的所述离子注入区中，远离所述第一离子掺杂区22的 所述离子注入区仅位于靠近所述第一离子掺杂区22的所述离子注入区的底面，而不位于靠近所述第一离子掺杂区22的所述离子注入区的侧面。各层所述离子注入区可以共用同一轴线；在相邻的所述离子注入区中，各层所述离子注入区在垂直于所述第一表面的方向上的掺杂深度可以相同也可以不同。
所述第一离子掺杂区22在平行于所述第一表面的方向上的宽度可以位于各层所述离子注入区在平行于所述第一表面的方向上的最大宽度与最小宽度之间；或者，所述第一离子掺杂区22在平行于所述第一表面的方向上的宽度可以大于各层所述离子注入区在平行于所述第一表面的方向上的最大宽度；或者，所述第一离子掺杂区22在平行于所述第一表面的方向上的宽度可以小于各层所述离子注入区在平行于所述第一表面的方向上的最小宽度。一实施例中，所述第二离子掺杂区23与所述第一离子掺杂区22的接触区域在平行于所述第一表面的方向上的宽度小于所述第一离子掺杂区22在平行于所述第一表面的方向上的宽度，以避免所述光电二极管横向边缘击穿；其中，当各层所述离子注入区层层堆叠时，所述第二离子掺杂区23与所述第一离子掺杂区22的接触区域在平行于所述第一表面的方向上的宽度为最靠近所述第一离子掺杂区22的离子注入区在平行于所述第一表面的方向上的宽度，那么，最靠近所述第一离子掺杂区22的离子注入区在平行于所述第一表面方向上的宽度小于所述第一离子掺杂区22在平行于所述第一表面方向上的宽度；当各层所述离子注入区层层包裹时，所述第二离子掺杂区23与所述第一离子掺杂区22的接触区域在平行于所述第一表面的方向上的宽度为最远离所述第一离子掺杂区22的离子注入区在平行于所述第一表面的方向上的宽度，那么，最远离所述第一离子掺杂区22的离子注入区在平行于所述第一表面方向上的宽度小于所述第一离子掺杂区22在平行于所述第一表面方向上的宽度。
并且，最靠近所述第一离子掺杂区22的离子注入区在平行于所述第一表面方向上的宽度越大，则所述倍增区27在平行于所述第一表面方向上的宽度越大；最远离所述第一离子掺杂区22的离子注入区在平行于所述第一表面方向上的宽度越大，则位于所述本征掺杂层211中所述离子注入区边缘区域的载流子扩散到所述倍增区27中的数量越多，从而实现所述倍增区27边缘区 域的载流子也能在弯曲内建电场的作用下扩散到所述倍增区27中而提高载流子的利用率，提高半导体器件的探测效率。
在图2a～图2b所示的实施例中，所述第二离子掺杂区23包含从所述第一表面朝向所述第二表面的方向上层层堆叠的四层离子注入区，即层层堆叠的第一离子注入区231、第二离子注入区232、第三离子注入区233和第四离子注入区234，所述第一离子注入区231至所述第四离子注入区234的离子掺杂浓度逐渐增大，所述第一离子注入区231至所述第四离子注入区234在平行于所述第一表面的方向上的宽度逐渐增大。所述第二离子掺杂区23内的离子注入区层数不做具体限制，可以根据需要进行设置。
所述半导体器件还包括：离子重掺杂区221，形成于所述第一离子掺杂区22的表面，所述离子重掺杂区221与所述第一离子掺杂区22的掺杂类型相同。
所述半导体器件还包括：保护环24，形成于所述第一离子掺杂区22的***。所述保护环24环绕所述第一离子掺杂区22，所述保护环24与所述第一离子掺杂区22之间间隔有所述衬底。
优选的，所述保护环24的深度不小于所述第一离子掺杂区22的深度。
所述保护环24可以为浅沟槽隔离结构或者离子掺杂环。若所述保护环24为离子掺杂环，所述离子掺杂环的掺杂类型可以为N型或P型。
所述半导体器件还包括：环形的深沟槽隔离结构(未图示)，形成于所述保护环24***的衬底中，所述深沟槽隔离结构与所述保护环24之间间隔所述衬底，所述深沟槽隔离结构用于实现相邻的光电二极管之间的隔离，避免串扰。
所述深沟槽隔离结构的深度不小于所述第一离子掺杂区22的深度。
所述深沟槽隔离结构形成于所述衬底中的环形沟槽(未图示)中，所述深沟槽隔离结构包括覆盖于所述环形沟槽的内表面上的绝缘材料层(未图示)以及填满所述环形沟槽的导电层(未图示)。
其中，由于在本发明的实施例中，无需通过增大所述第一离子掺杂区22在平行于所述第一表面的方向上的宽度来使得所述倍增区27的宽度增大，避免所述倍增区27的宽度过大而导致在形成所述浅沟槽隔离结构和所述深沟槽 隔离结构时刻蚀沟槽所产生的缺陷、损伤等直接与所述倍增区27接触，进而避免导致引起暗计数率增加而降低器件性能。
所述半导体器件还包括：第一电极25和第二电极26，所述第一电极25形成于所述离子重掺杂区221上，所述第二电极26形成于所述衬底的第一表面或第二表面，在图2a～图2b所示的实施例中，所述第二电极26形成于所述衬底的第二表面；所述离子重掺杂区221用于将所述第一离子掺杂区22接出，使得在通过所述第一电极25向所述第一离子掺杂区22施加电压时，减小接触电阻；通过所述第一电极25和所述第二电极26向所述光电二极管中施加反向偏置电压。
综上所述，本发明提供的半导体器件，包括：衬底，所述衬底具有相背的第一表面和第二表面；掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结。本发明的半导体器件能够提高半导体器件的探测效率。
本发明一实施例提供一种半导体器件的制造方法，参阅图3，图3是本发明一实施例的半导体器件的制造方法的流程图，所述半导体器件的制造方法包括：
步骤S1、提供一衬底，所述衬底具有相背的第一表面和第二表面；
步骤S2、形成掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离 子掺杂区与所述第二离子掺杂区构成缓变结。
下面参阅图2a～图2b更为详细的介绍本实施例提供的半导体器件的制造方法。
按照步骤S1，提供一衬底，所述衬底具有相背的第一表面和第二表面。
所述衬底包括基底21和形成于所述基底21上的本征掺杂层211，所述本征掺杂层211为通过外延工艺形成于所述基底21上的外延层，所述本征掺杂层211远离所述基底21的一侧为所述第一表面，所述基底21远离所述本征掺杂层211的一侧为所述第二表面。
其中，所述基底21与所述本征掺杂层211的掺杂类型可以相同也可以不同，例如，所述基底21的掺杂类型为P型，所述本征掺杂层211的掺杂类型可以为N型或P型；所述基底21的掺杂类型为N型，所述本征掺杂层211的掺杂类型可以为N型或P型。优选的，所述基底21为P+型，所述本征掺杂层211为P-型，且所述基底21的掺杂浓度大于所述本征掺杂层211的掺杂浓度。
所述衬底的材质可以为本领域技术人员熟知的任意合适的底材，例如可以是以下所提到的材料中的至少一种：硅(Si)、锗(Ge)、锗硅(SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)或磷化铟(InP)等。
按照步骤S2，形成掺杂类型相反的第一离子掺杂区22和第二离子掺杂区23，所述第一离子掺杂区22和所述第二离子掺杂区23形成于所述衬底中，即所述第一离子掺杂区22从所述衬底的第一表面延伸至所述衬底中，所述第二离子掺杂区23从所述第一离子掺杂区22远离所述第一表面的一侧朝向所述第二表面延伸。
其中，所述第一离子掺杂区22与所述第二离子掺杂区23可以形成于所述本征掺杂层211中，由于所述本征掺杂层211的离子掺杂浓度很低，远小于所述第一离子掺杂区22与所述第二离子掺杂区23的离子掺杂浓度，因此，所述本征掺杂层211可以作为中性区域。
所述第一离子掺杂区22和所述第二离子掺杂区23掺杂类型相反，所述第二离子掺杂区23、所述基底21和所述本征掺杂层211掺杂类型相同，优选 的，所述第一离子掺杂区22掺杂类型为N型，所述第二离子掺杂区23、所述基底21、所述本征掺杂层211掺杂类型为P型，使得所述第一离子掺杂区22和所述第二离子掺杂区23之间形成P-N结。
所述第二离子掺杂区23包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区22与所述第二离子掺杂区23构成缓变结。最靠近所述第一离子掺杂区22的所述离子注入区与所述第一离子掺杂区22之间形成倍增区27。
其中，由于从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大，使得相邻的所述离子注入区之间构成垂直于所述第一表面的垂直内建电场，且所述垂直内建电场的方向与工作状态下向光电二极管中施加反向偏置电压所产生的电场方向相同，进而使得载流子向所述倍增区27的扩散速度得到提高，从而减少了扩散过程中的载流子损失，提高了雪崩发生的概率，从而提高半导体器件的探测效率。
其中，从所述第一表面朝向所述第二表面的方向上各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，使得在相邻的所述离子注入区之间形成的内建电场中，不仅包含垂直于所述第一表面的垂直内建电场还包含与所述垂直内建电场非平行的弯曲内建电场。所述弯曲内建电场能够将位于所述本征掺杂层211中的所述离子注入区的宽度范围外的边缘区域的载流子在弯曲内建电场的作用下扩散到所述倍增区27中(如图2b中的弯曲的箭头)，提高载流子的利用率，进而提高半导体器件的探测效率。
各层所述离子注入区可以包括但不限于层层包裹或者层层堆叠，根据需要进行设置。当各层所述离子注入区层层包裹时，各层所述离子注入区在垂直于所述第一表面的方向上的掺杂深度从所述第一离子掺杂区22与所述第二离子掺杂区23界面朝向所述第二表面延伸，即在相邻的所述离子注入区中，远离所述第一离子掺杂区22的所述离子注入区不仅位于靠近所述第一离子掺杂区22的所述离子注入区的底面，且还位于靠近所述第一离子掺杂区22的 所述离子注入区的侧面，即远离所述第一离子掺杂区22的所述离子注入区呈凹槽形包裹靠近所述第一离子掺杂区22的所述离子注入区。当各层所述离子注入区层层堆叠时，各层所述离子注入区在垂直于所述第一表面的方向上的掺杂深度从相邻所述离子注入区界面朝向所述第二表面延伸，呈台阶状分布类似半球形，即在相邻的所述离子注入区中，远离所述第一离子掺杂区22的所述离子注入区仅位于靠近所述第一离子掺杂区22的所述离子注入区的底面，而不位于靠近所述第一离子掺杂区22的所述离子注入区的侧面。各层所述离子注入区可以共用同一轴线；在相邻的所述离子注入区中，各层所述离子注入区在垂直于所述第一表面的方向上的掺杂深度可以相同也可以不同。
所述第一离子掺杂区22在平行于所述第一表面的方向上的宽度可以位于各层所述离子注入区在平行于所述第一表面的方向上的最大宽度与最小宽度之间；或者，所述第一离子掺杂区22在平行于所述第一表面的方向上的宽度可以大于各层所述离子注入区在平行于所述第一表面的方向上的最大宽度；或者，所述第一离子掺杂区22在平行于所述第一表面的方向上的宽度可以小于各层所述离子注入区在平行于所述第一表面的方向上的最小宽度。一实施例中，所述第二离子掺杂区23与所述第一离子掺杂区22的接触区域在平行于所述第一表面的方向上的宽度小于所述第一离子掺杂区22在平行于所述第一表面的方向上的宽度，以避免所述光电二极管横向边缘击穿；其中，当各层所述离子注入区层层堆叠时，所述第二离子掺杂区23与所述第一离子掺杂区22的接触区域在平行于所述第一表面的方向上的宽度为最靠近所述第一离子掺杂区22的离子注入区在平行于所述第一表面的方向上的宽度，那么，最靠近所述第一离子掺杂区22的离子注入区在平行于所述第一表面方向上的宽度小于所述第一离子掺杂区22在平行于所述第一表面方向上的宽度；当各层所述离子注入区层层包裹时，所述第二离子掺杂区23与所述第一离子掺杂区22的接触区域在平行于所述第一表面的方向上的宽度为最远离所述第一离子掺杂区22的离子注入区在平行于所述第一表面的方向上的宽度，那么，最远离所述第一离子掺杂区22的离子注入区在平行于所述第一表面方向上的宽度小于所述第一离子掺杂区22在平行于所述第一表面方向上的宽度。
并且，最靠近所述第一离子掺杂区22的离子注入区在平行于所述第一表面方向上的宽度越大，则所述倍增区27在平行于所述第一表面方向上的宽度越大；最远离所述第一离子掺杂区22的离子注入区在平行于所述第一表面方向上的宽度越大，则位于所述本征掺杂层211中所述离子注入区边缘区域的载流子扩散到所述倍增区27中的数量越多，从而实现所述倍增区27边缘区域的载流子也能在弯曲内建电场的作用下扩散到所述倍增区27中而提高载流子的利用率，提高半导体器件的探测效率。
在图2a～图2b所示的实施例中，所述第二离子掺杂区23包含从所述第一表面朝向所述第二表面的方向上层层堆叠的四层离子注入区，即层层堆叠的第一离子注入区231、第二离子注入区232、第三离子注入区233和第四离子注入区234，所述第一离子注入区231至所述第四离子注入区234的离子掺杂浓度逐渐增大，所述第一离子注入区231至所述第四离子注入区234在平行于所述第一表面的方向上的宽度逐渐增大。所述第二离子掺杂区23内的离子注入区层数不做具体限制，可以根据需要进行设置。
其中，可以采用离子注入工艺，先形成所述第一离子掺杂区22后形成所述第二离子掺杂区23，或者，先形成所述第二离子掺杂区23后形成所述第一离子掺杂区22。
以各层所述离子注入区层层堆叠为例，形成所述第二离子掺杂区23的步骤可以包括：首先，在所述衬底的第一表面形成图案化的掩膜层(未图示)，所述图案化掩膜层具有用于向所述衬底进行离子注入的开口；然后，当沿着所述第一表面朝向所述第二表面的方向依次形成各层所述离子注入区时，可以通过更换光罩多次调整所述开口的宽度变大，且在每次调整所述开口的宽度后，以具有每次调整后宽度的开口的所述图案化掩膜层为掩膜，向所述衬底进行离子注入，离子注入的能量和剂量随着每次调整所述开口的宽度增大而逐渐增大，使得每次所述离子注入后形成具有预定深度和宽度的一层离子注入区；当沿着所述第二表面朝向所述第一表面的方向依次形成各层所述离子注入区时，可以通过更换光罩多次调整所述开口的宽度变小，且在每次调整所述开口的宽度后，以具有每次调整后宽度的开口的所述图案化掩膜层为 掩膜，向所述衬底进行离子注入，离子注入的能量和剂量随着每次调整所述开口的宽度减小而逐渐减小，使得每次所述离子注入后形成具有预定深度和宽度的一层离子注入区。
并且，每次离子注入后，需要对所述衬底进行退火处理，以去除离子碰撞引起的半导体晶格的断裂或损伤。
所述半导体器件的制造方法还包括：采用离子注入工艺形成离子重掺杂区221于所述第一离子掺杂区22的表面，所述离子重掺杂区221与所述第一离子掺杂区22的掺杂类型相同。
所述半导体器件的制造方法还包括：形成保护环24于所述第一离子掺杂区22的***，所述保护环24环绕所述第一离子掺杂区22，所述保护环24与所述第一离子掺杂区22之间间隔有所述衬底。
优选的，所述保护环24的深度不小于所述第一离子掺杂区22的深度。
所述保护环24可以为浅沟槽隔离结构或者离子掺杂环。若所述保护环24为离子掺杂环，所述离子掺杂环的掺杂类型可以为N型或P型。
所述半导体器件的制造方法还包括：形成环形的深沟槽隔离结构(未图示)于所述保护环24***的衬底中，所述深沟槽隔离结构与所述保护环24之间间隔所述衬底，所述深沟槽隔离结构用于实现相邻的光电二极管之间的隔离，避免串扰。
所述深沟槽隔离结构的深度不小于所述第一离子掺杂区22的深度。
所述深沟槽隔离结构形成于所述衬底中的环形沟槽(未图示)中，所述深沟槽隔离结构包括覆盖于所述环形沟槽的内表面上的绝缘材料层(未图示)以及填满所述环形沟槽的导电层(未图示)。
其中，由于在本发明的实施例中，无需通过增大所述第一离子掺杂区22在平行于所述第一表面的方向上的宽度来使得所述倍增区27的宽度增大，避免所述倍增区27的宽度过大而导致在形成所述浅沟槽隔离结构和所述深沟槽隔离结构时刻蚀沟槽所产生的缺陷、损伤等直接与所述倍增区27接触，进而避免导致引起暗计数率增加而降低器件性能。
所述半导体器件的制造方法还包括：形成第一电极25于所述离子重掺杂 区221上，且形成第二电极26于所述衬底的第一表面或第二表面，在图2a～图2b所示的实施例中，所述第二电极26形成于所述衬底的第二表面；所述离子重掺杂区221用于将所述第一离子掺杂区22接出，使得在通过所述第一电极25向所述第一离子掺杂区22施加电压时，减小接触电阻；通过所述第一电极25和所述第二电极26向所述光电二极管中施加反向偏置电压。
综上所述，本发明提供的半导体器件的制造方法，包括：提供一衬底，所述衬底具有相背的第一表面和第二表面；形成掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结。本发明的半导体器件的制造方法能够提高半导体器件的探测效率。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (11)

  1. 一种半导体器件，其特征在于，包括：
    衬底，所述衬底具有相背的第一表面和第二表面；
    掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、且各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结。
  2. 如权利要求1所述的半导体器件，其特征在于，所述衬底包括基底和形成于所述基底上的本征掺杂层，所述第一离子掺杂区与所述第二离子掺杂区形成于所述本征掺杂层中。
  3. 如权利要求2所述的半导体器件，其特征在于，所述基底的掺杂类型为P型，所述第一离子掺杂区的掺杂类型为N型，所述第二离子掺杂区的掺杂类型为P型。
  4. 如权利要求1所述的半导体器件，其特征在于，各层所述离子注入区层层堆叠。
  5. 如权利要求1所述的半导体器件，其特征在于，在相邻的所述离子注入区中，远离所述第一离子掺杂区的所述离子注入区包裹靠近所述第一离子掺杂区的所述离子注入区。
  6. 如权利要求1所述的半导体器件，其特征在于，所述第二离子掺杂区与所述第一离子掺杂区的接触区域在平行于所述第一表面的方向上的宽度小于所述第一离子掺杂区在平行于所述第一表面的方向上的宽度。
  7. 如权利要求1所述的半导体器件，其特征在于，所述半导体器件还包括：
    保护环，形成于所述第一离子掺杂区的***。
  8. 一种半导体器件的制造方法，其特征在于，包括：
    提供一衬底，所述衬底具有相背的第一表面和第二表面；
    形成掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、且各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结。
  9. 如权利要求8所述的半导体器件的制造方法，其特征在于，各层所述离子注入区层层堆叠。
  10. 如权利要求8所述的半导体器件的制造方法，其特征在于，在相邻的所述离子注入区中，远离所述第一离子掺杂区的所述离子注入区包裹靠近所述第一离子掺杂区的所述离子注入区。
  11. 如权利要求8所述的半导体器件的制造方法，所述半导体器件的制造方法还包括：
    形成保护环于所述第一离子掺杂区的***。
PCT/CN2022/137471 2022-10-31 2022-12-08 半导体器件及其制造方法 WO2024092961A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211348912.9A CN115621352A (zh) 2022-10-31 2022-10-31 半导体器件及其制造方法
CN202211348912.9 2022-10-31

Publications (1)

Publication Number Publication Date
WO2024092961A1 true WO2024092961A1 (zh) 2024-05-10

Family

ID=84876116

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/137471 WO2024092961A1 (zh) 2022-10-31 2022-12-08 半导体器件及其制造方法

Country Status (2)

Country Link
CN (1) CN115621352A (zh)
WO (1) WO2024092961A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100078775A1 (en) * 2008-09-30 2010-04-01 Infineon Technologies Austria Ag Semiconductor device with a charge carrier compensation structure and method for the production of a semiconductor device
CN103178120A (zh) * 2011-12-26 2013-06-26 江苏宏微科技有限公司 外延型快速恢复二极管及其制备方法
CN109449083A (zh) * 2018-10-24 2019-03-08 武汉新芯集成电路制造有限公司 缓变结、高压器件和半导体器件及其制造方法
CN112825339A (zh) * 2019-11-20 2021-05-21 深圳市灵明光子科技有限公司 光电探测单元、光电探测结构和光电探测器及其制备方法
CN114242826A (zh) * 2021-12-02 2022-03-25 武汉新芯集成电路制造有限公司 单光子雪崩二极管及其形成方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7709618A (nl) * 1977-09-01 1979-03-05 Philips Nv Stralingsgevoelige halfgeleiderinrichting en werkwijze ter vervaardiging daarvan.
CA1301895C (en) * 1989-01-12 1992-05-26 Robert J. Mcintyre Silicon avalanche photodiode with low multiplication noise
KR970054544A (ko) * 1995-12-29 1997-07-31 김주용 에벌런치 포토 다이오드 및 그 제조방법
GB201014843D0 (en) * 2010-09-08 2010-10-20 Univ Edinburgh Single photon avalanche diode for CMOS circuits
CN103107231A (zh) * 2013-02-05 2013-05-15 武汉电信器件有限公司 一种基于非N型InP衬底的雪崩光电二极管及其制备方法
US10103285B1 (en) * 2017-04-13 2018-10-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of manufacturing the same
CN109638092A (zh) * 2018-11-15 2019-04-16 天津大学 基于标准cmos工艺的高探测效率低暗计数的spad
EP3748698A1 (en) * 2019-06-03 2020-12-09 Ams Ag Semiconductor body, avalanche photodiode and method for fabricating a semiconductor body
CN113299787B (zh) * 2021-05-21 2022-04-29 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
CN114141886A (zh) * 2021-11-22 2022-03-04 江苏尚飞光电科技股份有限公司 一种雪崩光电二极管阵列探测器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100078775A1 (en) * 2008-09-30 2010-04-01 Infineon Technologies Austria Ag Semiconductor device with a charge carrier compensation structure and method for the production of a semiconductor device
CN103178120A (zh) * 2011-12-26 2013-06-26 江苏宏微科技有限公司 外延型快速恢复二极管及其制备方法
CN109449083A (zh) * 2018-10-24 2019-03-08 武汉新芯集成电路制造有限公司 缓变结、高压器件和半导体器件及其制造方法
CN112825339A (zh) * 2019-11-20 2021-05-21 深圳市灵明光子科技有限公司 光电探测单元、光电探测结构和光电探测器及其制备方法
CN114242826A (zh) * 2021-12-02 2022-03-25 武汉新芯集成电路制造有限公司 单光子雪崩二极管及其形成方法

Also Published As

Publication number Publication date
CN115621352A (zh) 2023-01-17

Similar Documents

Publication Publication Date Title
US7348608B2 (en) Planar avalanche photodiode
US6359293B1 (en) Integrated optoelectronic device with an avalanche photodetector and method of making the same using commercial CMOS processes
CN113314638B (zh) 近红外单光子雪崩二极管探测器及制作方法
US6690079B2 (en) Light-receiving device
JP2010135360A (ja) アバランシェフォトダイオード
JP2006237610A (ja) アバランシェフォトダイオードの製造方法
JP2020107901A (ja) 平面のアバランシェ・フォトダイオード
JP2020009790A (ja) アバランシェフォトダイオード
JP2009252769A (ja) 半導体受光素子
CN117239000B (zh) 一种雪崩光电二极管及其制作方法、单光子探测器
US6495380B2 (en) Epitaxially grown avalanche photodiode
JPH04256376A (ja) アバランシェホトダイオード及びその製造方法
WO2024092961A1 (zh) 半导体器件及其制造方法
US10658538B2 (en) Optical detection device
JP2012174783A (ja) フォトダイオードおよびフォトダイオードアレイ
JP2023098820A (ja) 半導体基板内にゲルマニウム領域を配置した半導体装置
JP2007535810A (ja) プレーナ型雪崩効果光ダイオード
US10002979B1 (en) Unipolar doping in photodiode and phototransistor
JP5303793B2 (ja) フォトダイオード
JP2763352B2 (ja) 半導体受光素子
US20240162365A1 (en) Avalanche photodetectors with a combined lateral and vertical arrangement
KR102078316B1 (ko) 2차원 도핑 기술을 이용한 수광소자 및 그 제조방법
CN117936619A (zh) 一种光载无线电光电二极管结构
KR20230112262A (ko) 고농도 도핑된 에피층을 이용한 광대역 포토다이오드 및 그 제조방법
JPH0258277A (ja) 半導体受光素子の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22964256

Country of ref document: EP

Kind code of ref document: A1