WO2024082495A1 - 一种半导体结构及其制作方法 - Google Patents

一种半导体结构及其制作方法 Download PDF

Info

Publication number
WO2024082495A1
WO2024082495A1 PCT/CN2023/075977 CN2023075977W WO2024082495A1 WO 2024082495 A1 WO2024082495 A1 WO 2024082495A1 CN 2023075977 W CN2023075977 W CN 2023075977W WO 2024082495 A1 WO2024082495 A1 WO 2024082495A1
Authority
WO
WIPO (PCT)
Prior art keywords
contact pad
connecting portion
semiconductor structure
chip
conductive layer
Prior art date
Application number
PCT/CN2023/075977
Other languages
English (en)
French (fr)
Inventor
吕开敏
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2024082495A1 publication Critical patent/WO2024082495A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits

Definitions

  • the present disclosure relates to the semiconductor field, and in particular to a semiconductor structure and a method for manufacturing the same.
  • a chip is an integrated circuit that is made up of a large number of transistors. Different chips have different integration scales, ranging from hundreds of millions to tens or hundreds of transistors. Transistors have two states, on and off, represented by 1 and 0. Multiple transistors generate multiple 1 and 0 signals, which are set to specific functions (i.e. instructions and data) to represent or process letters, numbers, colors, graphics, etc. After the chip is powered on, it first generates a startup instruction to start the chip, and then continuously accepts new instructions and data to complete its functions.
  • the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can at least improve the problem of chip warping.
  • an embodiment of the present disclosure provides a semiconductor structure, including a chip, the chip having a first surface, and the first surface including an electrical connection area and a non-electrical connection area, wherein at least part of the non-electrical connection area is located at the edge of the first surface; a plurality of first contact pads, the first contact pads are located in the non-electrical connection area; a plurality of second contact pads, the second contact pads are located in the electrical connection area; and a connecting portion, the connecting portion is located between at least part of the first contact pads, and the top surface of the connecting portion is lower than the top surface of the first contact pad.
  • the first contact pads are arranged in an array, and the first contact pads and the connection parts form a grid structure, and the grid structure includes a square grid, a diamond grid, a trapezoidal grid or a cross grid.
  • the connecting portion is further located between two of the first contact pads at diagonal positions in the grid structure.
  • a plurality of the first contact pads are arranged in an array, and the connecting portion is located between two of the first contact pads at diagonal positions.
  • a thickness of the connecting portion is smaller than a thickness of the first contact pad.
  • the thickness of the connecting portion is 1/5 to 1/3 of the thickness of the first contact pad.
  • the first contact pad and the adjacent connecting portion are an integral structure.
  • the first contact pad includes: a first conductive layer and a second conductive layer stacked in sequence; the first conductive layer and the adjacent connecting portion are an integral structure.
  • all of the non-electrical connection areas are provided with the connection portions; or, the non-electrical connection areas include corner portions, and the connection portions are only located at the corner portions.
  • it further includes: a supporting portion, the supporting portion is located on the surface of the first contact pad; and an electrical connecting portion, the electrical connecting portion is located on the surface of the second contact pad.
  • a plurality of the chips are stacked, the supporting portion is used to support adjacent chips, and the electrical connecting portion is used to electrically connect adjacent chips.
  • the chip further has a second surface, the second surface is arranged opposite to the first surface, and the first contact pad is also located on the second surface;
  • the semiconductor structure further includes a welding structure, and the welding structure is located on the top surface of the first contact pad on the second surface.
  • the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, including: providing a chip, the chip having a first surface, and the first surface including a non-electrical connection area and an electrical connection area, wherein at least a portion of the non-electrical connection area is located at the edge of the first surface; forming a first contact pad, a second contact pad and a connecting portion, the first contact pad is located in the non-electrical connection area, the second contact pad is located in the electrical connection area, the connecting portion is located between at least a portion of the first contact pads, and the top surface of the connecting portion is lower than the top surface of the first contact pad.
  • the method for forming the connecting portion includes: forming a seed layer, wherein the seed layer is located on the surface of the chip; forming a first mask layer, wherein the first mask layer is located on the surface of the seed layer, the first mask layer having a target pattern, and the target pattern exposes a portion of the surface of the seed layer; and forming a connecting portion, wherein the connecting portion is located within the target pattern.
  • the first contact pad includes: a first conductive layer and a second conductive layer stacked in sequence
  • the method for forming the first contact pad includes: after forming the connecting portion, forming a second mask layer on the surface of the connecting portion, the second mask layer being spaced apart from the first mask layer; forming a second conductive layer, the second conductive layer being located between the first mask layer and the second conductive layer;
  • the connecting portion between the layer and the second mask layer, which is in contact with the second conductive layer, serves as the first conductive layer, and the first conductive layer and the second conductive layer serve as the first contact pad.
  • the method further includes: removing the first mask layer and the second mask layer; and etching the seed layer using the first contact pad as a mask to form the seed layer with a gap.
  • the method of forming the connection portion and the first contact pad includes: forming an initial conductive layer, the initial conductive layer being located on a surface of the chip; and etching the initial conductive layer to form the connection portion and the first contact pad.
  • FIG1 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG2 is a top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG3 is a top view of another semiconductor structure provided by an embodiment of the present disclosure.
  • FIG4 is a schematic diagram of a partial structure provided by an embodiment of the present disclosure.
  • FIG5 is a cross-sectional view of another semiconductor structure provided by an embodiment of the present disclosure.
  • FIG6 is a cross-sectional view of another semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 7 to 13 are schematic structural diagrams corresponding to the steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 14 to 16 are schematic structural diagrams corresponding to the steps of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure.
  • the present disclosure provides a semiconductor structure, which is implemented by arranging at least part of the non-electrical connection area of the chip to be located at the edge of the first surface of the chip, and arranging multiple first contact pads in the non-electrical connection area, and arranging a connecting portion between at least part of the first contact pads, and connecting different first contact pads through the connecting portion, thereby improving the stress resistance of the chip edge, reducing the stress effect of the passivation layer material on the chip, and thus improving the warping of the chip.
  • Figure 1 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a top view of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3 is a top view of another semiconductor structure provided by an embodiment of the present disclosure
  • Figure 4 is a partial schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 5 is a cross-sectional view along the dotted line direction of Figure 4
  • Figure 6 is another cross-sectional view along the dotted line direction of Figure 4.
  • the semiconductor structure includes: a chip 100, the chip 100 has a first surface 101, and the first surface 101 includes an electrical connection area 102 and a non-electrical connection area 103, wherein at least part of the non-electrical connection area 103 is located at the edge of the first surface 101; a plurality of first contact pads 110, the first contact pads 110 are located in the non-electrical connection area 103; a plurality of second contact pads 120, the second contact pads 120 are located in the electrical connection area 102; a connecting portion 130, the connecting portion 130 is located between at least part of the first contact pads 110, and the top surface of the connecting portion 130 is lower than the top surface of the first contact pad 110.
  • connection portion 130 in the non-electrical connection area 103 of the chip By setting a connection portion 130 in the non-electrical connection area 103 of the chip, the electrical performance of the chip 100 will not be affected.
  • the warped portion of the chip 100 By setting at least part of the non-electrical connection area 103 at the edge of the chip 100 and further providing a connection portion 130 in the non-electrical connection area 103, the warped portion of the chip 100 can be improved. By increasing the stress resistance of the first surface of the chip 100, the warping degree of the chip 100 can be reduced.
  • warpage mentioned here refers to the degree of bending of the chip after the chip is deformed compared to a chip with a flat surface.
  • the chip 100 may be a functional structure, that is, the chip 100 may have various circuit structures, such as transistors, wiring layers, word lines, bit lines, capacitors, and the like.
  • the first surface of the chip 100 may refer to the back surface of the chip, that is, the first contact pad 110 , the second contact pad 120 and the connecting portion 130 may be disposed on the back surface of the chip.
  • the electrical connection area 102 refers to an area with a functional structure, for example: an area where data information needs to be input or read.
  • the second contact pads 120 of the electrical connection area 102 are spaced apart from each other, and each second contact pad 120 can only be contacted and connected to a structure in the electrical connection area 102 in the chip 100.
  • a second contact pad 120 is only contacted and connected to a bit line in the electrical connection area 102, and data information is only provided to the bit line through the second contact pad 120.
  • Another second contact pad 120 is only contacted and connected to a word line in the electrical connection area 102, and data information is only provided to the word line through the second contact pad 120. Since the word line and the bit line in the electrical connection area 102 cannot be directly contacted and connected, the different second contact pads 120 electrically connected to the word line and the bit line, respectively, are also spaced apart from each other.
  • the non-electrical connection area 103 refers to an area without a functional structure. That is, the structure located in the non-electrical connection area 103 does not affect the specific function of the chip 100.
  • the non-electrical connection area 103 can usually be set at The edge of the chip 100 can also protect the electrical connection area 102 , because the non-electrical connection area 103 does not affect the function of the chip 100 . Therefore, even if the non-electrical connection area 103 is damaged to a certain extent, it will not have a significant impact on the chip 100 .
  • the first contact pad 110 may be a pad structure, and the first contact pad 110 located in the non-electrical connection region 103 may be located only on the surface of the chip 100 , that is, the first contact pad 110 may not contact the structure in the chip 100 .
  • the chip 100 further has a second surface 104, the second surface 104 is arranged opposite to the first surface 101, and the first contact pad 110 is also located on the second surface 104; the semiconductor structure further includes a welding structure 140, and the welding structure 140 is located on the top surface of the first contact pad 110 of the second surface 104.
  • the chips 100 are also welded and bonded, and the welding structure 140 of the second surface 104 of one chip 100 can be welded with the first contact pad 110 of the first surface 101 of another chip 100, so as to achieve the connection between the chips 100, and the first contact pad 110 is located in the non-electrical connection area 103 of the chip, and the welding bonding through the first contact pad 110 of the non-electrical connection area 103 can avoid affecting the function of the electrical connection area 102 in the chip 100.
  • the second contact pad 120 may include a pad structure and a conductive via, wherein the conductive via passes through the chip 100, and the pad structure is connected to the structure within the chip through the conductive via, so that signal data can be input into the circuit structure within the chip 100 or data information within the chip 100 can be read out through the pad structure of the second contact pad 120.
  • the second contact pad 120 may further include a pad structure located on the second surface 104 , that is, the second contact pad 120 includes a pad structure located on the first surface 101 , a conductive via penetrating the chip 100 , and a pad structure located on the second surface 104 .
  • the connecting portion 130 is used to connect the two first contact pads 110, thereby increasing the stress resistance of the first contact pad 110, and by providing the connecting portion 130, the contact area between the subsequent packaging material or the passivation layer material and the chip 100 substrate material can be reduced, thereby reducing the surface area where stress mismatch occurs between different materials, thereby reducing the warping of the chip 100, and by providing at least a portion of the connecting portion 130 in a non-electrical connection area located at the edge of the chip 100, the weight of the edge of the chip 100 can also be increased, thereby further balancing the warping of the chip edge.
  • connection portion 130 By setting the top surface of the connection portion 130 lower than the top surface of the first contact pad 110, it is possible to prevent the solder from overflowing onto the top surface of the connection portion 130 when the chips 100 are connected to each other, thereby preventing the soldering effect of the chips 100 from being affected.
  • solder as tin material as an example
  • the top surface of the connection portion 130 lower than the top surface of the first contact pad 110, the phenomenon of tin creeping can be avoided, and the reliability of the soldering of the chips 100 can be improved.
  • the plurality of first contact pads 110 are arranged in an array, and the plurality of first contact pads 110 and the plurality of connecting portions 130 form a grid structure, and the grid structure includes: a square grid, a diamond grid, a trapezoidal grid or a cross grid.
  • the grid structure here refers to the shape of the positive projection on the surface of the chip 100 after the plurality of first contact pads 110 and the plurality of connecting portions 130 are connected.
  • a grid is a description of the shape of the orthographic projection. For example, referring to FIG. 2 , the grid structure shown in FIG.
  • the grid structure can also be called a trapezoidal grid.
  • the plurality of first contact pads 110 can be connected into a whole, thereby increasing the stress resistance of the first contact pads 110, and reducing the warpage of the chip 100, thereby improving the yield of subsequent process steps.
  • connection portion 130 is also located between two first contact pads 110 at diagonal positions in the grid structure.
  • the first contact pads 110 in the non-electrical connection area 103 in the figure have four rows and nine columns, and the first contact pads 110 are defined as the first row, the second row, the third row, and the fourth row from top to bottom, and the first column to the ninth column from left to right.
  • connection portion 130 is also located between two first contact pads 110 at diagonal positions in the grid structure, which means that the connection portion 130 is located between the first contact pad 110 in the first row and the first column and the first contact pad 110 in the second row and the second column, or the connection portion 130 is located between the first contact pad 110 in the first row and the first column and the first contact pad 110 in the second row and the second column. Between the first contact pads 110 in the second row and the third column, and so on. That is to say, the extension direction of part of the connecting portion 130 is at a certain angle to the arrangement direction of the first contact pads 110, and the extension direction of part of the connecting portion 130 is the same as the arrangement direction of the first contact pads 110.
  • the connecting portion 130 By arranging the connecting portion 130 to be located between two first contact pads 110 at diagonal positions in the grid structure, the contact area between the connecting portion 130 and the surface of the chip 100 can be increased. It can be understood that the larger the contact area between the connecting portion 130 and the surface of the chip 100, the stronger the ability to improve the warping of the chip 100.
  • top to bottom and from left to right refer to the up, down, left and right in the structural diagram shown in FIG2 , and do not correspond to the actual structure.
  • the plurality of first contact pads 110 are arranged in an array, and the connection portion 130 is located between two diagonally located first contact pads 110. Referring to FIG. 3 , the extension direction of the connection portion 130 forms a certain angle with the arrangement direction of the first contact pads 110.
  • all non-electrical connection areas 103 are provided with connection parts 130; or, the non-electrical connection areas 103 include corners, and the connection parts 130 are only located at the corners.
  • the semiconductor structure shown in FIG2 is that all non-electrical connection areas 103 are provided with connection parts 130, that is, the first contact pads 110 located in the non-electrical connection areas 103 are connected to the connection parts 130; referring to FIG3 , the semiconductor structure shown in FIG3 is that the non-electrical connection areas 103 include corners, and the connection parts 130 are only located at the corners.
  • the corners of the chip 100 are usually the parts with the largest warpage of the chip 100. By only providing the connection parts 130 at the corners of the chip 100, the warpage of the chip 100 can be improved to a certain extent while reducing the cost of the entire semiconductor structure.
  • the thickness of the connection portion 130 is less than the thickness of the first contact pad 110 .
  • the thickness of the connection portion 130 is less than the thickness of the first contact pad 110 .
  • the thickness of the connecting portion 130 is 1/5 to 1/3 of the thickness of the first contact pad 110. Yes, the thicker the connection part 130 is, the stronger its ability to improve the warpage of the chip 100 is. However, the thicker the connection part 130 is, the more likely it is that the chips 100 will have abnormalities when connected to each other. Therefore, by setting the thickness of the connection part to 1/5 to 1/3 of the thickness of the first contact pad 110, the connection part 130 can improve the warpage of the chip 100 to a certain extent while having a certain reliability.
  • the thickness of the connecting portion 130 can be 2 to 4 ⁇ m, for example, 3 ⁇ m or 4 ⁇ m, etc. It can be understood that when the thickness of the connecting portion 130 is less than 2 ⁇ m, the ability of the connecting portion 130 to improve the warpage of the chip 100 is not strong. When the thickness of the connecting portion 130 is greater than 4 ⁇ m, the thickness of the connecting portion 130 is too thick, which may affect the subsequent welding of the chip 100. Therefore, by setting the thickness of the connecting portion 130 to 2 to 4 ⁇ m, the connecting portion 130 can have a certain improvement ability while avoiding affecting the subsequent welding of the chip 100.
  • the thickness refers to the size of the connecting portion 130 in a direction perpendicular to the surface of the chip 100 .
  • the first contact pad 110 and the adjacent connecting portion 130 are an integral structure.
  • the reliability of the connection between the first contact pad 110 and the adjacent connecting portion 130 can be improved, thereby avoiding connection abnormalities between the connecting portion 130 and the first contact pad 110.
  • the first contact pad 110 and the adjacent connection portion 130 are integrally structured. That is, when forming the first contact pad 110 and the connection portion 130 , the first contact pad 110 and the connection portion 130 are formed in the same process step, thereby reducing the abnormal connection between the first contact pad 110 and the connection portion 130 .
  • the first contact pad 110 and the adjacent connecting portion 130 may also be two different structures. That is, when forming the first contact pad 110 and the connecting portion 130, the first contact pad 110 and the connecting portion 130 are formed separately. By setting the first contact pad 110 and the adjacent connecting portion 130 as two different structures, the setting of the connecting portion 130 can be flexibly adjusted according to actual needs.
  • the material of the connecting portion 130 is the same as that of the first contact pad 110.
  • the material of the connecting portion 130 is the same as that of the first contact pad 110.
  • the material of the connecting part 130 may be a metal material such as copper, silver or gold
  • the material of the first contact pad 110 may also be a metal material such as copper, silver or gold
  • the material of the second contact pad 120 may also be a metal material such as copper, silver or gold.
  • the materials of the connecting part 130, the first contact pad 110 and the second contact pad 120 can be selected according to actual needs.
  • the width of the connection portion 130 is 0.1 to 2 ⁇ m. It is understood that the wider the width of the connection portion 130, the stronger the ability to improve the warpage of the chip 100. The wider the width of the connection portion 130, the material of the connection portion 130 will also expand and contract during the subsequent process. Therefore, when the width of the connection portion 130 is wider, the difference between different connection portions will be reduced. The reserved gap between 130 causes the connection parts 130 to be squeezed against each other. Therefore, when the width of the connection part 130 is less than 0.1 ⁇ m, the ability of the connection part 130 to improve the warpage of the chip 100 is weak. When the width of the connection part 130 is greater than 2 ⁇ m, the reliability of the connection part 130 may be affected.
  • the first contact pad 110 includes: a first conductive layer 111 and a second conductive layer 112 stacked in sequence; the first conductive layer 111 and the adjacent connecting portion 130 are an integral structure. It can be understood that the first contact pad 110 and the connecting portion 130 can be formed by first forming the first conductive layer 111 and the adjacent connecting portion 130, and then forming the second conductive layer. By setting the first conductive layer 111 and the adjacent connecting portion 130 as an integral structure, the reliability of the connection between the first conductive layer 111 and the connecting portion 130 can be increased.
  • the materials of the first conductive layer 111 and the second conductive layer 112 may be the same, for example, both may be metal materials such as copper, silver or gold; in other embodiments, the materials of the first conductive layer 111 and the second conductive layer 112 may also be different.
  • the chip 100 may further include a connection layer 180 .
  • the connection layer 180 is located on the top surface of the first contact pad 110 .
  • the connection layer 180 may facilitate the interconnection between the chips 100 and improve the tightness of the connection between the chips 100 .
  • the semiconductor structure may further include: a supporting portion, the supporting portion is located on the surface of the first contact pad 110; and an electrical connecting portion, the electrical connecting portion is located on the surface of the second contact pad 120. It can be understood that by setting the supporting portion on the surface of the first contact pad 110 and the electrical connecting portion on the surface of the second contact pad 120, the chips can be connected to each other through the supporting portion and the electrical connecting portion. By setting the supporting portion and the electrical connecting portion, the subsequent welding of the chip 100 can be facilitated.
  • the semiconductor structure includes: a plurality of stacked chips 100, and a supporting portion is used to support adjacent chips 100, and an electrical connecting portion is used to electrically connect adjacent chips. It can be understood that by setting the supporting portion and the electrical connecting portion, connection and signal transmission between different chips 100 can be achieved.
  • the material of the support portion may be a relatively hard material to play a supporting role
  • the material of the electrical connection portion may be a conductive material to play a role in signal transmission between the stacked chips 100 .
  • the chip 100 is provided with a non-electrical connection area 103, and at least a portion of the non-electrical connection area 103 is provided at the edge of the first surface 101 of the chip 100, and a plurality of first contact pads 110 are provided in the non-electrical connection area 103, and a connecting portion 130 is provided between at least a portion of the first contact pads 110, and different first contact pads 110 are connected through the connecting portion 130, thereby improving the stress resistance of the chip 100, reducing the stress effect of other materials on the chip 100, and thus improving the warping of the chip 100.
  • Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.
  • the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to the aforementioned embodiments can refer to the corresponding description of the aforementioned embodiments, and will not be repeated below.
  • FIG. 7 to 13 and FIG. 2 , FIG. 7 to 13 are schematic structural diagrams corresponding to the steps of the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
  • the method for manufacturing a semiconductor structure includes: providing a chip 100, the chip 100 has a first surface 101, and the first surface 101 includes a non-electrical connection area 103 and an electrical connection area 102, wherein at least a portion of the non-electrical connection area 103 is located at the edge of the first surface 101; forming a first contact pad 110, a second contact pad 120 and a connecting portion 130, the first contact pad 110 is located in the non-electrical connection area 103, the second contact pad 120 is located in the electrical connection area 102, the connecting portion 130 is located between at least a portion of the first contact pad 110, and the top surface of the connecting portion 130 is lower than the top surface of the first contact pad 110.
  • first contact pad 110 located in the non-electrical connection area 103
  • second contact pad 120 located in the electrical connection area 102
  • signal transmission between different chips 100 can be used.
  • a connecting portion 130 located at least in part of the first contact pad 110
  • the warping of the chip 100 can be improved and the stress resistance of the edge of the chip 100 can be increased.
  • the top surface of the connecting portion 130 lower than the top surface of the first contact pad 110
  • the solder can be prevented from overflowing to the top surface of the connecting portion 130 during the welding process, resulting in poor chip connection.
  • By setting the top surface of the connecting portion 130 lower than the top surface of the first contact pad 110 abnormalities can be avoided in the process of connecting different chips 100, thereby improving the reliability of the semiconductor structure manufacturing method.
  • the method for forming the connection portion 130 includes: forming a seed layer 150, the seed layer 150 is located on the surface of the chip 100; forming a first mask layer 160, the first mask layer 160 is located on the surface of the seed layer 150, the first mask layer 160 has a target pattern, and the target pattern exposes a portion of the surface of the seed layer 150; forming a connection portion 130, the connection portion 130 is located in the target pattern.
  • Forming the seed layer 150 can facilitate the subsequent formation of the connection portion 130, and can improve the morphology of the formed connection portion 130.
  • Forming the first mask layer 160 with the target pattern can be used to define the position and morphology of the connection portion 130, and forming the connection portion 130 can be used to improve the warpage of the chip 100.
  • a seed layer 150 is formed.
  • the seed layer 150 can be formed by UBM (Under Bump Metallurgy) sputtering.
  • UBM Under Bump Metallurgy
  • the surface flatness of the seed layer 150 can be improved by using UBM sputtering.
  • the seed layer 150 may be formed by sputtering titanium and/or copper.
  • a first mask layer 160 is formed.
  • the first mask layer 160 can be formed by first forming a first initial mask layer (not shown in the figure), and then exposing and developing the first initial mask layer to form a first mask layer 160 having a target pattern.
  • the material of the first mask layer 160 may be photoresist, and the photoresist may be positive photoresist and negative photoresist.
  • Positive photoresist refers to a material in which, under the irradiation of an exposure source such as ultraviolet rays, the illuminated portion is decomposed while the unexposed portion is retained.
  • Negative photoresist refers to a material in which, under the irradiation of an exposure source such as ultraviolet rays, the illuminated portion is retained while the unexposed portion is decomposed.
  • the resolution of positive photoresist is better than that of negative photoresist, and negative photoresist has strong heat resistance. The corresponding material can be selected according to actual needs.
  • connection portion 130 is formed.
  • the material of the connection portion 130 may be copper, and the connection portion 130 may be formed by direct copper electroplating.
  • the first contact pad 110 includes: a first conductive layer 111 and a second conductive layer 112 stacked in sequence, and the method of forming the first contact pad 110 includes: after forming the connecting portion 130, forming a second mask layer 170 on the surface of the connecting portion 130, and the second mask layer 170 is spaced from the first mask layer 160; forming a second conductive layer 112, and the second conductive layer 112 is located between the first mask layer 160 and the second mask layer 170, and the portion of the connecting portion 130 in contact with the second conductive layer 112 serves as the first conductive layer 111, and the first conductive layer 111 and the second conductive layer 112 serve as the first contact pad 110.
  • the second mask layer 170 By forming the second mask layer 170 and defining the desired morphology of the second conductive layer 112 by the second mask layer 170 and the first mask layer 160, by forming the second conductive layer 112 to form a first contact pad 110 whose top surface is higher than the connecting portion 130, and by using the portion of the connecting portion 130 that is in contact with the second conductive layer 112 as the first conductive layer 111, the reliability of the connection between the connecting portion 130 and the first contact pad 110 can be improved, and the interface state between the connecting portion 130 and the first contact pad 110 can be reduced.
  • a second mask layer 170 is formed.
  • the material of the second mask layer 170 may be the same as that of the first mask layer 160 , for example, a photoresist layer.
  • the material of the second mask layer 170 may also be other insulating materials, such as silicon nitride.
  • a top surface of the second mask layer 170 may be flush with a top surface of the first mask layer 160 .
  • the term “flush” here means that the top surface of the second mask layer 170 is completely flush with the top surface of the first mask layer 160, or that the height difference between the top surface of the second mask layer 170 and the top surface of the first mask layer 160 is within the allowable error range. If the height difference between the top surface of the second mask layer 170 and the top surface of the first mask layer 160 is within the allowable error range, the top surface of the second mask layer 170 can also be regarded as flush with the top surface of the first mask layer 160.
  • a second conductive layer 112 is formed.
  • the top surface of the formed second conductive layer 112 may be lower than the top surface of the second mask layer 170.
  • a connecting layer is also formed on the top surface of the second conductive layer 112.
  • the process further includes: removing the first mask layer 160 and the second mask layer 170; etching the seed layer 150 using the first contact pad 110 as a mask to form the spaced seed layer 150.
  • the spaced seed layer is formed by etching the seed layer 150 using the first contact pad 110 as a mask.
  • connection layer 180 is formed.
  • the connection layer 180 can facilitate the interconnection between the chips 100 and improve the tightness of the connection between the chips 100 .
  • the first mask layer 160 and the second mask layer 170 are removed, and the seed layer 150 is etched.
  • the method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure forms the first contact pad 110 and the connecting portion 130 by first forming the first conductive layer 111 and the connecting portion 130 and then forming the second conductive layer 112. This can improve the reliability of the connection between the first contact pad 110 and the connecting portion 130, and can flexibly set the material of the second conductive layer 112. The reliability of the first contact pad 110 connecting the chip 100,
  • Another embodiment of the present disclosure also provides a method for manufacturing another semiconductor structure.
  • the method for manufacturing the semiconductor structure is substantially the same as the above embodiment, and the main differences include: the method for forming a connecting portion and a first contact pad is different.
  • the method for manufacturing another semiconductor structure provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above embodiment can refer to the corresponding description of the above embodiment, and will not be repeated below.
  • the method for forming the connection portion 230 and the first contact pad 210 includes: forming an initial conductive layer 270, the initial conductive layer 270 being located on the surface of the chip 200; etching the initial conductive layer 270 to form the connection portion 230 and the first contact pad 210.
  • the connection portion 230 and the first contact pad 210 are formed in the same step, and the connection portion 230 and the first contact pad 210 are an integrated structure.
  • the method of etching the initial conductive layer 270 may be to form a mask layer 260 having a target pattern and then etch the initial conductive layer 270 using the mask layer 260 as a mask.
  • the method before forming the initial conductive layer 270 , the method further includes: forming a seed layer 250 .
  • connection portion 230 and the first contact pad 210 in the same step, which can reduce the process steps of the method for manufacturing the semiconductor structure, thereby reducing the process time of the method for manufacturing the entire semiconductor structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本公开实施例涉及半导体领域，提供一种半导体结构及其制作方法，其中，半导体结构包括：芯片，芯片具有第一面，且第一面包括电性连接区和非电性连接区，其中，至少部分非电性连接区位于第一面的边缘；多个第一接触垫，第一接触垫位于非电性连接区；多个第二接触垫，第二接触垫位于电性连接区；连接部，连接部至少位于部分第一接触垫之间，且连接部的顶表面低于第一接触垫的顶表面，可以改善芯片翘曲的问题。

Description

一种半导体结构及其制作方法
交叉引用
本公开要求于2022年10月21日递交的名称为“一种半导体结构及其制作方法”、申请号为202211296206.4的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及其制作方法。
背景技术
芯片是一种集成电路，由大量的晶体管构成。不同的芯片有不同的集成规模，大到几亿；小到几十、几百个晶体管。晶体管有两种状态，开和关，用1、0来表示。多个晶体管产生的多个1与0的信号，这些信号被设定成特定的功能(即指令和数据)，来表示或处理字母、数字、颜色和图形等。芯片加电以后，首先产生一个启动指令，来启动芯片，以后就不断接受新指令和数据，来完成功能。
随着电子技术的发展，小型化、轻薄化的电子产品已经成为发展趋势。与之相应地，芯片和基板不断减薄，芯片和基板的减薄导致芯片翘曲度也就越发明显和越来越不被接受。
因此有必要提出一种半导体结构以改善芯片的翘曲度。
发明内容
本公开实施例提供一种半导体结构及其制作方法，至少可以改善芯片翘曲的问题。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括芯片，所述芯片具有第一面，且所述第一面包括电性连接区和非电性连接区，其中，至少部分所述非电性连接区位于所述第一面的边缘；多个第一接触垫，所述第一接触垫位于所述非电性连接区；多个第二接触垫，所述第二接触垫位于所述电性连接区；连接部，所述连接部至少位于部分所述第一接触垫之间，且所述连接部的顶表面低于所述第一接触垫的顶表面。
在一些实施例中，多个所述第一接触垫呈阵列式排布，且多个所述第一接触垫与多个所述连接部构成网格结构，且所述网格结构包括：方形网格、菱形网格、梯形网格或者十字形网格。
在一些实施例中，所述连接部还位于所述网格结构中处于对角位置的两个所述第一接触垫之间。
在一些实施例中，多个所述第一接触垫呈阵列式排布，且所述连接部位于处于对角位置的两个所述第一接触垫之间。
在一些实施例中，在垂直于所述第一面的方向上，所述连接部的厚度小于所述第一接触垫的厚度。
在一些实施例中，所述连接部的厚度为所述第一接触垫厚度的1/5～1/3。
在一些实施例中，所述第一接触垫与邻近的所述连接部为一体结构。
在一些实施例中，所述第一接触垫包括：依次层叠的第一导电层及第二导电层；所述第一导电层与邻近的所述连接部为一体结构。
在一些实施例中，所有所述非电性连接区均设置有所述连接部；或者，所述非电性连接区包括边角部，所述连接部仅位于所述边角部。
在一些实施例中，还包括：支撑部，所述支撑部位于所述第一接触垫表面；电连接部，所述电连接部位于所述第二接触垫表面。
在一些实施例中，包括多个层叠设置的所述芯片，且所述支撑部用于支撑相邻的所述芯片，所述电连接部用于电连接相邻的所述芯片。
在一些实施例中，所述芯片还具有第二面，所述第二面与所述第一面相对设置，所述第一接触垫还位于所述第二面；所述半导体结构还包括焊接结构，所述焊接结构位于所述第二面的所述第一接触垫的顶面。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制作方法，包括：提供芯片，所述芯片具有第一面，且所述第一面包括非电性连接区以及电性连接区，其中，至少部分所述非电性连接区位于所述第一面的边缘；形成第一接触垫、第二接触垫及连接部，所述第一接触垫位于所述非电性连接区，所述第二接触垫位于所述电性连接区，所述连接部至少位于部分所述第一接触垫之间，且所述连接部的顶表面低于所述第一接触垫的顶表面。
在一些实施例中，形成所述连接部的方法包括：形成种子层，所述种子层位于所述芯片的表面；形成第一掩膜层，所述第一掩膜层位于所述种子层的表面，所述第一掩膜层具有目标图形，所述目标图形暴露部分所述种子层的表面；形成连接部，所述连接部位于所述目标图形内。
在一些实施例中，所述第一接触垫包括：依次层叠的第一导电层及第二导电层，形成所述第一接触垫的方法包括：形成所述连接部后，在所述连接部的表面形成第二掩膜层，所述第二掩膜层与所述第一掩膜层间隔；形成第二导电层，所述第二导电层位于所述第一掩膜 层及所述第二掩膜层之间，与所述第二导电层接触连接的部分所述连接部作为所述第一导电层，所述第一导电层及所述第二导电层作为所述第一接触垫。
在一些实施例中，形成所述第一接触垫之后还包括：去除所述第一掩膜层及所述第二掩膜层；以所述第一接触垫为掩膜刻蚀所述种子层，以形成间隔的所述种子层。
在一些实施例中，形成所述连接部及所述第一接触垫的方法包括：形成初始导电层，所述初始导电层位于所述芯片的表面；刻蚀所述初始导电层以形成所述连接部及所述第一接触垫。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的一种半导体结构的剖面图；
图2为本公开一实施例提供的一种半导体结构的俯视图；
图3为本公开一实施例提供的另一种半导体结构的俯视图；
图4为本公开一实施例提供的一种局部结构示意图；
图5为本公开一实施例提供的另一种半导体结构的剖视图；
图6为本公开一实施例提供的又一种半导体结构的剖视图；
图7至图13为本公开一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图；
图14至图16为本公开另一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图。
具体实施方式
本公开实施提供一种半导体结构，通过设置芯片的至少部分非电性连接区位于芯片第一面的边缘，且在非电性连接区内设置多个第一接触垫，在至少部分第一接触垫之间设置有连接部，通过连接部将不同的第一接触垫进行连接，从而提高芯片边缘的抗应力能力，减少钝化层材料对芯片的应力效果，从而改善芯片的翘曲。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员 可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
参考图1至图6，其中，图1为本公开一实施例提供的一种半导体结构的剖视图，图2为本公开一实施例提供的一种半导体结构的俯视图，图3为本公开一实施例提供的另一种半导体结构的俯视图，图4为本公开一实施例提供的一种半导体结构的局部示意图，图5为沿图4虚线方向的一种剖视图，图6为沿图4虚线方向的另一种剖视图。
具体的，半导体结构包括：芯片100，芯片100具有第一面101，且第一面101包括电性连接区102和非电性连接区103，其中，至少部分非电性连接区103位于第一面101的边缘；多个第一接触垫110，第一接触垫110位于非电性连接区103；多个第二接触垫120，第二接触垫120位于电性连接区102；连接部130，连接部130至少位于部分第一接触垫110之间，且连接部130的顶表面低于第一接触垫110的顶表面。
通过在芯片的非电性连接区103内设置连接部130，可以不影响芯片100的电学性能，通过设置至少部分非电性连接区103设置在芯片100的边缘，且非电性连接区103内还设有连接部130，可以对芯片100翘曲的部分进行改善，通过增加芯片100第一面的抗应力能力，可以降低芯片100的翘曲度。
可以理解的是，这里说的翘曲度是相较于表面平整的芯片，芯片发生形变后芯片的弯曲程度。
在一些实施例中，芯片100可以是具有功能的结构，也就是说，芯片100内可以具有各种电路结构，例如晶体管、布线层、字线、位线及电容等等。
在一些实施例中，芯片100的第一面可以是指芯片的背面，也就是说，第一接触垫110、第二接触垫120及连接部130可以设置在芯片的背面。
在一些实施例中，电性连接区102是指的具有功能结构的区域，例如：需要输入数据信息或者读取数据信息的区域，电性连接区102的第二接触垫120之间相互间隔，且每一第二接触垫120可以仅与芯片100内电性连接区102内的一个结构接触连接，例如，一第二接触垫120仅与电性连接区102内的一条位线接触连接，通过该第二接触垫120仅向该位线提供数据信息，另一第二接触垫120仅电性连接区102内的一条字线接触连接，通过该第二接触垫120仅向该字线提供数据信息，且由于电性连接区102内的字线和位线不能直接接触连接，因此分别与字线及位线电连接的不同第二接触垫120之间也相互间隔。
在一些实施例中，非电性连接区103是指的不具有功能结构的区域，也就是说，位于非电性连接区103内的结构不影响芯片100的具体功能，非电性连接区103通常可以设置在 芯片100的边缘，从而还可以起到保护电性连接区102的作用，因为非电性连接区103不影响芯片100的功能，因此，即使非电性连接区103出现一定的损伤也不会对芯片100造成较大的影响。
在一些实施例中，第一接触垫110可以是焊盘结构，位于非电性连接区103的第一接触垫110可以仅位于芯片100的表面，也就是说，第一接触垫110可以不与芯片100内的结构接触。
在一些实施例中，芯片100还具有第二面104，第二面104与第一面101相对设置，第一接触垫110还位于第二面104；半导体结构还包括焊接结构140，焊接结构140位于第二面104的第一接触垫110的顶面。可以理解的是，在一些实施例中，还会将芯片100之间的进行焊接键合，可以通过一芯片100的第二面104的焊接结构140与另一芯片100的第一面101的第一接触垫110进行焊接，从而实现芯片100之间的连接，且第一接触垫110是位于芯片的非电性连接区103的，通过非电性连接区103的第一接触垫110进行焊接键合可以避免影响芯片100内电性连接区102的功能。
在一些实施例中，第二接触垫120可以包括焊盘结构及导电过孔，导电过孔贯穿芯片100，通过导电过孔将焊盘结构与芯片内的结构连通，进而可以通过第二接触垫120的焊盘结构向芯片100内的电路结构输入信号数据或者读出芯片100内的数据信息。
在一些实施例中，第二接触垫120还可以包括位于第二面104的焊盘结构，也就是说，第二接触垫120包括位于第一面101的焊盘结构，贯穿芯片100的导电过孔及位于第二面104的焊盘结构。
在一些实施例中，连接部130用于连接两个第一接触垫110，从而可以增加第一接触垫110的抗应力能力，且通过设置有连接部130可以减少后续封装材料或者钝化层材料与芯片100基板材料的接触面积，从而可以减少出现不同材料之间应力不匹配现象的表面积，从而可以减小芯片100的翘曲度，且通过将至少部分连接部130设置与位于芯片100边缘的非电性连接区，还可以增加芯片100边缘的重量，从而进一步平衡芯片边缘的翘曲度。
通过设置连接部130的顶表面低于第一接触垫110的顶表面可以避免在芯片100与芯片100之间相互连接的时候出现焊料溢出至连接部130的顶面，避免影响芯片100的焊接效果。以焊料为锡材料为例，通过设置连接部130的顶表面低于第一接触垫110的顶表面，可以避免出现爬锡的现象，可以提高芯片100焊接的可靠性。
在一些实施例中，多个第一接触垫110呈阵列式排布，且多个第一接触垫110与多个连接部130构成网格结构，且网格结构包括：方形网格、菱形网格、梯形网格或者十字形网格。参考图2至图4，可以理解的是，这里网格结构是指多个第一接触垫110与多个连接部130连接后的在芯片100表面正投影的形状，方形网格、菱形网格、梯形网格或者十字形网 格是对正投影形状的描述，例如，参考图2，图2中所示的网格结构呈现梯形结构，也就可以称该网格结构为梯形网格。通过设置多个第一接触垫110与多个连接部130构成网格结构，可以将多个第一接触垫110连接成一个整体，从而可以增加第一接触垫110的抗应力作用，也就可以减少芯片100的翘曲度，进而提高后续的工艺步骤的良率。
在一些实施例中，连接部130还位于网格结构中处于对角位置的两个第一接触垫110之间。以图2为例，如图示，图中非电性连接区103中的第一接触垫110共有四排九列，定义第一接触垫110从上至下分别为第一排、第二排、第三排及第四排，从左至右，分别为第一列至第九列，这里的连接部130还位于网格结构中处于对角位置的两个第一接触垫110之间是指连接部130位于第一排第一列的第一接触垫110与第二排第二列的第一接触垫110之间，或者，连接部130位于第一排第一列的第一接触垫110与第二排第三列的第一接触垫110之间等等，也就是说，部分连接部130的延伸方向与第一接触垫110的排布方向呈一定的夹角，部分连接部130的延伸方向与第一接触垫110的排布方向相同，通过设置连接部130还位于网格结构中处于对角位置的两个第一接触垫110之间可以增加连接部130与芯片100表面的接触面积，可以理解的是，连接部130与芯片100表面的接触面积越大，改善芯片100翘曲度的能力也就越强。
需要说明的是，上述中的从上至下及从左至右，是指在图2所示的结构示意图中的上下左右，并非对应实际结构。
在一些实施例中，多个第一接触垫110呈阵列式排布，且连接部130位于处于对角位置的两个第一接触垫110之间。参考图3，连接部130的延伸方向与第一接触垫110的排布方向呈一定的夹角，通过设置多个第一接触垫110呈阵列式排布，且连接部130位于处于对角位置的两个第一接触垫110之间可以改善芯片100翘曲度。
在一些实施例中，所有非电性连接区103均设置有连接部130；或者，非电性连接区103包括边角部，连接部130仅位于边角部。参考图2，可以理解的是，图2所示的半导体结构即为所有非电性连接区103均设置有连接部130，也就是位于非电性连接区103的第一接触垫110均与连接部130连接；参考图3，图3所示的半导体结构即为非电性连接区103包括边角部，连接部130仅位于边角部，芯片100的边角部通常是芯片100翘曲度最大的部分，通过在仅芯片100的边角部设置连接部130可以具有一定的改善芯片100翘曲度的同时减少整个半导体结构的成本。
在一些实施例中，在垂直于第一面101的方向上，连接部130的厚度小于第一接触垫110的厚度，通过设置连接部130的厚度小于第一接触垫110的厚度可以提高在芯片100焊接的过程中的可靠性。
在一些实施例中，连接部130的厚度为第一接触垫110厚度的1/5～1/3，可以理解的 是，连接部130的厚度越厚改善芯片100翘曲度的能力也就越强，然而连接部130的厚度越厚，越容易导致芯片100在相互连接的时候出现异常，因此通过设置连接部的厚度为第一接触垫110厚度的1/5～1/3可以使连接部130具有一定的改善芯片100翘曲的同时具有一定可靠性。
在一些实施例中，连接部130的厚度可以为2～4μm，例如3μm或者4μm等，可以理解的是，当连接部130的厚度小于2μm时，连接部130改善芯片100翘曲度的能力不强，当连接部130的厚度大于4μm时，连接部130的厚度太厚，可以能会影响后续芯片100的焊接，因此通过设置连接部130的厚度为2～4μm可以使连接部130具有一定的改善能力的同时，避免影响后续芯片100的焊接。
可以理解的是，这里的厚度是指在垂直于芯片100表面的方向上，连接部130的尺寸。
在一些实施例中，第一接触垫110与邻近的连接部130为一体结构，通过设置第一接触垫110与邻近的连接部130为一体结构可以提高第一接触垫110与邻近连接部130之间连接的可靠性，从而避免连接部130与第一接触垫110之间出现连接异常。
第一接触垫110与邻近的连接部130为一体结构也就是说，在形成第一接触垫110与连接部130的时候通过在同一步工艺步骤中形成第一接触垫110与连接部130，从而可以减少第一接触垫110与连接部130之间连接的异常。
在另一些实施例中，第一接触垫110与邻近的连接部130也可以为两个不同的结构，也就是说，在形成第一接触垫110与连接部130的时候是分别形成第一接触垫110及连接部130，通过设置第一接触垫110与邻近的连接部130也可以为两个不同的结构可以根据实际的需求进行灵活调整连接部130的设置。
在一些实施例中，连接部130的材料与第一接触垫110的材料相同，通过设置连接部130的材料与第一接触垫110的材料相同可以避免连接部130与第一接触垫110之间因为材料不同导致异常，可以减少连接部130与第一接触垫110之间界面态，从而可以提高半导体结构的可靠性。
在一些实施例中，连接部130的材料可以是铜、银或者金等金属材料，第一接触垫110的材料也可以是铜、银或者金等金属材料，第二接触垫120的材料也可以是铜、银或者金等金属材料，可以根据实际的需求选择连接部130、第一接触垫110及第二接触垫120的材料。
在一些实施例中，连接部130的宽度为0.1～2μm，可以理解的是，连接部130的宽度越宽，改善芯片100的翘曲度的能力也就越强，连接部130的宽度越宽，在后续工艺中，连接部130的材料同样会发生热胀冷缩，因此，当连接部130的宽度越宽，会减少不同连接部 130之间预留的空隙，导致连接部130之间相互挤压，因此，当连接部130的宽度小于0.1μm时，连接部130改善芯片100翘曲度的能力较弱，当连接部130的宽度大于2μm时，可能会影响连接部130的可靠性。
在一些实施例中，参考图6，第一接触垫110包括：依次层叠的第一导电层111及第二导电层112；第一导电层111与邻近的连接部130为一体结构，可以理解的是，可以通过先形成第一导电层111与邻近的连接部130，再形成第二导电层的方式，以形成第一接触垫110及连接部130，通过设置第一导电层111与邻近的连接部130为一体结构可以增加第一导电层111与连接部130之间连接的可靠性。
在一些实施例中，第一导电层111及第二导电层112的材料可以相同，例如都可以是铜、银或者金等金属材料；在另一些实施例中，第一导电层111及第二导电层112的材料也可以不同。
在一些实施例中还可以包括：连接层180，连接层180位于第一接触垫110的顶面，连接层180可以便于芯片100之间的相互连接，可以提高芯片100连接的紧密性。
在一些实施例中，半导体结构还可以包括：支撑部，支撑部位于第一接触垫110表面；电连接部，电连接部位于第二接触垫120表面，可以理解的是，通过设置支撑部位于第一接触垫110表面，电连接部位于第二接触垫120表面可以通过支撑部及电连接部实现芯片的相互连接，通过设置支撑部与电连接部可以便于后续芯片100的焊接。
在一些实施例中，半导体结构包括：多个层叠设置的芯片100，且支撑部用于支撑相邻的芯片100，电连接部用于电连接相邻的芯片，可以理解的是，通过设置支撑部与电连接部可以实现不同芯片100之间的连接及信号传输。
在一些实施例中，支撑部的材料可以是材质较硬的材料，以起到支撑的作用，电连接部的材料可以是导电材料，以起到层叠的芯片100之间信号传输的作用。
本公开实施例通过设置芯片100具有非电性连接区103，且设置至少部分非电性连接区103位于芯片100的第一面101的边缘，且在非电性连接区103内设置多个第一接触垫110，在至少部分第一接触垫110之间设置连接部130，通过连接部130将不同的第一接触垫110进行连接，从而提高芯片100的抗应力能力，减少其他材料对芯片100的应力效果，从而改善芯片100的翘曲。
本公开另一实施例还提供一种半导体结构的制作方法，该半导体结构的制作方法可以用于形成上述半导体结构，以下将结合附图对本公开另一实施例提供的半导体结构的制作方法进行说明，需要说明的是，与前述实施例相同或者相应的部分可以参考前述实施例的相应说明，以下将不再赘述。
参考图7至图13及图2，图7至图13为本公开实施例提供半导体结构的制作方法各步骤对应的结构示意图。
具体的，半导体结构的制作方法包括：提供芯片100，芯片100具有第一面101，且第一面101包括非电性连接区103以及电性连接区102，其中，至少部分非电性连接区103位于第一面101的边缘；形成第一接触垫110、第二接触垫120及连接部130，第一接触垫110位于非电性连接区103，第二接触垫120位于电性连接区102，连接部130至少位于部分第一接触垫110之间，且连接部130的顶表面低于第一接触垫110的顶表面。
通过形成位于非电性连接区103的第一接触垫110可以用于将不同的芯片100进行连接，通过形成位于电性连接区102的第二接触垫120可以用于不同芯片100之间的信号传输，通过形成至少位于部分第一接触垫110的连接部130可以用于改善芯片100的翘曲度，增加芯片100边缘的抗应力能力，通过形成连接部130的顶面低于第一接触垫110的顶表面还可以避免焊接的过程中焊料溢出至连接部130的顶面导致芯片连接不良，通过设置连接部130的顶面低于第一接触垫110的顶表面可以避免在连接不同芯片100的过程中出现异常，从而可以提高半导体结构的制作方法的可靠性。
在一些实施例中，图7至图9，形成连接部130的方法包括：形成种子层150，种子层150位于芯片100的表面；形成第一掩膜层160，第一掩膜层160位于种子层150的表面，第一掩膜层160具有目标图形，目标图形暴露部分种子层150的表面；形成连接部130，连接部130位于目标图形内。通过形成种子层150可以便于后续形成连接部130，且可以改善形成的连接部130的形貌，通过形成具有目标图形的第一掩膜层160可以用于定义连接部130的位置及形貌，通过形成连接部130用于改善芯片100的翘曲度。
参考图7，形成种子层150，在一些实施例中，形成种子层150的方式可以采用UBM(Under Bump Metallurgy)溅射的方式形成，通过采用UBM溅射的方式可以提高形成种子层150的表面平整性。
在一些实施例中，可以通过溅射钛和/或铜以形成种子层150。
参考图8，形成第一掩膜层160，在一些实施例中，形成第一掩膜层160的方式可以是先形成第一初始掩膜层(图中未示出)，通过对第一初始掩膜层进行曝光显影等步骤以形成具有目标图形的第一掩膜层160。
在一些实施例中，第一掩膜层160的材料可以是光刻胶，光刻胶可以是正性光刻胶和负性光刻胶，正性光刻胶是指在紫外线等曝光源的照射下，受光照的部分发生分解，未受光照的部分保留，负性光刻胶是指在紫外线等曝光源的照射下，受光照的部分保留，未受光照的部分发生分解，正性光刻胶的分辨率较负性光刻胶要好，负性光刻胶耐热性强，可以根据实际需要选择对应的材料。
参考图9，形成连接部130，在一些实施例中，连接部130的材料可以是铜，可以通过直接电镀铜的方式形成连接部130。
参考图10及图11，在一些实施例中，第一接触垫110包括：依次层叠的第一导电层111及第二导电层112，形成所述第一接触垫110的方法包括：形成连接部130后，在连接部130的表面形成第二掩膜层170，第二掩膜层170与第一掩膜层160间隔；形成第二导电层112，第二导电层112位于第一掩膜层160及第二掩膜层170之间，与第二导电层112接触连接的部分连接部130作为第一导电层111，第一导电层111及第二导电层112作为第一接触垫110。通过形成第二掩膜层170，且通过第二掩膜层170及第一掩膜层160定义所需的第二导电层112的形貌，通过形成第二导电层112以形成顶表面高于连接部130的第一接触垫110，且通过将第二导电层112接触连接的部分连接部130作为第一导电层111可以提高连接部130与第一接触垫110之间连接的可靠性，可以减少连接部130与第一接触垫110之间的界面态。
参考图10，形成第二掩膜层170，第二掩膜层170的材料可以与第一掩膜层160相同，例如可以是光刻胶层，第二掩膜层170的材料也可以是其他绝缘材料，例如氮化硅等。
在一些实施例中，第二掩膜层170的顶面可以与第一掩膜层160的顶面齐平。
需要说明的是，这里的齐平是指第二掩膜层170的顶面与第一掩膜层160的顶面完全齐平，或者第二掩膜层170的顶面与第一掩膜层160的顶面高度差在误差允许的范围内，第二掩膜层170的顶面与第一掩膜层160的顶面高度差在误差允许的范围内也可以视为第二掩膜层170的顶面与第一掩膜层160的顶面齐平。
参考图11，形成第二导电层112，在一些实施例中，形成的第二导电层112的顶面可以低于第二掩膜层170的顶面，在一些实施例中，还会在第二导电层112的顶面形成连接层，通过形成第二导电层112的顶面低于第二掩膜层170的顶面可以为后续形成连接层预留空间；在另一些实施例中，形成的第二导电层的顶面也可以与第二掩膜层170的顶面齐平。
参考图12及图13，形成第一接触垫110之后还包括：去除第一掩膜层160及第二掩膜层170；以第一接触垫110为掩膜刻蚀种子层150，以形成间隔的种子层150。通过以第一接触垫110为掩膜刻蚀种子层150以形成间隔的种子层。
参考图12，形成连接层180，通过形成连接层180可以便于芯片100之间的相互连接，可以提高芯片100连接的紧密性。
参考图13，去除第一掩膜层160及第二掩膜层170，刻蚀种子层150。
本公开实施例提供的半导体结构的制作方法通过先形成第一导电层111及连接部130再形成第二导电层112的方法形成第一接触垫110及连接部130，可以在提高第一接触垫110与连接部130之间连接的可靠性的同时，可以灵活设置第二导电层112的材料，还可以提高 第一接触垫110连接芯片100的可靠性，
本公开另一实施例还提供另一种半导体结构的制作方法，该半导体结构的制作方法与上述实施例大致相同，主要区别包括：形成连接部及第一接触垫的方法不同，以下将结合附图对本公开另一实施例提供的另一种半导体结构的制作方法进行说明，需要说明的是，与前述实施例相同或者相应的部分可以参考前述实施例的相应说明，以下将不再赘述。
参考图14至图16，图14至图16为本公开另一实施例提供另一种半导体结构的制作方法各步骤对应的结构示意图。
具体的，形成连接部230及第一接触垫210的方法包括：形成初始导电层270，初始导电层270位于芯片200的表面；刻蚀初始导电层270以形成连接部230及第一接触垫210。也就是说，在同一步骤中形成连接部230及第一接触垫210，连接部230与第一接触垫210为一体式结构。
在一些实施例中，刻蚀初始导电层270的方法可以是通过形成具有目标图案的掩膜层260，以掩膜层260为掩膜刻蚀初始导电层270。
在一些实施例中，形成初始导电层270之前还包括：形成种子层250。
本公开实施例通过将连接部230及第一接触垫210在同一步中形成，可以减少半导体结构的制作方法的工艺步骤，从而可以降低整个半导体结构的制作方法的工艺时长。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各种改动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (17)

  1. 一种半导体结构，包括：
    芯片，所述芯片具有第一面，且所述第一面包括电性连接区和非电性连接区，其中，至少部分所述非电性连接区位于所述第一面的边缘；
    多个第一接触垫，所述第一接触垫位于所述非电性连接区；
    多个第二接触垫，所述第二接触垫位于所述电性连接区；
    连接部，所述连接部至少位于部分所述第一接触垫之间，且所述连接部的顶表面低于所述第一接触垫的顶表面。
  2. 根据权利要求1所述的半导体结构，其中，多个所述第一接触垫呈阵列式排布，且多个所述第一接触垫与多个所述连接部构成网格结构，且所述网格结构包括：方形网格、菱形网格、梯形网格或者十字形网格。
  3. 根据权利要求2所述的半导体结构，其中，所述连接部还位于所述网格结构中处于对角位置的两个所述第一接触垫之间。
  4. 根据权利要求1所述的半导体结构，其中，多个所述第一接触垫呈阵列式排布，且所述连接部位于处于对角位置的两个所述第一接触垫之间。
  5. 根据权利要求1所述的半导体结构，其中，在垂直于所述第一面的方向上，所述连接部的厚度小于所述第一接触垫的厚度。
  6. 根据权利要求1或5所述的半导体结构，其中，所述连接部的厚度为所述第一接触垫厚度的1/5～1/3。
  7. 根据权利要求1所述的半导体结构，其中，所述第一接触垫与邻近的所述连接部为一体结构。
  8. 根据权利要求1所述的半导体结构，其中，所述第一接触垫包括：依次层叠的第一导电层及第二导电层；所述第一导电层与邻近的所述连接部为一体结构。
  9. 根据权利要求1所述的半导体结构，其中，所有所述非电性连接区均设置有所述连接部；或者，所述非电性连接区包括边角部，所述连接部仅位于所述边角部。
  10. 根据权利要求1所述的半导体结构，其中，还包括：支撑部，所述支撑部位于所述第一接触垫表面；电连接部，所述电连接部位于所述第二接触垫表面。
  11. 根据权利要求10所述的半导体结构，其中，包括多个层叠设置的所述芯片，且所述支撑 部用于支撑相邻的所述芯片，所述电连接部用于电连接相邻的所述芯片。
  12. 根据权利要求1所述的半导体结构，其中，所述芯片还具有第二面，所述第二面与所述第一面相对设置，所述第一接触垫还位于所述第二面；所述半导体结构还包括焊接结构，所述焊接结构位于所述第二面的所述第一接触垫的顶面。
  13. 一种半导体结构的制作方法，包括：
    提供芯片，所述芯片具有第一面，且所述第一面包括非电性连接区以及电性连接区，其中，至少部分所述非电性连接区位于所述第一面的边缘；
    形成第一接触垫、第二接触垫及连接部，所述第一接触垫位于所述非电性连接区，所述第二接触垫位于所述电性连接区，所述连接部至少位于部分所述第一接触垫之间，且所述连接部的顶表面低于所述第一接触垫的顶表面。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，形成所述连接部的方法包括：
    形成种子层，所述种子层位于所述芯片的表面；
    形成第一掩膜层，所述第一掩膜层位于所述种子层的表面，所述第一掩膜层具有目标图形，所述目标图形暴露部分所述种子层的表面；
    形成连接部，所述连接部位于所述目标图形内。
  15. 根据权利要求14所述的半导体结构的制作方法，其中，所述第一接触垫包括：依次层叠的第一导电层及第二导电层，形成所述第一接触垫的方法包括：
    形成所述连接部后，在所述连接部的表面形成第二掩膜层，所述第二掩膜层与所述第一掩膜层间隔；
    形成第二导电层，所述第二导电层位于所述第一掩膜层及所述第二掩膜层之间，与所述第二导电层接触连接的部分所述连接部作为所述第一导电层，所述第一导电层及所述第二导电层作为所述第一接触垫。
  16. 根据权利要求15所述的半导体结构的制作方法，其中，形成所述第一接触垫之后还包括：
    去除所述第一掩膜层及所述第二掩膜层；
    以所述第一接触垫为掩膜刻蚀所述种子层，以形成间隔的所述种子层。
  17. 根据权利要求15所述的半导体结构的制作方法，其中，形成所述连接部及所述第一接触垫的方法包括：
    形成初始导电层，所述初始导电层位于所述芯片的表面；
    刻蚀所述初始导电层以形成所述连接部及所述第一接触垫。
PCT/CN2023/075977 2022-10-21 2023-02-14 一种半导体结构及其制作方法 WO2024082495A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211296206.4A CN117954395A (zh) 2022-10-21 2022-10-21 一种半导体结构及其制作方法
CN202211296206.4 2022-10-21

Publications (1)

Publication Number Publication Date
WO2024082495A1 true WO2024082495A1 (zh) 2024-04-25

Family

ID=90736751

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/075977 WO2024082495A1 (zh) 2022-10-21 2023-02-14 一种半导体结构及其制作方法

Country Status (2)

Country Link
CN (1) CN117954395A (zh)
WO (1) WO2024082495A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040262035A1 (en) * 2003-06-30 2004-12-30 Bing-Hong Ko Electronic component mounting structure
CN101147255A (zh) * 2005-02-23 2008-03-19 Nxp股份有限公司 具有附加接触焊盘的集成电路器件封装、引线框和电子装置
WO2017138443A1 (ja) * 2016-02-10 2017-08-17 シャープ株式会社 半導体装置及び表示装置
CN210778579U (zh) * 2019-07-29 2020-06-16 星科金朋半导体（江阴）有限公司 一种防静电基板结构
CN114023662A (zh) * 2021-09-17 2022-02-08 日月光半导体制造股份有限公司 扇出型封装结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040262035A1 (en) * 2003-06-30 2004-12-30 Bing-Hong Ko Electronic component mounting structure
CN101147255A (zh) * 2005-02-23 2008-03-19 Nxp股份有限公司 具有附加接触焊盘的集成电路器件封装、引线框和电子装置
WO2017138443A1 (ja) * 2016-02-10 2017-08-17 シャープ株式会社 半導体装置及び表示装置
CN210778579U (zh) * 2019-07-29 2020-06-16 星科金朋半导体（江阴）有限公司 一种防静电基板结构
CN114023662A (zh) * 2021-09-17 2022-02-08 日月光半导体制造股份有限公司 扇出型封装结构

Also Published As

Publication number Publication date
CN117954395A (zh) 2024-04-30

Similar Documents

Publication Publication Date Title
US10957719B2 (en) Semiconductor device and a method of manufacturing the same
KR20040041045A (ko) 반도체장치 및 그 제조방법
US20230215799A1 (en) Semiconductor package
JP2005354071A (ja) 再配置されたパターンを有する半導体パッケージ及びその製造方法
US7843069B2 (en) Wire bond pads
WO2024082495A1 (zh) 一种半导体结构及其制作方法
JP2008135486A (ja) 半導体装置及び半導体パッケージ
US6853080B2 (en) Electronic device and method of manufacturing the same, and electronic instrument
JP4150604B2 (ja) 半導体装置
JP2011249564A (ja) 半導体装置の製造方法及び実装構造
JP2001118994A (ja) 半導体装置
TW531861B (en) Semiconductor packaging device and its manufacturing method
WO2023142014A1 (zh) 触控显示面板、触控显示装置、触控显示母板
US20240138059A1 (en) Circuit board structure and manufacturing method thereof
JP2004172604A (ja) 半導体集積回路装置
JPH11282002A (ja) 電子部品及びその接合構造
JP2001332677A (ja) 半導体装置の製造方法
KR20030065812A (ko) 액정표시장치의 적층형 금속배선 형성방법
JPH03203330A (ja) 半導体集積回路装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23878499

Country of ref document: EP

Kind code of ref document: A1