WO2024077818A1 - 压控频率电路及相关产品 - Google Patents

压控频率电路及相关产品 Download PDF

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Publication number
WO2024077818A1
WO2024077818A1 PCT/CN2023/074939 CN2023074939W WO2024077818A1 WO 2024077818 A1 WO2024077818 A1 WO 2024077818A1 CN 2023074939 W CN2023074939 W CN 2023074939W WO 2024077818 A1 WO2024077818 A1 WO 2024077818A1
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WIPO (PCT)
Prior art keywords
pmos tube
tube
current
voltage
comparator
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PCT/CN2023/074939
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English (en)
French (fr)
Inventor
张涛
江力
杜得喜
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深圳英集芯科技股份有限公司
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Publication of WO2024077818A1 publication Critical patent/WO2024077818A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0029—Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present application belongs to the field of electronic technology, and specifically relates to a voltage-controlled frequency circuit and related products.
  • voltage control frequency technology is a method of changing the frequency by changing the voltage.
  • the changes in output load and input voltage are adjusted by the voltage regulator diode TL431, changing the size of the optocoupler current, which is reflected in the voltage detected by the control chip at the FB end.
  • the control chip changes the switching frequency and Ipeak value of the chip through the voltage control module inside the chip according to the voltage size of the FB port, thereby achieving output stability.
  • the embodiments of the present application provide a voltage-controlled frequency circuit and related products, so that when the feedback voltage changes, the switching frequency will not have a large jump, thereby stabilizing the power supply system; improving the valley jumping phenomenon of the chip with a quasi-resonant control method, stabilizing the power supply system loop, and alleviating the noise problem of the transformer.
  • an embodiment of the present application provides a voltage-controlled frequency circuit, characterized in that it includes a clock generation circuit and a charging current variation circuit, wherein the charging current variation circuit includes a plurality of charging current control units;
  • the clock generating circuit is used to generate a clock oscillation signal according to a charging current, the charging current is generated by the charging current varying circuit, and the frequency of the clock oscillation signal is proportional to the current of the charging current;
  • the charging current variation circuit is connected to the clock generation circuit, and is used to receive a feedback voltage, and control the plurality of charging current control units according to the first voltage interval in which the feedback voltage is currently located, so as to adjust the charging current output to the clock generation circuit.
  • the voltage range of the feedback voltage includes multiple voltage intervals, and the first voltage interval is any one of the multiple voltage intervals.
  • an embodiment of the present application provides a control chip circuit, wherein the control chip circuit includes the driving circuit as described in the first aspect.
  • an embodiment of the present application provides a power adapter, which includes the driving circuit as described in the first aspect, or the control chip circuit as described in the second aspect.
  • an embodiment of the present application provides an electronic device, which includes the voltage-controlled frequency circuit as described in the first aspect, or the control chip circuit as described in the second aspect, or the power adapter as described in the third aspect.
  • the clock generating circuit generates a clock oscillation signal according to the charging current, and the charging current is generated by the charging current changing circuit; then, the charging current changing circuit receives the feedback voltage, and controls the multiple charging currents according to the first voltage interval currently in the multiple voltage intervals included in the feedback voltage.
  • a current control unit is used to adjust the charging current output to the clock generation circuit.
  • FIG. 1a is a circuit diagram of a conventional voltage-controlled frequency circuit
  • FIG1b is a comparison diagram of the feedback voltage VFB and the charging current in a conventional voltage-controlled frequency circuit
  • FIG1c is a comparison diagram of feedback voltage VFB and switching frequency in a conventional voltage-controlled frequency circuit
  • FIG2a is a schematic diagram of the structure of an NMOS tube provided in an embodiment of the present application.
  • FIG2b is a schematic diagram of the structure of a PMOS tube provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of a voltage-controlled frequency circuit provided in an embodiment of the present application.
  • FIG4 is a circuit diagram of a charging current control unit provided in an embodiment of the present application.
  • FIG5 is a comparison diagram of the feedback voltage VFB and the charging current ICARCE1 provided in an embodiment of the present application;
  • FIG6 is a comparison diagram of the feedback voltage VFB and the switching frequency Fre-CLK1 provided in an embodiment of the present application;
  • FIG. 7 is a comparison diagram of the feedback voltage VFB and the clock frequency FCLK1 provided in an embodiment of the present application.
  • FIG8 is a circuit diagram of another charging current variation circuit provided in an embodiment of the present application.
  • FIG. 9 is a circuit diagram of a clock generation circuit provided in an embodiment of the present application.
  • Figure 1a is a circuit diagram of a traditional voltage-controlled frequency circuit.
  • Op amps A1 and A2 form a subtractor.
  • VFB Vref0
  • op amp A2 clamps the voltage at point V1 to VFB.
  • Op amp A1 clamps the voltage at point V2 to Vref0.
  • Current I (Vref0-VFB)/R1.
  • Mirror current IK I*K is generated by mirror tube P2.
  • IR I*K*R.
  • P tubes P12 and P11 form a current mirror.
  • IS S*IREF0 (where IREF0 is the reference bias current).
  • the magnitude of the charging current increases linearly with the increase of the VFB voltage.
  • Figure 1b is a comparison diagram of the feedback voltage VFB and the charging current in a traditional voltage-controlled frequency circuit.
  • the charging current ICARGE0 is proportional to the feedback voltage VFB.
  • the feedback voltage VFB changes faster, the charging current ICARGE0 will jump quickly.
  • Figure 1c is a comparison diagram of the feedback voltage VFB and the switching frequency in a traditional voltage-controlled frequency circuit.
  • the switching frequency Frequency is proportional to the feedback voltage VFB.
  • the switching frequency Frequency will jump quickly.
  • Capacitor C1, comparator A3, inverter INV1, inverter INV2 and capacitor C12 form an OSC circuit, and its specific working principle is shown in Figure 1a:
  • the traditional design usually sets the voltage of the FB port to a very narrow range, which makes the switching frequency have a large range of variation.
  • the frequency change slope is too fast, a small change in the VFB voltage causes a large change in the switching frequency. This may directly lead to system instability, especially for chips with quasi-resonant control mode, causing valley jumping problems; resulting in power control system loop instability and transformer noise problems.
  • an embodiment of the present application provides a voltage-controlled frequency circuit, the voltage-controlled frequency circuit includes a clock generation circuit and a charging current change circuit, and the charging current change circuit includes multiple charging current control units.
  • the voltage-controlled frequency circuit can be applied to the scenario where the switching frequency is reduced to cause a voltage jump when the feedback voltage changes.
  • the clock generation circuit can generate a clock oscillation signal according to the charging current, and the charging current is generated by the charging current change circuit; the feedback voltage is then received by the charging current change circuit, and the multiple charging current control units are controlled according to the first voltage interval currently in the multiple voltage intervals included in the feedback voltage, so as to adjust the charging current output to the clock generation circuit.
  • This solution can be applied to a variety of scenarios, including but not limited to the application scenarios mentioned above, for example, it can be applied to chips with quasi-resonant control mode to improve the valley jumping phenomenon; it can be applied to transformers to alleviate the noise problem of transformers.
  • FIG. 2a is a schematic diagram of the structure of an NMOS tube provided in an embodiment of the present application.
  • the first end of the NMOS tube is a gate
  • the second end is a source
  • the third end is a drain
  • the fourth end is a substrate
  • the fourth end is grounded.
  • FIG. 2b is a schematic diagram of the structure of a PMOS tube provided in an embodiment of the present application.
  • the first end of the PMOS tube is a gate
  • the second end is a source
  • the third end is a drain
  • the fourth end is a substrate
  • the fourth end is used to connect to a power supply, such as VCC and VDD.
  • the specific voltage-controlled frequency circuit is introduced in detail below.
  • FIG3 is a schematic diagram of the structure of a voltage-controlled frequency circuit 30 provided in an embodiment of the present application.
  • the voltage-controlled frequency circuit 30 includes a clock generating circuit 310 and a charging current changing circuit 320 , and the charging current changing circuit 320 includes a plurality of charging current control units 321 ;
  • the clock generating circuit 310 is used to generate a clock oscillation signal according to the charging current, the charging current is generated by the charging current changing circuit 320, and the frequency of the clock oscillation signal is proportional to the current of the charging current;
  • the charging current variation circuit 320 is connected to the clock generation circuit, and is used to receive the feedback voltage, and control the plurality of charging current control units 321 according to the first voltage interval in which the feedback voltage is currently located, so as to adjust the charging current output to the clock generation circuit 310.
  • the voltage range of the feedback voltage includes multiple voltage intervals, and the first voltage interval is any one of the multiple voltage intervals.
  • the embodiment of the present application divides the voltage range of the feedback voltage into multiple voltage intervals, and at the same time sets multiple charging current control units 321 in the above-mentioned charging current change circuit 320; the charging current control unit 321 is used to adjust the charging current in different change stages according to the different voltage intervals in which the feedback voltage is located, so that the switching frequency will not have a large jump.
  • the charging current changes in the current change stage.
  • the voltage interval of the feedback voltage changes, it is necessary to switch to a change stage corresponding to the current voltage interval through multiple charging current control units 321. Therefore, when the feedback voltage changes across the voltage interval, the voltage will not suddenly jump.
  • the change rate of the charging current is different.
  • the clock oscillation signal is generated by the clock generating circuit 310 according to the charging current, and the charging current is generated by the charging current changing circuit 320; then, the feedback voltage is received by the charging current changing circuit 320, and according to the first voltage interval currently in the multiple voltage intervals included in the feedback voltage, the multiple charging current control units 321 are controlled to adjust the charging current output to the clock generating circuit 310.
  • the method of increasing the switching frequency slope in stages is adopted, and when the feedback voltage changes, the switching frequency will not have a large jump. It not only stabilizes the power supply system, but also improves the valley jumping phenomenon for chips with quasi-resonant control mode, the power supply system loop is more stable, and the noise problem of the transformer can be alleviated.
  • the charging current variation circuit further includes a first comparator A1 , a first NMOS transistor N1 , a second NMOS transistor N2 , a first PMOS transistor P1 , a second PMOS transistor P2 and a first current source IREF1 ;
  • the positive input terminal of the first comparator A1 is connected to the feedback voltage, and the negative input terminal of the first comparator A1 is connected to the output terminal of the first comparator A1 and the multiple charging current control units 321 to control the multiple charging current control units 321 to adjust the charging current output to the clock generating circuit;
  • the drain of the first NMOS tube N1 is connected to the gate of the first NMOS tube N1 and the gate of the second NMOS tube N2, and the source of the first NMOS tube N1 and the source of the second NMOS tube N2 are both grounded;
  • the drain of the second NMOS tube N2 is connected to the drain of the first PMOS tube P1 and the clock generating circuit;
  • the gate of the first PMOS tube P1 is connected to the gate of the second PMOS tube P2, the drain of the second PMOS tube P2 and the input end of the first current source IREF1;
  • the source of the first PMOS tube P1, the source of the second PMOS tube P2 and the multiple charging current control units 321 are all connected to the first power supply VCC, and the output end of the first current source IREF1 is grounded.
  • the first PMOS tube P1 and the second PMOS tube P2 are used to generate an initial charging current.
  • the first comparator A1 receives and outputs the feedback voltage, cooperates with the multiple charging current change circuits to switch between different circuit change stages, and then adjusts the conduction state of the first NMOS tube N1 and the second NMOS tube N2 to obtain the corresponding adjustment current; finally, the charging current is obtained by subtracting the adjustment current from the initial charging current. Therefore, when the adjustment current is zero, the charging current is the maximum and equal to the initial charging current; when the adjustment current is equal to the initial charging current, the charging current is the minimum and equal to zero.
  • the staged control of the charging current is achieved through the cooperation of the internal devices and units of the charging current variation circuit.
  • the specific circuit of the single charging current control unit 321 is introduced below.
  • FIG. 4 is a charging current control unit provided in an embodiment of the present application.
  • the charging current control unit 321 includes a third PMOS tube P3, a fourth PMOS tube P4, a third NMOS tube N3, a first resistor R1 and a second comparator A2;
  • the source of the third PMOS tube P3 and the source of the fourth PMOS tube P4 are both connected to the first power supply VCC, the source of the first PMOS tube and the source of the second PMOS tube;
  • the gate of the third PMOS transistor P3 is connected to the gate of the fourth PMOS transistor P4, the drain of the third PMOS transistor P3 and the drain of the third NMOS transistor N3;
  • the drain of the fourth PMOS transistor P4 is connected to the drain of the first NMOS transistor and the gate of the first NMOS transistor;
  • the gates of the three NMOS transistors are connected to the output end of the second comparator A2, and the source of the third NMOS transistor N3 is connected to the inverting input end of the second comparator A2 and one end of the first resistor R1;
  • the non-inverting input terminal of the second comparator A2 is connected to the first reference voltage
  • the other end of the first resistor R1 is connected to the output end of the first comparator and the inverting input end of the first comparator.
  • the third PMOS tube P3, the fourth PMOS tube P4, the third NMOS tube N3, the first resistor R1 and the second comparator A2 can be components in any charging current control unit 321; the first reference voltage can be the reference voltage in any charging current control unit 321.
  • the third PMOS tube P3 and the fourth PMOS tube P4 form a current mirror.
  • the first reference voltage in the second comparator A2 is compared with the feedback voltage output by the first comparator. If the feedback voltage is less than the first reference voltage, the third NMOS tube N3 is started, and then the current mirror formed by the third PMOS tube P3 and the fourth PMOS tube P4 starts to work, and the driving current output from the fourth PMOS tube P4 is K times the current of the third PMOS tube P3, that is, K*I1. Then, the conduction state of the first NMOS tube and the second NMOS tube is adjusted by the driving current to obtain the corresponding adjustment current. Finally, the size of the charging current is adjusted according to the adjustment current.
  • the charging current control unit 321 compares the reference voltage with the feedback voltage, and when the feedback voltage is greater than the reference voltage, the charging current control unit 321 is started to adjust the charging current.
  • Fig. 5 is a comparison diagram of the feedback voltage VFB and the charging current ICARCE1 provided in an embodiment of the present application. It can be seen from the figure that as the feedback voltage VFB increases, the charging current ICARCE1 increases.
  • Fig. 6 is a comparison diagram of the feedback voltage VFB and the switching frequency Fre-CLK1 provided in an embodiment of the present application. It can be seen from the figure that as the feedback voltage VFB increases, the switching frequency Fre-CLK1 increases.
  • Fig. 7 is a comparison diagram of the feedback voltage VFB and the clock frequency FCLK1 provided in an embodiment of the present application. It can be seen from the figure that as the feedback voltage VFB increases, the clock frequency FCLK1 increases.
  • FIG. 8 and FIG. 9 Please refer to FIG. 8 and FIG. 9 , and the solution of the present application will be described below through three frequency change phase solutions.
  • FIG8 is a circuit diagram of another charging current variation circuit provided in an embodiment of the present application.
  • the charging current variation circuit includes a first charging current control unit, a second charging current control unit, and a third charging current control unit;
  • the first charging current control unit includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fifth NMOS transistor N5, a fourth comparator A4 and a second resistor R2;
  • the second charging current control unit includes a seventh PMOS tube P7, an eighth PMOS tube P8, a sixth NMOS tube N6, a fifth comparator A5 and a third resistor R3;
  • the third charging current control unit includes a ninth PMOS transistor P9, a tenth PMOS transistor P10, a seventh NMOS transistor N7, a sixth comparator A6 and a fourth resistor R4;
  • the source of the fifth PMOS tube P5 is connected to the source of the sixth PMOS tube P6, the source of the seventh PMOS tube P7, the source of the eighth PMOS tube P8, the source of the ninth PMOS tube P9, the source of the tenth PMOS tube P10, The first power supply VCC, the source of the first PMOS tube and the source of the second PMOS tube;
  • the gate of the fifth PMOS tube P5 is connected to the gate of the sixth PMOS tube P6, the drain of the fifth PMOS tube P5 and the drain of the fifth NMOS tube N5;
  • the drain of the sixth PMOS tube P6 is connected to the drain of the eighth PMOS tube P8, the drain of the tenth PMOS tube P10, the drain of the first NMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube;
  • the gate of the fifth NMOS transistor is connected to the output end of the fourth comparator A4, and the source of the fifth NMOS transistor N5 is connected to the inverting input end of the fourth comparator A4 and one end of the second resistor R2; the non-inverting input end of the fourth comparator A4 is connected to the third reference voltage Vref3; the other end of the second resistor R2 is connected to one end of the third resistor R3, one end of the fourth resistor R4, the output end of the first comparator and the inverting input end of the first comparator;
  • the gate of the seventh PMOS transistor P7 is connected to the gate of the eighth PMOS transistor P8, the drain of the seventh PMOS transistor P7 and the drain of the sixth NMOS transistor N6; the gate of the sixth NMOS transistor N6 is connected to the output end of the fifth comparator A5, and the source of the sixth NMOS transistor N6 is connected to the inverting input end of the fifth comparator A5 and the other end of the third resistor R3; the non-inverting input end of the fifth comparator A5 is connected to the fourth reference voltage Vref4;
  • the gate of the ninth PMOS tube P9 is connected to the gate of the tenth PMOS tube P10, the drain of the ninth PMOS tube P9 and the drain of the seventh NMOS tube N7; the gate of the seventh NMOS tube N7 is connected to the output end of the sixth comparator A6, and the source of the seventh NMOS tube N7 is connected to the inverting input end of the sixth comparator A6 and the other end of the fourth resistor R4; the non-inverting input end of the sixth comparator A6 is connected to the fifth reference voltage Vref5.
  • the first comparator and the fourth comparator A4, the fifth comparator A5 and the sixth comparator A6 respectively form a subtractor.
  • the third reference voltage Vref3 is greater than the fourth reference voltage Vref4, and the fourth reference voltage Vref4 is greater than the fifth reference voltage Vref5.
  • the third current of the first PMOS tube is L times of the first current source, and the current of the first current source is IREF1; the third current is the initial charging current, that is, L*IREF1;
  • the fourth comparator A4, the fifth comparator A5 and the sixth comparator A6 all output a high level, and respectively turn on the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7, so that the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7, the eighth PMOS tube P8, the ninth PMOS tube P9 and the tenth PMOS tube P10 are all turned on;
  • the magnitude of the charging current gradually decreases in stages as the VFB voltage decreases.
  • the change in the charging slope gradually increases according to the range of the VFB voltage (i.e., the FB voltage gradually increases), and the switching frequency change rate gradually increases, thereby avoiding the problem of excessive switching frequency jumps, resulting in system instability and noise.
  • FIG9 is a circuit diagram of a clock generation circuit provided in an embodiment of the present application.
  • the clock generation circuit includes a first capacitor CT1, a second capacitor CT2, a first inverter INV1, a second inverter INV2, a fourth NMOS transistor N4, and a third comparator A3;
  • the non-inverting input terminal of the third comparator A3 is connected to the drain of the fourth NMOS tube N4, one end of the first capacitor CT1, the drain of the second NMOS tube and the drain of the first PMOS tube; the inverting input terminal of the third comparator A3 is connected to the second reference voltage;
  • the output end of the third comparator A3 is connected to the input end of the first inverter INV1; the output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and one end of the second capacitor CT2; the output end of the second inverter INV2 outputs the clock oscillation signal and is connected to the gate of the fourth NMOS transistor N4;
  • the other end of the second capacitor CT2, the source of the fourth NMOS transistor N4 and the other end of the first capacitor CT1 are all grounded.
  • the voltage of the first capacitor CT1 is zero, the output of the third comparator A3 is low level, so that the output of the second inverter INV2 is low level, the fourth NMOS tube N4 is turned off, and the charging current starts to charge the first capacitor CT1;
  • the output of the third comparator A3 is high, so that the output of the second inverter INV2 is high, the fourth NMOS tube N4 is turned on, and the first capacitor CT1 starts to discharge;
  • the output of the third comparator A3 is at a low level, so that the output of the second inverter INV2 is at a low level, the fourth NMOS tube N4 is turned off, the charging current starts to charge the first capacitor CT1, and the voltage of the first capacitor CT1 starts to increase.
  • the working process of the clock generation circuit of the present invention is as follows:
  • step (2) Repeat the steps in step (2).
  • the clock generating circuit by controlling the charging current, the clock generating circuit generates a clock oscillation signal to control the external device.
  • the embodiment of the present application provides a control chip circuit, the control chip circuit includes the above-mentioned voltage-controlled frequency circuit.
  • the above-mentioned voltage-controlled frequency circuit can be applied to the control chip, so that the above-mentioned voltage-controlled frequency circuit is applied to corresponding scenarios to realize corresponding functions.
  • An embodiment of the present application provides a power adapter, and the above-mentioned voltage-controlled frequency circuit and the above-mentioned control chip circuit can be applied to the power adapter.
  • An embodiment of the present application provides an electronic device, which may include the voltage-controlled frequency circuit or chip control circuit or power adapter described above.
  • the electronic device may be a power bank, a charger, or any device that requires a voltage-controlled oscillator.

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Abstract

本申请实施例提供了一种压控频率电路及相关产品，所述压控频率电路通过所述时钟产生电路根据充电电流产生时钟震荡信号，所述充电电流由所述充电电流变化电路生成；再通过所述充电电流变化电路接收反馈电压，并根据反馈电压所包括的多个电压区间中当前所处的第一电压区间，控制所述多个充电电流控制单元，以调整输出至所述时钟产生电路的充电电流。这样，根据反馈电压所处的不同电压范围，采用阶段逐次增加开关频率斜率的方法，在反馈电压变化时，开关频率不会有较大的跳变。既稳定了电源***，对于准谐振控制方式的芯片，又改善了跳谷现象，电源***环路更加稳定，还能缓解变压器的噪音问题。

Description

压控频率电路及相关产品
本申请要求于2022年10月09日提交中国专利局、申请号为202211228279X、申请名称为“压控频率电路及相关产品”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于电子技术领域，具体涉及一种压控频率电路及相关产品。
背景技术
电源控制芯片中，电压控制频率技术是一种通过改变电压大小来改变频率的一种方法。开关电源控制***中，输出负载和输入电压的变化通过稳压二极管TL431调节，改变光耦电流大小，从而反映到控制芯片检测FB端的电压。控制芯片根据FB端口的电压大小，通过芯片内部的压控模块改变芯片的开关频率和Ipeak值，从而达到输出稳定。
传统的设计通常是将FB端口的电压设置为很窄的一个变化范围，令开关频率有一个很大的变化范围，导致频率变化斜率太快时，VFB电压较小的变动，引起开关频率较大变化。这样可能直接导致***不稳定，特别是准谐振控制方式的芯片，引起跳谷的问题；带来电源控制***环路不稳和变压器噪音问题。
发明内容
本申请实施例提供了一种压控频率电路及相关产品，以期在反馈电压变化时，使开关频率不会有较大的跳变，稳定了电源***；改善准谐振控制方式的芯片的跳谷现象，稳定电源***环路，缓解变压器的噪音问题。
第一方面，本申请实施例提供了一种压控频率电路，其特征在于，包括时钟产生电路和充电电流变化电路，所述充电电流变化电路包括多个充电电流控制单元；
所述时钟产生电路，用于根据充电电流产生时钟震荡信号，所述充电电流由所述充电电流变化电路生成，所述时钟震荡信号的频率大小与所述充电电流的电流大小成正比；
所述充电电流变化电路，连接所述时钟产生电路，用于接收反馈电压，并根据所述反馈电压当前所处的第一电压区间，控制所述多个充电电流控制单元，以调整输出至所述时钟产生电路的所述充电电流，
其中，所述反馈电压的电压范围包括多个电压区间，所述第一电压区间为所述多个电压区间中的任一个。
第二方面，本申请实施例提供了一种控制芯片电路，所述控制芯片电路包括如第一方面所述的驱动电路。
第三方面，本申请实施例提供了一种电源适配器，所述电源适配器包括如第一方面所述的驱动电路，或者，如第二方面所述的控制芯片电路。
第四方面，本申请实施例提供了一种电子设备，所述电子设备包括如第一方面所述的压控频率电路，或者，如第二方面所述的控制芯片电路，或者，如第三方面所述的电源适配器。
可以看出，本申请实施例中，首先通过所述时钟产生电路根据充电电流产生时钟震荡信号，所述充电电流由所述充电电流变化电路生成；再通过所述充电电流变化电路接收反馈电压，并根据反馈电压所包括的多个电压区间中当前所处的第一电压区间，控制所述多个充电 电流控制单元，以调整输出至所述时钟产生电路的充电电流。这样，根据反馈电压所处的不同电压范围，采用阶段逐次增加开关频率斜率的方法，在反馈电压变化时，开关频率不会有较大的跳变。既稳定了电源***，对于准谐振控制方式的芯片，又改善了跳谷现象，电源***环路更加稳定，还能缓解变压器的噪音问题。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a是传统压控频率电路的电路示意图；
图1b是传统压控频率电路中反馈电压VFB与充电电流的对照图；
图1c是传统压控频率电路中反馈电压VFB与开关频率的对照图；
图2a是本申请实施例提供的一种NMOS管的结构示意图；
图2b是本申请实施例提供的一种PMOS管的结构示意图；
图3是本申请实施例提供的一种压控频率电路的结构示意图；
图4是本申请实施例提供的充电电流控制单元的电路图；
图5是本申请实施例提供的反馈电压VFB与充电电流ICARCE1的对照图；
图6是本申请实施例提供的反馈电压VFB与开关频率Fre-CLK1的对照图；
图7是本申请实施例提供的反馈电压VFB与时钟频率FCLK1的对照图；
图8是本申请实施例提供的另一种充电电流变化电路的电路图；
图9是本申请实施例提供的时钟产生电路的电路图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、***、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、***、产品或设备固有的其他步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
如图1a所示，图1a是传统压控频率电路的电路示意图。运放A1和A2构成一个减法器，当VFB<Vref0时，运放A2把V1点电压钳位到VFB。运放A1钳位V2点电压为Vref0。电流I＝(Vref0-VFB)/R1。通过镜像管P2产生镜像电流IK＝I*K，同时此镜像电流通过NMOS管N7和N8后，产生的镜像电流为IR＝I*K*R。P管P12和P11构成电流镜。IS＝S*IREF0(其中，IREF0 为基准偏置电流)。充电电流ICHARGE0＝IS-IR,即ICHARGE0＝S*IREF0-{(Vref0-VFB)*K*R/R1}。充电电流的大小随着VFB电压的增大而线性增加。同理，压控频率Fre_clk＝ICHARGE0/(C1*Vref5)随着VFB电压增大而线性增加。
如图1b所示，图1b是传统压控频率电路中反馈电压VFB与充电电流的对照图。由图1b可知，充电电流ICARGE0与反馈电压VFB成正比，当反馈电压VFB变化速率较快时，充电电流ICARGE0会快速跳变。
如图1c所述，图1c是传统压控频率电路中反馈电压VFB与开关频率的对照图。由图1c可知，开关频率Frequency与反馈电压VFB成正比，当反馈电压VFB变化速率较快时，开关频率Frequency会快速跳变。
电容C1、比较器A3、反向器INV1、反向器INV2和电容C12构成一个OSC电路，其具体工作原理如图1a所示：
(1)初始时C1电容电压为“0”，比较器A3的输出端为0，因此VCLK＝0，开关管N0关闭，充电电流ICHARGE0开始给电容C1充电；
(2)在C1电容充电过程中，当V3>Vref5时，比较器A3输出信号发生翻转，通过由反向器INV1,C12产生的延迟TDELAY后，VCLK＝1，开关管N0导通，电容C1放电；
(3)当V3<Vref5时，A3再次翻转，输出信号VCLK＝0，开关管N0关闭，充电电流ICHARGE0开始给电容CT充电，V3增加；
(4)重复(2)动作。
可以看出，传统的设计通常是将FB端口的电压设置为很窄的一个变化范围，令开关频率有一个很大的变化范围，导致频率变化斜率太快时，VFB电压较小的变动，引起开关频率较大变化。这样可能直接导致***不稳定，特别是准谐振控制方式的芯片，引起跳谷的问题；带来电源控制***环路不稳和变压器噪音问题。
为解决上述问题，本申请实施例提供了一种压控频率电路，所述压控频率电路包括时钟产生电路和充电电流变化电路，所述充电电流变化电路包括多个充电电流控制单元。该压控频率电路可以应用于在反馈电压变化时，使开关频率降低电压跳变的场景中。可以通过所述时钟产生电路根据充电电流产生时钟震荡信号，所述充电电流由所述充电电流变化电路生成；再通过所述充电电流变化电路接收反馈电压，并根据反馈电压所包括的多个电压区间中当前所处的第一电压区间，控制所述多个充电电流控制单元，以调整输出至所述时钟产生电路的充电电流。本方案可以适用于多种场景，包括但不限于上述提到的应用场景，例如，应用于准谐振控制方式的芯片中，改善跳谷现象；应用于变压器中，缓解变压器的噪音问题。
本申请实施例中，如图2a所示，图2a是本申请实施例提供的一种NMOS管的结构示意图。针对NMOS管，NMOS管的第一端为栅极，第二端为源极，第三端为漏极，第四端为衬底，第四端接地。如图2b所示，图2b是本申请实施例提供的一种PMOS管的结构示意图。针对PMOS管，PMOS管的第一端为栅极，第二端为源极，第三端为漏极，第四端为衬底，第四端用于接入电源，如VCC、VDD。
下面对具体的压控频率电路进行详细的介绍。
请参阅图3，图3是本申请实施例提供的一种压控频率电路30的结构示意图。所述压控频率电路30包括时钟产生电路310和充电电流变化电路320，所述充电电流变化电路320包括多个充电电流控制单元321；
所述时钟产生电路310，用于根据充电电流产生时钟震荡信号，所述充电电流由所述充电电流变化电路320生成，所述时钟震荡信号的频率大小与所述充电电流的电流大小成正比；
所述充电电流变化电路320，连接所述时钟产生电路，用于接收反馈电压，并根据反馈电压当前所处的第一电压区间，控制所述多个充电电流控制单元321，以调整输出至所述时钟产生电路310的充电电流，
其中，所述反馈电压的电压范围包括多个电压区间，所述第一电压区间为所述多个电压区间中的任一个。
具体实现中，本申请实施例将所述反馈电压的电压范围划分成多个电压区间，同时在上述充电电流变化电路320中设置多个充电电流控制单元321；所述充电电流控制单元321用于根据所述反馈电压所处的不同电压区间，进行不同变化阶段的充电电流调整，使得开关频率不会有较大的跳变。
具体的，所述充电电流在当前变化阶段中变化，当所述反馈电压的电压区间改变时，则需要经过多个充电电流控制单元321切换成与当前电压区间相对应的变化阶段，因此所述反馈电压跨电压区间变化时，电压不会突然跳变。此外，在每个变化阶段中，所述充电电流的变化速率有不相同。
可以看出，本实施例中，首先通过所述时钟产生电路310根据充电电流产生时钟震荡信号，所述充电电流由所述充电电流变化电路320生成；再通过所述充电电流变化电路320接收反馈电压，并根据反馈电压所包括的多个电压区间中当前所处的第一电压区间，控制所述多个充电电流控制单元321，以调整输出至所述时钟产生电路310的充电电流。这样，根据反馈电压所处的不同电压范围，采用阶段逐次增加开关频率斜率的方法，在反馈电压变化时，开关频率不会有较大的跳变。既稳定了电源***，对于准谐振控制方式的芯片，又改善了跳谷现象，电源***环路更加稳定，还能缓解变压器的噪音问题。
在一个可能的实施例中，请参阅图4或图8，所述充电电流变化电路还包括第一比较器A1、第一NMOS管N1、第二NMOS管N2、第一PMOS管P1、第二PMOS管P2和第一电流源IREF1；
所述第一比较器A1的正相输入端接入所述反馈电压，所述第一比较器A1的反相输入端连接所述第一比较器A1的输出端和所述多个充电电流控制单元321以控制所述多个充电电流控制单元321调整输出至所述时钟产生电路的充电电流；
所述第一NMOS管N1的漏极连接所述第一NMOS管N1的栅极和所述第二NMOS管N2的栅极，所述第一NMOS管N1的源极和所述第二NMOS管N2的源极均接地；所述第二NMOS管N2的漏极连接所述第一PMOS管P1的漏极和所述时钟产生电路；所述第一PMOS管P1的栅极连接所述第二PMOS管P2的栅极、所述第二PMOS管P2的漏极和所述第一电流源IREF1的输入端；所述第一PMOS管P1的源极、第二PMOS管P2的源极和所述多个充电电流控制单元321均连接第一电源VCC，所述第一电流源IREF1的输出端接地。
具体实现中，所述第一PMOS管P1和所述第二PMOS管P2用于生成初始充电电流。所述第一比较器A1接收并输出所述反馈电压，配合所述多个充电电流变化电路进行电路不同变化阶段的切换，进而调整所述第一NMOS管N1和所述第二NMOS管N2的导通状态，得到相应的调整电流；最终由所述初始充电电流减去所述调整电流，得到充电电流。因此，当所述调整电流为零时，所述充电电流最大，等于所述初始充电电流；当所述调整电流等于所述初始充电电流时，所述充电电流最小，等于零。
可以看出，本实施例中，通过充电电流变化电路内部器件和单元的配合，实现了对所述充电电流的阶段性控制。
下面对单个充电电流控制单元321的具体电路进行介绍。
在一个可能的实施例中，请参阅继续图4，图4是本申请实施例提供的充电电流控制单 元321的电路图。所述充电电流控制单元321包括第三PMOS管P3、第四PMOS管P4、第三NMOS管N3、第一电阻R1和第二比较器A2；
所述第三PMOS管P3的源极和所述第四PMOS管P4的源极均连接所述第一电源VCC、所述第一PMOS管的源极和所述第二PMOS管的源极；
所述第三PMOS管P3的栅极连接所述第四PMOS管P4的栅极、所述第三PMOS管P3的漏极和所述第三NMOS管N3的漏极；
所述第四PMOS管P4的漏极连接所述第一NMOS管的漏极和所述第一NMOS管的栅极；
所述三NMOS管的栅极连接所述第二比较器A2的输出端，所述第三NMOS管N3的源极连接所述第二比较器A2的反相输入端和所述第一电阻R1的一端；
所述第二比较器A2的正相输入端接入第一基准电压；
所述第一电阻R1的另一端连接所述第一比较器的输出端和所述第一比较器的反相输入端。
可以理解的是，第三PMOS管P3、第四PMOS管P4、第三NMOS管N3、第一电阻R1和第二比较器A2可以是任意充电电流控制单元321中的器件；所述第一基准电压可以是任意充电电流控制单元321中的基准电压。
具体实现中，所述第三PMOS管P3和所述第四PMOS管P4构成电流镜。所述第二比较器A2中的第一基准电压与所述第一比较器输出的反馈电压进行比较，若所述反馈电压小于所述第一基准电压，则启动所述第三NMOS管N3，进而使所述第三PMOS管P3和所述第四PMOS管P4构成的电流镜开始工作，从所述第四PMOS管P4中所输出的驱动电流是所述第三PMOS管P3的电流的K倍，即K*I1。进而，通过所述驱动电流调整所述第一NMOS管和所述第二NMOS管的导通状态，得到相应的所述调整电流。最终根据所述调整电流调整所述充电电流的大小。
可以看出，本实施例中，所述充电电流控制单元321通过基准电压与反馈电压进行比较，在反馈电压大于基准电压时将本充电电流控制单元321启动，加入对充电电流的调整工作中。
请参阅图5，图5是本申请实施例提供的反馈电压VFB与充电电流ICARCE1的对照图。从图中可以看出，随着所述反馈电压VFB的增加，所述充电电流ICARCE1增加。
请参阅图6，图6是本申请实施例提供的反馈电压VFB与开关频率Fre-CLK1的对照图。从图中可以看出，随着所述反馈电压VFB的增加，所述开关频率Fre-CLK1增加。
请参阅图7，图7是本申请实施例提供的反馈电压VFB与时钟频率FCLK1的对照图。从图中可以看出，随着所述反馈电压VFB的增加，所述时钟频率FCLK1增加。
请参阅图8和图9，下面通过三个频率变化阶段的方案对本申请的方案进行说明。
在一个可能的实施例中，图8是本申请实施例提供的另一种充电电流变化电路的电路图。所述充电电流变化电路包括第一充电电流控制单元、第二充电电流控制单元和第三充电电流控制单元；
所述第一充电电流控制单元包括第五PMOS管P5、第六PMOS管P6、第五NMOS管N5、第四比较器A4和第二电阻R2；
所述第二充电电流控制单元包括第七PMOS管P7、第八PMOS管P8、第六NMOS管N6、第五比较器A5和第三电阻R3；
所述第三充电电流控制单元包括第九PMOS管P9、第十PMOS管P10、第七NMOS管N7、第六比较器A6和第四电阻R4；
所述第五PMOS管P5的源极连接所述第六PMOS管P6的源极、所述第七PMOS管P7的源极、所述第八PMOS管P8的源极、所述第九PMOS管P9的源极、所述第十PMOS管P10的源极、 所述第一电源VCC、所述第一PMOS管的源极和所述第二PMOS管的源极；
所述第五PMOS管P5的栅极连接所述第六PMOS管P6的栅极、所述第五PMOS管P5的漏极和所述第五NMOS管N5的漏极；所述第六PMOS管P6的漏极连接所述第八PMOS管P8的漏极、所述第十PMOS管P10的漏极、所述第一NMOS管的漏极、所述第一NMOS管的栅极和所述第二NMOS管的栅极；
所述第五NMOS管的栅极连接所述第四比较器A4的输出端，所述第五NMOS管N5的源极连接所述第四比较器A4的反相输入端和所述第二电阻R2的一端；所述第四比较器A4的正相输入端接入第三基准电压Vref3；所述第二电阻R2的另一端连接所述第三电阻R3的一端、所述第四电阻R4的一端、所述第一比较器的输出端和所述第一比较器的反相输入端；
所述第七PMOS管P7的栅极连接所述第八PMOS管P8的栅极、所述第七PMOS管P7的漏极和所述第六NMOS管N6的漏极；所述第六NMOS管N6的栅极连接所述第五比较器A5的输出端，所述第六NMOS管N6的源极连接所述第五比较器A5的反相输入端和所述第三电阻R3的另一端；所述第五比较器A5的正相输入端接入第四基准电压Vref4；
所述第九PMOS管P9的栅极连接所述第十PMOS管P10的栅极、所述第九PMOS管P9的漏极和所述第七NMOS管N7的漏极；所述第七NMOS管N7的栅极连接所述第六比较器A6的输出端，所述第七NMOS管N7的源极连接所述第六比较器A6的反相输入端和所述第四电阻R4的另一端；所述第六比较器A6的正相输入端接入第五基准电压Vref5。
示例的，所述第一比较器与所述第四比较器A4、第五比较器A5和第六比较器A6分别构成一个减法器。
示例的，所述第三基准电压Vref3大于所述第四基准电压Vref4，第四基准电压Vref4大于所述第五基准电压Vref5。
具体实现中，当所述反馈电压大于所述第三基准电压时，所述第四比较器A4、第五比较器A5和所述第六比较器A6均输出低电平，分别将所述第五NMOS管N5、所述第六NMOS管N6和所述第七NMOS管N7关断，使得所述第五PMOS管P5、所述第七PMOS管P7、所述第九PMOS管P9、所述第六PMOS管P6、所述第八PMOS管P8、所述第十PMOS管P10也关断、所述第一NMOS管和所述第二NMOS管均关断，所述充电电流达到最大值，即充电电流ICHRGE1＝L*IREF1；时钟频率也达到最大，最大时钟频率FCLK1＝(L*IREF1)*Vref4/CT1(忽略CT1和INV1间的延迟)；进而使得开关频率达到最大。
当所述反馈电压大于第四基准电压且小于第三基准电压时，所述第四比较器A4输出高电平，将所述第五NMOS管N5导通，使得所述第五PMOS管P5和所述第六PMOS管P6导通；所述第六PMOS管P6向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第一电流为所述第五PMOS管P5电流的K倍；所述第五PMOS管P5电流为I1＝(Vref3-VFB)/R2，所述第一电流IK＝K*I1＝K*(Vref1-VFB)/R2；
所述第二NMOS管的第二电流为所述第一电流的J倍，即所述第二电流IJ＝J*K*I1＝J*K*(Vref1-VFB)/R2；
所述第一PMOS管的第三电流为所述第一电流源的L倍，所述第一电流源的电流为IREF1；所述第三电流为所述初始充电电流，即L*IREF1；
所述充电电流等于所述第三电流减去所述第二电流，即所述充电电流ICHARGE1＝L*IREF1-IJ＝L*IREF1-J*K*(Vref1-VFB)/R2。
当所述反馈电压大于第五基准电压且小于第四基准电压时，所述第四比较器A4和所述第五比较器A5均输出高电平，分别将所述第五NMOS管N5和所述第六NMOS管N6导通，使得所 述第五PMOS管P5、第六PMOS管P6、第七PMOS管P7和第八PMOS管P8均导通；所述第六PMOS管P6向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第一电流为所述第五PMOS管P5电流的K倍，即所述第一电流IK＝K*I1＝K*(Vref1-VFB)/R2。所述第八PMOS管P8向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第四电流为所述第七PMOS管P7电流的N倍；所述第七PMOS管P7电流I2＝(Vref4-VFB)/R2，所述第四电流IN＝N*I2＝N*(Vref4-VFB)/R3；
所述第二NMOS管的第二电流等于所述第一电流与所述第四电流之和的J倍，即所述第二电流IJ＝J*K*(Vref3-VFB)/R2+J*N*(Vref4-VFB)/R3；
所述第一PMOS管的第三电流为所述第一电流源的L倍，即所述第三电流＝L*IREF1；
所述充电电流等于所述第三电流减去所述第二电流，即所述充电电流ICHARGE1＝L*IREF1-J*K*(Vref3-VFB)-J*N*(Vref4-VFB)/R3。
当所述反馈电压小于所述第五基准电压时，所述第四比较器A4、所述第五比较器A5和所述第六比较器A6均输出高电平，分别将所述第五NMOS管N5、所述第六NMOS管N6和第七NMOS管N7导通，使得所述第五PMOS管P5、第六PMOS管P6、第七PMOS管P7、第八PMOS管P8、第九PMOS管P9和第十PMOS管P10均导通；所述第六PMOS管P6向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第一电流为所述第五PMOS管P5电流的K倍，即所述第一电流IK＝K*I1＝K*(Vref3-VFB)/R2；
所述第八PMOS管P8向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第四电流为所述第七PMOS管P7电流的N倍，IN＝N*I2＝N*(Vref4-VFB)/R3；
所述第十PMOS管P10向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第五电流为所述第九PMOS管P9电流的M倍，所述第九PMOS管P9电流IM＝M*I3＝M*(Vref5-VFB)/R4；
所述第二NMOS管的第二电流等于所述第一电流、所述第四电流与所述第五电流之和的J倍，即所述第二电流IJ＝J*(IK+IN+IM)；
所述第一PMOS管的第三电流为所述第一电流源的L倍，即所述第三电流＝L*IREF1；
所述充电电流等于所述第三电流减去所述第二电流，即所述充电电流ICHARGE1＝L*IREF1-J*(IK+IN+IM)。
可以看出，本实施例中，充电电流的大小随着VFB电压的减小而分段逐渐减小。充电斜率的变化量根据VFB电压所处范围逐次变大(即：FB电压逐渐变高)，开关频率变化率逐次增加，避免了开关频率跳变过大，导致***不稳定，产生噪音的问题。
在一个可能的实施例中，图9是本申请实施例提供的时钟产生电路的电路图。所述时钟产生电路包括第一电容CT1、第二电容CT2、第一反向器INV1、第二反向器INV2、第四NMOS管N4和第三比较器A3；
所述第三比较器A3的正相输入端连接所述第四NMOS管N4的漏极、所述第一电容CT1的一端、所述第二NMOS管的漏极和所述第一PMOS管的漏极连接；所述第三比较器A3的反相输入端接入第二基准电压；
所述第三比较器A3的输出端连接所述第一反向器INV1的输入端；所述第一反向器INV1的输出端连接所述第二反向器INV2的输入端和所述第二电容CT2的一端；所述第二反向器INV2的输出端输出所述时钟震荡信号、并连接所述第四NMOS管N4的栅极；
所述第二电容CT2的另一端、所述第四NMOS管N4的源极和所述第一电容CT1的另一端均接地。
具体实现中，在初始时刻时，所述第一电容CT1的电压为零，所述第三比较器A3的输出为低电平，使得所述第二反向器INV2的输出为低电平，所述第四NMOS管N4关断，所述充电电流开始为所述第一电容CT1充电；
在所述充电电流为所述第一电容CT1充电过程中，若且所述第一电容CT1的电压大于所述第二基准电压时，所述第三比较器A3输出为高电平，使得所述第二反向器INV2输出为高电平，所述第四NMOS管N4导通，所述第一电容CT1开始放电；
当所述第一电容CT1的电压小于所述第二基准电压时，所述第三比较器A3的输出为低电平，使得所述第二反向器INV2的输出为低电平，所述第四NMOS管N4关断，所述充电电流开始为所述第一电容CT1充电，所述第一电容CT1电压开始升高。
具体实现中，本发明时钟产生电路的工作过程如下：
(1)初始时第一电容CT1CT的第一电容CT1电压为“0”，第三比较器A3的输出端为0，因此VCLK1＝0，开关管N5关闭，充电电流ICHARGE1开始给电容C1充电；
(2)在CT电容充电过程中，当V8>Vref4时，比较器A3输出信号发生翻转，通过由反向器INV1,CT1产生的延迟TDELAY1后，VCLK1＝1，开关管N5导通，电容CT放电；
(3)当V8<Vref4时，A3再次翻转，输出信号VCLK1＝0，开关管N5关闭，充电电流ICHARGE1开始给电容CT充电，V8增加；
(4)重复步骤(2)的动作。
可以看出，本实施例中，通过所述充电电流的控制，所述时钟产生电路生成时钟振荡信号对外部器件进行控制。
本申请实施例提供了一种控制芯片电路，所述控制芯片电路包括上述的压控频率电路。上述压控频率电路可以应用于所述控制芯片，以将上述压控频率电路应用于相应的场景中，实现相应的功能。
本申请实施例提供了一种电源适配器，上述压控频率电路以及上述控制芯片电路均可以应用于电源适配器。
本申请实施例提供了一种电子设备，该电子设备可以包括上文所描述的压控频率电路或者芯片控制电路或者电源适配器，例如，电子设备可以为充电宝、充电器、或者任意需要使用到压控振荡器的设备。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，可轻易想到变化或替换，均可作各种更动与修改，包含上述不同功能、实施步骤的组合，包含软件和硬件的实施方式，均在本发明的保护范围。

Claims (10)

  1. 一种压控频率电路，其特征在于，包括时钟产生电路和充电电流变化电路，所述充电电流变化电路包括多个充电电流控制单元；
    所述时钟产生电路，用于根据充电电流产生时钟震荡信号，所述充电电流由所述充电电流变化电路生成，所述时钟震荡信号的频率大小与所述充电电流的电流大小成正比；
    所述充电电流变化电路，连接所述时钟产生电路，用于接收反馈电压，并根据所述反馈电压当前所处的第一电压区间，控制所述多个充电电流控制单元，以调整输出至所述时钟产生电路的所述充电电流，
    其中，所述反馈电压的电压范围包括多个电压区间，所述第一电压区间为所述多个电压区间中的任一个；
    所述充电电流在当前变化阶段中变化，当所述反馈电压的电压区间改变时，则通过所述多个充电电流控制单元切换成与当前电压区间相对应的变化阶段，以避免所述反馈电压在跨电压区间变化时开关频率突然跳变。
  2. 根据权利要求1所述的压控频率电路，其特征在于，所述充电电流变化电路还包括第一比较器、第一NMOS管、第二NMOS管、第一PMOS管、第二PMOS管和第一电流源；
    所述第一比较器的正相输入端接入所述反馈电压，所述第一比较器的反相输入端连接所述第一比较器的输出端和所述多个充电电流控制单元以控制所述多个充电电流控制单元调整输出至所述时钟产生电路的所述充电电流；
    所述第一NMOS管的漏极连接所述第一NMOS管的栅极和所述第二NMOS管的栅极，所述第一NMOS管的源极和所述第二NMOS管的源极均接地；所述第二NMOS管的漏极连接所述第一PMOS管的漏极和所述时钟产生电路；所述第一PMOS管的栅极连接所述第二PMOS管的栅极、所述第二PMOS管的漏极和所述第一电流源的输入端；所述第一PMOS管的源极、第二PMOS管的源极和所述多个充电电流控制单元均连接第一电源VCC，所述第一电流源的输出端接地。
  3. 根据权利要求2所述的压控频率电路，其特征在于，所述时钟产生电路包括第一电容、第二电容、第一反向器、第二反向器、第四NMOS管和第三比较器；
    所述第三比较器的正相输入端连接所述第四NMOS管的漏极、所述第一电容的一端、所述第二NMOS管的漏极和所述第一PMOS管的漏极连接；所述第三比较器的反相输入端接入第二基准电压；
    所述第三比较器的输出端连接所述第一反向器的输入端；所述第一反向器的输出端连接所述第二反向器的输入端和所述第二电容的一端；所述第二反向器的输出端输出所述时钟震荡信号、并连接所述第四NMOS管的栅极；
    所述第二电容的另一端、所述第四NMOS管的源极和所述第一电容的另一端均接地。
  4. 根据权利要求2或3所述的压控频率电路，其特征在于，所述充电电流控制单元包括第三PMOS管、第四PMOS管、第三NMOS管、第一电阻和第二比较器；
    所述第三PMOS管的源极和所述第四PMOS管的源极均连接所述第一电源VCC、所述第一PMOS管的源极和所述第二PMOS管的源极；
    所述第三PMOS管的栅极连接所述第四PMOS管的栅极、所述第三PMOS管的漏极和所述第三NMOS管的漏极；
    所述第四PMOS管的漏极连接所述第一NMOS管的漏极和所述第一NMOS管的栅极；
    所述三NMOS管的栅极连接所述第二比较器的输出端，所述第三NMOS管的源极连接所述 第二比较器的反相输入端和所述第一电阻的一端；
    所述第二比较器的正相输入端接入第一基准电压；
    所述第一电阻的另一端连接所述第一比较器的输出端和所述第一比较器的反相输入端。
  5. 根据权利要求3所述的压控频率电路，其特征在于，所述充电电流变化电路包括第一充电电流控制单元、第二充电电流控制单元和第三充电电流控制单元；
    所述第一充电电流控制单元包括第五PMOS管、第六PMOS管、第五NMOS管、第四比较器和第二电阻；
    所述第二充电电流控制单元包括第七PMOS管、第八PMOS管、第六NMOS管、第五比较器和第三电阻；
    所述第三充电电流控制单元包括第九PMOS管、第十PMOS管、第七NMOS管、第六比较器和第四电阻；
    所述第五PMOS管的源极连接所述第六PMOS管的源极、所述第七PMOS管的源极、所述第八PMOS管的源极、所述第九PMOS管的源极、所述第十PMOS管的源极、所述第一电源VCC、所述第一PMOS管的源极和所述第二PMOS管的源极；
    所述第五PMOS管的栅极连接所述第六PMOS管的栅极、所述第五PMOS管的漏极和所述第五NMOS管的漏极；所述第六PMOS管的漏极连接所述第八PMOS管的漏极、所述第十PMOS管的漏极、所述第一NMOS管的漏极、所述第一NMOS管的栅极和所述第二NMOS管的栅极；
    所述第五NMOS管的栅极连接所述第四比较器的输出端，所述第五NMOS管的源极连接所述第四比较器的反相输入端和所述第二电阻的一端；所述第四比较器的正相输入端接入第三基准电压；所述第二电阻的另一端连接所述第三电阻的一端、所述第四电阻的一端、所述第一比较器的输出端和所述第一比较器的反相输入端；
    所述第七PMOS管的栅极连接所述第八PMOS管的栅极、所述第七PMOS管的漏极和所述第六NMOS管的漏极；所述第六NMOS管的栅极连接所述第五比较器的输出端，所述第六NMOS管的源极连接所述第五比较器的反相输入端和所述第三电阻的另一端；所述第五比较器的正相输入端接入第四基准电压；
    所述第九PMOS管的栅极连接所述第十PMOS管的栅极、所述第九PMOS管的漏极和所述第七NMOS管的漏极；所述第七NMOS管的栅极连接所述第六比较器的输出端，所述第七NMOS管的源极连接所述第六比较器的反相输入端和所述第四电阻的另一端；所述第六比较器的正相输入端接入第五基准电压。
  6. 根据权利要求5所述的压控频率电路，其特征在于，
    当所述反馈电压大于所述第三基准电压时，所述第四比较器、第五比较器和所述第六比较器均输出低电平，分别将所述第五NMOS管、所述第六NMOS管和所述第七NMOS管关断，使得所述第五PMOS管、所述第七PMOS管、所述第九PMOS管、所述第六PMOS管、所述第八PMOS管、所述第十PMOS管也关断、所述第一NMOS管和所述第二NMOS管均关断，所述充电电流达到最大值；
    当所述反馈电压大于第四基准电压且小于第三基准电压时，所述第四比较器输出高电平，将所述第五NMOS管导通，使得所述第五PMOS管和所述第六PMOS管导通；所述第六PMOS管向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第一电流为所述第五PMOS管电流的K倍，所述第二NMOS管的第二电流为所述第一电流的J倍，所述第一PMOS管的第三电流为所述第一电流源的L倍，所述充电电流等于所述第三电流减去所述第二电流；
    当所述反馈电压大于第五基准电压且小于第四基准电压时，所述第四比较器和所述第五 比较器均输出高电平，分别将所述第五NMOS管和所述第六NMOS管导通，使得所述第五PMOS管、第六PMOS管、第七PMOS管和第八PMOS管均导通；所述第六PMOS管向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第一电流为所述第五PMOS管电流的K倍，所述第八PMOS管向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第四电流为所述第七PMOS管电流的N倍；所述第二NMOS管的第二电流等于所述第一电流与所述第四电流之和的J倍，所述第一PMOS管的第三电流为所述第一电流源的L倍，所述充电电流等于所述第三电流减去所述第二电流；
    当所述反馈电压小于所述第五基准电压时，所述第四比较器、所述第五比较器和所述第六比较器均输出高电平，分别将所述第五NMOS管、所述第六NMOS管和第七NMOS管导通，使得所述第五PMOS管、第六PMOS管、第七PMOS管、第八PMOS管、第九PMOS管和第十PMOS管均导通；所述第六PMOS管向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第一电流为所述第五PMOS管电流的K倍，所述第八PMOS管向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第四电流为所述第七PMOS管电流的N倍，所述第十PMOS管向所述第一NMOS管的漏极和栅极以及所述第二NMOS管的栅极输出的第五电流为所述第九PMOS管电流的M倍；所述第二NMOS管的第二电流等于所述第一电流、所述第四电流与所述第五电流之和的J倍，所述第一PMOS管的第三电流为所述第一电流源的L倍，所述充电电流等于所述第三电流减去所述第二电流。
  7. 根据权利要求5所述的压控频率电路，其特征在于，
    在初始时刻时，所述第一电容的电压为零，所述第三比较器的输出为低电平，使得所述第二反向器的输出为低电平，所述第四NMOS管关断，所述充电电流开始为所述第一电容充电；
    在所述充电电流为所述第一电容充电过程中，当所述第一电容的电压大于所述第二基准电压时，所述第三比较器输出为高电平，使得所述第二反向器输出为高电平，所述第四NMOS管导通，所述第一电容开始放电；
    当所述第一电容的电压小于所述第二基准电压时，所述第三比较器的输出为低电平，使得所述第二反向器的输出为低电平，所述第四NMOS管关断，所述充电电流开始为所述第一电容充电，所述第一电容电压开始升高。
  8. 一种控制芯片电路，其特征在于，所述控制芯片电路包括如权利要求1-7任一项所述的压控频率电路。
  9. 一种电源适配器，其特征在于，所述电源适配器包括如权利要求1-7任一项所述的压控频率电路，或者，如权利要求8所述的控制芯片电路。
  10. 一种电子设备，其特征在于，所述电子设备包括如权利要求1-7任一项所述的压控频率电路，或者，如权利要求8所述的控制芯片电路，或者，如权利要求9所述的电源适配器。
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