WO2024032122A1 - Cellule de mémoire et procédé de fabrication, mémoire dynamique, dispositif de stockage et procédé de lecture-écriture - Google Patents

Cellule de mémoire et procédé de fabrication, mémoire dynamique, dispositif de stockage et procédé de lecture-écriture Download PDF

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Publication number
WO2024032122A1
WO2024032122A1 PCT/CN2023/098853 CN2023098853W WO2024032122A1 WO 2024032122 A1 WO2024032122 A1 WO 2024032122A1 CN 2023098853 W CN2023098853 W CN 2023098853W WO 2024032122 A1 WO2024032122 A1 WO 2024032122A1
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Prior art keywords
electrode
gate
substrate
layer
insulating layer
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PCT/CN2023/098853
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English (en)
Chinese (zh)
Inventor
朱正勇
王桂磊
李辉辉
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北京超弦存储器研究院
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Publication of WO2024032122A1 publication Critical patent/WO2024032122A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4026—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using bipolar transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of storage technology. Specifically, this application relates to a storage unit and a manufacturing method, a dynamic memory, a storage device, and a reading and writing method.
  • DRAM Dynamic Random Access Memory
  • This application proposes a storage unit and a manufacturing method, a dynamic memory, a storage device, and a reading and writing method.
  • a storage unit including:
  • a storage capacitor including a first electrode, a capacitive dielectric layer and a second electrode arranged sequentially in a direction away from the substrate, the first electrode being connected to a reference potential terminal;
  • a transistor consisting of:
  • a drain electrode, a semiconductor layer and a main gate electrode are arranged in sequence in a direction away from the substrate.
  • the main gate electrode is columnar and electrically connected to the word line.
  • the main gate electrode is on the positive side of the substrate.
  • the projection is located within the orthographic projection of the first electrode on the substrate, the drain electrode is electrically connected to the second electrode, the semiconductor layer is located between the main gate electrode and the second electrode, and surrounding the main gate sidewall;
  • a source electrode surrounding the main gate and located on the side of the semiconductor layer away from the main gate, the source electrode being in contact with the semiconductor layer;
  • the memory unit further includes: a first insulating layer located on one side of the substrate and provided with a first receiving hole penetrating the first insulating layer, the first electrode, a capacitive dielectric layer and All or part of the structure of at least one of the second electrodes is located in the first receiving hole.
  • the second electrode is multiplexed as the drain, the second electrode extends on the first insulating layer, and the orthographic projection of the back gate on the substrate is in contact with the second electrode.
  • the orthographic projections of the outer contours on the substrate overlap.
  • the storage unit also includes:
  • a second gate insulating layer is located between the main gate and the semiconductor layer.
  • the memory cell further includes a third gate insulating layer; the back gate is located between the source and the drain, and the third gate insulating layer is located on the back gate between the source electrode and the back gate electrode and the semiconductor layer.
  • the back gate is in direct contact with the drain; or the memory unit further includes: a connection portion, The connecting portion connects the back gate and the drain; the connecting portion is located on the first insulating layer and directly overlaps the drain and the back gate respectively, and the connecting portion surrounds The back gate is overlapped with the back gate.
  • the storage unit also includes:
  • a first conductive layer located between the substrate and the first insulating layer and overlapping the first electrode, the first conductive layer including the reference potential terminal;
  • a second conductive layer is located on the side of the source electrode away from the substrate.
  • the second conductive layer includes a bit line, and the bit line is electrically connected to the source electrode through a via hole;
  • a third conductive layer is located on a side of the second conductive layer away from the substrate and is insulated from the second conductive layer.
  • the third conductive layer includes the word line, and the word line is connected to the word line through a via hole.
  • the main gate is electrically connected; or, the third conductive layer is located on the upper surface of the main gate and is directly connected to the main gate, the second conductive layer is located above the third conductive layer and Insulated from the third conductive layer.
  • the storage unit also includes:
  • An insulating dielectric layer located between the substrate and the first conductive layer
  • a second insulating layer located between the transistor and the second conductive layer and covering the transistor
  • a third insulating layer is located between the second conductive layer and the third conductive layer.
  • embodiments of the present application provide a dynamic memory, including a substrate, a plurality of word lines, a plurality of bit lines, a plurality of reference potential terminals and a plurality of the above-mentioned memory cells located on the substrate;
  • a plurality of the memory cells are divided into a plurality of memory unit groups, and the plurality of memory unit groups are arranged in a direction perpendicular to the substrate;
  • Each of the memory cell groups includes a plurality of memory cells arranged in an array in a direction parallel to the substrate, wherein each of the memory cells located in the same row is electrically connected to the same word line. Each memory cell in the same column is electrically connected to the same bit line.
  • embodiments of the present application provide a storage device, which includes the above-mentioned dynamic memory.
  • inventions of the present application provide a method of manufacturing a memory unit.
  • the manufacturing method includes:
  • a substrate is provided, and a plurality of reference potential terminals and a plurality of storage capacitors are formed on the substrate through a patterning process.
  • the storage capacitors include first electrodes and capacitive media arranged sequentially in a direction away from the substrate. layer and a second electrode, the first electrode being connected to the reference potential terminal;
  • a plurality of transistors are formed on the side of the storage capacitor away from the substrate through a patterning process.
  • Each transistor includes a drain electrode, a semiconductor layer and a main gate electrode arranged sequentially in a direction away from the substrate.
  • a source electrode surrounding the main gate and located on a side of the semiconductor layer away from the main gate; and a back gate surrounding the main gate and located on a side of the semiconductor layer away from the main gate, wherein , the main gate is columnar and its orthographic projection on the substrate is located within the orthographic projection of the first electrode on the substrate, the drain is electrically connected to the second electrode, and
  • a semiconductor layer is located between the main gate and the second electrode and surrounds the main gate sidewall, the source is in contact with the semiconductor layer, the back gate is electrically connected to the drain, and Insulated from the source, the back gate and the source form an auxiliary capacitor;
  • a plurality of word lines and a plurality of bit lines are formed through a patterning process, the word lines are electrically connected to the main gate, and the bit lines are electrically connected to the source.
  • multiple reference potential terminals and multiple storage capacitors are formed on the substrate through a patterning process, including:
  • the reference potential terminal is formed on one side of the substrate through a patterning process
  • a first electrode, a capacitive dielectric layer and a second electrode located in the first accommodation hole are formed through a patterning process to form the storage capacitor, wherein the first electrode overlaps the reference potential terminal.
  • the second electrode is reused as the drain electrode, and a plurality of transistors are formed on a side of the storage capacitor away from the substrate through a patterning process, including:
  • a first gate insulating layer is formed on the source unit, and a second accommodation hole is formed through the first gate insulating layer, the source unit and the sacrificial layer through a patterning process.
  • the orthographic projection of the hole on the substrate is located within the orthographic projection of the drain electrode on the substrate, wherein the source unit penetrated by the second receiving hole is the source electrode;
  • a semiconductor layer, a second gate insulating layer and a main gate are sequentially deposited in the second accommodation hole, and the semiconductor layer overlaps the drain electrode;
  • the remaining sacrificial layer is removed, and a third gate insulating layer and the back gate are formed in sequence.
  • the third gate insulating layer is located between the semiconductor layer and the back gate, and the back gate is connected to the back gate. between the source electrodes and between the back gate electrode and the drain electrode.
  • the back gate electrode is located between the drain electrode and the source electrode and surrounds the sidewalls of the main gate electrode.
  • the back gate electrode The orthographic projection of the gate electrode on the substrate overlaps the orthographic projection of the drain electrode on the substrate, and the back gate electrode is electrically connected to the drain electrode.
  • a third gate insulating layer and the back gate including:
  • Second photoresist layer on the substrate after fabricating the semiconductor layer, the first gate insulating layer and the main gate, and expose and develop the second photoresist layer. Remove the second photoresist layer located in the area to be etched, and then perform local etching using the unremoved second photoresist layer as a mask to remove part of the first gate insulating layer and part of the sacrificial layer layer so that part of the drain electrode is exposed;
  • the third gate insulating layer is attached to part of the upper surface of the drain, part of the sidewalls of the semiconductor layer, and the source.
  • the lower surface of the back gate electrode and the lower surface and side walls of the first gate insulating layer; the upper surface, lower surface of the back gate and the side surface close to the semiconductor layer are all in contact with the third gate insulating layer ;
  • connection portion is formed through a patterning process, and the connection portion surrounds the back gate and overlaps the back gate and the drain respectively.
  • connection portion after forming the connection portion, forming a plurality of transistors on a side of the storage capacitor away from the substrate through a patterning process, further comprising:
  • the upper surface of the second insulating layer is planarized.
  • embodiments of the present application provide a reading and writing method for reading and writing the above-mentioned storage unit.
  • the reading and writing method includes:
  • a first level is applied to the main gate of the memory cell to be written through the word line to turn on the transistor, and is transmitted to the source of the memory cell to be written through the bit line.
  • store signal to store the The signal is written into the storage unit to be written as storage data;
  • a second level is applied to the main gate of the memory cell to be read through the word line, so that the bit line senses the stored data of the memory cell to be read.
  • each storage unit includes a transistor and a storage capacitor, and in the storage unit, the back gate and the source form an auxiliary capacitor. , thereby increasing the capacitance of the memory unit, allowing the storage node to be maintained for a longer period of time, thus reducing the refresh frequency of the dynamic memory without adding film layers to ensure the integration of the dynamic memory.
  • the memory unit manufacturing method provided by the embodiment of the present application can obtain a memory unit with a lower refresh frequency and a higher integration level.
  • Figure 1 is a schematic circuit structure diagram of a dynamic memory provided by an embodiment of the present application.
  • Figure 2 is a schematic circuit structure diagram of a memory unit in a dynamic memory provided by an embodiment of the present application
  • Figure 3 is a schematic structural diagram of a dynamic memory provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a storage unit in a dynamic memory provided by an embodiment of the present application.
  • Figure 5 is a schematic diagram of the frame structure of a storage device provided by an embodiment of the present application.
  • Figure 6 is a schematic flowchart of a method of manufacturing a memory unit provided by an embodiment of the present application.
  • Figure 7 is a schematic flowchart of step S1 in a method for manufacturing a memory unit provided by an embodiment of the present application.
  • Figure 8 is a side view of the process flow of step S101 in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 9 is a top view of the process flow of step S101 in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 10 is a side view of the process flow of step S102 in the manufacturing method of the memory unit shown in Figure 7;
  • FIG 11 is a top view of the process flow of step S102 in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 12 is a side view of the process flow of step S103 in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 13 is a top view of the process flow of step S103 in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 14 is a side view of the memory unit after step S1 is completed in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 15 is a schematic flowchart of step S2 in a method for manufacturing a memory unit provided by an embodiment of the present application;
  • Figure 16 is a side view of the process flow of step S201 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 17 is a top view of the process flow of step S201 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 18 is a side view of the process flow of step S202 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 19 is a top view of the process flow of step S202 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 20 is a side view of the process flow of step S203 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 21 is a top view of the process flow of step S203 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 22 is a schematic flowchart of step S204 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 23 is a side view of the process flow of step S2041 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 24 is a top view of the process flow of step S2041 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 25 is a side view of the process flow of step S2042 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 26 is a top view of the process flow of step S2042 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 27 is a side view of the process flow of step S2043 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 28 is a top view of the process flow of step S2043 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 29 is a side view of the memory unit after step S2 is completed in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 30 is a schematic flow chart of a reading and writing method provided by an embodiment of the present application.
  • FIG. 31 is a graph showing transfer characteristics of transistors in a memory cell when writing different data.
  • connection may include wireless connections or wireless couplings.
  • the term “and/or” used herein refers to at least one of the items defined by the term. For example, “A and/or B” can be realized as “A”, or as “B”, or as “A and B” ".
  • DRAM memory has the advantages of simpler structure, lower manufacturing cost, and higher capacity density.
  • DRAM memory usually includes multiple memory cells, and each memory cell includes transistors. Since the transistors exist across channels, Leakage phenomenon, which will cause the charge stored in the memory unit to gradually drain, so the stored data needs to be refreshed frequently to ensure the effectiveness of the stored data.
  • the storage unit and production method, dynamic memory, storage device, and reading and writing method provided by this application are intended to solve the above technical problems of the existing technology.
  • the embodiment of the present application provides a storage unit and a dynamic memory.
  • the dynamic memory provided by this embodiment includes a substrate 100, a plurality of word lines WL, a plurality of bit lines BL located on the substrate 100, a plurality of reference potential terminals Vref and a plurality of memory cells.
  • the memory unit 10 includes a storage capacitor C1 and a transistor T.
  • the storage capacitor C1 includes a first electrode 104, a capacitive dielectric layer 105 and a second electrode 106 sequentially arranged in a direction away from the substrate 100.
  • the first electrode 104 is connected to the reference potential terminal Vref.
  • the transistor T includes: a drain electrode, a semiconductor layer 109 and a main gate electrode 111 arranged in sequence in a direction away from the substrate 100, a source electrode 107 surrounding the main gate electrode 111 and located on the side of the semiconductor layer 109 away from the main gate electrode 111;
  • the back gate 113 surrounds the main gate 111 and is located on the side of the semiconductor layer 109 away from the main gate 111 .
  • the main gate 111 is columnar and is electrically connected to the word line WL.
  • the orthographic projection of the main gate 111 on the substrate 100 is located within the orthographic projection of the first electrode 104 on the substrate 100.
  • the drain is electrically connected to the second electrode 106.
  • the semiconductor layer 109 is located between the main gate 111 and the second electrode 106 and surrounds the sidewall of the main gate 111, the source 107 is in contact with the semiconductor layer 109, and the back gate 113 is electrically connected to the drain and insulated from the source 107, The back gate 113 and the source 107 form a auxiliary capacitor C2.
  • the second electrode 106 is multiplexed as a drain, the second electrode 106 extends on the first insulating layer 103 , and the front projection of the back gate 113 on the substrate 100 It overlaps with the orthographic projection of the outer contour of the second electrode 106 on the substrate 100 .
  • the second electrode in the memory cell 10 is multiplexed as a drain, both the second electrode and the drain are marked with “106”.
  • the second electrode and the drain electrode can also be provided separately and electrically connected.
  • the second electrode 106 is multiplexed as a drain electrode. This can further simplify the structure of the memory unit 10 and improve the integration of the dynamic memory.
  • auxiliary capacitor C2 is shown in FIG. 2 , in fact, the auxiliary capacitor C2 is composed of the back gate 113 of the transistor T and the source 107 of the transistor. Therefore, the memory unit 10 is not added. complexity.
  • each memory cell 10 includes a transistor T and a storage capacitor C1, and in the memory cell 10, the back gate 113 and the source 107 form an auxiliary capacitor C2, thereby increasing the number of memory cells.
  • the capacitance of 10 enables the storage node N1 to be maintained for a longer period of time, thereby reducing the refresh frequency of the dynamic memory without adding film layers to ensure the integration of the dynamic memory.
  • the bit line BL can obtain the storage node signal; if the memory unit 10 is in the "0" state, the bit line BL cannot obtain the storage node signal. , that is, the data signal read by the bit line BL in the two states of "1" or "0” is greatly different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, the current can only be output through the detection transistor T.
  • the current signal or the voltage signal can be used for detection. , which facilitates the design of peripheral detection circuits according to specific needs and has better adaptability.
  • the material of the semiconductor layer 109 includes metal oxide. Due to the inherent characteristics of metal oxide semiconductors (low electron mobility and other factors), when the material of the semiconductor layer 109 is metal oxide, the leakage current of the transistor T can be smaller and the speed of charge loss on the storage capacitor can be reduced. Therefore, the data storage time of the dynamic memory can be extended, which is beneficial to reducing the refresh frequency and power consumption of the dynamic memory.
  • the material of the metal oxide may be Indium Gallium Zinc Oxide (IGZO for short).
  • IGZO Indium Gallium Zinc Oxide
  • the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thus ensuring the working performance of the dynamic memory.
  • the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz , AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials, just ensure that the leakage current of the transistor can meet the requirements, and the details can be adjusted according to the actual situation.
  • multiple memory cells 10 are divided into multiple memory unit groups 1000 , and the multiple memory unit groups 1000 are arranged in a direction perpendicular to the substrate 100 ;
  • Each memory cell group 1000 includes a plurality of memory cells 10 arranged in an array in a direction parallel to the substrate 100.
  • Each memory cell 10 located in the same row is electrically connected to the same word line WL, and each memory cell 10 located in the same column is electrically connected.
  • Memory cell 10 is electrically connected to the same bit line BL.
  • different arrangements can be selected according to specific storage capacity requirements and space constraints on dynamic memory, that is, by adjusting the number of storage unit groups 1000 (i.e. Adjust the number of stacking levels of the dynamic memory in the Y direction), or adjust the number of storage units 10 in each storage unit group 1000 (including adjusting the number of storage units 10 in each row and/or each column) to achieve storage Optimized design of capacity and storage space.
  • the dynamic memory includes 1st to nth word lines WL, 1st to mth bit lines BL, and 1st to mth reference potential terminals Vref.
  • the memory unit 10 also includes a first insulating layer 103.
  • the first insulating layer 103 is located on one side of the substrate 100, and the first insulating layer 103 is provided with Through the first receiving hole of the first insulating layer 103, all or part of the structure of at least one of the first electrode 104, the capacitive dielectric layer 105 and the second electrode 106 is located in the first receiving hole.
  • the memory unit 10 further includes a first conductive layer 102 , a second conductive layer 116 and a third conductive layer 118 .
  • the first conductive layer 102 is located between the substrate 100 and the first insulating layer 103 and overlaps the first electrode 104.
  • the first conductive layer 102 includes a reference potential terminal Vref; the second conductive layer 116 is located in the memory unit 10 away from the substrate 100.
  • the second conductive layer 116 is located on the side of the source electrode 107 away from the substrate 100
  • the second conductive layer 116 includes a bit line BL
  • the bit line BL is electrically connected to the source electrode 107 through a via hole
  • the third The conductive layer 118 is located on a side of the second conductive layer 116 away from the substrate 100.
  • the third conductive layer 118 includes a word line WL, and the word line WL is electrically connected to the main gate 111 through a via hole.
  • the memory unit 10 further includes an insulating dielectric layer 101 , and the insulating dielectric layer 101 is located between the substrate 100 and the first conductive layer 102 .
  • the memory unit 10 further includes a second insulating layer 115 and a third insulating layer 117 .
  • the second insulating layer 115 covers the transistor T, that is, the second insulating layer 115 is located between the transistor T and the second conductive layer 116
  • the third insulating layer 117 is located between the second conductive layer 116 and the third conductive layer 118 .
  • the third conductive layer 118 can also be located on the upper surface of the main gate 111 and directly connected to the main gate 111.
  • the second conductive layer 116 is located above the third conductive layer 118 and connected to the third conductive layer 118. insulation.
  • the second conductive layer 116 is insulated from the third conductive layer 118 by disposing an insulating layer between the third conductive layer 118 and the second conductive layer 116 .
  • the structural arrangement shown in Figure 4 is that the transistor T adopts a vertical channel structure, so that the drain 106 can be positioned closer to the storage capacitor C1, and the main gate 111 and the source 107 can be positioned closer to the word line WL. and the bit line BL to facilitate the electrical connection between the drain electrode 106 and the storage capacitor C1, and the source electrode 107 and the bit line BL, and the main gate 111 and the word line WL.
  • the position design of the above-mentioned first to third conductive layers is conducive to the connection between the storage capacitor C1 and the reference potential terminal Vref, and is conducive to the connection between the transistor T and the word line WL and the bit line BL, thereby conducive to realizing the structural optimization of the dynamic memory.
  • the first insulating layer 103 forms a first receiving hole 1031 penetrating the first insulating layer 103 through a deep etching method (please refer to FIG. 10 ), and the storage capacitor C1 is formed in the first receiving hole 1031 .
  • the first electrode 104 of the storage capacitor C1 can be overlapped with the reference potential terminal Vref located under the first insulating layer 103, and the first receiving hole 1031 can be used to make the opposing area of the first electrode 104 and the second electrode 106 larger, thereby The charge storage capacity of each memory cell 10 is improved as much as possible within a limited space, thereby further reducing the refresh frequency of the dynamic memory.
  • the memory unit 10 further includes a first gate insulating layer 108 and a second gate insulating layer 110 .
  • the first gate insulating layer 108 covers the source 107; the second gate insulating layer 110 is located between the main gate 111 and the semiconductor layer 109 to insulate the main gate 111 from the semiconductor layer 109.
  • the memory unit 10 further includes a third gate insulating layer 112 , a back gate 113 is located between the source 107 and the drain 106 , and the third gate The insulating layer 112 is located between the back gate 113 and the source 107 and between the back gate 113 and the semiconductor layer 109 .
  • the third gate insulating layer 112 serves as a dielectric layer of the auxiliary capacitor C2.
  • the third gate insulating layer 112 is also located between the back gate 113 and the drain 106 .
  • the memory unit 10 further includes a connection part 114 , which connects the back gate 113 and the drain 106 .
  • the connection part 114 is located on the first insulating layer. 103 and directly overlap with the drain electrode 106 and the back gate 113 respectively.
  • the connecting portion 114 surrounds the back gate 113 and overlaps with the back gate 113 .
  • the connection portion 114 is used to overlap the drain electrode 106 and the back gate electrode 113. Since the connection portion 114 surrounds the back gate electrode 113, a sufficient connection between the drain electrode 106 and the back gate electrode 113 can be ensured.
  • the back gate 113 can also be in direct contact with the drain 106.
  • the number of film layers of the memory unit 10 is smaller, which is beneficial to simplifying the manufacturing process of the dynamic memory.
  • an embodiment of the present application provides a storage device.
  • the storage device includes the dynamic memory in the above embodiment and has the beneficial effects of the dynamic memory in the above embodiment, which will not be described again here.
  • the storage device in the embodiment of the present application may be the main memory of a computer, etc., and the specific details may be determined according to the actual situation.
  • an embodiment of the present application provides a method of manufacturing a memory unit, as shown in Figures 1-4 and 6.
  • the manufacturing method provided by this embodiment includes:
  • the storage capacitor C1 includes first electrodes 104 sequentially arranged in a direction away from the substrate 100. , the capacitive dielectric layer 105 and the second electrode 106. The first electrode 104 is connected to the reference potential terminal Vref.
  • Each transistor T includes a drain, a semiconductor layer 109 and a main gate 111 sequentially arranged in a direction away from the substrate 100 , the source electrode 107 surrounding the main gate 111 and located on the side of the semiconductor layer 109 away from the main gate 111 , and the back gate 113 surrounding the main gate 111 and located on the side of the semiconductor layer 109 away from the main gate 111 .
  • the main gate 111 is columnar and is electrically connected to the word line WL.
  • the orthographic projection of the main gate 111 on the substrate 100 is located within the orthographic projection of the first electrode 104 on the substrate 100.
  • the drain is electrically connected to the second electrode 106.
  • the semiconductor layer 109 is located between the main gate 111 and the second electrode 106 and surrounds the sidewall of the main gate 111, the source 107 is in contact with the semiconductor layer 109, and the back gate 113 is electrically connected to the drain and insulated from the source 107, The back gate 113 and the source 107 form a auxiliary capacitor C2.
  • S3 Multiple word lines WL and multiple bit lines BL are formed through a patterning process.
  • the word lines WL are electrically connected to the main gate 111, and the bit lines BL are electrically connected to the source electrode 107.
  • each memory cell group 1000 includes a plurality of memory cells 10 arranged in an array in a direction parallel to the substrate 100 , wherein each memory cell 10 located in the same row is electrically connected to the same word line WL, and each memory cell 10 located in the same column is electrically connected to the same bit line BL.
  • the manufacturing method of the memory unit provided in this embodiment is relatively simple.
  • the memory unit 10 includes a transistor T and a storage capacitor C1. Since the transistor T includes a back gate 113, the back gate 113 and the source 107 form an auxiliary capacitor C2.
  • the storage capacitor C1 and The auxiliary capacitor C2 is jointly used to store charges, which is equivalent to increasing the capacity of the storage unit 10, thus reducing the refresh frequency of the dynamic memory; and since the capacity of the storage unit 10 is not increased, the capacity of the storage unit 10 is not increased. Volume, that is, does not affect the integration of dynamic memory.
  • step S1 includes:
  • S101 Form a reference potential terminal Vref on one side of the substrate 100 through a patterning process.
  • Figure 8 is a cross-sectional view along the line A-A in Figure 9
  • first the first conductive layer 102 is formed on the substrate 100, and then the first conductive layer 102 is patterned to form a reference Potential terminal Vref.
  • the reference potential terminal Vref can be a common electrode or, of course, a reference potential line. That is, the reference potential terminal Vref can be a structure that can provide a reference potential and can be connected to one pole of the storage capacitor.
  • FIG. 8 is a cross-sectional view along the line A-A in Figure 9
  • the method for manufacturing a memory cell provided in this embodiment further includes forming an insulating dielectric layer 101 on the substrate 100 ;
  • the conductive layer 102 includes: forming a first conductive layer 102 on a side of the insulating dielectric layer 101 away from the substrate 100 .
  • S102 Deposit the first insulating layer 103 on the side of the reference potential terminal Vref away from the substrate 100, and form a plurality of The first receiving hole 1031 penetrates the first insulating layer 103 .
  • the first receiving hole 1031 exposes the reference potential terminal Vref, so that the reference potential terminal Vref can communicate with the subsequently produced storage capacitor C1.
  • An electrode 104 overlaps.
  • S103 Form the first electrode 104, the capacitive dielectric layer 105 and the second electrode 106 located in the first receiving hole 1031 through a patterning process to form the storage capacitor C1, where the first electrode 104 overlaps the reference potential terminal Vref.
  • the depth of the first accommodation hole 1031 (that is, the thickness of the first insulating layer 103) and the size of the first accommodation hole 1031 on a plane parallel to the substrate 100 have an impact on the volume of the storage capacitor C1. , that is, it has an impact on the capacitance of the storage capacitor C1. Therefore, by designing the thickness of the first insulating layer 103 and the size of the first receiving hole 1031 on a plane parallel to the substrate 100, the capacitance of the storage capacitor C1 can be adjusted. Adjustment.
  • FIG. 12 is a cross-sectional view along the line C-C in Figure 13
  • manufacturing the storage capacitor C1 in the first receiving hole 1031 not only enables the first electrode 104 of the storage capacitor C1 to be connected to the first
  • the reference potential terminal Vref under an insulating layer 103 is overlapped, and the first receiving hole 1031 is used to make the opposing area of the first electrode 104 and the second electrode 106 larger, thereby improving each memory cell 10 as much as possible in a limited space.
  • the charge storage capacity further reduces the refresh frequency of dynamic memory.
  • an insulating material needs to be deposited.
  • the insulating material covers the second electrode 106 and is also used as a part of the first insulating layer 103 ; and then the second insulating material is deposited.
  • the electrode 106 is exposed. It should be noted that in order to achieve higher precision in subsequent structures, it is necessary to ensure that the second electrode 106 has a high flatness. Therefore, chemical mechanical polishing can be used to expose the second electrode 106, thereby improving the flatness of the second electrode 106. Spend.
  • step S2 includes:
  • S201 Form a sacrificial layer 200 on the side of the second electrode 106 away from the substrate 100, and form the source unit 107' on the sacrificial layer 200 through a patterning process.
  • the sacrificial layer 200 will be etched away in subsequent processes, and the thickness of the sacrificial layer 200 determines the source electrode 107 and the drain electrode 106 Therefore, the thickness of the sacrificial layer 200 needs to be designed according to specific requirements.
  • S202 Form the first gate insulating layer 108 on the source unit 107', and form a second receiving hole 400 penetrating the first gate insulating layer 108, the source unit 107' and the sacrificial layer 200 through a patterning process.
  • the orthographic projection of the hole 400 on the substrate 100 is located within the orthographic projection of the drain electrode 106 on the substrate 100 , wherein the source unit 107 ′ penetrated by the second receiving hole 400 is the source electrode 107 .
  • step 202 specifically includes: forming a first gate insulating layer 108 on the source unit 107'; A first photoresist layer 300 is formed on the layer 108, and then the first photoresist layer 300 is exposed and developed to remove the first photoresist layer 300 located in the area to be etched; The layer 300 is used as a mask for etching to obtain the second receiving hole 400 penetrating the first gate insulating layer 108 , the source unit 107 ′ and the sacrificial layer 200 .
  • the shape of the second receiving hole 400 is designed according to the shape of the main grid 111 that needs to be formed. For example, if a cylindrical main grid 111 needs to be formed, the second receiving hole 400 will be a circular receiving hole. If a prism needs to be formed, the shape of the second receiving hole 400 will be designed.
  • the second receiving hole 400 formed by the main gate 111 is a corresponding polygonal receiving hole.
  • S203 The semiconductor layer 109, the second gate insulating layer 110 and the main gate 111 are sequentially deposited in the second accommodation hole 400, and the semiconductor layer 109 is in contact with the drain electrode 106.
  • the formed source 107 has a corresponding annular shape according to the shape of the main gate 111.
  • the main gate 111 is a cylinder.
  • the source 107 will be a four-sided ring.
  • the third gate insulating layer 112 is located between the semiconductor layer 109 and the back gate 113, and between the back gate 113 and the source. 107 and between the back gate 113 and the drain 106.
  • the back gate 113 is located on the side of the drain 106 away from the substrate 100 and between the drain 106 and the source 107.
  • the back gate 113 surrounds the main gate. 111, the orthographic projection of the back gate 113 on the substrate 100 overlaps with the orthographic projection of the drain 106 on the substrate 100, and the orthographic projection of the back gate 113 on the substrate 100 overlaps with the main gate 111 on the substrate 100.
  • the front projection on the substrate 100 has no overlap, and the back gate 113 and the drain 106 are electrically connected.
  • step S204 includes:
  • S2041 Form the second photoresist layer 500 on the substrate 100 after the semiconductor layer 109, the first gate insulating layer 108 and the main gate 111 are formed, and expose and develop the second photoresist layer 500 to remove it.
  • the second photoresist layer 500 located in the area to be etched is then partially etched using the unremoved second photoresist layer 500 as a mask to remove part of the first gate insulating layer 108 and part of the sacrificial layer 200. So that part of the drain electrode 106 is exposed.
  • Figure 23 is a G-G cross-sectional view in Figure 24
  • the edge part of the drain electrode 106 is located in the area to be etched, and the source electrode 107 has no intersection with the area to be etched.
  • the edge portion of the drain electrode 106 needs to be exposed to facilitate the subsequent electrical connection between the back gate 113 and the drain electrode 106 .
  • S2042 Remove the remaining sacrificial layer 200, and form the third gate insulating layer 112 and the back gate 113 in sequence.
  • FIGS. 25 and 26 are cross-sectional views along the line H-H in FIG. 26
  • the third gate insulating layer 112 is first formed, and then the back gate 113 is formed.
  • the third gate insulating layer 112 is attached to part of the upper surface of the drain electrode 106, part of the sidewalls of the semiconductor layer 109, the lower surface of the source electrode 107, and the lower surface and sidewalls of the first gate insulating layer 108; the back gate 113
  • the upper surface, lower surface and the side surface close to the semiconductor layer 109 are all in contact with the third gate insulating layer 112 .
  • the back gate 113 and the source 107 form an auxiliary capacitor C2
  • the third gate insulation layer 112 located between the back gate 113 and the source 107 serves as a dielectric layer of the auxiliary capacitor C2.
  • the material of the layer 112 and the thickness of the third gate insulating layer 112 can adjust the capacitance of the auxiliary capacitor C2.
  • adjusting the overlapping area of the back gate 113 and the source 107 can also adjust the capacitance of the auxiliary capacitor C2.
  • connection portion 114 is formed through a patterning process.
  • the connection portion 114 surrounds the back gate 113 and overlaps the back gate 113 and the drain electrode 106 respectively.
  • the connecting portion 114 surrounds the back gate 113 so that the connecting portion 114 and the back gate 113, and the connecting portion 114 and the drain 106 all have Larger overlap area, thereby reducing overlap resistance.
  • step S2 also includes: forming a second insulating layer 115 on the substrate 100 after the connection portion 114 is formed, and covering the second insulating layer 115 Transistor T.
  • the upper surface of the second insulating layer 115 is planarized to facilitate the subsequent production of the word line WL and the bit line BL.
  • embodiments of the present application provide a reading and writing method for reading and writing the storage unit in the above embodiment, as shown in Figures 1 to 4 and Figure 30.
  • the reading and writing method includes:
  • the first level is applied to the main gate 111 of the memory cell 10 to be written through the word line WL to turn on the transistor T, and the first level is applied to the memory cell 10 to be written through the bit line BL.
  • the source 107 transmits the storage signal to write the storage signal into the storage unit 10 to be written as storage data.
  • a first level (for example, 5V, the specific value can be adjusted according to the actual situation) is applied to the main gate 111 through the word line WL, so that the transistor is in a conducting state, and the first level
  • the size is related to the structure of the transistor, the material of the semiconductor layer 109 in the transistor and other factors, and can be adjusted according to the actual situation.
  • the transistor when the transistor is turned on, a voltage is applied to the source electrode 107 through the bit line BL, the source electrode 107 and the drain electrode 106 are connected through the semiconductor layer 109 , and a data signal is written to the storage capacitor C1 .
  • the drain 106 and the back gate 113 are electrically connected, so the voltages on the source 107 and the drain 106 are the same as the voltage on the back gate 113 . That is to say, the voltage on the back gate 113 determines the amount of charge in the storage capacitor C1, and further determines whether the binary value of the data signal stored in the memory unit 10 is 0 or 1.
  • the back gate 113 and the source 107 form the auxiliary capacitor C2
  • the charge stored in the auxiliary capacitor C2 can make the storage node N1 (ie, the back gate 113 , the drain electrode 116 and the second electrode of the storage capacitor C1) can be maintained for a longer period of time, thereby reducing the refresh frequency.
  • T2 In the read state, the second level is applied to the main gate 111 of the memory cell 10 to be read through the word line WL, so that the bit line BL senses the storage data of the memory cell 10 to be read.
  • the transistor T when the memory cell 10 previously stored data "1", the back gate 113 and the drain 106 had a higher potential, and under the combined effect of the second level, the transistor T was in a conductive state. , so a more obvious electrical signal can be measured through the bit line BL. When a relatively obvious electrical signal is measured, the read data is judged to be "1". When the memory cell 10 previously stored data "0”, the potentials on the back gate 113 and the drain 106 were low. After the second level was applied to the main gate 111, the transistor was still in an off state, so the bit No electrical signal is detected on line BL, and the read data is judged to be "0" at this time.
  • the reference potential is provided to the reference potential terminal Vref.
  • the reference potential is ground potential.
  • the reading and writing method provided in this embodiment can adopt either the current detection method or the voltage detection method.
  • current detection when the memory cell 10 previously stored data “1”, the back gate 113 and the drain 106 has a higher potential, and under the combined effect of the second level, the transistor T is in a conductive state, so a relatively obvious current can be measured through the bit line BL.
  • the read data is judged to be "1”.
  • the memory cell 10 previously stored data "0” after the second level is applied to the main gate 111, the transistor T is still in the off state, so it can be considered that the bit line BL has not detected current. At this time, it is judged The data read is "0".
  • the threshold voltage of the transistor T is related to the potential on the back gate 113 and the drain 106.
  • the abscissa in FIG. 31 is the voltage applied to the main gate 111 (ie, the second level), and the ordinate is the output current of the transistor.
  • the second level applied to the main gate 111 is a certain value (the dotted line position in Figure 31)
  • the voltage on the back gate 113 and the drain 106 that is, the data written by the transistor is "1" or "0”
  • the data written by the transistor is "1" or "0”
  • Data can be read from the memory cell 10 by detecting the current on the bit line BL.
  • the value of the second level can be determined according to the parameters of the transistor and the magnitude of the voltage applied to the back gate 113 and the drain 106 during the writing operation. It should be noted that the value of the second level needs to be appropriate (it needs to be between the threshold voltage when the transistor stores “1" and the threshold voltage when the transistor stores "0").
  • the output current of the transistor when storing data "1" (that is, the potential on the drain 106 and the back gate 113 is high) is the same as when storing data "0" (that is, the potential on the drain 106 and the back gate 113 is low)
  • the output currents of the transistors will be very close in size, so it will be difficult to determine whether the read data is "0" or "1" during a read operation, which affects the performance of dynamic memory.
  • the most appropriate value of the second level can be determined through experiments or simulations to maximize the difference in output current when the transistor performs read operations in different states, thereby improving read performance.
  • the bit line BL can obtain the storage node N1 signal, and if the memory unit 10 is in the "0" state, the bit line BL can obtain the signal.
  • the storage node N1 signal cannot be obtained, that is, the data signal read by the bit line BL in the two states of "1" or "0” is very different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, which can only pass detection
  • the magnitude of the current output by the transistor T is used to determine the "1" or "0" state of the memory cell 10.
  • the current signal can be used for detection.
  • the voltage signal is detected, which facilitates the design of peripheral detection circuits according to specific needs and has better adaptability.
  • each storage unit includes a transistor and a storage capacitor, and in the storage unit, the back gate and the source form an auxiliary capacitor. , thereby increasing the capacitance of the memory cell, allowing the storage node N1 to be maintained for a longer period of time, thereby reducing the refresh frequency of the dynamic memory without adding film layers to ensure the integration of the dynamic memory.
  • the bit line In the storage unit, dynamic memory, reading and writing method and storage device provided by the embodiments of this application, during the reading process, if the storage unit is in the "1" state, the bit line can obtain the storage node signal, and the storage unit is in the "0" state. state, the bit line cannot obtain the storage node signal, that is, the data signal read by the bit line in the two states of "1" or "0” is greatly different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, which can only In terms of judging the "1" or "0" state of the memory cell by detecting the output current of the transistor, in this embodiment, since no signal is detected in the "0" state, the current signal can be used for detection. The voltage signal is detected, which facilitates the design of peripheral detection circuits according to specific needs and has better adaptability.
  • the method for manufacturing a memory unit provided by the embodiment of the present application can obtain a dynamic memory with a lower refresh frequency and a higher integration level.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted.
  • steps, measures, and solutions in the prior art with various operations, methods, and processes disclosed in this application can also be replaced, changed, rearranged, decomposed, combined, or deleted.
  • first and second are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, “plurality” means two or more.

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Abstract

Des modes de réalisation de la présente invention concernent une cellule de mémoire et un procédé de fabrication, une mémoire dynamique, un dispositif de stockage et un procédé de lecture-écriture. La cellule de mémoire comprend un transistor et un condensateur de stockage. Le transistor comprend un drain, une couche semi-conductrice et une grille principale agencés séquentiellement dans une direction s'éloignant d'un substrat, une source entourant la grille principale et située sur le côté de la couche semi-conductrice à distance de la grille principale, et une grille arrière entourant la grille principale et située sur le côté de la couche semi-conductrice à distance de la grille principale. La grille arrière est électriquement connectée au drain et est isolée de la source, et la grille arrière et la source constituent un condensateur auxiliaire. Selon le présent mode de réalisation, la densité d'intégration de la mémoire dynamique n'est pas affectée tandis que la capacité de la cellule de mémoire est augmentée pour réduire une fréquence de rafraîchissement de la mémoire dynamique. De plus, les performances anti-bruit de la mémoire dynamique sont améliorées et la conception d'un circuit de détection périphérique est facilitée.
PCT/CN2023/098853 2022-08-08 2023-06-07 Cellule de mémoire et procédé de fabrication, mémoire dynamique, dispositif de stockage et procédé de lecture-écriture WO2024032122A1 (fr)

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