WO2024032122A1 - Memory cell and fabrication method, dynamic memory, storage device, and read-write method - Google Patents

Memory cell and fabrication method, dynamic memory, storage device, and read-write method Download PDF

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Publication number
WO2024032122A1
WO2024032122A1 PCT/CN2023/098853 CN2023098853W WO2024032122A1 WO 2024032122 A1 WO2024032122 A1 WO 2024032122A1 CN 2023098853 W CN2023098853 W CN 2023098853W WO 2024032122 A1 WO2024032122 A1 WO 2024032122A1
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WIPO (PCT)
Prior art keywords
electrode
gate
substrate
layer
insulating layer
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PCT/CN2023/098853
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French (fr)
Chinese (zh)
Inventor
朱正勇
王桂磊
李辉辉
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北京超弦存储器研究院
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Publication of WO2024032122A1 publication Critical patent/WO2024032122A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4026—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using bipolar transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of storage technology. Specifically, this application relates to a storage unit and a manufacturing method, a dynamic memory, a storage device, and a reading and writing method.
  • DRAM Dynamic Random Access Memory
  • This application proposes a storage unit and a manufacturing method, a dynamic memory, a storage device, and a reading and writing method.
  • a storage unit including:
  • a storage capacitor including a first electrode, a capacitive dielectric layer and a second electrode arranged sequentially in a direction away from the substrate, the first electrode being connected to a reference potential terminal;
  • a transistor consisting of:
  • a drain electrode, a semiconductor layer and a main gate electrode are arranged in sequence in a direction away from the substrate.
  • the main gate electrode is columnar and electrically connected to the word line.
  • the main gate electrode is on the positive side of the substrate.
  • the projection is located within the orthographic projection of the first electrode on the substrate, the drain electrode is electrically connected to the second electrode, the semiconductor layer is located between the main gate electrode and the second electrode, and surrounding the main gate sidewall;
  • a source electrode surrounding the main gate and located on the side of the semiconductor layer away from the main gate, the source electrode being in contact with the semiconductor layer;
  • the memory unit further includes: a first insulating layer located on one side of the substrate and provided with a first receiving hole penetrating the first insulating layer, the first electrode, a capacitive dielectric layer and All or part of the structure of at least one of the second electrodes is located in the first receiving hole.
  • the second electrode is multiplexed as the drain, the second electrode extends on the first insulating layer, and the orthographic projection of the back gate on the substrate is in contact with the second electrode.
  • the orthographic projections of the outer contours on the substrate overlap.
  • the storage unit also includes:
  • a second gate insulating layer is located between the main gate and the semiconductor layer.
  • the memory cell further includes a third gate insulating layer; the back gate is located between the source and the drain, and the third gate insulating layer is located on the back gate between the source electrode and the back gate electrode and the semiconductor layer.
  • the back gate is in direct contact with the drain; or the memory unit further includes: a connection portion, The connecting portion connects the back gate and the drain; the connecting portion is located on the first insulating layer and directly overlaps the drain and the back gate respectively, and the connecting portion surrounds The back gate is overlapped with the back gate.
  • the storage unit also includes:
  • a first conductive layer located between the substrate and the first insulating layer and overlapping the first electrode, the first conductive layer including the reference potential terminal;
  • a second conductive layer is located on the side of the source electrode away from the substrate.
  • the second conductive layer includes a bit line, and the bit line is electrically connected to the source electrode through a via hole;
  • a third conductive layer is located on a side of the second conductive layer away from the substrate and is insulated from the second conductive layer.
  • the third conductive layer includes the word line, and the word line is connected to the word line through a via hole.
  • the main gate is electrically connected; or, the third conductive layer is located on the upper surface of the main gate and is directly connected to the main gate, the second conductive layer is located above the third conductive layer and Insulated from the third conductive layer.
  • the storage unit also includes:
  • An insulating dielectric layer located between the substrate and the first conductive layer
  • a second insulating layer located between the transistor and the second conductive layer and covering the transistor
  • a third insulating layer is located between the second conductive layer and the third conductive layer.
  • embodiments of the present application provide a dynamic memory, including a substrate, a plurality of word lines, a plurality of bit lines, a plurality of reference potential terminals and a plurality of the above-mentioned memory cells located on the substrate;
  • a plurality of the memory cells are divided into a plurality of memory unit groups, and the plurality of memory unit groups are arranged in a direction perpendicular to the substrate;
  • Each of the memory cell groups includes a plurality of memory cells arranged in an array in a direction parallel to the substrate, wherein each of the memory cells located in the same row is electrically connected to the same word line. Each memory cell in the same column is electrically connected to the same bit line.
  • embodiments of the present application provide a storage device, which includes the above-mentioned dynamic memory.
  • inventions of the present application provide a method of manufacturing a memory unit.
  • the manufacturing method includes:
  • a substrate is provided, and a plurality of reference potential terminals and a plurality of storage capacitors are formed on the substrate through a patterning process.
  • the storage capacitors include first electrodes and capacitive media arranged sequentially in a direction away from the substrate. layer and a second electrode, the first electrode being connected to the reference potential terminal;
  • a plurality of transistors are formed on the side of the storage capacitor away from the substrate through a patterning process.
  • Each transistor includes a drain electrode, a semiconductor layer and a main gate electrode arranged sequentially in a direction away from the substrate.
  • a source electrode surrounding the main gate and located on a side of the semiconductor layer away from the main gate; and a back gate surrounding the main gate and located on a side of the semiconductor layer away from the main gate, wherein , the main gate is columnar and its orthographic projection on the substrate is located within the orthographic projection of the first electrode on the substrate, the drain is electrically connected to the second electrode, and
  • a semiconductor layer is located between the main gate and the second electrode and surrounds the main gate sidewall, the source is in contact with the semiconductor layer, the back gate is electrically connected to the drain, and Insulated from the source, the back gate and the source form an auxiliary capacitor;
  • a plurality of word lines and a plurality of bit lines are formed through a patterning process, the word lines are electrically connected to the main gate, and the bit lines are electrically connected to the source.
  • multiple reference potential terminals and multiple storage capacitors are formed on the substrate through a patterning process, including:
  • the reference potential terminal is formed on one side of the substrate through a patterning process
  • a first electrode, a capacitive dielectric layer and a second electrode located in the first accommodation hole are formed through a patterning process to form the storage capacitor, wherein the first electrode overlaps the reference potential terminal.
  • the second electrode is reused as the drain electrode, and a plurality of transistors are formed on a side of the storage capacitor away from the substrate through a patterning process, including:
  • a first gate insulating layer is formed on the source unit, and a second accommodation hole is formed through the first gate insulating layer, the source unit and the sacrificial layer through a patterning process.
  • the orthographic projection of the hole on the substrate is located within the orthographic projection of the drain electrode on the substrate, wherein the source unit penetrated by the second receiving hole is the source electrode;
  • a semiconductor layer, a second gate insulating layer and a main gate are sequentially deposited in the second accommodation hole, and the semiconductor layer overlaps the drain electrode;
  • the remaining sacrificial layer is removed, and a third gate insulating layer and the back gate are formed in sequence.
  • the third gate insulating layer is located between the semiconductor layer and the back gate, and the back gate is connected to the back gate. between the source electrodes and between the back gate electrode and the drain electrode.
  • the back gate electrode is located between the drain electrode and the source electrode and surrounds the sidewalls of the main gate electrode.
  • the back gate electrode The orthographic projection of the gate electrode on the substrate overlaps the orthographic projection of the drain electrode on the substrate, and the back gate electrode is electrically connected to the drain electrode.
  • a third gate insulating layer and the back gate including:
  • Second photoresist layer on the substrate after fabricating the semiconductor layer, the first gate insulating layer and the main gate, and expose and develop the second photoresist layer. Remove the second photoresist layer located in the area to be etched, and then perform local etching using the unremoved second photoresist layer as a mask to remove part of the first gate insulating layer and part of the sacrificial layer layer so that part of the drain electrode is exposed;
  • the third gate insulating layer is attached to part of the upper surface of the drain, part of the sidewalls of the semiconductor layer, and the source.
  • the lower surface of the back gate electrode and the lower surface and side walls of the first gate insulating layer; the upper surface, lower surface of the back gate and the side surface close to the semiconductor layer are all in contact with the third gate insulating layer ;
  • connection portion is formed through a patterning process, and the connection portion surrounds the back gate and overlaps the back gate and the drain respectively.
  • connection portion after forming the connection portion, forming a plurality of transistors on a side of the storage capacitor away from the substrate through a patterning process, further comprising:
  • the upper surface of the second insulating layer is planarized.
  • embodiments of the present application provide a reading and writing method for reading and writing the above-mentioned storage unit.
  • the reading and writing method includes:
  • a first level is applied to the main gate of the memory cell to be written through the word line to turn on the transistor, and is transmitted to the source of the memory cell to be written through the bit line.
  • store signal to store the The signal is written into the storage unit to be written as storage data;
  • a second level is applied to the main gate of the memory cell to be read through the word line, so that the bit line senses the stored data of the memory cell to be read.
  • each storage unit includes a transistor and a storage capacitor, and in the storage unit, the back gate and the source form an auxiliary capacitor. , thereby increasing the capacitance of the memory unit, allowing the storage node to be maintained for a longer period of time, thus reducing the refresh frequency of the dynamic memory without adding film layers to ensure the integration of the dynamic memory.
  • the memory unit manufacturing method provided by the embodiment of the present application can obtain a memory unit with a lower refresh frequency and a higher integration level.
  • Figure 1 is a schematic circuit structure diagram of a dynamic memory provided by an embodiment of the present application.
  • Figure 2 is a schematic circuit structure diagram of a memory unit in a dynamic memory provided by an embodiment of the present application
  • Figure 3 is a schematic structural diagram of a dynamic memory provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a storage unit in a dynamic memory provided by an embodiment of the present application.
  • Figure 5 is a schematic diagram of the frame structure of a storage device provided by an embodiment of the present application.
  • Figure 6 is a schematic flowchart of a method of manufacturing a memory unit provided by an embodiment of the present application.
  • Figure 7 is a schematic flowchart of step S1 in a method for manufacturing a memory unit provided by an embodiment of the present application.
  • Figure 8 is a side view of the process flow of step S101 in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 9 is a top view of the process flow of step S101 in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 10 is a side view of the process flow of step S102 in the manufacturing method of the memory unit shown in Figure 7;
  • FIG 11 is a top view of the process flow of step S102 in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 12 is a side view of the process flow of step S103 in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 13 is a top view of the process flow of step S103 in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 14 is a side view of the memory unit after step S1 is completed in the manufacturing method of the memory unit shown in Figure 7;
  • Figure 15 is a schematic flowchart of step S2 in a method for manufacturing a memory unit provided by an embodiment of the present application;
  • Figure 16 is a side view of the process flow of step S201 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 17 is a top view of the process flow of step S201 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 18 is a side view of the process flow of step S202 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 19 is a top view of the process flow of step S202 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 20 is a side view of the process flow of step S203 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 21 is a top view of the process flow of step S203 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 22 is a schematic flowchart of step S204 in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 23 is a side view of the process flow of step S2041 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 24 is a top view of the process flow of step S2041 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 25 is a side view of the process flow of step S2042 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 26 is a top view of the process flow of step S2042 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 27 is a side view of the process flow of step S2043 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 28 is a top view of the process flow of step S2043 in the manufacturing method of the memory unit shown in Figure 22;
  • Figure 29 is a side view of the memory unit after step S2 is completed in the manufacturing method of the memory unit shown in Figure 15;
  • Figure 30 is a schematic flow chart of a reading and writing method provided by an embodiment of the present application.
  • FIG. 31 is a graph showing transfer characteristics of transistors in a memory cell when writing different data.
  • connection may include wireless connections or wireless couplings.
  • the term “and/or” used herein refers to at least one of the items defined by the term. For example, “A and/or B” can be realized as “A”, or as “B”, or as “A and B” ".
  • DRAM memory has the advantages of simpler structure, lower manufacturing cost, and higher capacity density.
  • DRAM memory usually includes multiple memory cells, and each memory cell includes transistors. Since the transistors exist across channels, Leakage phenomenon, which will cause the charge stored in the memory unit to gradually drain, so the stored data needs to be refreshed frequently to ensure the effectiveness of the stored data.
  • the storage unit and production method, dynamic memory, storage device, and reading and writing method provided by this application are intended to solve the above technical problems of the existing technology.
  • the embodiment of the present application provides a storage unit and a dynamic memory.
  • the dynamic memory provided by this embodiment includes a substrate 100, a plurality of word lines WL, a plurality of bit lines BL located on the substrate 100, a plurality of reference potential terminals Vref and a plurality of memory cells.
  • the memory unit 10 includes a storage capacitor C1 and a transistor T.
  • the storage capacitor C1 includes a first electrode 104, a capacitive dielectric layer 105 and a second electrode 106 sequentially arranged in a direction away from the substrate 100.
  • the first electrode 104 is connected to the reference potential terminal Vref.
  • the transistor T includes: a drain electrode, a semiconductor layer 109 and a main gate electrode 111 arranged in sequence in a direction away from the substrate 100, a source electrode 107 surrounding the main gate electrode 111 and located on the side of the semiconductor layer 109 away from the main gate electrode 111;
  • the back gate 113 surrounds the main gate 111 and is located on the side of the semiconductor layer 109 away from the main gate 111 .
  • the main gate 111 is columnar and is electrically connected to the word line WL.
  • the orthographic projection of the main gate 111 on the substrate 100 is located within the orthographic projection of the first electrode 104 on the substrate 100.
  • the drain is electrically connected to the second electrode 106.
  • the semiconductor layer 109 is located between the main gate 111 and the second electrode 106 and surrounds the sidewall of the main gate 111, the source 107 is in contact with the semiconductor layer 109, and the back gate 113 is electrically connected to the drain and insulated from the source 107, The back gate 113 and the source 107 form a auxiliary capacitor C2.
  • the second electrode 106 is multiplexed as a drain, the second electrode 106 extends on the first insulating layer 103 , and the front projection of the back gate 113 on the substrate 100 It overlaps with the orthographic projection of the outer contour of the second electrode 106 on the substrate 100 .
  • the second electrode in the memory cell 10 is multiplexed as a drain, both the second electrode and the drain are marked with “106”.
  • the second electrode and the drain electrode can also be provided separately and electrically connected.
  • the second electrode 106 is multiplexed as a drain electrode. This can further simplify the structure of the memory unit 10 and improve the integration of the dynamic memory.
  • auxiliary capacitor C2 is shown in FIG. 2 , in fact, the auxiliary capacitor C2 is composed of the back gate 113 of the transistor T and the source 107 of the transistor. Therefore, the memory unit 10 is not added. complexity.
  • each memory cell 10 includes a transistor T and a storage capacitor C1, and in the memory cell 10, the back gate 113 and the source 107 form an auxiliary capacitor C2, thereby increasing the number of memory cells.
  • the capacitance of 10 enables the storage node N1 to be maintained for a longer period of time, thereby reducing the refresh frequency of the dynamic memory without adding film layers to ensure the integration of the dynamic memory.
  • the bit line BL can obtain the storage node signal; if the memory unit 10 is in the "0" state, the bit line BL cannot obtain the storage node signal. , that is, the data signal read by the bit line BL in the two states of "1" or "0” is greatly different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, the current can only be output through the detection transistor T.
  • the current signal or the voltage signal can be used for detection. , which facilitates the design of peripheral detection circuits according to specific needs and has better adaptability.
  • the material of the semiconductor layer 109 includes metal oxide. Due to the inherent characteristics of metal oxide semiconductors (low electron mobility and other factors), when the material of the semiconductor layer 109 is metal oxide, the leakage current of the transistor T can be smaller and the speed of charge loss on the storage capacitor can be reduced. Therefore, the data storage time of the dynamic memory can be extended, which is beneficial to reducing the refresh frequency and power consumption of the dynamic memory.
  • the material of the metal oxide may be Indium Gallium Zinc Oxide (IGZO for short).
  • IGZO Indium Gallium Zinc Oxide
  • the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thus ensuring the working performance of the dynamic memory.
  • the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz , AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials, just ensure that the leakage current of the transistor can meet the requirements, and the details can be adjusted according to the actual situation.
  • multiple memory cells 10 are divided into multiple memory unit groups 1000 , and the multiple memory unit groups 1000 are arranged in a direction perpendicular to the substrate 100 ;
  • Each memory cell group 1000 includes a plurality of memory cells 10 arranged in an array in a direction parallel to the substrate 100.
  • Each memory cell 10 located in the same row is electrically connected to the same word line WL, and each memory cell 10 located in the same column is electrically connected.
  • Memory cell 10 is electrically connected to the same bit line BL.
  • different arrangements can be selected according to specific storage capacity requirements and space constraints on dynamic memory, that is, by adjusting the number of storage unit groups 1000 (i.e. Adjust the number of stacking levels of the dynamic memory in the Y direction), or adjust the number of storage units 10 in each storage unit group 1000 (including adjusting the number of storage units 10 in each row and/or each column) to achieve storage Optimized design of capacity and storage space.
  • the dynamic memory includes 1st to nth word lines WL, 1st to mth bit lines BL, and 1st to mth reference potential terminals Vref.
  • the memory unit 10 also includes a first insulating layer 103.
  • the first insulating layer 103 is located on one side of the substrate 100, and the first insulating layer 103 is provided with Through the first receiving hole of the first insulating layer 103, all or part of the structure of at least one of the first electrode 104, the capacitive dielectric layer 105 and the second electrode 106 is located in the first receiving hole.
  • the memory unit 10 further includes a first conductive layer 102 , a second conductive layer 116 and a third conductive layer 118 .
  • the first conductive layer 102 is located between the substrate 100 and the first insulating layer 103 and overlaps the first electrode 104.
  • the first conductive layer 102 includes a reference potential terminal Vref; the second conductive layer 116 is located in the memory unit 10 away from the substrate 100.
  • the second conductive layer 116 is located on the side of the source electrode 107 away from the substrate 100
  • the second conductive layer 116 includes a bit line BL
  • the bit line BL is electrically connected to the source electrode 107 through a via hole
  • the third The conductive layer 118 is located on a side of the second conductive layer 116 away from the substrate 100.
  • the third conductive layer 118 includes a word line WL, and the word line WL is electrically connected to the main gate 111 through a via hole.
  • the memory unit 10 further includes an insulating dielectric layer 101 , and the insulating dielectric layer 101 is located between the substrate 100 and the first conductive layer 102 .
  • the memory unit 10 further includes a second insulating layer 115 and a third insulating layer 117 .
  • the second insulating layer 115 covers the transistor T, that is, the second insulating layer 115 is located between the transistor T and the second conductive layer 116
  • the third insulating layer 117 is located between the second conductive layer 116 and the third conductive layer 118 .
  • the third conductive layer 118 can also be located on the upper surface of the main gate 111 and directly connected to the main gate 111.
  • the second conductive layer 116 is located above the third conductive layer 118 and connected to the third conductive layer 118. insulation.
  • the second conductive layer 116 is insulated from the third conductive layer 118 by disposing an insulating layer between the third conductive layer 118 and the second conductive layer 116 .
  • the structural arrangement shown in Figure 4 is that the transistor T adopts a vertical channel structure, so that the drain 106 can be positioned closer to the storage capacitor C1, and the main gate 111 and the source 107 can be positioned closer to the word line WL. and the bit line BL to facilitate the electrical connection between the drain electrode 106 and the storage capacitor C1, and the source electrode 107 and the bit line BL, and the main gate 111 and the word line WL.
  • the position design of the above-mentioned first to third conductive layers is conducive to the connection between the storage capacitor C1 and the reference potential terminal Vref, and is conducive to the connection between the transistor T and the word line WL and the bit line BL, thereby conducive to realizing the structural optimization of the dynamic memory.
  • the first insulating layer 103 forms a first receiving hole 1031 penetrating the first insulating layer 103 through a deep etching method (please refer to FIG. 10 ), and the storage capacitor C1 is formed in the first receiving hole 1031 .
  • the first electrode 104 of the storage capacitor C1 can be overlapped with the reference potential terminal Vref located under the first insulating layer 103, and the first receiving hole 1031 can be used to make the opposing area of the first electrode 104 and the second electrode 106 larger, thereby The charge storage capacity of each memory cell 10 is improved as much as possible within a limited space, thereby further reducing the refresh frequency of the dynamic memory.
  • the memory unit 10 further includes a first gate insulating layer 108 and a second gate insulating layer 110 .
  • the first gate insulating layer 108 covers the source 107; the second gate insulating layer 110 is located between the main gate 111 and the semiconductor layer 109 to insulate the main gate 111 from the semiconductor layer 109.
  • the memory unit 10 further includes a third gate insulating layer 112 , a back gate 113 is located between the source 107 and the drain 106 , and the third gate The insulating layer 112 is located between the back gate 113 and the source 107 and between the back gate 113 and the semiconductor layer 109 .
  • the third gate insulating layer 112 serves as a dielectric layer of the auxiliary capacitor C2.
  • the third gate insulating layer 112 is also located between the back gate 113 and the drain 106 .
  • the memory unit 10 further includes a connection part 114 , which connects the back gate 113 and the drain 106 .
  • the connection part 114 is located on the first insulating layer. 103 and directly overlap with the drain electrode 106 and the back gate 113 respectively.
  • the connecting portion 114 surrounds the back gate 113 and overlaps with the back gate 113 .
  • the connection portion 114 is used to overlap the drain electrode 106 and the back gate electrode 113. Since the connection portion 114 surrounds the back gate electrode 113, a sufficient connection between the drain electrode 106 and the back gate electrode 113 can be ensured.
  • the back gate 113 can also be in direct contact with the drain 106.
  • the number of film layers of the memory unit 10 is smaller, which is beneficial to simplifying the manufacturing process of the dynamic memory.
  • an embodiment of the present application provides a storage device.
  • the storage device includes the dynamic memory in the above embodiment and has the beneficial effects of the dynamic memory in the above embodiment, which will not be described again here.
  • the storage device in the embodiment of the present application may be the main memory of a computer, etc., and the specific details may be determined according to the actual situation.
  • an embodiment of the present application provides a method of manufacturing a memory unit, as shown in Figures 1-4 and 6.
  • the manufacturing method provided by this embodiment includes:
  • the storage capacitor C1 includes first electrodes 104 sequentially arranged in a direction away from the substrate 100. , the capacitive dielectric layer 105 and the second electrode 106. The first electrode 104 is connected to the reference potential terminal Vref.
  • Each transistor T includes a drain, a semiconductor layer 109 and a main gate 111 sequentially arranged in a direction away from the substrate 100 , the source electrode 107 surrounding the main gate 111 and located on the side of the semiconductor layer 109 away from the main gate 111 , and the back gate 113 surrounding the main gate 111 and located on the side of the semiconductor layer 109 away from the main gate 111 .
  • the main gate 111 is columnar and is electrically connected to the word line WL.
  • the orthographic projection of the main gate 111 on the substrate 100 is located within the orthographic projection of the first electrode 104 on the substrate 100.
  • the drain is electrically connected to the second electrode 106.
  • the semiconductor layer 109 is located between the main gate 111 and the second electrode 106 and surrounds the sidewall of the main gate 111, the source 107 is in contact with the semiconductor layer 109, and the back gate 113 is electrically connected to the drain and insulated from the source 107, The back gate 113 and the source 107 form a auxiliary capacitor C2.
  • S3 Multiple word lines WL and multiple bit lines BL are formed through a patterning process.
  • the word lines WL are electrically connected to the main gate 111, and the bit lines BL are electrically connected to the source electrode 107.
  • each memory cell group 1000 includes a plurality of memory cells 10 arranged in an array in a direction parallel to the substrate 100 , wherein each memory cell 10 located in the same row is electrically connected to the same word line WL, and each memory cell 10 located in the same column is electrically connected to the same bit line BL.
  • the manufacturing method of the memory unit provided in this embodiment is relatively simple.
  • the memory unit 10 includes a transistor T and a storage capacitor C1. Since the transistor T includes a back gate 113, the back gate 113 and the source 107 form an auxiliary capacitor C2.
  • the storage capacitor C1 and The auxiliary capacitor C2 is jointly used to store charges, which is equivalent to increasing the capacity of the storage unit 10, thus reducing the refresh frequency of the dynamic memory; and since the capacity of the storage unit 10 is not increased, the capacity of the storage unit 10 is not increased. Volume, that is, does not affect the integration of dynamic memory.
  • step S1 includes:
  • S101 Form a reference potential terminal Vref on one side of the substrate 100 through a patterning process.
  • Figure 8 is a cross-sectional view along the line A-A in Figure 9
  • first the first conductive layer 102 is formed on the substrate 100, and then the first conductive layer 102 is patterned to form a reference Potential terminal Vref.
  • the reference potential terminal Vref can be a common electrode or, of course, a reference potential line. That is, the reference potential terminal Vref can be a structure that can provide a reference potential and can be connected to one pole of the storage capacitor.
  • FIG. 8 is a cross-sectional view along the line A-A in Figure 9
  • the method for manufacturing a memory cell provided in this embodiment further includes forming an insulating dielectric layer 101 on the substrate 100 ;
  • the conductive layer 102 includes: forming a first conductive layer 102 on a side of the insulating dielectric layer 101 away from the substrate 100 .
  • S102 Deposit the first insulating layer 103 on the side of the reference potential terminal Vref away from the substrate 100, and form a plurality of The first receiving hole 1031 penetrates the first insulating layer 103 .
  • the first receiving hole 1031 exposes the reference potential terminal Vref, so that the reference potential terminal Vref can communicate with the subsequently produced storage capacitor C1.
  • An electrode 104 overlaps.
  • S103 Form the first electrode 104, the capacitive dielectric layer 105 and the second electrode 106 located in the first receiving hole 1031 through a patterning process to form the storage capacitor C1, where the first electrode 104 overlaps the reference potential terminal Vref.
  • the depth of the first accommodation hole 1031 (that is, the thickness of the first insulating layer 103) and the size of the first accommodation hole 1031 on a plane parallel to the substrate 100 have an impact on the volume of the storage capacitor C1. , that is, it has an impact on the capacitance of the storage capacitor C1. Therefore, by designing the thickness of the first insulating layer 103 and the size of the first receiving hole 1031 on a plane parallel to the substrate 100, the capacitance of the storage capacitor C1 can be adjusted. Adjustment.
  • FIG. 12 is a cross-sectional view along the line C-C in Figure 13
  • manufacturing the storage capacitor C1 in the first receiving hole 1031 not only enables the first electrode 104 of the storage capacitor C1 to be connected to the first
  • the reference potential terminal Vref under an insulating layer 103 is overlapped, and the first receiving hole 1031 is used to make the opposing area of the first electrode 104 and the second electrode 106 larger, thereby improving each memory cell 10 as much as possible in a limited space.
  • the charge storage capacity further reduces the refresh frequency of dynamic memory.
  • an insulating material needs to be deposited.
  • the insulating material covers the second electrode 106 and is also used as a part of the first insulating layer 103 ; and then the second insulating material is deposited.
  • the electrode 106 is exposed. It should be noted that in order to achieve higher precision in subsequent structures, it is necessary to ensure that the second electrode 106 has a high flatness. Therefore, chemical mechanical polishing can be used to expose the second electrode 106, thereby improving the flatness of the second electrode 106. Spend.
  • step S2 includes:
  • S201 Form a sacrificial layer 200 on the side of the second electrode 106 away from the substrate 100, and form the source unit 107' on the sacrificial layer 200 through a patterning process.
  • the sacrificial layer 200 will be etched away in subsequent processes, and the thickness of the sacrificial layer 200 determines the source electrode 107 and the drain electrode 106 Therefore, the thickness of the sacrificial layer 200 needs to be designed according to specific requirements.
  • S202 Form the first gate insulating layer 108 on the source unit 107', and form a second receiving hole 400 penetrating the first gate insulating layer 108, the source unit 107' and the sacrificial layer 200 through a patterning process.
  • the orthographic projection of the hole 400 on the substrate 100 is located within the orthographic projection of the drain electrode 106 on the substrate 100 , wherein the source unit 107 ′ penetrated by the second receiving hole 400 is the source electrode 107 .
  • step 202 specifically includes: forming a first gate insulating layer 108 on the source unit 107'; A first photoresist layer 300 is formed on the layer 108, and then the first photoresist layer 300 is exposed and developed to remove the first photoresist layer 300 located in the area to be etched; The layer 300 is used as a mask for etching to obtain the second receiving hole 400 penetrating the first gate insulating layer 108 , the source unit 107 ′ and the sacrificial layer 200 .
  • the shape of the second receiving hole 400 is designed according to the shape of the main grid 111 that needs to be formed. For example, if a cylindrical main grid 111 needs to be formed, the second receiving hole 400 will be a circular receiving hole. If a prism needs to be formed, the shape of the second receiving hole 400 will be designed.
  • the second receiving hole 400 formed by the main gate 111 is a corresponding polygonal receiving hole.
  • S203 The semiconductor layer 109, the second gate insulating layer 110 and the main gate 111 are sequentially deposited in the second accommodation hole 400, and the semiconductor layer 109 is in contact with the drain electrode 106.
  • the formed source 107 has a corresponding annular shape according to the shape of the main gate 111.
  • the main gate 111 is a cylinder.
  • the source 107 will be a four-sided ring.
  • the third gate insulating layer 112 is located between the semiconductor layer 109 and the back gate 113, and between the back gate 113 and the source. 107 and between the back gate 113 and the drain 106.
  • the back gate 113 is located on the side of the drain 106 away from the substrate 100 and between the drain 106 and the source 107.
  • the back gate 113 surrounds the main gate. 111, the orthographic projection of the back gate 113 on the substrate 100 overlaps with the orthographic projection of the drain 106 on the substrate 100, and the orthographic projection of the back gate 113 on the substrate 100 overlaps with the main gate 111 on the substrate 100.
  • the front projection on the substrate 100 has no overlap, and the back gate 113 and the drain 106 are electrically connected.
  • step S204 includes:
  • S2041 Form the second photoresist layer 500 on the substrate 100 after the semiconductor layer 109, the first gate insulating layer 108 and the main gate 111 are formed, and expose and develop the second photoresist layer 500 to remove it.
  • the second photoresist layer 500 located in the area to be etched is then partially etched using the unremoved second photoresist layer 500 as a mask to remove part of the first gate insulating layer 108 and part of the sacrificial layer 200. So that part of the drain electrode 106 is exposed.
  • Figure 23 is a G-G cross-sectional view in Figure 24
  • the edge part of the drain electrode 106 is located in the area to be etched, and the source electrode 107 has no intersection with the area to be etched.
  • the edge portion of the drain electrode 106 needs to be exposed to facilitate the subsequent electrical connection between the back gate 113 and the drain electrode 106 .
  • S2042 Remove the remaining sacrificial layer 200, and form the third gate insulating layer 112 and the back gate 113 in sequence.
  • FIGS. 25 and 26 are cross-sectional views along the line H-H in FIG. 26
  • the third gate insulating layer 112 is first formed, and then the back gate 113 is formed.
  • the third gate insulating layer 112 is attached to part of the upper surface of the drain electrode 106, part of the sidewalls of the semiconductor layer 109, the lower surface of the source electrode 107, and the lower surface and sidewalls of the first gate insulating layer 108; the back gate 113
  • the upper surface, lower surface and the side surface close to the semiconductor layer 109 are all in contact with the third gate insulating layer 112 .
  • the back gate 113 and the source 107 form an auxiliary capacitor C2
  • the third gate insulation layer 112 located between the back gate 113 and the source 107 serves as a dielectric layer of the auxiliary capacitor C2.
  • the material of the layer 112 and the thickness of the third gate insulating layer 112 can adjust the capacitance of the auxiliary capacitor C2.
  • adjusting the overlapping area of the back gate 113 and the source 107 can also adjust the capacitance of the auxiliary capacitor C2.
  • connection portion 114 is formed through a patterning process.
  • the connection portion 114 surrounds the back gate 113 and overlaps the back gate 113 and the drain electrode 106 respectively.
  • the connecting portion 114 surrounds the back gate 113 so that the connecting portion 114 and the back gate 113, and the connecting portion 114 and the drain 106 all have Larger overlap area, thereby reducing overlap resistance.
  • step S2 also includes: forming a second insulating layer 115 on the substrate 100 after the connection portion 114 is formed, and covering the second insulating layer 115 Transistor T.
  • the upper surface of the second insulating layer 115 is planarized to facilitate the subsequent production of the word line WL and the bit line BL.
  • embodiments of the present application provide a reading and writing method for reading and writing the storage unit in the above embodiment, as shown in Figures 1 to 4 and Figure 30.
  • the reading and writing method includes:
  • the first level is applied to the main gate 111 of the memory cell 10 to be written through the word line WL to turn on the transistor T, and the first level is applied to the memory cell 10 to be written through the bit line BL.
  • the source 107 transmits the storage signal to write the storage signal into the storage unit 10 to be written as storage data.
  • a first level (for example, 5V, the specific value can be adjusted according to the actual situation) is applied to the main gate 111 through the word line WL, so that the transistor is in a conducting state, and the first level
  • the size is related to the structure of the transistor, the material of the semiconductor layer 109 in the transistor and other factors, and can be adjusted according to the actual situation.
  • the transistor when the transistor is turned on, a voltage is applied to the source electrode 107 through the bit line BL, the source electrode 107 and the drain electrode 106 are connected through the semiconductor layer 109 , and a data signal is written to the storage capacitor C1 .
  • the drain 106 and the back gate 113 are electrically connected, so the voltages on the source 107 and the drain 106 are the same as the voltage on the back gate 113 . That is to say, the voltage on the back gate 113 determines the amount of charge in the storage capacitor C1, and further determines whether the binary value of the data signal stored in the memory unit 10 is 0 or 1.
  • the back gate 113 and the source 107 form the auxiliary capacitor C2
  • the charge stored in the auxiliary capacitor C2 can make the storage node N1 (ie, the back gate 113 , the drain electrode 116 and the second electrode of the storage capacitor C1) can be maintained for a longer period of time, thereby reducing the refresh frequency.
  • T2 In the read state, the second level is applied to the main gate 111 of the memory cell 10 to be read through the word line WL, so that the bit line BL senses the storage data of the memory cell 10 to be read.
  • the transistor T when the memory cell 10 previously stored data "1", the back gate 113 and the drain 106 had a higher potential, and under the combined effect of the second level, the transistor T was in a conductive state. , so a more obvious electrical signal can be measured through the bit line BL. When a relatively obvious electrical signal is measured, the read data is judged to be "1". When the memory cell 10 previously stored data "0”, the potentials on the back gate 113 and the drain 106 were low. After the second level was applied to the main gate 111, the transistor was still in an off state, so the bit No electrical signal is detected on line BL, and the read data is judged to be "0" at this time.
  • the reference potential is provided to the reference potential terminal Vref.
  • the reference potential is ground potential.
  • the reading and writing method provided in this embodiment can adopt either the current detection method or the voltage detection method.
  • current detection when the memory cell 10 previously stored data “1”, the back gate 113 and the drain 106 has a higher potential, and under the combined effect of the second level, the transistor T is in a conductive state, so a relatively obvious current can be measured through the bit line BL.
  • the read data is judged to be "1”.
  • the memory cell 10 previously stored data "0” after the second level is applied to the main gate 111, the transistor T is still in the off state, so it can be considered that the bit line BL has not detected current. At this time, it is judged The data read is "0".
  • the threshold voltage of the transistor T is related to the potential on the back gate 113 and the drain 106.
  • the abscissa in FIG. 31 is the voltage applied to the main gate 111 (ie, the second level), and the ordinate is the output current of the transistor.
  • the second level applied to the main gate 111 is a certain value (the dotted line position in Figure 31)
  • the voltage on the back gate 113 and the drain 106 that is, the data written by the transistor is "1" or "0”
  • the data written by the transistor is "1" or "0”
  • Data can be read from the memory cell 10 by detecting the current on the bit line BL.
  • the value of the second level can be determined according to the parameters of the transistor and the magnitude of the voltage applied to the back gate 113 and the drain 106 during the writing operation. It should be noted that the value of the second level needs to be appropriate (it needs to be between the threshold voltage when the transistor stores “1" and the threshold voltage when the transistor stores "0").
  • the output current of the transistor when storing data "1" (that is, the potential on the drain 106 and the back gate 113 is high) is the same as when storing data "0" (that is, the potential on the drain 106 and the back gate 113 is low)
  • the output currents of the transistors will be very close in size, so it will be difficult to determine whether the read data is "0" or "1" during a read operation, which affects the performance of dynamic memory.
  • the most appropriate value of the second level can be determined through experiments or simulations to maximize the difference in output current when the transistor performs read operations in different states, thereby improving read performance.
  • the bit line BL can obtain the storage node N1 signal, and if the memory unit 10 is in the "0" state, the bit line BL can obtain the signal.
  • the storage node N1 signal cannot be obtained, that is, the data signal read by the bit line BL in the two states of "1" or "0” is very different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, which can only pass detection
  • the magnitude of the current output by the transistor T is used to determine the "1" or "0" state of the memory cell 10.
  • the current signal can be used for detection.
  • the voltage signal is detected, which facilitates the design of peripheral detection circuits according to specific needs and has better adaptability.
  • each storage unit includes a transistor and a storage capacitor, and in the storage unit, the back gate and the source form an auxiliary capacitor. , thereby increasing the capacitance of the memory cell, allowing the storage node N1 to be maintained for a longer period of time, thereby reducing the refresh frequency of the dynamic memory without adding film layers to ensure the integration of the dynamic memory.
  • the bit line In the storage unit, dynamic memory, reading and writing method and storage device provided by the embodiments of this application, during the reading process, if the storage unit is in the "1" state, the bit line can obtain the storage node signal, and the storage unit is in the "0" state. state, the bit line cannot obtain the storage node signal, that is, the data signal read by the bit line in the two states of "1" or "0” is greatly different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, which can only In terms of judging the "1" or "0" state of the memory cell by detecting the output current of the transistor, in this embodiment, since no signal is detected in the "0" state, the current signal can be used for detection. The voltage signal is detected, which facilitates the design of peripheral detection circuits according to specific needs and has better adaptability.
  • the method for manufacturing a memory unit provided by the embodiment of the present application can obtain a dynamic memory with a lower refresh frequency and a higher integration level.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted.
  • steps, measures, and solutions in the prior art with various operations, methods, and processes disclosed in this application can also be replaced, changed, rearranged, decomposed, combined, or deleted.
  • first and second are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, “plurality” means two or more.

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Abstract

Embodiments of the present application provide a memory cell and a fabrication method, a dynamic memory, a storage device, and a read-write method. The memory cell comprises a transistor and a storage capacitor. The transistor comprises a drain, a semiconductor layer, and a main gate sequentially arranged in a direction moving away from a substrate, a source surrounding the main gate and located on the side of the semiconductor layer distant from the main gate, and a back gate surrounding the main gate and located on the side of the semiconductor layer distant from the main gate. The back gate is electrically connected to the drain and is insulated from the source, and the back gate and the source constitute an auxiliary capacitor. According to the present embodiment, the integration density of the dynamic memory is not affected while the capacitance of the memory cell is increased to reduce a refresh frequency of the dynamic memory. Moreover, the anti-noise performance of the dynamic memory is improved and the design of a peripheral detection circuit is facilitated.

Description

存储单元及制作方法、动态存储器、存储装置、读写方法Storage unit and manufacturing method, dynamic memory, storage device, reading and writing method
本申请要求于2022年08月08日提交至中国国家知识产权局、申请号为202210946208.7、发明名称为“动态存储器、其制作方法、读取方法及存储装置”的专利申请的优先权。This application requests the priority of the patent application submitted to the State Intellectual Property Office of China on August 8, 2022, with the application number 202210946208.7 and the invention title "Dynamic Memory, Its Production Method, Reading Method and Storage Device".
技术领域Technical field
本申请涉及存储技术领域，具体而言，本申请涉及一种存储单元及制作方法、动态存储器、存储装置、读写方法。This application relates to the field of storage technology. Specifically, this application relates to a storage unit and a manufacturing method, a dynamic memory, a storage device, and a reading and writing method.
背景技术Background technique
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是一种半导体存储器，和静态存储器相比，DRAM存储器具有结构较为简单、制造成本较低、容量密度较高的优点。Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared with static memory, DRAM memory has the advantages of simpler structure, lower manufacturing cost, and higher capacity density.
发明内容Contents of the invention
本申请提出一种存储单元及制作方法、动态存储器、存储装置、读写方法。This application proposes a storage unit and a manufacturing method, a dynamic memory, a storage device, and a reading and writing method.
第一个方面，本申请实施例提供了一种存储单元，包括：In a first aspect, embodiments of the present application provide a storage unit, including:
一存储电容，包括在远离衬底的方向上依次排布的第一电极、电容介质层以及第二电极，所述第一电极与参考电位端连接；A storage capacitor, including a first electrode, a capacitive dielectric layer and a second electrode arranged sequentially in a direction away from the substrate, the first electrode being connected to a reference potential terminal;
一晶体管，包括：A transistor consisting of:
在远离所述衬底的方向上依次排布的漏极、半导体层和主栅极，所述主栅极呈柱状且与字线电连接，所述主栅极在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影内，所述漏极与所述第二电极电连接，所述半导体层位于所述主栅极与所述第二电极之间且环绕所述主栅极侧壁；A drain electrode, a semiconductor layer and a main gate electrode are arranged in sequence in a direction away from the substrate. The main gate electrode is columnar and electrically connected to the word line. The main gate electrode is on the positive side of the substrate. The projection is located within the orthographic projection of the first electrode on the substrate, the drain electrode is electrically connected to the second electrode, the semiconductor layer is located between the main gate electrode and the second electrode, and surrounding the main gate sidewall;
环绕所述主栅极且位于所述半导体层远离所述主栅极一侧的源极，所述源极与所述半导体层接触；a source electrode surrounding the main gate and located on the side of the semiconductor layer away from the main gate, the source electrode being in contact with the semiconductor layer;
环绕所述主栅极且位于所述半导体层远离所述主栅极一侧的背栅极，所述背栅极与所述漏极电连接且与所述源极绝缘，所述背栅极与所述源极构成辅助电容。A back gate surrounding the main gate and located on the side of the semiconductor layer away from the main gate, the back gate is electrically connected to the drain and insulated from the source, the back gate and the source electrode form an auxiliary capacitor.
可选地，所述存储单元还包括：第一绝缘层，位于所述衬底的一侧且设置有贯穿所述第一绝缘层的第一容纳孔，所述第一电极、电容介质层以及第二电极中至少之一的全部或部分结构位于所述第一容纳孔内。Optionally, the memory unit further includes: a first insulating layer located on one side of the substrate and provided with a first receiving hole penetrating the first insulating layer, the first electrode, a capacitive dielectric layer and All or part of the structure of at least one of the second electrodes is located in the first receiving hole.
可选地，所述第二电极复用为所述漏极，所述第二电极在所述第一绝缘层上延伸，所述背栅极在衬底上的正投影与所述第二电极的外轮廓在衬底上的正投影交叠。Optionally, the second electrode is multiplexed as the drain, the second electrode extends on the first insulating layer, and the orthographic projection of the back gate on the substrate is in contact with the second electrode. The orthographic projections of the outer contours on the substrate overlap.
可选地，所述存储单元还包括：Optionally, the storage unit also includes:
第一栅极绝缘层，覆盖所述源极；a first gate insulating layer covering the source;
第二栅极绝缘层，位于所述主栅极与所述半导体层之间。A second gate insulating layer is located between the main gate and the semiconductor layer.
可选地，所述存储单元还包括第三栅极绝缘层；所述背栅极位于所述源极与所述漏极之间，且所述第三栅极绝缘层位于所述背栅极与所述源极之间以及所述背栅极与所述半导体层之间。Optionally, the memory cell further includes a third gate insulating layer; the back gate is located between the source and the drain, and the third gate insulating layer is located on the back gate between the source electrode and the back gate electrode and the semiconductor layer.
可选地，所述背栅极与所述漏极直接接触；或者所述存储单元还包括：连接部， 所述连接部连接所述背栅极和所述漏极；所述连接部位于所述第一绝缘层上并分别与所述漏极和所述背栅极直接搭接，所述连接部环绕所述背栅极并与所述背栅极搭接。Optionally, the back gate is in direct contact with the drain; or the memory unit further includes: a connection portion, The connecting portion connects the back gate and the drain; the connecting portion is located on the first insulating layer and directly overlaps the drain and the back gate respectively, and the connecting portion surrounds The back gate is overlapped with the back gate.
可选地，所述存储单元还包括：Optionally, the storage unit also includes:
第一导电层，位于所述衬底与所述第一绝缘层之间且与所述第一电极搭接，所述第一导电层包括所述参考电位端；A first conductive layer, located between the substrate and the first insulating layer and overlapping the first electrode, the first conductive layer including the reference potential terminal;
第二导电层，位于所述源极远离所述衬底的一侧，所述第二导电层包括位线，所述位线通过过孔与所述源极电连接；A second conductive layer is located on the side of the source electrode away from the substrate. The second conductive layer includes a bit line, and the bit line is electrically connected to the source electrode through a via hole;
第三导电层，位于所述第二导电层远离所述衬底的一侧且与所述第二导电层绝缘，所述第三导电层包括所述字线，所述字线通过过孔与所述主栅极电连接；或者，所述第三导电层位于所述主栅极的上表面与所述主栅极直接连接，所述第二导电层位于所述第三导电层的上方且与所述第三导电层绝缘。A third conductive layer is located on a side of the second conductive layer away from the substrate and is insulated from the second conductive layer. The third conductive layer includes the word line, and the word line is connected to the word line through a via hole. The main gate is electrically connected; or, the third conductive layer is located on the upper surface of the main gate and is directly connected to the main gate, the second conductive layer is located above the third conductive layer and Insulated from the third conductive layer.
可选地，所述存储单元还包括：Optionally, the storage unit also includes:
绝缘介质层，位于所述衬底与所述第一导电层之间；An insulating dielectric layer located between the substrate and the first conductive layer;
第二绝缘层，位于所述晶体管和所述第二导电层之间，并覆盖晶体管；a second insulating layer located between the transistor and the second conductive layer and covering the transistor;
第三绝缘层，位于所述第二导电层和所述第三导电层之间。A third insulating layer is located between the second conductive layer and the third conductive layer.
第二个方面，本申请实施例提供了一种动态存储器，包括衬底、位于所述衬底上的多条字线、多条位线、多条参考电位端和多个上述的存储单元；In a second aspect, embodiments of the present application provide a dynamic memory, including a substrate, a plurality of word lines, a plurality of bit lines, a plurality of reference potential terminals and a plurality of the above-mentioned memory cells located on the substrate;
多个所述存储单元分为多个存储单元组，多个所述存储单元组在垂直于所述衬底的方向上排布；A plurality of the memory cells are divided into a plurality of memory unit groups, and the plurality of memory unit groups are arranged in a direction perpendicular to the substrate;
每个所述存储单元组包括多个在平行于所述衬底的方向上呈阵列排布的所述存储单元，其中位于同一行的各所述存储单元与同一所述字线电连接，位于同一列的各所述存储单元与同一所述位线电连接。Each of the memory cell groups includes a plurality of memory cells arranged in an array in a direction parallel to the substrate, wherein each of the memory cells located in the same row is electrically connected to the same word line. Each memory cell in the same column is electrically connected to the same bit line.
第三个方面，本申请实施例提供了一种存储装置，该存储装置包括上述的动态存储器。In a third aspect, embodiments of the present application provide a storage device, which includes the above-mentioned dynamic memory.
第四个方面，本申请实施例提供了一种存储单元的制作方法，该制作方法包括：In a fourth aspect, embodiments of the present application provide a method of manufacturing a memory unit. The manufacturing method includes:
提供一衬底，通过构图工艺在所述衬底上形成多条参考电位端和多个存储电容，所述存储电容包括在远离所述衬底的方向上依次排布的第一电极、电容介质层以及第二电极，所述第一电极与所述参考电位端连接；A substrate is provided, and a plurality of reference potential terminals and a plurality of storage capacitors are formed on the substrate through a patterning process. The storage capacitors include first electrodes and capacitive media arranged sequentially in a direction away from the substrate. layer and a second electrode, the first electrode being connected to the reference potential terminal;
通过构图工艺在所述存储电容远离所述衬底的一侧形成多个晶体管，每个所述晶体管包括在远离所述衬底的方向上依次排布的漏极、半导体层和主栅极、环绕所述主栅极且位于所述半导体层远离所述主栅极一侧的源极以及环绕所述主栅极且位于所述半导体层远离所述主栅极一侧的背栅极，其中，所述主栅极呈柱状且在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影内，所述漏极与所述第二电极电连接，所述半导体层位于所述主栅极与所述第二电极之间且环绕所述主栅极侧壁，所述源极与所述半导体层接触，所述背栅极与所述漏极电连接且与所述源极绝缘，所述背栅极与所述源极构成辅助电容；A plurality of transistors are formed on the side of the storage capacitor away from the substrate through a patterning process. Each transistor includes a drain electrode, a semiconductor layer and a main gate electrode arranged sequentially in a direction away from the substrate. a source electrode surrounding the main gate and located on a side of the semiconductor layer away from the main gate; and a back gate surrounding the main gate and located on a side of the semiconductor layer away from the main gate, wherein , the main gate is columnar and its orthographic projection on the substrate is located within the orthographic projection of the first electrode on the substrate, the drain is electrically connected to the second electrode, and A semiconductor layer is located between the main gate and the second electrode and surrounds the main gate sidewall, the source is in contact with the semiconductor layer, the back gate is electrically connected to the drain, and Insulated from the source, the back gate and the source form an auxiliary capacitor;
通过构图工艺形成多条字线和多条位线，所述字线与所述主栅极电连接，所述位线与所述源极电连接。A plurality of word lines and a plurality of bit lines are formed through a patterning process, the word lines are electrically connected to the main gate, and the bit lines are electrically connected to the source.
可选地，通过构图工艺在所述衬底上形成多条参考电位端和多个存储电容，包括： Optionally, multiple reference potential terminals and multiple storage capacitors are formed on the substrate through a patterning process, including:
通过构图工艺在所述衬底的一侧形成所述参考电位端；The reference potential terminal is formed on one side of the substrate through a patterning process;
在所述参考电位端远离所述衬底的一侧沉积第一绝缘层，并形成多个贯穿所述第一绝缘层的第一容纳孔；Deposit a first insulating layer on the side of the reference potential end away from the substrate, and form a plurality of first receiving holes penetrating the first insulating layer;
通过构图工艺形成位于所述第一容纳孔内的第一电极、电容介质层和第二电极，以形成所述存储电容，其中所述第一电极与所述参考电位端搭接。A first electrode, a capacitive dielectric layer and a second electrode located in the first accommodation hole are formed through a patterning process to form the storage capacitor, wherein the first electrode overlaps the reference potential terminal.
可选地，所述第二电极复用为所述漏极，通过构图工艺在所述存储电容远离所述衬底的一侧形成多个晶体管，包括：Optionally, the second electrode is reused as the drain electrode, and a plurality of transistors are formed on a side of the storage capacitor away from the substrate through a patterning process, including:
在所述第二电极远离所述衬底的一侧形成牺牲层，并通过构图工艺在所述牺牲层上形成源极单元；Form a sacrificial layer on the side of the second electrode away from the substrate, and form a source unit on the sacrificial layer through a patterning process;
在所述源极单元上形成第一栅极绝缘层，通过构图工艺形成贯穿所述第一栅极绝缘层、所述源极单元和所述牺牲层的第二容纳孔，所述第二容纳孔在所述衬底上的正投影位于所述漏极在所述衬底上的正投影内，其中，被所述第二容纳孔贯穿的所述源极单元为所述源极；A first gate insulating layer is formed on the source unit, and a second accommodation hole is formed through the first gate insulating layer, the source unit and the sacrificial layer through a patterning process. The orthographic projection of the hole on the substrate is located within the orthographic projection of the drain electrode on the substrate, wherein the source unit penetrated by the second receiving hole is the source electrode;
在所述第二容纳孔内依次沉积半导体层、第二栅极绝缘层和主栅极，所述半导体层与所述漏极搭接；A semiconductor layer, a second gate insulating layer and a main gate are sequentially deposited in the second accommodation hole, and the semiconductor layer overlaps the drain electrode;
去除剩余牺牲层，并依次形成第三栅极绝缘层和所述背栅极，所述第三栅极绝缘层位于所述半导体层与所述背栅极之间、所述背栅极与所述源极之间以及所述背栅极与所述漏极之间，所述背栅极位于所述漏极与所述源极之间且包围所述主栅极的侧壁，所述背栅极在所述衬底上的正投影与所述漏极在所述衬底上的正投影交叠，所述背栅极与所述漏极电连接。The remaining sacrificial layer is removed, and a third gate insulating layer and the back gate are formed in sequence. The third gate insulating layer is located between the semiconductor layer and the back gate, and the back gate is connected to the back gate. between the source electrodes and between the back gate electrode and the drain electrode. The back gate electrode is located between the drain electrode and the source electrode and surrounds the sidewalls of the main gate electrode. The back gate electrode The orthographic projection of the gate electrode on the substrate overlaps the orthographic projection of the drain electrode on the substrate, and the back gate electrode is electrically connected to the drain electrode.
可选地，去除剩余牺牲层，并依次形成第三栅极绝缘层和所述背栅极，包括：Optionally, remove the remaining sacrificial layer, and sequentially form a third gate insulating layer and the back gate, including:
在制作完所述半导体层、所述第一栅极绝缘层和所述主栅极的所述衬底上形成第二光刻胶层，并对所述第二光刻胶层进行曝光、显影以去除位于待刻蚀区域的第二光刻胶层，再以未去除的第二光刻胶层作为掩膜进行局部刻蚀，以去除部分所述第一栅极绝缘层和部分所述牺牲层，以使部分所述漏极暴露；Form a second photoresist layer on the substrate after fabricating the semiconductor layer, the first gate insulating layer and the main gate, and expose and develop the second photoresist layer. Remove the second photoresist layer located in the area to be etched, and then perform local etching using the unremoved second photoresist layer as a mask to remove part of the first gate insulating layer and part of the sacrificial layer layer so that part of the drain electrode is exposed;
去除剩余牺牲层，并依次形成第三栅极绝缘层和背栅极，所述第三栅极绝缘层附着在所述漏极的部分上表面、所述半导体层的部分侧壁、所述源极的下表面以及所述第一栅极绝缘层的下表面和侧壁；所述背栅极的上表面、下表面以及靠近所述半导体层的侧面均与所述第三栅极绝缘层接触；Remove the remaining sacrificial layer, and form a third gate insulating layer and a back gate in sequence. The third gate insulating layer is attached to part of the upper surface of the drain, part of the sidewalls of the semiconductor layer, and the source. The lower surface of the back gate electrode and the lower surface and side walls of the first gate insulating layer; the upper surface, lower surface of the back gate and the side surface close to the semiconductor layer are all in contact with the third gate insulating layer ;
通过构图工艺形成连接部，所述连接部环绕所述背栅极且分别与所述背栅极和所述漏极搭接。A connection portion is formed through a patterning process, and the connection portion surrounds the back gate and overlaps the back gate and the drain respectively.
可选地，在形成连接部之后，通过构图工艺在所述存储电容远离所述衬底的一侧形成多个晶体管，还包括：Optionally, after forming the connection portion, forming a plurality of transistors on a side of the storage capacitor away from the substrate through a patterning process, further comprising:
在制作完所述连接部的所述衬底上形成第二绝缘层，所述第二绝缘层覆盖晶体管；forming a second insulating layer on the substrate after the connection portion is produced, and the second insulating layer covers the transistor;
对所述第二绝缘层的上表面进行平坦化处理。The upper surface of the second insulating layer is planarized.
第五个方面，本申请实施例提供了一种读写方法，用于对上述的存储单元进行读写，所述读写方法包括：In a fifth aspect, embodiments of the present application provide a reading and writing method for reading and writing the above-mentioned storage unit. The reading and writing method includes:
在写入状态时，通过所述字线向待写入的存储单元的主栅极施加第一电平以使晶体管导通，并通过位线向所述待写入的存储单元的源极传输存储信号，以将所述存储 信号写入所述待写入的存储单元作为存储数据；In the writing state, a first level is applied to the main gate of the memory cell to be written through the word line to turn on the transistor, and is transmitted to the source of the memory cell to be written through the bit line. store signal to store the The signal is written into the storage unit to be written as storage data;
在读取状态时，通过所述字线向待读取的存储单元的主栅极施加第二电平，以使所述位线感测所述待读取的存储单元的存储数据。In the read state, a second level is applied to the main gate of the memory cell to be read through the word line, so that the bit line senses the stored data of the memory cell to be read.
本申请实施例提供的技术方案带来的有益技术效果包括：The beneficial technical effects brought by the technical solutions provided by the embodiments of this application include:
1)本申请实施例提供的存储单元、动态存储器、读写方法及存储装置，每个存储单元包括一个晶体管和一个存储电容，而在该存储单元中，背栅极和源极构成一个辅助电容，从而增加存储单元的电容量，使得存储节点能够维持更长的时间，从而在无需增加膜层以保证动态存储器的集成度的同时降低了动态存储器的刷新频率。1) In the storage unit, dynamic memory, reading and writing method and storage device provided by the embodiments of this application, each storage unit includes a transistor and a storage capacitor, and in the storage unit, the back gate and the source form an auxiliary capacitor. , thereby increasing the capacitance of the memory unit, allowing the storage node to be maintained for a longer period of time, thus reducing the refresh frequency of the dynamic memory without adding film layers to ensure the integration of the dynamic memory.
2)本申请实施例提供的存储单元、动态存储器、读写方法及存储装置，在读取过程中，存储单元处于“1”状态则位线能够获取存储节点信号，存储单元处于“0”状态则位线不能获取存储节点信号，也就是“1”或“0”两种状态下位线读取的数据信号差异巨大，使得动态存储器的抗噪声性能增强；而且相对于现有技术中只能通过检测晶体管输出电流的大小来实现存储单元的“1”或“0”状态的判断，本实施例由于“0”状态下检测不到信号则既可以利用电流检测也可以利用电压信号进行检测，从而便于根据具体需求设计***检测电路，具有更好地适应性。2) In the storage unit, dynamic memory, reading and writing method and storage device provided by the embodiments of this application, during the reading process, if the storage unit is in the "1" state, the bit line can obtain the storage node signal, and the storage unit is in the "0" state. Then the bit line cannot obtain the storage node signal, that is, the data signal read by the bit line in the two states of "1" or "0" is very different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, which can only pass The size of the output current of the transistor is detected to determine the "1" or "0" state of the memory cell. In this embodiment, since no signal is detected in the "0" state, either current detection or voltage signal can be used for detection, so that It is convenient to design peripheral detection circuits according to specific needs and has better adaptability.
3)本申请实施例提供的存储单元的制作方法，获得的存储单元具有较低的刷新频率以及较高的集成度。3) The memory unit manufacturing method provided by the embodiment of the present application can obtain a memory unit with a lower refresh frequency and a higher integration level.
本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。Additional aspects and advantages of the invention will be set forth in part in the description which follows, and will be obvious from the description, or may be learned by practice of the invention.
附图说明Description of drawings
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
图1为本申请实施例提供的一种动态存储器的电路结构示意图；Figure 1 is a schematic circuit structure diagram of a dynamic memory provided by an embodiment of the present application;
图2为本申请实施例提供的一种动态存储器中的存储单元的电路结构示意图；Figure 2 is a schematic circuit structure diagram of a memory unit in a dynamic memory provided by an embodiment of the present application;
图3为本申请实施例提供的一种动态存储器的结构示意图；Figure 3 is a schematic structural diagram of a dynamic memory provided by an embodiment of the present application;
图4为本申请实施例提供的一种动态存储器中一个存储单元的结构示意图；Figure 4 is a schematic structural diagram of a storage unit in a dynamic memory provided by an embodiment of the present application;
图5为本申请实施例提供的一种存储装置的框架结构示意图；Figure 5 is a schematic diagram of the frame structure of a storage device provided by an embodiment of the present application;
图6为本申请实施例提供的一种存储单元的制作方法的流程示意图；Figure 6 is a schematic flowchart of a method of manufacturing a memory unit provided by an embodiment of the present application;
图7为本申请实施例提供的一种存储单元的制作方法中步骤S1的流程示意图；Figure 7 is a schematic flowchart of step S1 in a method for manufacturing a memory unit provided by an embodiment of the present application;
图8为图7中所示的存储单元的制作方法中步骤S101的工艺流程的侧视图；Figure 8 is a side view of the process flow of step S101 in the manufacturing method of the memory unit shown in Figure 7;
图9为图7中所示的存储单元的制作方法中步骤S101的工艺流程的俯视图；Figure 9 is a top view of the process flow of step S101 in the manufacturing method of the memory unit shown in Figure 7;
图10为图7中所示的存储单元的制作方法中步骤S102的工艺流程的侧视图；Figure 10 is a side view of the process flow of step S102 in the manufacturing method of the memory unit shown in Figure 7;
图11为图7中所示的存储单元的制作方法中步骤S102的工艺流程的俯视图；Figure 11 is a top view of the process flow of step S102 in the manufacturing method of the memory unit shown in Figure 7;
图12为图7中所示的存储单元的制作方法中步骤S103的工艺流程的侧视图；Figure 12 is a side view of the process flow of step S103 in the manufacturing method of the memory unit shown in Figure 7;
图13为图7中所示的存储单元的制作方法中步骤S103的工艺流程的俯视图；Figure 13 is a top view of the process flow of step S103 in the manufacturing method of the memory unit shown in Figure 7;
图14为图7中所示的存储单元的制作方法中完成步骤S1后的存储单元的侧视图；Figure 14 is a side view of the memory unit after step S1 is completed in the manufacturing method of the memory unit shown in Figure 7;
图15为本申请实施例提供的一种存储单元的制作方法中步骤S2的流程示意图；Figure 15 is a schematic flowchart of step S2 in a method for manufacturing a memory unit provided by an embodiment of the present application;
图16为图15中所示的存储单元的制作方法中步骤S201的工艺流程的侧视图；Figure 16 is a side view of the process flow of step S201 in the manufacturing method of the memory unit shown in Figure 15;
图17为图15中所示的存储单元的制作方法中步骤S201的工艺流程的俯视图； Figure 17 is a top view of the process flow of step S201 in the manufacturing method of the memory unit shown in Figure 15;
图18为图15中所示的存储单元的制作方法中步骤S202的工艺流程的侧视图；Figure 18 is a side view of the process flow of step S202 in the manufacturing method of the memory unit shown in Figure 15;
图19为图15中所示的存储单元的制作方法中步骤S202的工艺流程的俯视图；Figure 19 is a top view of the process flow of step S202 in the manufacturing method of the memory unit shown in Figure 15;
图20为图15中所示的存储单元的制作方法中步骤S203的工艺流程的侧视图；Figure 20 is a side view of the process flow of step S203 in the manufacturing method of the memory unit shown in Figure 15;
图21为图15中所示的存储单元的制作方法中步骤S203的工艺流程的俯视图；Figure 21 is a top view of the process flow of step S203 in the manufacturing method of the memory unit shown in Figure 15;
图22为图15中所示的存储单元的制作方法中步骤S204的流程示意图；Figure 22 is a schematic flowchart of step S204 in the manufacturing method of the memory unit shown in Figure 15;
图23为图22中所示的存储单元的制作方法中步骤S2041的工艺流程的侧视图；Figure 23 is a side view of the process flow of step S2041 in the manufacturing method of the memory unit shown in Figure 22;
图24为图22中所示的存储单元的制作方法中步骤S2041的工艺流程的俯视图；Figure 24 is a top view of the process flow of step S2041 in the manufacturing method of the memory unit shown in Figure 22;
图25为图22中所示的存储单元的制作方法中步骤S2042的工艺流程的侧视图；Figure 25 is a side view of the process flow of step S2042 in the manufacturing method of the memory unit shown in Figure 22;
图26为图22中所示的存储单元的制作方法中步骤S2042的工艺流程的俯视图；Figure 26 is a top view of the process flow of step S2042 in the manufacturing method of the memory unit shown in Figure 22;
图27为图22中所示的存储单元的制作方法中步骤S2043的工艺流程的侧视图；Figure 27 is a side view of the process flow of step S2043 in the manufacturing method of the memory unit shown in Figure 22;
图28为图22中所示的存储单元的制作方法中步骤S2043的工艺流程的俯视图；Figure 28 is a top view of the process flow of step S2043 in the manufacturing method of the memory unit shown in Figure 22;
图29为图15中所示的存储单元的制作方法中完成步骤S2后的存储单元的侧视图；Figure 29 is a side view of the memory unit after step S2 is completed in the manufacturing method of the memory unit shown in Figure 15;
图30为本申请实施例提供的一种读写方法的流程示意图；Figure 30 is a schematic flow chart of a reading and writing method provided by an embodiment of the present application;
图31为在写入不同的数据时存储单元中晶体管的转移特性曲线图。FIG. 31 is a graph showing transfer characteristics of transistors in a memory cell when writing different data.
附图标记：
10-存储单元；1000-存储单元组；100-衬底；101-绝缘介质层；102-第一导电层；
103-第一绝缘层；104-第一电极；105-电容介质层；106-第二电极(漏极)；107-源极；107′-源极单元；108-第一栅极绝缘层；109-半导体层；110-第二栅极绝缘层；111-主栅极；112-第三栅极绝缘层；113-背栅极；1031-第一通孔；114-连接部；115-第二绝缘层；116-第二导电层；WL-字线；117-第三绝缘层；118-第三导电层；BL-位线；200-牺牲层；300-第一光刻胶层；400-第二通孔；500-第二光刻胶层。Reference signs:
10-storage unit; 1000-storage unit group; 100-substrate; 101-insulating dielectric layer; 102-first conductive layer;
103-first insulating layer; 104-first electrode; 105-capacitive dielectric layer; 106-second electrode (drain); 107-source; 107'-source unit; 108-first gate insulating layer; 109-semiconductor layer; 110-second gate insulating layer; 111-main gate; 112-third gate insulating layer; 113-back gate; 1031-first through hole; 114-connection portion; 115-th Two insulating layers; 116-second conductive layer; WL-word line; 117-third insulating layer; 118-third conductive layer; BL-bit line; 200-sacrificial layer; 300-first photoresist layer; 400 - second through hole; 500 - second photoresist layer.
具体实施方式Detailed ways
下面结合本申请中的附图描述本申请的实施例。应理解，下面结合附图所阐述的实施方式，是用于解释本申请实施例的技术方案的示例性描述，对本申请实施例的技术方案不构成限制。The embodiments of the present application are described below with reference to the drawings in the present application. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not limit the technical solutions of the embodiments of the present application.
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但不排除实现为本技术领域所支持其他特征、信息、数据、步骤、操作、元件、组件和/或它们的组合等。应该理解，当我们称一个元件被“连接”或“耦接”到另一元件时，该一个元件可以直接连接或耦接到另一元件，也可以指该一个元件和另一元件通过中间元件建立连接关系。此外，这里使用的“连接”或“耦接”可以包括无线连接或无线耦接。这里使用的术语“和/或”指该术语所限定的项目中的至少一个，例如“A和/或B”可以实现为“A”，或者实现为“B”，或者实现为“A和B”。Those skilled in the art will understand that, unless expressly stated otherwise, the singular forms "a", "an", "the" and "the" used herein may also include the plural form. It should be further understood that the word "comprising" used in the description of this application refers to the presence of the described features, integers, steps, operations, elements and/or components, but does not exclude the implementation of other features, information supported by the technical field. , data, steps, operations, elements, components and/or their combinations, etc. It should be understood that when we refer to an element being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or one element and the other element may be connected to the other element through intervening elements. Establish connections. Additionally, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and/or" used herein refers to at least one of the items defined by the term. For example, "A and/or B" can be realized as "A", or as "B", or as "A and B" ".
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.
DRAM存储器具有结构较为简单、制造成本较低、容量密度较高的优点。DRAM存储器通常包括多个存储单元，每个存储单元中均包括晶体管，由于晶体管存在跨沟道 泄漏现象，这会使得存储单元中存储的电荷逐渐流失，因此存储的数据需要频繁刷新才能保证存储数据的有效性。DRAM memory has the advantages of simpler structure, lower manufacturing cost, and higher capacity density. DRAM memory usually includes multiple memory cells, and each memory cell includes transistors. Since the transistors exist across channels, Leakage phenomenon, which will cause the charge stored in the memory unit to gradually drain, so the stored data needs to be refreshed frequently to ensure the effectiveness of the stored data.
目前主流的DRAM中，为了降低刷新率，常规设计是电容需要做到足够大，这会使得DRAM的结构不紧凑、集成度较低。In current mainstream DRAM, in order to reduce the refresh rate, the conventional design requires the capacitor to be large enough, which will make the DRAM structure uncompact and low-integration.
本申请提供的存储单元及制作方法、动态存储器、存储装置、读写方法，旨在解决现有技术的如上技术问题。The storage unit and production method, dynamic memory, storage device, and reading and writing method provided by this application are intended to solve the above technical problems of the existing technology.
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。需要指出的是，下述实施方式之间可以相互参考、借鉴或结合，对于不同实施方式中相同的术语、相似的特征以及相似的实施步骤等，不再重复描述。The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. It should be noted that the following embodiments can be referred to, borrowed from, or combined with each other. The same terms, similar features, and similar implementation steps in different embodiments will not be repeatedly described.
本申请实施例提供了一种存储单元和动态存储器。如图1至图4所示，本实施例提供的动态存储器包括衬底100、位于衬底100上的多条字线WL、多条位线BL、多条参考电位端Vref和多个存储单元10。存储单元10包括一存储电容C1和一晶体管T。The embodiment of the present application provides a storage unit and a dynamic memory. As shown in Figures 1 to 4, the dynamic memory provided by this embodiment includes a substrate 100, a plurality of word lines WL, a plurality of bit lines BL located on the substrate 100, a plurality of reference potential terminals Vref and a plurality of memory cells. 10. The memory unit 10 includes a storage capacitor C1 and a transistor T.
存储电容C1包括在远离衬底100的方向上依次排布的第一电极104、电容介质层105以及第二电极106，第一电极104与参考电位端Vref连接。The storage capacitor C1 includes a first electrode 104, a capacitive dielectric layer 105 and a second electrode 106 sequentially arranged in a direction away from the substrate 100. The first electrode 104 is connected to the reference potential terminal Vref.
晶体管T包括：在远离衬底100的方向上依次排布的漏极、半导体层109和主栅极111、环绕主栅极111且位于半导体层109远离主栅极111一侧的源极107以及环绕主栅极111且位于半导体层109远离主栅极111一侧的背栅极113。主栅极111呈柱状且与字线WL电连接，主栅极111在衬底100上的正投影位于第一电极104在衬底100上的正投影内，漏极与第二电极106电连接，半导体层109位于主栅极111与第二电极106之间且环绕主栅极111侧壁，源极107与半导体层109接触，背栅极113与漏极电连接且与源极107绝缘，背栅极113与源极107构成辅助电容C2。The transistor T includes: a drain electrode, a semiconductor layer 109 and a main gate electrode 111 arranged in sequence in a direction away from the substrate 100, a source electrode 107 surrounding the main gate electrode 111 and located on the side of the semiconductor layer 109 away from the main gate electrode 111; The back gate 113 surrounds the main gate 111 and is located on the side of the semiconductor layer 109 away from the main gate 111 . The main gate 111 is columnar and is electrically connected to the word line WL. The orthographic projection of the main gate 111 on the substrate 100 is located within the orthographic projection of the first electrode 104 on the substrate 100. The drain is electrically connected to the second electrode 106. , the semiconductor layer 109 is located between the main gate 111 and the second electrode 106 and surrounds the sidewall of the main gate 111, the source 107 is in contact with the semiconductor layer 109, and the back gate 113 is electrically connected to the drain and insulated from the source 107, The back gate 113 and the source 107 form a auxiliary capacitor C2.
如图4所示，在一个可选的实施例中，第二电极106复用为漏极，第二电极106在第一绝缘层103上延伸，背栅极113在衬底100上的正投影与第二电极106的外轮廓在衬底100上的正投影交叠。如图4所示，由于存储单元10中第二电极复用为漏极，第二电极和漏极均用“106”标注。需要说明的是，第二电极和漏极也可以分开设置并进行电连接。在本实施例中，第二电极106复用为漏极。如此能够进一步简化存储单元10的结构，提升动态存储器的集成度。As shown in FIG. 4 , in an optional embodiment, the second electrode 106 is multiplexed as a drain, the second electrode 106 extends on the first insulating layer 103 , and the front projection of the back gate 113 on the substrate 100 It overlaps with the orthographic projection of the outer contour of the second electrode 106 on the substrate 100 . As shown in FIG. 4 , since the second electrode in the memory cell 10 is multiplexed as a drain, both the second electrode and the drain are marked with “106”. It should be noted that the second electrode and the drain electrode can also be provided separately and electrically connected. In this embodiment, the second electrode 106 is multiplexed as a drain electrode. This can further simplify the structure of the memory unit 10 and improve the integration of the dynamic memory.
需要说明的是，虽然图2中示出了辅助电容C2，但实际上，辅助电容C2是由晶体管T中的背栅极113与晶体管中的源极107构成的，因此并未增加存储单元10的复杂度。It should be noted that although the auxiliary capacitor C2 is shown in FIG. 2 , in fact, the auxiliary capacitor C2 is composed of the back gate 113 of the transistor T and the source 107 of the transistor. Therefore, the memory unit 10 is not added. complexity.
本实施例提供的动态存储器中，每个存储单元10包括一个晶体管T和一个存储电容C1，而在该存储单元10中，背栅极113和源极107构成一个辅助电容C2，从而增加存储单元10的电容量，使得存储节点N1能够维持更长的时间，从而在无需增加膜层以保证动态存储器的集成度的同时降低了动态存储器的刷新频率。In the dynamic memory provided by this embodiment, each memory cell 10 includes a transistor T and a storage capacitor C1, and in the memory cell 10, the back gate 113 and the source 107 form an auxiliary capacitor C2, thereby increasing the number of memory cells. The capacitance of 10 enables the storage node N1 to be maintained for a longer period of time, thereby reducing the refresh frequency of the dynamic memory without adding film layers to ensure the integration of the dynamic memory.
本实施例提供的动态存储器中，在读取过程中，存储单元10处于“1”状态则位线BL能够获取存储节点信号，存储单元10处于“0”状态则位线BL不能获取存储节点信号，也就是“1”或“0”两种状态下位线BL读取的数据信号差异巨大，使得动态存储器的抗噪声性能增强；而且相对于现有技术中只能通过检测晶体管T输出电流 的大小来实现存储单元10的“1”或“0”状态的判断而言，本实施例由于“0”状态下检测不到信号，则既可以利用电流信号进行检测也可以利用电压信号进行检测，从而便于根据具体需求设计***检测电路，具有更好地适应性。In the dynamic memory provided by this embodiment, during the reading process, if the memory unit 10 is in the "1" state, the bit line BL can obtain the storage node signal; if the memory unit 10 is in the "0" state, the bit line BL cannot obtain the storage node signal. , that is, the data signal read by the bit line BL in the two states of "1" or "0" is greatly different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, the current can only be output through the detection transistor T In order to realize the judgment of the "1" or "0" state of the memory cell 10, in this embodiment, since no signal is detected in the "0" state, either the current signal or the voltage signal can be used for detection. , which facilitates the design of peripheral detection circuits according to specific needs and has better adaptability.
可选地，如图4所示，本实施例提供的动态存储器中，半导体层109的材料包括金属氧化物。由于金属氧化物半导体的固有特性(电子迁移率较低等因素)，因此半导体层109的材料采用金属氧化物时，可以使晶体管T的漏电流较小，减小存储电容上电荷流失的速度，因此可以延长动态存储器的数据保存时间，有利于降低动态存储器的刷新频率和功耗。Optionally, as shown in FIG. 4 , in the dynamic memory provided by this embodiment, the material of the semiconductor layer 109 includes metal oxide. Due to the inherent characteristics of metal oxide semiconductors (low electron mobility and other factors), when the material of the semiconductor layer 109 is metal oxide, the leakage current of the transistor T can be smaller and the speed of charge loss on the storage capacitor can be reduced. Therefore, the data storage time of the dynamic memory can be extended, which is beneficial to reducing the refresh frequency and power consumption of the dynamic memory.
具体地，金属氧化物的材料可以为铟镓锌氧化物(Indium Gallium Zinc Oxide，简称IGZO)。当金属氧化物材料为IGZO时，晶体管的漏电流较小(漏电流小于或者等于10-15A)，由此保证了动态存储器的工作性能。需要说明的是，金属氧化物的材料也可以是ITO，IWO、ZnOx、InOx、In2O3、InWO、SnO2、TiOx、InSnOx、ZnxOyNz、MgxZnyOz、InxZnyOz、InxGayZnzOa、ZrxInyZnzOa、HfxInyZnzOa、SnxInyZnzOa、AlxSnyInzZnaOd、SixInyZnzOa、ZnxSnyOz、AlxZnySnzOa、GaxZnySnzOa、ZrxZnySnzOa、InGaSiO等材料，保证晶体管的漏电流能满足要求即可，具体可根据实际情况进行调整。Specifically, the material of the metal oxide may be Indium Gallium Zinc Oxide (IGZO for short). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thus ensuring the working performance of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz , AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials, just ensure that the leakage current of the transistor can meet the requirements, and the details can be adjusted according to the actual situation.
可选地，如图3所示，本实施例提供的动态存储器中，多个存储单元10分为多个存储单元组1000，多个存储单元组1000在垂直于衬底100的方向上排布；每个存储单元组1000包括多个在平行于衬底100的方向上呈阵列排布的存储单元10，其中位于同一行的各存储单元10与同一字线WL电连接，位于同一列的各存储单元10与同一位线BL电连接。Optionally, as shown in FIG. 3 , in the dynamic memory provided by this embodiment, multiple memory cells 10 are divided into multiple memory unit groups 1000 , and the multiple memory unit groups 1000 are arranged in a direction perpendicular to the substrate 100 ; Each memory cell group 1000 includes a plurality of memory cells 10 arranged in an array in a direction parallel to the substrate 100. Each memory cell 10 located in the same row is electrically connected to the same word line WL, and each memory cell 10 located in the same column is electrically connected. Memory cell 10 is electrically connected to the same bit line BL.
具体地，如图3所示，在实施过程中，可根据具体的存储容量的需求以及对动态存储器的空间限制，选择不同的排布方式，也就是通过调整存储单元组1000的个数(即调整动态存储器在Y方向上的堆叠级数)，或者通过调整每个存储单元组1000中存储单元10的个数(包括调整每行和/或每列中存储单元10的个数)，实现存储容量与存储空间的优化设计。Specifically, as shown in Figure 3, during the implementation process, different arrangements can be selected according to specific storage capacity requirements and space constraints on dynamic memory, that is, by adjusting the number of storage unit groups 1000 (i.e. Adjust the number of stacking levels of the dynamic memory in the Y direction), or adjust the number of storage units 10 in each storage unit group 1000 (including adjusting the number of storage units 10 in each row and/or each column) to achieve storage Optimized design of capacity and storage space.
具体的，如图1所示，该动态存储器包括第1至第n条字线WL，第1至第m条位线BL以及第1至第m条参考电位端Vref。Specifically, as shown in FIG. 1 , the dynamic memory includes 1st to nth word lines WL, 1st to mth bit lines BL, and 1st to mth reference potential terminals Vref.
可选地，如图4所示，本实施例提供的动态存储器中，存储单元10还包括第一绝缘层103，第一绝缘层103位于衬底100的一侧，第一绝缘层103设置有贯穿第一绝缘层103的第一容纳孔，第一电极104、电容介质层105以及第二电极106中至少之一的全部或部分结构位于第一容纳孔内。Optionally, as shown in Figure 4, in the dynamic memory provided by this embodiment, the memory unit 10 also includes a first insulating layer 103. The first insulating layer 103 is located on one side of the substrate 100, and the first insulating layer 103 is provided with Through the first receiving hole of the first insulating layer 103, all or part of the structure of at least one of the first electrode 104, the capacitive dielectric layer 105 and the second electrode 106 is located in the first receiving hole.
可选地，如图4所示，本实施例提供的动态存储器中，存储单元10还包括第一导电层102、第二导电层116和第三导电层118。第一导电层102位于衬底100与第一绝缘层103之间且与第一电极104搭接，第一导电层102包括参考电位端Vref；第二导电层116位于存储单元10远离衬底100的一侧(具体地，第二导电层116位于源极107远离衬底100的一侧)，第二导电层116包括位线BL，位线BL通过过孔与源极107电连接；第三导电层118位于第二导电层116远离衬底100的一侧，第三导电层118包括字线WL，字线WL通过过孔与主栅极111电连接。 Optionally, as shown in FIG. 4 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes a first conductive layer 102 , a second conductive layer 116 and a third conductive layer 118 . The first conductive layer 102 is located between the substrate 100 and the first insulating layer 103 and overlaps the first electrode 104. The first conductive layer 102 includes a reference potential terminal Vref; the second conductive layer 116 is located in the memory unit 10 away from the substrate 100. (specifically, the second conductive layer 116 is located on the side of the source electrode 107 away from the substrate 100), the second conductive layer 116 includes a bit line BL, and the bit line BL is electrically connected to the source electrode 107 through a via hole; the third The conductive layer 118 is located on a side of the second conductive layer 116 away from the substrate 100. The third conductive layer 118 includes a word line WL, and the word line WL is electrically connected to the main gate 111 through a via hole.
具体地，如图4所示，本实施例提供的动态存储器中，存储单元10还包括绝缘介质层101，绝缘介质层101位于衬底100与第一导电层102之间。Specifically, as shown in FIG. 4 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes an insulating dielectric layer 101 , and the insulating dielectric layer 101 is located between the substrate 100 and the first conductive layer 102 .
具体地，如图4所示，本实施例提供的动态存储器中，存储单元10还包括第二绝缘层115和第三绝缘层117。其中，第二绝缘层115覆盖晶体管T，即第二绝缘层115位于晶体管T和第二导电层116之间，第三绝缘层117位于第二导电层116和第三导电层118之间。Specifically, as shown in FIG. 4 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes a second insulating layer 115 and a third insulating layer 117 . The second insulating layer 115 covers the transistor T, that is, the second insulating layer 115 is located between the transistor T and the second conductive layer 116 , and the third insulating layer 117 is located between the second conductive layer 116 and the third conductive layer 118 .
需要说明的是，第三导电层118也可以位于主栅极111的上表面与主栅极111直接连接，此时第二导电层116位于第三导电层118的上方且与第三导电层118绝缘。具体地，通过在第三导电层118和第二导电层116之间设置绝缘层来实现第二导电层116与第三导电层118绝缘。It should be noted that the third conductive layer 118 can also be located on the upper surface of the main gate 111 and directly connected to the main gate 111. In this case, the second conductive layer 116 is located above the third conductive layer 118 and connected to the third conductive layer 118. insulation. Specifically, the second conductive layer 116 is insulated from the third conductive layer 118 by disposing an insulating layer between the third conductive layer 118 and the second conductive layer 116 .
具体地，如图4所示的结构设置，即晶体管T采用垂直沟道结构，从而能够使漏极106的位置更靠近存储电容C1，主栅极111和源极107的位置更靠近字线WL和位线BL，以便于漏极106与存储电容C1的电连接，以及源极107与位线BL、主栅极111与字线WL电连接。上述第一至第三导电层的位置设计有利于存储电容C1与参考电位端Vref的连接，以及有利于晶体管T与字线WL和位线BL的连接，从而有利于实现动态存储器的结构优化。Specifically, the structural arrangement shown in Figure 4 is that the transistor T adopts a vertical channel structure, so that the drain 106 can be positioned closer to the storage capacitor C1, and the main gate 111 and the source 107 can be positioned closer to the word line WL. and the bit line BL to facilitate the electrical connection between the drain electrode 106 and the storage capacitor C1, and the source electrode 107 and the bit line BL, and the main gate 111 and the word line WL. The position design of the above-mentioned first to third conductive layers is conducive to the connection between the storage capacitor C1 and the reference potential terminal Vref, and is conducive to the connection between the transistor T and the word line WL and the bit line BL, thereby conducive to realizing the structural optimization of the dynamic memory.
在本实施例中，第一绝缘层103通过深刻蚀方法形成贯穿第一绝缘层103的第一容纳孔1031(请参考图10)，并将存储电容C1形成于第一容纳孔1031内，不仅能够使存储电容C1的第一电极104与位于第一绝缘层103下的参考电位端Vref搭接，而且利用第一容纳孔1031使得第一电极104与第二电极106相对的面积更大，从而在有限的空间内尽可能提升每个存储单元10的电荷存储能力，从而进一步降低动态存储器的刷新频率。In this embodiment, the first insulating layer 103 forms a first receiving hole 1031 penetrating the first insulating layer 103 through a deep etching method (please refer to FIG. 10 ), and the storage capacitor C1 is formed in the first receiving hole 1031 . The first electrode 104 of the storage capacitor C1 can be overlapped with the reference potential terminal Vref located under the first insulating layer 103, and the first receiving hole 1031 can be used to make the opposing area of the first electrode 104 and the second electrode 106 larger, thereby The charge storage capacity of each memory cell 10 is improved as much as possible within a limited space, thereby further reducing the refresh frequency of the dynamic memory.
具体地，如图4所示，本实施例提供的动态存储器中，存储单元10还包括第一栅极绝缘层108和第二栅极绝缘层110。第一栅极绝缘层108覆盖源极107；第二栅极绝缘层110位于主栅极111与半导体层109之间以使主栅极111与半导体层109绝缘。Specifically, as shown in FIG. 4 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes a first gate insulating layer 108 and a second gate insulating layer 110 . The first gate insulating layer 108 covers the source 107; the second gate insulating layer 110 is located between the main gate 111 and the semiconductor layer 109 to insulate the main gate 111 from the semiconductor layer 109.
具体地，如图4所示，本实施例提供的动态存储器中，存储单元10还包括第三栅极绝缘层112，背栅极113位于源极107与漏极106之间，且第三栅极绝缘层112位于背栅极113与源极107之间以及背栅极113与半导体层109之间。在本实施例中，第三栅极绝缘层112作为辅助电容C2的介电层。可选地，如图4所示，本实施例中，第三栅极绝缘层112还位于背栅极113与漏极106之间。Specifically, as shown in FIG. 4 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes a third gate insulating layer 112 , a back gate 113 is located between the source 107 and the drain 106 , and the third gate The insulating layer 112 is located between the back gate 113 and the source 107 and between the back gate 113 and the semiconductor layer 109 . In this embodiment, the third gate insulating layer 112 serves as a dielectric layer of the auxiliary capacitor C2. Optionally, as shown in FIG. 4 , in this embodiment, the third gate insulating layer 112 is also located between the back gate 113 and the drain 106 .
可选地，如图4所示，本实施例提供的动态存储器中，存储单元10还包括连接部114，该连接部114连接背栅极113和漏极106，连接部114位于第一绝缘层103上并分别与漏极106和背栅极113直接搭接，连接部114环绕背栅极113并与背栅极113搭接。在本实施例中，采用连接部114对漏极106和背栅极113进行搭接，由于连接部114环绕背栅极113，能够保证漏极106和背栅极113之间的连接较为充分。Optionally, as shown in FIG. 4 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes a connection part 114 , which connects the back gate 113 and the drain 106 . The connection part 114 is located on the first insulating layer. 103 and directly overlap with the drain electrode 106 and the back gate 113 respectively. The connecting portion 114 surrounds the back gate 113 and overlaps with the back gate 113 . In this embodiment, the connection portion 114 is used to overlap the drain electrode 106 and the back gate electrode 113. Since the connection portion 114 surrounds the back gate electrode 113, a sufficient connection between the drain electrode 106 and the back gate electrode 113 can be ensured.
需要说明的是，背栅极113也可以与漏极106直接接触，此时存储单元10的膜层数量更少，有利于简化动态存储器的制作工艺。It should be noted that the back gate 113 can also be in direct contact with the drain 106. In this case, the number of film layers of the memory unit 10 is smaller, which is beneficial to simplifying the manufacturing process of the dynamic memory.
基于同一发明构思，本申请实施例提供了一种存储装置，如图5所示，该存储装 置包括上述实施例中的动态存储器，具有上述实施例中的动态存储器的有益效果，在此不再赘述。具体地，本申请实施例中的存储装置可以为计算机的主存等，具体可根据实际情况进行确定。Based on the same inventive concept, an embodiment of the present application provides a storage device. As shown in Figure 5, the storage device The device includes the dynamic memory in the above embodiment and has the beneficial effects of the dynamic memory in the above embodiment, which will not be described again here. Specifically, the storage device in the embodiment of the present application may be the main memory of a computer, etc., and the specific details may be determined according to the actual situation.
基于同一发明构思，本申请实施例提供了一种存储单元的制作方法，如图1-4以及图6所示，本实施例提供的制作方法包括：Based on the same inventive concept, an embodiment of the present application provides a method of manufacturing a memory unit, as shown in Figures 1-4 and 6. The manufacturing method provided by this embodiment includes:
S1：提供一衬底100，通过构图工艺在衬底100上形成多条参考电位端Vref和多个存储电容C1，存储电容C1包括在远离衬底100的方向上依次排布的第一电极104、电容介质层105以及第二电极106，第一电极104与参考电位端Vref连接。S1: Provide a substrate 100, and form multiple reference potential terminals Vref and multiple storage capacitors C1 on the substrate 100 through a patterning process. The storage capacitor C1 includes first electrodes 104 sequentially arranged in a direction away from the substrate 100. , the capacitive dielectric layer 105 and the second electrode 106. The first electrode 104 is connected to the reference potential terminal Vref.
S2：通过构图工艺在存储电容C1远离衬底100的一侧形成多个晶体管T，每个晶体管T包括在远离衬底100的方向上依次排布的漏极、半导体层109和主栅极111、环绕主栅极111且位于半导体层109远离主栅极111一侧的源极107以及环绕主栅极111且位于半导体层109远离主栅极111一侧的背栅极113。主栅极111呈柱状且与字线WL电连接，主栅极111在衬底100上的正投影位于第一电极104在衬底100上的正投影内，漏极与第二电极106电连接，半导体层109位于主栅极111与第二电极106之间且环绕主栅极111侧壁，源极107与半导体层109接触，背栅极113与漏极电连接且与源极107绝缘，背栅极113与源极107构成辅助电容C2。S2: Multiple transistors T are formed on the side of the storage capacitor C1 away from the substrate 100 through a patterning process. Each transistor T includes a drain, a semiconductor layer 109 and a main gate 111 sequentially arranged in a direction away from the substrate 100 , the source electrode 107 surrounding the main gate 111 and located on the side of the semiconductor layer 109 away from the main gate 111 , and the back gate 113 surrounding the main gate 111 and located on the side of the semiconductor layer 109 away from the main gate 111 . The main gate 111 is columnar and is electrically connected to the word line WL. The orthographic projection of the main gate 111 on the substrate 100 is located within the orthographic projection of the first electrode 104 on the substrate 100. The drain is electrically connected to the second electrode 106. , the semiconductor layer 109 is located between the main gate 111 and the second electrode 106 and surrounds the sidewall of the main gate 111, the source 107 is in contact with the semiconductor layer 109, and the back gate 113 is electrically connected to the drain and insulated from the source 107, The back gate 113 and the source 107 form a auxiliary capacitor C2.
S3：通过构图工艺形成多条字线WL和多条位线BL，字线WL与主栅极111电连接，位线BL与源极107电连接。S3: Multiple word lines WL and multiple bit lines BL are formed through a patterning process. The word lines WL are electrically connected to the main gate 111, and the bit lines BL are electrically connected to the source electrode 107.
具体地，重复步骤S1至步骤S3，即能够获得存储单元10，多个存储单元10分为多个存储单元组1000。如图3所示，多个存储单元组1000在垂直于衬底100的方向上排布；每个存储单元组1000包括多个在平行于衬底100的方向上呈阵列排布的存储单元10，其中位于同一行的各存储单元10与同一字线WL电连接，位于同一列的各存储单元10与同一位线BL电连接。Specifically, by repeating steps S1 to S3, the storage units 10 can be obtained, and the plurality of storage units 10 are divided into a plurality of storage unit groups 1000. As shown in FIG. 3 , multiple memory cell groups 1000 are arranged in a direction perpendicular to the substrate 100 ; each memory cell group 1000 includes a plurality of memory cells 10 arranged in an array in a direction parallel to the substrate 100 , wherein each memory cell 10 located in the same row is electrically connected to the same word line WL, and each memory cell 10 located in the same column is electrically connected to the same bit line BL.
本实施例提供的存储单元的制作方法较为简单，存储单元10包括晶体管T和存储电容C1，由于晶体管T包括背栅极113，背栅极113与源极107构成辅助电容C2，存储电容C1和辅助电容C2共同用于对电荷的存储，相当于增加了存储单元10的容量，从而降低了动态存储器的刷新频率；并且由于并未增加存储单元10的容量，因此并不会增加存储单元10的体积，也就是并不会影响动态存储器的集成度。The manufacturing method of the memory unit provided in this embodiment is relatively simple. The memory unit 10 includes a transistor T and a storage capacitor C1. Since the transistor T includes a back gate 113, the back gate 113 and the source 107 form an auxiliary capacitor C2. The storage capacitor C1 and The auxiliary capacitor C2 is jointly used to store charges, which is equivalent to increasing the capacity of the storage unit 10, thus reducing the refresh frequency of the dynamic memory; and since the capacity of the storage unit 10 is not increased, the capacity of the storage unit 10 is not increased. Volume, that is, does not affect the integration of dynamic memory.
可选地，如图7至图14所示，本实施例提供的存储单元的制作方法中，步骤S1包括：Optionally, as shown in Figures 7 to 14, in the method of manufacturing a memory unit provided in this embodiment, step S1 includes:
S101：通过构图工艺在衬底100的一侧形成参考电位端Vref。S101: Form a reference potential terminal Vref on one side of the substrate 100 through a patterning process.
具体地，如图8和图9所示(图8为图9中A-A向剖视图)，先在衬底100上形成第一导电层102，再对第一导电层102进行图形化处理以形成参考电位端Vref。参考电位端Vref可以为公共电极，当然也可以为参考电位线，也就是参考电位端Vref只要是能够提供参考电位且能够与存储电容的一极实现连接的结构即可。可选地，如图8所示，在形成第一导电层102之前，本实施例提供的存储单元的制作方法还包括在衬底100上形成绝缘介质层101；在衬底100上形成第一导电层102包括：在绝缘介质层101远离衬底100的一侧形成第一导电层102。Specifically, as shown in Figures 8 and 9 (Figure 8 is a cross-sectional view along the line A-A in Figure 9), first the first conductive layer 102 is formed on the substrate 100, and then the first conductive layer 102 is patterned to form a reference Potential terminal Vref. The reference potential terminal Vref can be a common electrode or, of course, a reference potential line. That is, the reference potential terminal Vref can be a structure that can provide a reference potential and can be connected to one pole of the storage capacitor. Optionally, as shown in FIG. 8 , before forming the first conductive layer 102 , the method for manufacturing a memory cell provided in this embodiment further includes forming an insulating dielectric layer 101 on the substrate 100 ; The conductive layer 102 includes: forming a first conductive layer 102 on a side of the insulating dielectric layer 101 away from the substrate 100 .
S102：在参考电位端Vref远离衬底100的一侧沉积第一绝缘层103，并形成多个 贯穿第一绝缘层103的第一容纳孔1031。S102: Deposit the first insulating layer 103 on the side of the reference potential terminal Vref away from the substrate 100, and form a plurality of The first receiving hole 1031 penetrates the first insulating layer 103 .
具体地，如图10和图11所示(图10为图11中B-B向剖视图)，第一容纳孔1031使得参考电位端Vref暴露，以便于参考电位端Vref与后续制作的存储电容C1的第一电极104搭接。Specifically, as shown in Figures 10 and 11 (Figure 10 is a cross-sectional view along the line B-B in Figure 11), the first receiving hole 1031 exposes the reference potential terminal Vref, so that the reference potential terminal Vref can communicate with the subsequently produced storage capacitor C1. An electrode 104 overlaps.
S103：通过构图工艺形成位于第一容纳孔1031内的第一电极104、电容介质层105和第二电极106，以形成存储电容C1，其中第一电极104与参考电位端Vref搭接。S103: Form the first electrode 104, the capacitive dielectric layer 105 and the second electrode 106 located in the first receiving hole 1031 through a patterning process to form the storage capacitor C1, where the first electrode 104 overlaps the reference potential terminal Vref.
需要说明的是，第一容纳孔1031的深度(即第一绝缘层103的厚度)以及第一容纳孔1031在平行于衬底100的平面上的尺寸，对存储电容C1的体积均有所影响，也就是对存储电容C1的电容量有影响，因此通过设计第一绝缘层103的厚度以及第一容纳孔1031在平行于衬底100的平面上的尺寸，能够对存储电容C1的电容量进行调整。It should be noted that the depth of the first accommodation hole 1031 (that is, the thickness of the first insulating layer 103) and the size of the first accommodation hole 1031 on a plane parallel to the substrate 100 have an impact on the volume of the storage capacitor C1. , that is, it has an impact on the capacitance of the storage capacitor C1. Therefore, by designing the thickness of the first insulating layer 103 and the size of the first receiving hole 1031 on a plane parallel to the substrate 100, the capacitance of the storage capacitor C1 can be adjusted. Adjustment.
具体地，如图12和图13所示(图12为图13中C-C向剖视图)，将存储电容C1制作在第一容纳孔1031内，不仅能够使存储电容C1的第一电极104与位于第一绝缘层103下的参考电位端Vref搭接，而且利用第一容纳孔1031使得第一电极104与第二电极106相对的面积更大，从而在有限的空间内尽可能提升每个存储单元10的电荷存储能力，从而进一步降低动态存储器的刷新频率。Specifically, as shown in Figures 12 and 13 (Figure 12 is a cross-sectional view along the line C-C in Figure 13), manufacturing the storage capacitor C1 in the first receiving hole 1031 not only enables the first electrode 104 of the storage capacitor C1 to be connected to the first The reference potential terminal Vref under an insulating layer 103 is overlapped, and the first receiving hole 1031 is used to make the opposing area of the first electrode 104 and the second electrode 106 larger, thereby improving each memory cell 10 as much as possible in a limited space. The charge storage capacity further reduces the refresh frequency of dynamic memory.
具体地，如图14所示，在制作完存储电容C1之后，还需要沉积绝缘材料，该绝缘材料覆盖第二电极106且该绝缘材料也作为第一绝缘层103的一部分；之后再使得第二电极106暴露即可。需要说明的是，为了使得后续结构具有更高精度，需要保证第二电极106具有较高的平整度，因此可以采用化学机械抛光的方式使得第二电极106暴露，从而提高第二电极106的平整度。Specifically, as shown in FIG. 14 , after the storage capacitor C1 is fabricated, an insulating material needs to be deposited. The insulating material covers the second electrode 106 and is also used as a part of the first insulating layer 103 ; and then the second insulating material is deposited. The electrode 106 is exposed. It should be noted that in order to achieve higher precision in subsequent structures, it is necessary to ensure that the second electrode 106 has a high flatness. Therefore, chemical mechanical polishing can be used to expose the second electrode 106, thereby improving the flatness of the second electrode 106. Spend.
可选地，如图15至图21所示，本实施例提供的存储单元的制作方法中，步骤S2包括：Optionally, as shown in Figures 15 to 21, in the method of manufacturing a memory unit provided in this embodiment, step S2 includes:
S201：在第二电极106远离衬底100的一侧形成牺牲层200，并通过构图工艺在牺牲层200上形成源极单元107′。S201: Form a sacrificial layer 200 on the side of the second electrode 106 away from the substrate 100, and form the source unit 107' on the sacrificial layer 200 through a patterning process.
具体地，如图16和图17所示(图16为图17中D-D向剖视图)，牺牲层200在后续制程中会被刻蚀掉，牺牲层200的厚度决定着源极107与漏极106之间的距离，因此，需要根据具体的需求设计牺牲层200的厚度。Specifically, as shown in Figures 16 and 17 (Figure 16 is a D-D cross-sectional view in Figure 17), the sacrificial layer 200 will be etched away in subsequent processes, and the thickness of the sacrificial layer 200 determines the source electrode 107 and the drain electrode 106 Therefore, the thickness of the sacrificial layer 200 needs to be designed according to specific requirements.
S202：在源极单元107′上形成第一栅极绝缘层108，通过构图工艺形成贯穿第一栅极绝缘层108、源极单元107′和牺牲层200的第二容纳孔400，第二容纳孔400在衬底100上的正投影位于漏极106在衬底100上的正投影内，其中，被第二容纳孔400贯穿的源极单元107′为源极107。S202: Form the first gate insulating layer 108 on the source unit 107', and form a second receiving hole 400 penetrating the first gate insulating layer 108, the source unit 107' and the sacrificial layer 200 through a patterning process. The orthographic projection of the hole 400 on the substrate 100 is located within the orthographic projection of the drain electrode 106 on the substrate 100 , wherein the source unit 107 ′ penetrated by the second receiving hole 400 is the source electrode 107 .
具体地，如图18和图19所示(图18为图19中E-E向剖视图)，步骤202具体包括：在源极单元107′上形成第一栅极绝缘层108；在第一栅极绝缘层108上形成第一光刻胶层300，再对第一光刻胶层300进行曝光、显影以去除位于待刻蚀区域的第一光刻胶层300；以未去除的第一光刻胶层300作为掩膜进行刻蚀从而获得贯穿第一栅极绝缘层108、源极单元107′和牺牲层200的第二容纳孔400。Specifically, as shown in Figures 18 and 19 (Figure 18 is a cross-sectional view along E-E in Figure 19), step 202 specifically includes: forming a first gate insulating layer 108 on the source unit 107'; A first photoresist layer 300 is formed on the layer 108, and then the first photoresist layer 300 is exposed and developed to remove the first photoresist layer 300 located in the area to be etched; The layer 300 is used as a mask for etching to obtain the second receiving hole 400 penetrating the first gate insulating layer 108 , the source unit 107 ′ and the sacrificial layer 200 .
第二容纳孔400的形状根据需要形成的主栅极111的形状进行设计，例如，若需要形成圆柱形的主栅极111则形成的第二容纳孔400为圆形容纳孔，若需要形成棱柱 形的主栅极111则形成的第二容纳孔400为相应的多边形容纳孔。The shape of the second receiving hole 400 is designed according to the shape of the main grid 111 that needs to be formed. For example, if a cylindrical main grid 111 needs to be formed, the second receiving hole 400 will be a circular receiving hole. If a prism needs to be formed, the shape of the second receiving hole 400 will be designed. The second receiving hole 400 formed by the main gate 111 is a corresponding polygonal receiving hole.
S203：在第二容纳孔400内依次沉积半导体层109、第二栅极绝缘层110和主栅极111，半导体层109与漏极106接触。S203: The semiconductor layer 109, the second gate insulating layer 110 and the main gate 111 are sequentially deposited in the second accommodation hole 400, and the semiconductor layer 109 is in contact with the drain electrode 106.
具体地，如图20和图21所示(图20为图21中F-F向剖视图)，形成的源极107依据主栅极111的形状而呈现相应的环形，例如，若主栅极111为圆柱形则源极107为圆环形，若主栅极111为四棱柱形则源极107为四边环形。Specifically, as shown in FIGS. 20 and 21 (FIG. 20 is a cross-sectional view along the F-F direction in FIG. 21), the formed source 107 has a corresponding annular shape according to the shape of the main gate 111. For example, if the main gate 111 is a cylinder. If the main gate 111 is a square prism, the source 107 will be a four-sided ring.
S204：去除剩余牺牲层200，并依次形成第三栅极绝缘层112和背栅极113，第三栅极绝缘层112位于半导体层109与背栅极113之间、背栅极113与源极107之间以及背栅极113与漏极106之间，背栅极113位于漏极106远离衬底100的一侧且位于漏极106与源极107之间，背栅极113包围主栅极111的侧壁，背栅极113在衬底100上的正投影与漏极106在衬底100上的正投影交叠，背栅极113在衬底100上的正投影与主栅极111在衬底100上的正投影无交叠，背栅极113与漏极106电连接。S204: Remove the remaining sacrificial layer 200, and sequentially form the third gate insulating layer 112 and the back gate 113. The third gate insulating layer 112 is located between the semiconductor layer 109 and the back gate 113, and between the back gate 113 and the source. 107 and between the back gate 113 and the drain 106. The back gate 113 is located on the side of the drain 106 away from the substrate 100 and between the drain 106 and the source 107. The back gate 113 surrounds the main gate. 111, the orthographic projection of the back gate 113 on the substrate 100 overlaps with the orthographic projection of the drain 106 on the substrate 100, and the orthographic projection of the back gate 113 on the substrate 100 overlaps with the main gate 111 on the substrate 100. The front projection on the substrate 100 has no overlap, and the back gate 113 and the drain 106 are electrically connected.
进一步地，如图22至图29所示，在本实施例提供的存储单元的制作方法中，步骤S204包括：Further, as shown in Figures 22 to 29, in the method of manufacturing a memory unit provided in this embodiment, step S204 includes:
S2041：在制作完半导体层109、第一栅极绝缘层108和主栅极111的衬底100上形成第二光刻胶层500，并对第二光刻胶层500进行曝光、显影以去除位于待刻蚀区域的第二光刻胶层500，再以未去除的第二光刻胶层500作为掩膜进行局部刻蚀，以去除部分第一栅极绝缘层108和部分牺牲层200，以使部分漏极106暴露。S2041: Form the second photoresist layer 500 on the substrate 100 after the semiconductor layer 109, the first gate insulating layer 108 and the main gate 111 are formed, and expose and develop the second photoresist layer 500 to remove it. The second photoresist layer 500 located in the area to be etched is then partially etched using the unremoved second photoresist layer 500 as a mask to remove part of the first gate insulating layer 108 and part of the sacrificial layer 200. So that part of the drain electrode 106 is exposed.
具体地，如图23和图24所示(图23为图24中G-G向剖视图)，漏极106的边缘部分位于待刻蚀区域内，源极107与待刻蚀区域无交集，经过步骤S2041之后需要将漏极106的边缘部分暴露，以便于后续背栅极113与漏极106的电连接。Specifically, as shown in Figures 23 and 24 (Figure 23 is a G-G cross-sectional view in Figure 24), the edge part of the drain electrode 106 is located in the area to be etched, and the source electrode 107 has no intersection with the area to be etched. After step S2041 Afterwards, the edge portion of the drain electrode 106 needs to be exposed to facilitate the subsequent electrical connection between the back gate 113 and the drain electrode 106 .
S2042：去除剩余牺牲层200，并依次形成第三栅极绝缘层112和背栅极113。S2042: Remove the remaining sacrificial layer 200, and form the third gate insulating layer 112 and the back gate 113 in sequence.
具体地，如图25和图26所示(图25为图26中H-H向剖视图)，剩余的牺牲层200去除之后先形成第三栅极绝缘层112，再形成背栅极113。第三栅极绝缘层112附着在漏极106的部分上表面、半导体层109的部分侧壁、源极107的下表面以及第一栅极绝缘层108的下表面和侧壁；背栅极113的上表面、下表面以及靠近半导体层109的侧面均与第三栅极绝缘层112接触。其中，背栅极113与源极107形成辅助电容C2，位于背栅极113和源极107之间的第三栅极绝缘层112作为辅助电容C2的介电层，通过调节第三栅极绝缘层112的材料以及第三栅极绝缘层112的厚度，能够调节辅助电容C2的电容量。或者调节背栅极113与源极107的交叠面积也能够调节辅助电容C2的电容量。Specifically, as shown in FIGS. 25 and 26 (FIG. 25 is a cross-sectional view along the line H-H in FIG. 26), after the remaining sacrificial layer 200 is removed, the third gate insulating layer 112 is first formed, and then the back gate 113 is formed. The third gate insulating layer 112 is attached to part of the upper surface of the drain electrode 106, part of the sidewalls of the semiconductor layer 109, the lower surface of the source electrode 107, and the lower surface and sidewalls of the first gate insulating layer 108; the back gate 113 The upper surface, lower surface and the side surface close to the semiconductor layer 109 are all in contact with the third gate insulating layer 112 . Among them, the back gate 113 and the source 107 form an auxiliary capacitor C2, and the third gate insulation layer 112 located between the back gate 113 and the source 107 serves as a dielectric layer of the auxiliary capacitor C2. By adjusting the third gate insulation The material of the layer 112 and the thickness of the third gate insulating layer 112 can adjust the capacitance of the auxiliary capacitor C2. Alternatively, adjusting the overlapping area of the back gate 113 and the source 107 can also adjust the capacitance of the auxiliary capacitor C2.
S2043：通过构图工艺形成连接部114，连接部114环绕背栅极113且分别与背栅极113和漏极106搭接。S2043: The connection portion 114 is formed through a patterning process. The connection portion 114 surrounds the back gate 113 and overlaps the back gate 113 and the drain electrode 106 respectively.
具体地，如图27和图28所示(图27为图28中I-I向剖视图)，连接部114环绕背栅极113使得连接部114与背栅极113、连接部114与漏极106均具有较大的搭接面积，从而降低搭接电阻。Specifically, as shown in FIGS. 27 and 28 (FIG. 27 is a cross-sectional view along the line I-I in FIG. 28), the connecting portion 114 surrounds the back gate 113 so that the connecting portion 114 and the back gate 113, and the connecting portion 114 and the drain 106 all have Larger overlap area, thereby reducing overlap resistance.
进一步地，如图29所示，本实施例提供的存储单元的制作方法中，步骤S2还包括：在制作完连接部114的衬底100上形成第二绝缘层115，第二绝缘层115覆盖晶体管T。 Further, as shown in FIG. 29 , in the method of manufacturing a memory unit provided by this embodiment, step S2 also includes: forming a second insulating layer 115 on the substrate 100 after the connection portion 114 is formed, and covering the second insulating layer 115 Transistor T.
具体地，第二绝缘层115的上表面进行平坦化处理以便于后续字线WL和位线BL的制作。Specifically, the upper surface of the second insulating layer 115 is planarized to facilitate the subsequent production of the word line WL and the bit line BL.
基于同一发明构思，本申请实施例提供了一种读写方法，用于对上述实施例中的存储单元进行读写，如图1至图4以及图30所示，该读写方法包括：Based on the same inventive concept, embodiments of the present application provide a reading and writing method for reading and writing the storage unit in the above embodiment, as shown in Figures 1 to 4 and Figure 30. The reading and writing method includes:
T1：在写入状态时，通过字线WL向待写入的存储单元10的主栅极111施加第一电平以使晶体管T导通，并通过位线BL向待写入的存储单元10的源极107传输存储信号，以将存储信号写入待写入的存储单元10作为存储数据。T1: In the writing state, the first level is applied to the main gate 111 of the memory cell 10 to be written through the word line WL to turn on the transistor T, and the first level is applied to the memory cell 10 to be written through the bit line BL. The source 107 transmits the storage signal to write the storage signal into the storage unit 10 to be written as storage data.
在动态存储器处于写入工作模式时，通过字线WL向主栅极111施加第一电平(例如5V，具体数值可根据实际情况进行调整)，以使晶体管处于导通状态，第一电平的大小与晶体管的结构、晶体管中半导体层109的材料等因素相关，具体可根据实际情况进行调整。When the dynamic memory is in the write operation mode, a first level (for example, 5V, the specific value can be adjusted according to the actual situation) is applied to the main gate 111 through the word line WL, so that the transistor is in a conducting state, and the first level The size is related to the structure of the transistor, the material of the semiconductor layer 109 in the transistor and other factors, and can be adjusted according to the actual situation.
如图1至图4所示，当晶体管导通时，通过位线BL向源极107施加电压，源极107和漏极106通过半导体层109导通，向存储电容C1写入数据信号。并且当晶体管T导通时，漏极106和背栅极113电连接，因此源极107、漏极106上电压的大小和背栅极113上电压的大小相同。也就是背栅极113上的电压的大小决定了存储电容C1中的电荷量的大小，进而决定了存储单元10中所存储的数据信号的二进制是0还是1。当通过位线BL向源极107施加高电压(例如5V时)时，数据“1”被写入存储单元10，当通过位线BL向源极107施加低电压(例如0V)时，数据“0”被写入存储单元10。As shown in FIGS. 1 to 4 , when the transistor is turned on, a voltage is applied to the source electrode 107 through the bit line BL, the source electrode 107 and the drain electrode 106 are connected through the semiconductor layer 109 , and a data signal is written to the storage capacitor C1 . And when the transistor T is turned on, the drain 106 and the back gate 113 are electrically connected, so the voltages on the source 107 and the drain 106 are the same as the voltage on the back gate 113 . That is to say, the voltage on the back gate 113 determines the amount of charge in the storage capacitor C1, and further determines whether the binary value of the data signal stored in the memory unit 10 is 0 or 1. When a high voltage (for example, 5V) is applied to the source electrode 107 through the bit line BL, data "1" is written into the memory cell 10. When a low voltage (for example, 0V) is applied to the source electrode 107 through the bit line BL, the data "1" 0” is written to memory cell 10.
由于背栅极113与源极107构成辅助电容C2，因此，即使在完成数据写入之后晶体管T转变为关断状态，辅助电容C2中存储的电荷也能够使得存储节点N1(即背栅极113、漏极116以及存储电容C1的第二电极)的电位能够维持更长的时间，从而降低刷新频率。Since the back gate 113 and the source 107 form the auxiliary capacitor C2, even if the transistor T transitions to the off state after completing the data writing, the charge stored in the auxiliary capacitor C2 can make the storage node N1 (ie, the back gate 113 , the drain electrode 116 and the second electrode of the storage capacitor C1) can be maintained for a longer period of time, thereby reducing the refresh frequency.
T2：在读取状态时，通过字线WL向待读取的存储单元10的主栅极111施加第二电平，以使位线BL感测待读取的存储单元10的存储数据。T2: In the read state, the second level is applied to the main gate 111 of the memory cell 10 to be read through the word line WL, so that the bit line BL senses the storage data of the memory cell 10 to be read.
如图1至图4所示，在数据读取时，对主栅极111施加第二电平，若该存储单元10处于“1”状态，则主栅极111在第二电平(例如主栅极电位VG＝0.3V，此时源极电位VS＝0)下打开，能够获取存储节点N1的信号；若该存储单元10处于“0”状态，则在相同的栅极和源极偏置下晶体管T未导通，即无法检测到存储节点的信号。As shown in FIGS. 1 to 4 , when data is read, a second level is applied to the main gate 111 . If the memory cell 10 is in the “1” state, the main gate 111 is at the second level (for example, the main gate 111 ). The gate potential VG=0.3V, at this time the source potential VS=0) is turned on, and the signal of the storage node N1 can be obtained; if the memory cell 10 is in the "0" state, then the same gate and source bias The lower transistor T is not turned on, that is, the signal from the storage node cannot be detected.
具体的，当存储单元10之前存储的是数据“1”时，背栅极113和漏极106上具有一较高的电位，在第二电平的共同作用下，晶体管T处于导通的状态，因此可通过位线BL测得较为明显的电信号。当测得较为明显的电信号时，判断读取的数据为“1”。当存储单元10之前存储的是数据“0”时，背栅极113和漏极106上的电位较低，主栅极111上施加第二电平后，晶体管仍处于关断的状态，因此位线BL并未检测到电信号，此时判断读取的数据为“0”。Specifically, when the memory cell 10 previously stored data "1", the back gate 113 and the drain 106 had a higher potential, and under the combined effect of the second level, the transistor T was in a conductive state. , so a more obvious electrical signal can be measured through the bit line BL. When a relatively obvious electrical signal is measured, the read data is judged to be "1". When the memory cell 10 previously stored data "0", the potentials on the back gate 113 and the drain 106 were low. After the second level was applied to the main gate 111, the transistor was still in an off state, so the bit No electrical signal is detected on line BL, and the read data is judged to be "0" at this time.
需要说明的是，在存储单元的读写过程中，均向参考电位端Vref提供参考电位。在一个具体的实施例中，参考电位为地电位。It should be noted that during the reading and writing process of the memory cell, the reference potential is provided to the reference potential terminal Vref. In a specific embodiment, the reference potential is ground potential.
本实施例提供的读写方法，既可以采用电流检测方式也可以采用电压检测方式。以电流检测为例，当存储单元10之前存储的是数据“1”时，背栅极113和漏极106 上具有一较高的电位，在第二电平的共同作用下，晶体管T处于导通的状态，因此可通过位线BL测得较为明显的电流。当测得较为明显的电流时，判断读取的数据为“1”。当存储单元10之前存储的是数据“0”时，主栅极111上施加第二电平后，晶体管T仍处于关断的状态，因此可以认为位线BL并未检测到电流，此时判断读取的数据为“0”。The reading and writing method provided in this embodiment can adopt either the current detection method or the voltage detection method. Taking current detection as an example, when the memory cell 10 previously stored data “1”, the back gate 113 and the drain 106 has a higher potential, and under the combined effect of the second level, the transistor T is in a conductive state, so a relatively obvious current can be measured through the bit line BL. When a relatively obvious current is measured, the read data is judged to be "1". When the memory cell 10 previously stored data "0", after the second level is applied to the main gate 111, the transistor T is still in the off state, so it can be considered that the bit line BL has not detected current. At this time, it is judged The data read is "0".
需要说明的是，晶体管T的阈值电压的大小和背栅极113以及漏极106上电位的大小相关，对于N型场效应晶体管(晶体管导通时载流子为电子)，背栅极113以及漏极106上的电位越高，阈值电压越小，即主栅极111和源极107之间的压差较小时，晶体管T也能被导通；背栅极113以及漏极106上的电位越低，阈值电压越大。It should be noted that the threshold voltage of the transistor T is related to the potential on the back gate 113 and the drain 106. For an N-type field effect transistor (carriers are electrons when the transistor is turned on), the back gate 113 and The higher the potential on the drain 106, the smaller the threshold voltage, that is, when the voltage difference between the main gate 111 and the source 107 is small, the transistor T can also be turned on; the potential on the back gate 113 and the drain 106 The lower it is, the greater the threshold voltage is.
如图31所示，图31中的横坐标为施加在主栅极111上的电压(即第二电平)，纵坐标为晶体管的输出电流。当施加在主栅极111上的第二电平为某一特定值(图31中虚线位置)时，背栅极113和漏极106上电压的高低(即晶体管写入的数据是“1”还是“0”)会使晶体管的输出电流(即通过位线BL所测的电流)的大小具有显著的差别。通过检测位线BL上电流即可实现将数据从存储单元10中读出，当晶体管写入数据“1”时，晶体管的输出电流较大，因此读取的数据也是“1”；当晶体管写入数据“0”时，晶体管的输出电流极为微弱，因此读取的数据也是“0”。As shown in FIG. 31 , the abscissa in FIG. 31 is the voltage applied to the main gate 111 (ie, the second level), and the ordinate is the output current of the transistor. When the second level applied to the main gate 111 is a certain value (the dotted line position in Figure 31), the voltage on the back gate 113 and the drain 106 (that is, the data written by the transistor is "1" or "0") will make a significant difference in the size of the output current of the transistor (that is, the current measured through the bit line BL). Data can be read from the memory cell 10 by detecting the current on the bit line BL. When the transistor writes the data "1", the output current of the transistor is large, so the read data is also "1"; when the transistor writes the data "1" When data "0" is entered, the output current of the transistor is extremely weak, so the data read is also "0".
第二电平的数值可根据晶体管的参数以及在进行写操作时施加给背栅极113和漏极106上电压的大小确定。需要说明的是，第二电平的数值需要是合适的(需要位于晶体管存储“1”时的阈值电压与晶体管存储“0”时的阈值电压之间)，若第二电平的数值不合适，存储数据“1”(即漏极106和背栅极113上的电位较高)时晶体管的输出电流与存储数据“0”(即漏极106和背栅极113上的电位较低)时晶体管的输出电流的大小会非常接近，因此在进行读取操作时会难以判断所读取的数据是“0”还是“1”，这对于动态存储器的性能造成了影响。可通过实验或者模拟的方法确定最合适的第二电平的值，以使晶体管在不同的状态下进行读操作时输出电流的差异最大，以提高读取性能。The value of the second level can be determined according to the parameters of the transistor and the magnitude of the voltage applied to the back gate 113 and the drain 106 during the writing operation. It should be noted that the value of the second level needs to be appropriate (it needs to be between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0"). If the value of the second level is inappropriate, , the output current of the transistor when storing data "1" (that is, the potential on the drain 106 and the back gate 113 is high) is the same as when storing data "0" (that is, the potential on the drain 106 and the back gate 113 is low) The output currents of the transistors will be very close in size, so it will be difficult to determine whether the read data is "0" or "1" during a read operation, which affects the performance of dynamic memory. The most appropriate value of the second level can be determined through experiments or simulations to maximize the difference in output current when the transistor performs read operations in different states, thereby improving read performance.
通过上述说明可知，本实施例提供的存储单元，在读取过程中，存储单元10处于“1”状态则位线BL能够获取存储节点N1信号，存储单元10处于“0”状态则位线BL不能获取存储节点N1信号，也就是“1”或“0”两种状态下位线BL读取的数据信号差异巨大，使得动态存储器的抗噪声性能增强；而且相对于现有技术中只能通过检测晶体管T输出电流的大小来实现存储单元10的“1”或“0”状态的判断而言，本实施例由于“0”状态下检测不到信号，则既可以利用电流信号进行检测也可以利用电压信号进行检测，从而便于根据具体需求设计***检测电路，具有更好地适应性。It can be seen from the above description that in the memory unit provided by this embodiment, during the reading process, if the memory unit 10 is in the "1" state, the bit line BL can obtain the storage node N1 signal, and if the memory unit 10 is in the "0" state, the bit line BL can obtain the signal. The storage node N1 signal cannot be obtained, that is, the data signal read by the bit line BL in the two states of "1" or "0" is very different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, which can only pass detection The magnitude of the current output by the transistor T is used to determine the "1" or "0" state of the memory cell 10. In this embodiment, since no signal is detected in the "0" state, the current signal can be used for detection. The voltage signal is detected, which facilitates the design of peripheral detection circuits according to specific needs and has better adaptability.
应用本申请实施例，至少能够实现如下有益效果：By applying the embodiments of this application, at least the following beneficial effects can be achieved:
1)本申请实施例提供的存储单元、动态存储器、读写方法及存储装置，每个存储单元包括一个晶体管和一个存储电容，而在该存储单元中，背栅极和源极构成一个辅助电容，从而增加存储单元的电容量，使得存储节点N1能够维持更长的时间，从而在无需增加膜层以保证动态存储器的集成度的同时降低了动态存储器的刷新频率。1) In the storage unit, dynamic memory, reading and writing method and storage device provided by the embodiments of this application, each storage unit includes a transistor and a storage capacitor, and in the storage unit, the back gate and the source form an auxiliary capacitor. , thereby increasing the capacitance of the memory cell, allowing the storage node N1 to be maintained for a longer period of time, thereby reducing the refresh frequency of the dynamic memory without adding film layers to ensure the integration of the dynamic memory.
2)本申请实施例提供的存储单元、动态存储器、读写方法及存储装置，在读取过程中，存储单元处于“1”状态则位线能够获取存储节点信号，存储单元处于“0” 状态则位线不能获取存储节点信号，也就是“1”或“0”两种状态下位线读取的数据信号差异巨大，使得动态存储器的抗噪声性能增强；而且相对于现有技术中只能通过检测晶体管输出电流的大小来实现存储单元的“1”或“0”状态的判断而言，本实施例由于“0”状态下检测不到信号，则既可以利用电流信号进行检测也可以利用电压信号进行检测，从而便于根据具体需求设计***检测电路，具有更好地适应性。2) In the storage unit, dynamic memory, reading and writing method and storage device provided by the embodiments of this application, during the reading process, if the storage unit is in the "1" state, the bit line can obtain the storage node signal, and the storage unit is in the "0" state. state, the bit line cannot obtain the storage node signal, that is, the data signal read by the bit line in the two states of "1" or "0" is greatly different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, which can only In terms of judging the "1" or "0" state of the memory cell by detecting the output current of the transistor, in this embodiment, since no signal is detected in the "0" state, the current signal can be used for detection. The voltage signal is detected, which facilitates the design of peripheral detection circuits according to specific needs and has better adaptability.
3)本申请实施例提供的存储单元的制作方法，获得的动态存储器具有较低的刷新频率以及较高的集成度。3) The method for manufacturing a memory unit provided by the embodiment of the present application can obtain a dynamic memory with a lower refresh frequency and a higher integration level.
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。Those skilled in the art can understand that the steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Furthermore, the steps, measures, and solutions in the prior art with various operations, methods, and processes disclosed in this application can also be replaced, changed, rearranged, decomposed, combined, or deleted.
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。The terms “first” and “second” are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, "plurality" means two or more.
应该理解的是，虽然附图的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤的实施顺序并不受限于箭头所指示的顺序。除非本文中有明确的说明，否则在本申请实施例的一些实施场景中，各流程中的步骤可以按照需求以其他的顺序执行。而且，各流程图中的部分或全部步骤基于实际的实施场景，可以包括多个子步骤或者多个阶段。这些子步骤或者阶段中的部分或全部可以在同一时刻被执行，也可以在不同的时刻被执行在执行时刻不同的场景下，这些子步骤或者阶段的执行顺序可以根据需求灵活配置，本申请实施例对此不限制。It should be understood that although various steps in the flowchart of the accompanying drawings are shown in sequence as indicated by arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated in this article, in some implementation scenarios of the embodiments of this application, the steps in each process may be executed in other orders according to requirements. Moreover, some or all of the steps in each flowchart are based on actual implementation scenarios and may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time or at different times. In scenarios with different execution times, the execution order of these sub-steps or stages can be flexibly configured according to needs. This application implements There is no limit to this.
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请的方案技术构思的前提下，采用基于本申请技术思想的其他类似实施手段，同样属于本申请实施例的保护范畴。 The above are only some implementations of the present application. It should be pointed out that for those of ordinary skill in the technical field, other similar implementation means based on the technical ideas of the present application may be adopted without departing from the technical concept of the present application. , also belongs to the protection scope of the embodiments of this application.

Claims (16)

  1. 一种存储单元，其特征在于，包括：A storage unit, characterized by including:
    一存储电容，包括在远离衬底的方向上依次排布的第一电极、电容介质层以及第二电极，所述第一电极与参考电位端连接；A storage capacitor, including a first electrode, a capacitive dielectric layer and a second electrode arranged sequentially in a direction away from the substrate, the first electrode being connected to a reference potential terminal;
    一晶体管，包括：A transistor consisting of:
    在远离所述衬底的方向上依次排布的漏极、半导体层和主栅极，所述主栅极呈柱状且与字线电连接，所述主栅极在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影内，所述漏极与所述第二电极电连接，所述半导体层位于所述主栅极与所述第二电极之间且环绕所述主栅极侧壁；A drain electrode, a semiconductor layer and a main gate electrode are arranged in sequence in a direction away from the substrate. The main gate electrode is columnar and electrically connected to the word line. The main gate electrode is on the positive side of the substrate. The projection is located within the orthographic projection of the first electrode on the substrate, the drain electrode is electrically connected to the second electrode, the semiconductor layer is located between the main gate electrode and the second electrode, and surrounding the main gate sidewall;
    环绕所述主栅极且位于所述半导体层远离所述主栅极一侧的源极，所述源极与所述半导体层接触；a source electrode surrounding the main gate and located on the side of the semiconductor layer away from the main gate, the source electrode being in contact with the semiconductor layer;
    环绕所述主栅极且位于所述半导体层远离所述主栅极一侧的背栅极，所述背栅极与所述漏极电连接且与所述源极绝缘，所述背栅极与所述源极构成辅助电容。A back gate surrounding the main gate and located on the side of the semiconductor layer away from the main gate, the back gate is electrically connected to the drain and insulated from the source, the back gate and the source electrode form an auxiliary capacitor.
  2. 根据权利要求1所述的存储单元，其特征在于，还包括：The storage unit according to claim 1, further comprising:
    第一绝缘层，位于所述衬底的一侧且设置有贯穿所述第一绝缘层的第一容纳孔，所述第一电极、电容介质层以及第二电极中至少之一的全部或部分结构位于所述第一容纳孔内。A first insulating layer located on one side of the substrate and provided with a first receiving hole penetrating the first insulating layer, all or part of at least one of the first electrode, the capacitive dielectric layer and the second electrode The structure is located in the first receiving hole.
  3. 根据权利要求2所述的存储单元，其特征在于，所述第二电极复用为所述漏极，所述第二电极在所述第一绝缘层上延伸，所述背栅极在衬底上的正投影与所述第二电极的外轮廓在衬底上的正投影交叠。The memory cell of claim 2, wherein the second electrode is multiplexed as the drain, the second electrode extends on the first insulating layer, and the back gate is on the substrate. The orthographic projection on the substrate overlaps with the orthographic projection of the outer contour of the second electrode on the substrate.
  4. 根据权利要求1所述的存储单元，其特征在于，还包括：The storage unit according to claim 1, further comprising:
    第一栅极绝缘层，覆盖所述源极；a first gate insulating layer covering the source;
    第二栅极绝缘层，位于所述主栅极与所述半导体层之间。A second gate insulating layer is located between the main gate and the semiconductor layer.
  5. 根据权利要求3所述的存储单元，其特征在于，还包括第三栅极绝缘层；The memory cell according to claim 3, further comprising a third gate insulating layer;
    所述背栅极位于所述源极与所述漏极之间，且所述第三栅极绝缘层位于所述背栅极与所述源极之间以及所述背栅极与所述半导体层之间。The back gate is located between the source and the drain, and the third gate insulating layer is located between the back gate and the source and between the back gate and the semiconductor. between layers.
  6. 根据权利要求5所述的存储单元，其特征在于，The storage unit according to claim 5, characterized in that:
    所述背栅极与所述漏极直接接触；或者The back gate is in direct contact with the drain; or
    所述存储单元还包括：连接部，所述连接部连接所述背栅极和所述漏极；所述连接部位于所述第一绝缘层上并分别与所述漏极和所述背栅极直接搭接，所述连接部环绕所述背栅极并与所述背栅极搭接。The memory unit further includes: a connection portion connecting the back gate and the drain; the connection portion is located on the first insulating layer and is connected to the drain and the back gate respectively. The electrodes are directly overlapped, and the connecting portion surrounds the back gate and overlaps the back gate.
  7. 根据权利要求1-6中任一项所述的存储单元，其特征在于，还包括：The storage unit according to any one of claims 1-6, further comprising:
    第一导电层，位于所述衬底与所述第一绝缘层之间且与所述第一电极搭接，所述第一导电层包括所述参考电位端；A first conductive layer, located between the substrate and the first insulating layer and overlapping the first electrode, the first conductive layer including the reference potential end;
    第二导电层，位于所述源极远离所述衬底的一侧，所述第二导电层包括位线，所述位线通过过孔与所述源极电连接；A second conductive layer is located on the side of the source electrode away from the substrate. The second conductive layer includes a bit line, and the bit line is electrically connected to the source electrode through a via hole;
    第三导电层，位于所述第二导电层远离所述衬底的一侧且与所述第二导电层绝缘，所述第三导电层包括所述字线，所述字线通过过孔与所述主栅极电连接；或者，所述第三导电层位于所述主栅极的上表面与所述主栅极直接连接，所述第二导电层位于所 述第三导电层的上方且与所述第三导电层绝缘。A third conductive layer is located on a side of the second conductive layer away from the substrate and is insulated from the second conductive layer. The third conductive layer includes the word line, and the word line is connected to the word line through a via hole. The main gate is electrically connected; or, the third conductive layer is located on the upper surface of the main gate and is directly connected to the main gate, and the second conductive layer is located on the upper surface of the main gate. above the third conductive layer and insulated from the third conductive layer.
  8. 根据权利要求7所述的存储单元，其特征在于，还包括：The storage unit according to claim 7, further comprising:
    绝缘介质层，位于所述衬底与所述第一导电层之间；An insulating dielectric layer located between the substrate and the first conductive layer;
    第二绝缘层，位于所述晶体管和所述第二导电层之间，并覆盖晶体管；a second insulating layer located between the transistor and the second conductive layer and covering the transistor;
    第三绝缘层，位于所述第二导电层和所述第三导电层之间。A third insulating layer is located between the second conductive layer and the third conductive layer.
  9. 一种动态存储器，其特征在于，包括衬底、位于所述衬底上的多条字线、多条位线、多条参考电位端和多个权利要求1至8中任一项所述的存储单元；A dynamic memory, characterized by comprising a substrate, a plurality of word lines, a plurality of bit lines, a plurality of reference potential terminals located on the substrate and a plurality of the power sources described in any one of claims 1 to 8. storage unit;
    多个所述存储单元分为多个存储单元组，多个所述存储单元组在垂直于所述衬底的方向上排布；A plurality of the memory cells are divided into a plurality of memory unit groups, and the plurality of memory unit groups are arranged in a direction perpendicular to the substrate;
    每个所述存储单元组包括多个在平行于所述衬底的方向上呈阵列排布的所述存储单元，其中位于同一行的各所述存储单元与同一所述字线电连接，位于同一列的各所述存储单元与同一所述位线电连接。Each of the memory cell groups includes a plurality of memory cells arranged in an array in a direction parallel to the substrate, wherein each of the memory cells located in the same row is electrically connected to the same word line. Each memory cell in the same column is electrically connected to the same bit line.
  10. 一种存储装置，其特征在于，包括权利要求9所述的动态存储器。A storage device, characterized by comprising the dynamic memory according to claim 9.
  11. 一种存储单元的制作方法，其特征在于，包括：A method of manufacturing a storage unit, which is characterized by including:
    提供一衬底，通过构图工艺在所述衬底上形成多条参考电位端和多个存储电容，所述存储电容包括在远离所述衬底的方向上依次排布的第一电极、电容介质层以及第二电极，所述第一电极与所述参考电位端连接；A substrate is provided, and a plurality of reference potential terminals and a plurality of storage capacitors are formed on the substrate through a patterning process. The storage capacitors include first electrodes and capacitive media arranged sequentially in a direction away from the substrate. layer and a second electrode, the first electrode being connected to the reference potential terminal;
    通过构图工艺在所述存储电容远离所述衬底的一侧形成多个晶体管，每个所述晶体管包括在远离所述衬底的方向上依次排布的漏极、半导体层和主栅极、环绕所述主栅极且位于所述半导体层远离所述主栅极一侧的源极以及环绕所述主栅极且位于所述半导体层远离所述主栅极一侧的背栅极，其中，所述主栅极呈柱状且在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影内，所述漏极与所述第二电极电连接，所述半导体层位于所述主栅极与所述第二电极之间且环绕所述主栅极侧壁，所述源极与所述半导体层接触，所述背栅极与所述漏极电连接且与所述源极绝缘，所述背栅极与所述源极构成辅助电容；A plurality of transistors are formed on the side of the storage capacitor away from the substrate through a patterning process. Each transistor includes a drain electrode, a semiconductor layer and a main gate electrode arranged sequentially in a direction away from the substrate. a source electrode surrounding the main gate and located on a side of the semiconductor layer away from the main gate; and a back gate surrounding the main gate and located on a side of the semiconductor layer away from the main gate, wherein , the main gate is columnar and its orthographic projection on the substrate is located within the orthographic projection of the first electrode on the substrate, the drain is electrically connected to the second electrode, and A semiconductor layer is located between the main gate and the second electrode and surrounds the main gate sidewall, the source is in contact with the semiconductor layer, the back gate is electrically connected to the drain, and Insulated from the source, the back gate and the source form an auxiliary capacitor;
    通过构图工艺形成多条字线和多条位线，所述字线与所述主栅极电连接，所述位线与所述源极电连接。A plurality of word lines and a plurality of bit lines are formed through a patterning process, the word lines are electrically connected to the main gate, and the bit lines are electrically connected to the source.
  12. 根据权利要求11所述的存储单元的制作方法，其特征在于，通过构图工艺在所述衬底上形成多条参考电位端和多个存储电容，包括：The method of manufacturing a memory cell according to claim 11, wherein a plurality of reference potential terminals and a plurality of storage capacitors are formed on the substrate through a patterning process, including:
    通过构图工艺在所述衬底的一侧形成所述参考电位端；The reference potential terminal is formed on one side of the substrate through a patterning process;
    在所述参考电位端远离所述衬底的一侧沉积第一绝缘层，并形成多个贯穿所述第一绝缘层的第一容纳孔；Deposit a first insulating layer on the side of the reference potential end away from the substrate, and form a plurality of first receiving holes penetrating the first insulating layer;
    通过构图工艺形成位于所述第一容纳孔内的第一电极、电容介质层和第二电极，以形成所述存储电容，其中所述第一电极与所述参考电位端搭接。A first electrode, a capacitive dielectric layer and a second electrode located in the first accommodation hole are formed through a patterning process to form the storage capacitor, wherein the first electrode overlaps the reference potential terminal.
  13. 根据权利要求12所述的存储单元的制作方法，其特征在于，所述第二电极复用为所述漏极，通过构图工艺在所述存储电容远离所述衬底的一侧形成多个晶体管，包括：The method of manufacturing a memory cell according to claim 12, wherein the second electrode is reused as the drain electrode, and a plurality of transistors are formed on a side of the storage capacitor away from the substrate through a patterning process. ,include:
    在所述第二电极远离所述衬底的一侧形成牺牲层，并通过构图工艺在所述牺牲层上形成源极单元； Form a sacrificial layer on the side of the second electrode away from the substrate, and form a source unit on the sacrificial layer through a patterning process;
    在所述源极单元上形成第一栅极绝缘层，通过构图工艺形成贯穿所述第一栅极绝缘层、所述源极单元和所述牺牲层的第二容纳孔，所述第二容纳孔在所述衬底上的正投影位于所述漏极在所述衬底上的正投影内，其中，被所述第二容纳孔贯穿的所述源极单元为所述源极；A first gate insulating layer is formed on the source unit, and a second accommodation hole is formed through the first gate insulating layer, the source unit and the sacrificial layer through a patterning process. The orthographic projection of the hole on the substrate is located within the orthographic projection of the drain electrode on the substrate, wherein the source unit penetrated by the second receiving hole is the source electrode;
    在所述第二容纳孔内依次沉积半导体层、第二栅极绝缘层和主栅极，所述半导体层与所述漏极搭接；A semiconductor layer, a second gate insulating layer and a main gate are sequentially deposited in the second accommodation hole, and the semiconductor layer overlaps the drain electrode;
    去除剩余牺牲层，并依次形成第三栅极绝缘层和所述背栅极，所述第三栅极绝缘层位于所述半导体层与所述背栅极之间、所述背栅极与所述源极之间以及所述背栅极与所述漏极之间，所述背栅极位于所述漏极与所述源极之间且包围所述主栅极的侧壁，所述背栅极在所述衬底上的正投影与所述漏极在所述衬底上的正投影交叠，所述背栅极与所述漏极电连接。The remaining sacrificial layer is removed, and a third gate insulating layer and the back gate are formed in sequence. The third gate insulating layer is located between the semiconductor layer and the back gate, and the back gate is connected to the back gate. between the source electrodes and between the back gate electrode and the drain electrode. The back gate electrode is located between the drain electrode and the source electrode and surrounds the sidewalls of the main gate electrode. The back gate electrode The orthographic projection of the gate electrode on the substrate overlaps the orthographic projection of the drain electrode on the substrate, and the back gate electrode is electrically connected to the drain electrode.
  14. 根据权利要求13所述的存储单元的制作方法，其特征在于，去除剩余牺牲层，并依次形成第三栅极绝缘层和所述背栅极，包括：The method of manufacturing a memory cell according to claim 13, wherein removing the remaining sacrificial layer and sequentially forming a third gate insulating layer and the back gate includes:
    在制作完所述半导体层、所述第一栅极绝缘层和所述主栅极的所述衬底上形成第二光刻胶层，并对所述第二光刻胶层进行曝光、显影以去除位于待刻蚀区域的第二光刻胶层，再以未去除的第二光刻胶层作为掩膜进行局部刻蚀，以去除部分所述第一栅极绝缘层和部分所述牺牲层，以使部分所述漏极暴露；Form a second photoresist layer on the substrate after fabricating the semiconductor layer, the first gate insulating layer and the main gate, and expose and develop the second photoresist layer. Remove the second photoresist layer located in the area to be etched, and then perform local etching using the unremoved second photoresist layer as a mask to remove part of the first gate insulating layer and part of the sacrificial layer layer so that part of the drain electrode is exposed;
    去除剩余牺牲层，并依次形成第三栅极绝缘层和背栅极，所述第三栅极绝缘层附着在所述漏极的部分上表面、所述半导体层的部分侧壁、所述源极的下表面以及所述第一栅极绝缘层的下表面和侧壁；所述背栅极的上表面、下表面以及靠近所述半导体层的侧面均与所述第三栅极绝缘层接触；Remove the remaining sacrificial layer, and form a third gate insulating layer and a back gate in sequence. The third gate insulating layer is attached to part of the upper surface of the drain, part of the sidewalls of the semiconductor layer, and the source. The lower surface of the back gate electrode and the lower surface and side walls of the first gate insulating layer; the upper surface, lower surface of the back gate and the side surface close to the semiconductor layer are all in contact with the third gate insulating layer ;
    通过构图工艺形成连接部，所述连接部环绕所述背栅极且分别与所述背栅极和所述漏极搭接。A connection portion is formed through a patterning process, and the connection portion surrounds the back gate and overlaps the back gate and the drain respectively.
  15. 根据权利要求14所述的存储单元的制作方法，其特征在于，在形成连接部之后，通过构图工艺在所述存储电容远离所述衬底的一侧形成多个晶体管，还包括：The method of manufacturing a memory cell according to claim 14, wherein after forming the connection portion, forming a plurality of transistors on a side of the storage capacitor away from the substrate through a patterning process, further comprising:
    在制作完所述连接部的所述衬底上形成第二绝缘层，所述第二绝缘层覆盖晶体管；forming a second insulating layer on the substrate after the connection portion is produced, and the second insulating layer covers the transistor;
    对所述第二绝缘层的上表面进行平坦化处理。The upper surface of the second insulating layer is planarized.
  16. 一种读写方法，其特征在于，用于对权利要求1至8中任一项所述的存储单元进行读写，所述读写方法包括：A reading and writing method, characterized in that it is used to read and write the storage unit according to any one of claims 1 to 8, and the reading and writing method includes:
    在写入状态时，通过所述字线向待写入的存储单元的主栅极施加第一电平以使晶体管导通，并通过位线向所述待写入的存储单元的源极传输存储信号，以将所述存储信号写入所述待写入的存储单元作为存储数据；In the writing state, a first level is applied to the main gate of the memory cell to be written through the word line to turn on the transistor, and is transmitted to the source of the memory cell to be written through the bit line. store a signal to write the storage signal into the storage unit to be written as storage data;
    在读取状态时，通过所述字线向待读取的存储单元的主栅极施加第二电平，以使所述位线感测所述待读取的存储单元的存储数据。 In the read state, a second level is applied to the main gate of the memory cell to be read through the word line, so that the bit line senses the stored data of the memory cell to be read.
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