WO2024103647A1 - Circuit de stockage, unité de stockage, dispositif électronique et procédé de lecture-écriture de données - Google Patents

Circuit de stockage, unité de stockage, dispositif électronique et procédé de lecture-écriture de données Download PDF

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Publication number
WO2024103647A1
WO2024103647A1 PCT/CN2023/092592 CN2023092592W WO2024103647A1 WO 2024103647 A1 WO2024103647 A1 WO 2024103647A1 CN 2023092592 W CN2023092592 W CN 2023092592W WO 2024103647 A1 WO2024103647 A1 WO 2024103647A1
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WIPO (PCT)
Prior art keywords
electrode
gate
read
write
transistor
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PCT/CN2023/092592
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English (en)
Chinese (zh)
Inventor
朱正勇
康卜文
赵超
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北京超弦存储器研究院
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Publication of WO2024103647A1 publication Critical patent/WO2024103647A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/10—Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of semiconductor technology, and in particular to a storage circuit, a storage unit, an electronic device, and a data reading and writing method.
  • the storage unit of a traditional memory includes a transistor and a capacitor (as shown in Figure 1, where SN is a storage node, BL is a bit line, WL is a word line, C is a capacitor, G is a gate of the transistor, S is a source of the transistor, and D is a drain of the transistor).
  • This type of storage unit requires a larger capacitor, which is not conducive to further improving the storage density of the memory, and data reading is destructive, which is not conducive to reducing power consumption.
  • the present application embodiment provides a storage circuit, which may include:
  • the write transistor comprises a first electrode, a second electrode and a first gate; the second electrode is connected to a write bit line; the first gate is connected to a write word line;
  • the read transistor comprises a third electrode, a fourth electrode and a second gate; the third electrode is connected to the read bit line, the fourth electrode is connected to the reference voltage terminal; the second gate is used as a storage node and is connected to the first electrode;
  • the first end of the capacitor is connected to the read word line; the second end of the capacitor is connected to the storage node; the capacitor is configured to change the gate voltage of the read transistor through capacitive coupling during the data reading phase.
  • the capacitor may be a coupling capacitor used for coupling.
  • the read transistor may include only one gate. In the solution provided by this embodiment, the read transistor does not need to be provided with multiple gates, which can simplify the process and facilitate integration.
  • the read transistor may further include a third gate
  • the third gate is configured to adjust a turn-on threshold voltage of the read transistor.
  • the write transistor may further include a fourth gate
  • the fourth gate is configured to adjust a turn-on threshold voltage of the write transistor.
  • the read bit line and the write bit line are connected to different independent signal terminals; or,
  • the read bit line and the write bit line are connected to the same signal terminal.
  • the embodiment of the present application further provides a data reading and writing method based on the storage circuit; the method may include:
  • a voltage is applied to a read word line connected through a capacitor to change the voltage of the second gate of the read transistor.
  • the voltage applied by the read word line causes the read transistor to turn on when data 1 is stored in the storage node and to turn off when data 0 is stored.
  • the signal change on the read bit line is detected. When the signal change exceeds a first threshold, the read data is determined to be 1. When the signal change is less than a second threshold, the read data is determined to be 0.
  • the present application also provides a storage unit, including:
  • the write transistor includes a first electrode, a second electrode and a first gate, and the read transistor includes a third electrode.
  • the capacitor comprises a first plate and a second plate insulated from each other; the second plate is connected to the first plate and the second plate;
  • the read transistor, the write transistor and the second electrode plate are stacked on a substrate, and the second electrode plate of the capacitor is located between the read transistor and the write transistor.
  • the write transistor is located above the second plate of the capacitor, and the read transistor is located below the second plate of the capacitor.
  • the read transistor and the write transistor are respectively vertical transistors
  • the second gate of the read transistor is located on the substrate and extends in a direction perpendicular to the substrate
  • the second plate of the capacitor is located on the second gate and contacts the second gate.
  • the storage unit further includes: a read bit line, a read word line, a write bit line, and a write word line, the first gate is connected to the write word line; the second electrode is connected to the write bit line; the third electrode is connected to the read bit line; the first plate is connected to the read word line, and the first plate of the capacitor and the read word line are connected to form an integrated structure.
  • the read word line and the second plate of the capacitor are separated from each other by a dielectric layer
  • the second electrode plate extends in a direction perpendicular to the substrate and has a side wall, the read word line surrounds the side wall of the second electrode plate, and the dielectric layer surrounds the side wall of the second electrode plate;
  • the read word line has an opening, and the opening surrounds the second plate of the capacitor.
  • the second plate is located on top of the second gate of the read transistor and is connected to the second gate.
  • the write transistor further includes a first semiconductor layer surrounding the first gate and being insulated from the first gate
  • the read transistor further includes a second semiconductor layer surrounding the second gate and being insulated from the second gate.
  • the first gate extends in a direction perpendicular to the substrate, the second semiconductor layer surrounds a sidewall of the second gate, and the first semiconductor layer surrounds a sidewall and a bottom wall of the first gate.
  • the second electrode plate of the capacitor contacts a surface of the first semiconductor layer close to the substrate.
  • the present disclosure provides a storage unit, including:
  • the write transistor comprises a first gate, a first electrode, a second electrode and a first semiconductor layer, wherein the first semiconductor layer is connected to the first electrode and the second electrode respectively; the first gate is connected to the write word line; the second electrode is connected to the write bit line;
  • the read transistor comprises a second gate, a third electrode, a fourth electrode and a second semiconductor layer, wherein the second semiconductor layer is connected to the third electrode and the fourth electrode respectively; the second gate is connected to the first electrode; and the third electrode is connected to the read bit line;
  • the capacitor includes a first plate and a second plate, wherein the first plate is connected to the read word line; and the second plate is connected to the second gate and the first electrode.
  • the second gate extends in a direction perpendicular to the substrate, and the second semiconductor layer surrounds a sidewall of the second gate;
  • the first gate extends in a direction perpendicular to the substrate, and the first semiconductor layer surrounds the side wall of the first gate and a bottom wall close to the substrate.
  • the second semiconductor layer also surrounds the bottom wall of the second gate electrode close to the substrate side
  • the fourth electrode is arranged on the second semiconductor layer close to the substrate side and contacts the surface of the second semiconductor layer close to the substrate side
  • the third electrode is connected to the read bit line to form an integrated structure, and the third electrode surrounds the side wall of the second semiconductor layer.
  • the first electrode is connected to the second electrode plate to form an integrated structure, the first electrode contacts the surface of the first semiconductor layer close to the substrate, and contacts the surface of the second gate electrode away from the substrate; the second electrode is connected to the write bit line to form an integrated structure, and the second electrode surrounds the side wall of the first semiconductor layer.
  • the first electrode plate and the read word line are connected to form an integrated structure.
  • the second electrode plate extends in a direction perpendicular to the substrate, the read word line is provided with an opening, and the second electrode plate is disposed in the opening.
  • the second electrode plate is disposed on the same layer as the first electrode plate.
  • the write word line is disposed on a side of the first gate away from the substrate and is in contact with a surface of the first gate away from the substrate.
  • the read bit line and the write bit line are connected to different signal terminals, or the read bit line and the write bit line are connected to the same signal terminal through vias.
  • An embodiment of the present application further provides a storage array, comprising the storage circuit or the storage unit.
  • An embodiment of the present application further provides an electronic device, comprising the storage circuit or the storage unit.
  • the electronic device may include any one or more of the following: a smart mobile terminal, a computer, a tablet computer, and a wearable device.
  • FIG1 is a schematic diagram of a 1T1C storage circuit in a technical solution
  • FIG2 is a schematic diagram of a 2T1C storage circuit according to some embodiments of the present application.
  • FIG3 is a schematic diagram of a 2T1C storage circuit in which a back gate is added to a read transistor in some embodiments of the present application;
  • FIG4 is a flow chart of a method for writing data into a 2T1C storage circuit according to some embodiments of the present application.
  • FIG5 is a schematic diagram of an IV curve of a read transistor during data writing in a 2T1C storage circuit according to some embodiments of the present application.
  • FIG6 is a flow chart of a method for reading data from a 2T1C storage circuit according to some embodiments of the present application.
  • FIG. 7 is a diagram of a read transistor during data reading in a 2T1C storage circuit according to some embodiments of the present application. Schematic diagram of IV curve;
  • FIG8 is a schematic diagram of a storage circuit in which a second electrode and a third electrode are connected in some embodiments of the present application;
  • FIG9 is a schematic diagram of a first 2T1C storage array structure in some embodiments of the present application.
  • FIG10 is a schematic diagram of a second 2T1C storage array structure according to some embodiments of the present application.
  • FIG11 is a schematic diagram of a 2T1C storage unit structure in some embodiments of the present application.
  • FIG12A is a cross-sectional view along the AA direction in FIG12B;
  • FIG. 12B is a top view after forming a read bit line provided by an exemplary embodiment
  • FIG13A is a cross-sectional view along the AA direction in FIG13B;
  • FIG13B is a top view after forming a fifth insulating layer provided by an exemplary embodiment
  • FIG14A is a cross-sectional view along the AA direction in FIG14B;
  • FIG14B is a top view after forming a fourth conductive layer provided by an exemplary embodiment
  • FIG15A is a cross-sectional view along the AA direction in FIG15B;
  • FIG. 15B is a top view after forming a read word line provided by an exemplary embodiment
  • FIG16A is a cross-sectional view along the AA direction in FIG16B;
  • FIG. 16B is a top view after forming a write bit line provided by an exemplary embodiment
  • FIG17A is a cross-sectional view along the AA direction in FIG17B;
  • FIG. 17B is a top view of an exemplary embodiment after forming a write word line
  • FIG18A is a block diagram of an electronic device including a storage circuit according to some embodiments of the present application.
  • FIG18B is a block diagram of the structure of an electronic device including a storage unit according to some embodiments of the present application.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors with opposite polarities or when the current direction changes during circuit operation. Therefore, in the present disclosure, the "source electrode” and the “drain electrode” may be interchanged.
  • parallel means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°.
  • perpendicular means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.
  • the "A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process.
  • the orthographic projection of B is within the range of the orthographic projection of A means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • a and B are an integrated structure” may refer to the fact that there is no obvious Generally, the film layers formed by patterning on a film layer to form a connection are integrated. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.
  • the specification may have presented the method and/or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and/or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.
  • the present application embodiment provides a storage circuit 1, as shown in FIG2 , which may include:
  • the write transistor TR_W may include a first electrode P1, a second electrode P2 and a first gate G1; the second electrode P2 is connected to a write bit line W_BL; the first gate G1 is connected to a write word line W_WL;
  • the read transistor TR_R may include a third electrode P3, a fourth electrode P4 and a second gate G2; the third electrode P3 is connected to the read bit line R_BL, and the fourth electrode P4 is connected to the reference voltage terminal; the second gate G2 is used as a storage node and is connected to the first electrode P1;
  • the second gate is only used to distinguish from the first gate in name, and does not mean that the read transistor must have more than one gate.
  • the read transistor has only one gate.
  • the presence of the capacitor can adjust the voltage of the read transistor, and there is no need to set a back gate, thereby simplifying the device structure and routing design.
  • the read transistor When the read transistor reads a signal 1 or 0 of a bit, the on or off state of the read transistor has no direct relationship with the charge stored in the capacitor. Therefore, the memory cell is based on the working principle of 2T0C, and the capacitor is not used to store the read charge. The charge only needs to make the transistor turn on or off accordingly when 1 or 0 is stored. Therefore, the capacitor size can be smaller. Compared with 1T1C, the solution provided by this embodiment can have a capacitor C size smaller than that of the capacitor in the 1T1C solution, thereby reducing the device size and improving the integration.
  • the first end of the capacitor C is connected to the read word line R_WL; the second end of the capacitor C is connected to the storage node SN; the capacitor C is configured to change the gate voltage of the read transistor TR_R through capacitive coupling during the data reading phase.
  • FIG. 2 is a schematic diagram of a storage circuit using N-type transistors as an example, and in other embodiments, P-type transistors may also be used to implement the circuit).
  • the function of the capacitor C is different from that of the capacitor in the 1T1C storage circuit.
  • the capacitor C is set to write data on the storage node SN through the write transistor TR_W during the data writing phase; in the data reading phase, a voltage is applied to the read word line connected by the capacitor to change the voltage of the second gate G2 of the read transistor TR_R, and the voltage applied by the read word line makes the read transistor TR_R turn on when the storage node SN stores data "1".
  • the solution provided in this embodiment can control the opening and closing of the read transistor through the read word line and the capacitor when reading data in the storage array, turn on a row of storage cells to be read, and turn off the storage cells in other rows, thereby avoiding the storage cells in other rows from interfering with the storage cells to be read, thereby improving performance.
  • the read transistor may include only one gate (ie, the read transistor includes only the second gate G2).
  • the solution provided in this embodiment can simplify the process and is more conducive to integration.
  • the write transistor may include only one gate (ie, the write transistor includes only the first gate G1).
  • the solution provided in this embodiment can simplify the process and is more conducive to integration.
  • the read transistor TR_R may further include a third gate G3;
  • the third gate G3 is configured to adjust a turn-on threshold voltage of the read transistor TR_R.
  • the write transistor TR_W may further include a fourth gate G4 ;
  • the fourth gate G4 is configured to adjust a turn-on threshold voltage of the write transistor TR_W.
  • the read transistor TR_R may further include a third gate G3, and the write transistor TR_W may further include a fourth gate G4, wherein the third gate G3 is configured to adjust the turn-on threshold voltage of the read transistor TR_R, and the fourth gate G4 is configured to adjust the turn-on threshold voltage of the write transistor TR_W.
  • a voltage may be input to the third gate G3 as required, so that the turn-on threshold voltage of the read transistor TR_R is within a desired voltage range, and a voltage may be input to the fourth gate G4 as required, so that the turn-on threshold voltage of the write transistor TR_W is within a desired voltage range, thereby improving circuit performance.
  • the write transistor TR_W has two gates, or the read transistor TR_R has two gates, one is a control gate and the other is a back gate.
  • the turn-on threshold voltage of the transistor is set.
  • the read transistor TR_R in the scheme of FIG. 2 of the embodiment of the present application is not provided with a back gate (or auxiliary gate)
  • a back gate or auxiliary gate
  • the IGZO transistor usually has a negative threshold bias, in order to make the turn-on voltage threshold of the IGZO transistor meet the functional requirements of the embodiment of the present application
  • a back gate i.e., the third gate G3 mentioned above
  • a back gate i.e., the fourth gate G4 mentioned above
  • one of the first electrode P1 and the second electrode P2 is a source electrode, and the other is a drain electrode; one of the third electrode P3 and the fourth electrode P4 is a source electrode, and the other is a drain electrode.
  • the source electrode or the drain electrode can be identified in the product according to the direction of current flow.
  • the embodiment of the present application further provides a data writing method based on the storage circuit; as shown in FIG4 , the method may include steps S101-S102:
  • the gate voltage on the read transistor TR_R i.e., the voltage of the second gate G2
  • the read transistor TR_R is in a closed state regardless of whether it corresponds to the write data "1" or the write data "0".
  • the voltage of the storage node SN is controlled by the read word line R_WL connected to the read transistor TR_R.
  • the voltage of the first end of the capacitor C can be pulled down, so that the voltage of the second end is relatively low, and the read transistor TR_R cannot be turned on even if the data corresponding to the input signal 1 is input.
  • the read word line R_WL when writing data to a storage node SN, the read word line R_WL may be kept at a low voltage to turn off the read transistor TR_R, and in addition, the write transistor TR_W may be turned on to write data "1" or "0" to the storage node SN.
  • the state of the read transistor TR_R when writing data "1" and “0” may be as shown in FIG. 5 (a schematic diagram of the state when both the read transistor and the write transistor are N-type transistors).
  • the horizontal axis is the voltage difference V GS between the gate and source of the read transistor TR_R, the vertical axis is the drain current ID of the read transistor TR_R, 0 means when the written data is "0", 1 means when the written data is "1”, and LV means that the read word line R_WL inputs the first voltage during the data writing process, that is, the low voltage.
  • a voltage may be added to the read word line R_WL, which may also be interpreted as raising the voltage of the read word line R_WL, so that the initial voltage V0 of the second gate G2 increases to V0+ ⁇ V.
  • V0+ ⁇ V is greater than the above-mentioned turn-on threshold voltage Vth of the read transistor TR_R, and the read transistor TR_R is turned on; when storing data "0", V0+ ⁇ V is still less than the turn-on threshold voltage Vth, and the read transistor TR_R is turned off.
  • the method may further include:
  • a first fixed voltage is input through the third gate G3 so that the turn-on threshold voltage of the read transistor TR_R is within a required voltage range.
  • the method further includes:
  • a second fixed voltage is input through the fourth gate G4 so that the turn-on threshold voltage of the write transistor TR_W is within a required voltage range.
  • the embodiment of the present application further provides a data reading method based on the storage circuit; as shown in FIG6 , the method may include steps S201-S202:
  • the signal change amount on the read bit line R_BL is detected.
  • the read data is determined to be "1"
  • the signal change is less than a second threshold, the read data is determined to be "0".
  • the state of the read transistor TR_R when reading data "1" and “0” can be as shown in Figure 7 (the figure is explained by taking an N-type read transistor and an N-type write transistor as examples), wherein the abscissa is the voltage difference V GS between the gate and the source of the read transistor TR_R, the ordinate is the drain current ID of the read transistor TR_R, 0 refers to when the written data is "0", 1 refers to when the written data is "1", LV refers to a first voltage (for example, it can be a low voltage for an N-type transistor), and HV refers to a second voltage input to the read word line R_WL during the data reading process (for example, it can be a high voltage for an N-type transistor), that is, at this time, during the data reading process, the input voltage on the read word line R_WL is changed from the first voltage to the second voltage, for example, it refers to a change from a low voltage to a high voltage for an N-type
  • the second electrode P2 and the third electrode P3 may be different electrodes, respectively configured to be connected to different bit lines; or,
  • the second electrode P2 and the third electrode P3 are configured to be connected to the same bit line.
  • the read bit line R_BL and the write bit line W_BL may be independent and different bit lines, that is, the read bit line R_BL and the write bit line W_BL are connected to different signal terminals, and different signals may be input to independently control the read bit line R_BL and the write bit line W_BL; in this solution, the second electrode P2 and the third electrode P3 are connected to different bit lines, or,
  • the read bit line R_BL and the write bit line W_BL can be connected to the same signal terminal, but the routing in the memory cell array can be the same or different bit lines.
  • the read bit line R_BL and the write bit line W_BL are different bit lines, the read bit line R_BL and the write bit line W_BL can be connected in a peripheral area, and the peripheral area can be the periphery or the top or the bottom of the memory cell array.
  • FIG. 8 this figure is a schematic diagram of a storage circuit taking an N-type transistor as an example, and a P-type transistor may also be used in other embodiments
  • the second electrode P2 and the third electrode P3 are configured to be connected to the same bit line.
  • the different bit lines are the read bit line R_BL and the write bit line W_BL, which do not share a common routing in the memory cell array region; the same bit line serves as both the read bit line R_BL and the write bit line W_BL, and shares a common routing in the memory cell array region.
  • bit line bit line
  • word lines word lines
  • the BL connected to the second pole P2 and the third pole P3 shares a line in the memory array region.
  • the BL connected to the second pole P2 and the third pole P3 may be two lines in the storage array area, but one line in the peripheral area.
  • a via is provided in the array area or the peripheral area, and the via connects the write bit line W_BL connected to the second pole P2 and the read bit line R_BL connected to the third pole P3.
  • each storage circuit may have only three signal lines, including two word line signal lines and one bit line signal line, which is beneficial to layout design, especially layout design in a narrow space, and improves the practicality of the storage circuit of the embodiment of the present application.
  • FIG. 9 and 10 are both schematic diagrams of storage circuits using N-type transistors as examples, and P-type transistors may be used in other embodiments), which may include multiple of the above-mentioned storage circuits.
  • FIG. 9 is a schematic diagram of a memory array in which a write bit line W_BL and a read bit line R_BL are separately arranged, wherein W_BL1, W_BL2, W_BL3, ..., W_BLx refer to different write bit lines, and x is a positive integer; R_BL1, R_BL2, R_BL3, ..., R_BLx refer to different read bit lines; W_WL1, W_WL2, W_WL3, ..., W_WLy refer to different write word lines, and y is a positive integer; R_WL1, R_WL2, R_WL3, ..., R_WLy refer to different read word lines. As shown in FIG.
  • the memory array may include memory circuits arranged in an array along a first direction X and a second direction Y, respectively.
  • the first end of the capacitor C of the memory circuits in the same row distributed along the first direction X may be connected to the same read word line R_WL, for example, the first plate of the capacitor of the memory circuit in the first row is connected to the first read word line R_WL1; R_WL2 to R_Wly are similar and will not be described in detail.
  • the first gates G1 of the write transistors TR_W of the storage circuits in the same row distributed along the first direction X can be connected to the same write word line W_WL; for example, the first gates G1 of the write transistors TR_W of the storage circuits in the first row can be connected to the first write word line W_WL1; W_WL2 to W_WLy are similar and will not be repeated.
  • the third electrodes P3 of the read transistors TR_R of the storage circuits in the same column distributed along the second direction Y are connected to the same read bit line R_BL; for example, the third electrodes P3 of the read transistors TR_R of the storage circuits in the first column are connected to the same read bit line R_BL.
  • the transistor P3 is connected to the first read bit line R_BL1; R_BL2 to R_BLx are similar and will not be described in detail.
  • the second electrodes P2 of the write transistors TR_W of the storage circuits in the same column distributed along the second direction Y are connected to the same write bit line W_BL.
  • the second electrodes P2 of the write transistors TR_W of the storage circuits in the first column are connected to the first write bit line W_BL1.
  • W_BL2 to W_BLx are similar and will not be described in detail.
  • FIG10 is a schematic diagram of a storage array in which a write bit line W_BL and a read bit line R_BL are combined.
  • BL in FIG10 refers to a common bit line after the write bit line W_BL and the read bit line R_BL are combined.
  • BL1, BL2, BL3, ..., BLx refer to different common bit lines, and x is a positive integer
  • W_WL1, W_WL2, W_WL3, ..., W_WLy refer to different write word lines, and y is a positive integer
  • R_WL1, R_WL2, R_WL3, ..., R_WLy refer to different read word lines.
  • the memory array may include memory circuits arranged in an array along a first direction X and a second direction Y.
  • the first ends of the capacitors C of the memory circuits in the same row arranged along the first direction X may be connected to the same read word line R_WL, for example, the first ends of the capacitors C of the memory circuits in the first row are connected to the first read word line R_WL1; R_WL2 to R_Wly are similar and will not be described in detail.
  • the first gates G1 of the write transistors TR_W of the storage circuits in the same row distributed along the first direction X can be connected to the same write word line W_WL; for example, the first gates G1 of the write transistors TR_W of the storage circuits in the first row can be connected to the first write word line W_WL1; W_WL2 to W_WLy are similar and will not be repeated.
  • the third electrode P3 of the read transistor TR_R and the second electrode P2 of the write transistor TR_W of the storage circuits in the same column distributed along the second direction Y are connected to the same common bit line; for example, the third electrode P3 of the read transistor TR_R and the second electrode P2 of the write transistor TR_W of the storage circuits in the first column are connected to the first common bit line BL1.
  • BL2 to BLx are similar and will not be described in detail.
  • the read word line R_WL may extend along a first direction X
  • the write word line W_WL may extend along the first direction X.
  • the read bit line R_BL may extend along the second direction Y
  • the write bit line W_BL may extend along the second direction Y.
  • the common bit lines BL1 to BLx may extend along the second direction Y.
  • FIG. 11 is a cross-sectional view of a memory cell provided by an exemplary embodiment along a direction perpendicular to the substrate.
  • the application embodiment further provides a storage unit 2, as shown in FIG11 , which may include:
  • a substrate (not shown in FIG. 11 ), a common electrode layer CG disposed on the substrate, and configured to be connected to a reference voltage; wherein, when the transistor is an N-type transistor, the common electrode layer CG may be connected to a low potential reference voltage terminal, and when the transistor is a P-type transistor, the common electrode layer CG may be connected to a high potential reference voltage terminal; the common electrode layer CG may serve as a fourth electrode P4 of the read transistor TR_R;
  • the common electrode layer CG, the read transistor TR_R, the read word line R_WL, the write transistor TR_W and the write word line W_WL are stacked on the substrate; the read transistor TR_R, the capacitor C and the write transistor TR_W are stacked in sequence on the substrate.
  • One plate of the capacitor C (such as the plate connected to the second gate G2) is embedded in the conductive layer where the read word line R_WL is located and is insulated from the read word line R_WL;
  • the channel layer (i.e., the second semiconductor layer SE2) of the read transistor TR_R surrounds the side wall of the second gate G2 extending vertically (i.e., extending in a direction perpendicular to the substrate) to form a surrounding channel layer, and the read bit line R_BL surrounds the outer side of the channel layer of the read transistor TR_R;
  • the second semiconductor layer SE2 can also surround the bottom wall of the second gate G2 close to the substrate, that is, the second semiconductor layer SE2 can form a structure including a first receiving hole, and the second gate G2 is arranged in the first receiving hole;
  • the channel layer (ie, the first semiconductor layer SE1) of the write transistor TR_W surrounds the sidewall of the vertically extending (ie, extending in a direction perpendicular to the substrate) first gate G1 to form a surrounding channel layer and is insulated from the first gate G1.
  • the write bit line W_BL surrounds the outer side of the channel layer of the write transistor TR_W.
  • the first semiconductor layer SE1 may also surround the bottom wall of the first gate G1 close to the substrate, that is, the first semiconductor layer SE1 may form a structure including a second accommodating hole, and the first gate G1 is disposed in the second accommodating hole.
  • both the write transistor TR_W and the read transistor TR_R are vertical transistors, and the channel layer surrounds the gate and is insulated from the gate, that is, the first semiconductor layer SE1 surrounds the first gate and is insulated from the first gate G1, and the second semiconductor layer SE2 surrounds the second gate G2 and is insulated from the second gate G2.
  • the common electrode layer CG is disposed on the upper surface of the substrate; the common electrode layer CG may be disposed on a side of the first semiconductor layer SE1 close to the substrate;
  • the read transistor TR_R is disposed above the common electrode layer CG, that is, the common electrode layer CG is away from the substrate, and the channel length direction of the read transistor TR_R is perpendicular to the common electrode layer CG;
  • the read word line R_WL is disposed above the read transistor TR_R, that is, the read transistor TR_R is away from one side of the substrate;
  • the capacitor C includes a first plate C1 and a second plate C2 , and the first plate C1 may be connected to the read word line R_WL to form an integrated structure.
  • the read word line R_WL and the second plate C2 of the capacitor C are separated from each other by a dielectric layer J.
  • the second plate C2 extends along a direction perpendicular to the substrate and has a sidewall
  • the read word line R_WL surrounds the sidewall of the second plate C2
  • the dielectric layer J surrounds the sidewall of the second plate C2;
  • the read word line R_WL has an opening, and the opening surrounds the second electrode plate C2 of the capacitor C, that is, the second electrode plate C2 is arranged in the opening, and the second electrode plate C2 is located on the top of the second gate G2 of the read transistor TR_R and is connected to the second gate G2.
  • the second electrode plate C2 can be in contact with the surface of the second gate G2 away from the substrate.
  • the second electrode C2 of the capacitor C can be a conductive film layer, and the capacitor C is arranged above the read transistor TR_R (that is, the read transistor TR_R is away from the substrate side) and is located between the read transistor TR_R and the write transistor TR_W.
  • the capacitor C is arranged between the two transistors, which improves the performance compared with the 2T0C solution. At the same time, there is no need to increase the area of the storage unit.
  • the first electrode plate C1 and the second electrode plate C2 of the capacitor C may be disposed in different regions of the same conductive film layer, and the two are separated from each other by a dielectric layer J.
  • the first electrode plate C1 and the second electrode plate C2 can be arranged in the same layer, that is, formed by a single patterning process.
  • an insulating layer is arranged on the second gate G2 of the read transistor TR_R and the top of the second semiconductor layer SE2, and the insulating layer exposes the top of the second gate G2.
  • the tops of the insulating layer and the second gate G2 are flat, and a conductive layer is formed on the side of the insulating layer away from the substrate, and the conductive layer is etched to form the first electrode plate and the second electrode plate of the capacitor separated from each other in different regions, with a gap formed by etching between the two, and a dielectric film is deposited in the gap to form a dielectric layer, and the first electrode plate and the second electrode plate and the top of the dielectric layer between the two are exposed by a flattening process.
  • the second electrode plate C2 and the first electrode plate C1 are both conductive layers and plate-shaped, and may be located in the same layer.
  • the first electrode plate C1 surrounds the side wall of the second electrode plate C2.
  • the second electrode plate C2 may be in contact with a surface of the first semiconductor layer SE1 that is close to the substrate.
  • the orthographic projection of the first electrode plate C1 on the substrate may be located outside the orthographic projection of the second gate G2 on the substrate.
  • the orthographic projection of the first electrode plate C1 on the substrate may be located outside the orthographic projection of the first gate G1 on the substrate.
  • the common electrode layer CG, the read transistor TR_R, the read word line R_WL, the write transistor TR_W and the write word line W_WL are vertically stacked, which reduces the volume of the storage unit, reduces space occupation, and facilitates product integration and commercialization.
  • the stacking order and stacking position of the common electrode layer CG, the read transistor TR_R, the read word line R_WL, the write transistor TR_W and the write word line W_WL can be adjusted according to needs.
  • the stacking method in the above embodiment is not the only solution.
  • the read transistor TR_R may include: a second gate G2, a second gate dielectric layer GM2, a second semiconductor layer SE2, a third electrode P3, and a fourth electrode P4;
  • the second gate G2 is disposed above the common electrode layer CG (i.e., the side of the common electrode layer CG away from the substrate); the second gate G2 extends in a direction perpendicular to the substrate;
  • the second gate dielectric layer GM2 contacts the second gate G2 and surrounds the outside of the second gate G2;
  • the second semiconductor layer SE2 contacts the second gate dielectric layer GM2 and surrounds the outside of the second gate dielectric layer GM2; the second semiconductor layer SE2 surrounds the side wall of the second gate G2;
  • the third electrode P3 surrounds the side wall of the second semiconductor layer SE2;
  • the fourth electrode P4 is disposed on a side of the second semiconductor layer SE2 close to the substrate and contacts a surface of the second semiconductor layer SE2 close to the substrate.
  • the second semiconductor layer SE2 further surrounds a bottom wall of the second gate G2 close to the substrate.
  • the third electrode P3 may be connected to the read bit line R_BL to form an integrated structure.
  • the storage node SN is located above the second gate G2 (ie, the second gate G2 is away from the substrate), and is connected to the second gate G2, for example, in contact with a surface of the second gate G2 away from the substrate.
  • the storage node SN and the first electrode P1 may be connected to form an integrated structure.
  • the write transistor TR_W may include: a first gate G1, a first gate dielectric layer GM1 and a first semiconductor layer SE1, a first electrode P1 and a second electrode P2;
  • the first gate G1 is disposed above the storage node SN (ie, the storage node SN is away from the substrate); the first gate G1 extends in a direction perpendicular to the substrate;
  • the first gate dielectric layer GM1 is in contact with the first gate G1 and surrounds the outside of the first gate G1;
  • the first semiconductor layer GM1 contacts the first gate dielectric layer GM1 and surrounds the The first semiconductor layer GM1 surrounds the sidewall of the first gate G1 and the bottom wall of the first gate G1 close to the substrate;
  • the first electrode P1 is in contact with a surface of the first semiconductor layer SE1 close to the substrate, and is in contact with a surface of the second gate G2 away from the substrate;
  • the second pole P2 surrounds the sidewall of the first semiconductor layer SE1.
  • the first semiconductor layer SE1 is located on a side of the second electrode plate C2 away from the substrate, and is in contact with the second electrode plate C2.
  • the second pole P2 may be connected to the write bit line W_BL to form an integrated structure.
  • first pole P1 and the second pole plate C2 may be connected to form an integrated structure.
  • the write word line W_WL may be disposed on a side of the first gate G1 away from the substrate and in contact with a surface of the first gate G1 away from the substrate.
  • the write word line W_WL may be isolated from the first semiconductor layer SE1 by the first gate dielectric layer GM1.
  • the read bit line R_WL may be isolated from the second semiconductor layer SE2 by the second gate dielectric layer GM2 .
  • the read bit line R_BL and the write bit line W_BL may be connected to different signal terminals, or the read bit line R_BL and the write bit line W_BL may be connected through a via and then connected to the same signal terminal.
  • the via may be provided in a peripheral area.
  • the read bit line R_BL and the write bit line W_BL can be the same bit line
  • the second pole P2 and the third pole P3 are connected to the bit line
  • the bit line can be connected to the second pole P2 to form an integrated structure, or connected to the third pole P3 to form an integrated structure, for example, the bit line can be connected to the second pole P2 to form an integrated structure, in which case the third pole P3 is connected to the bit line through a via; or, the bit line can be connected to the third pole P3 to form an integrated structure, in which case the second pole P2 is connected to the bit line through a via.
  • the technical solution of this embodiment is further explained below through the preparation process of the storage unit of this embodiment.
  • the "patterning process” mentioned in this embodiment includes depositing a film layer, coating a photoresist, exposing a mask, developing, Etching, stripping of photoresist and other processes are mature preparation processes in related technologies.
  • the "photolithography process” mentioned in this embodiment includes coating film layer, mask exposure and development, which is a mature preparation process in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.
  • thin film refers to a layer of thin film made by a deposition or coating process of a certain material on a substrate. If the "thin film” does not require a composition process or a photolithography process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” still requires a composition process or a photolithography process during the entire production process, it is called a “thin film” before the composition process and a "layer” after the composition process. The "layer” after the composition process or the photolithography process contains at least one "pattern".
  • the manufacturing process of the storage unit may include:
  • the forming of the common electrode layer CG and the read bit line R_BL may include:
  • a second insulating film is deposited on the substrate forming the aforementioned structure to form a second insulating layer 12; the second insulating layer 12 covers the common electrode layer CG;
  • a third insulating film is deposited on the substrate forming the aforementioned structure to form a third insulating layer 13; as shown in FIG. 12A and FIG. 12B, where FIG. 12A is a cross-sectional view along the AA direction in FIG. 12B, and FIG. 12B is a top view after the read bit line R_BL is formed.
  • the common electrode layer CG can be used as the fourth electrode P4 of the read transistor TR_R, and a part of the read bit line R_BL can be used as the third electrode P3 of the read transistor TR_R.
  • the third electrodes P3 of the read transistors TR_R in the same column are connected to form a read bit line R_BL.
  • the second semiconductor layer SE2, the second gate dielectric layer GM2 and the second gate G2 may be formed.
  • the method comprises: depositing a fourth insulating film on the substrate forming the aforementioned structure to form a fourth insulating layer 14;
  • a first via hole is formed to expose the common electrode layer CG and penetrate the read bit line R_BL, the sidewall of the first via hole exposes the read bit line R_BL, and a second semiconductor film, a second gate dielectric film, and a second gate electrode film are sequentially deposited to form a second semiconductor layer SE2, a second gate dielectric layer GM2, and a second gate G2.
  • the second gate G2 can fill the first via hole.
  • the second gate dielectric layer GM2 is disposed between the second semiconductor layer SE2 and the second gate G2 to isolate the second semiconductor layer SE2 and the second gate G2.
  • FIGS. 13A and 13B A fifth insulating film is deposited on the substrate forming the aforementioned structure to form a fifth insulating layer 15, as shown in FIGS. 13A and 13B, wherein FIG. 13A is a cross-sectional view along the AA direction in FIG. 13B, and FIG. 13B is a top view after the fifth insulating layer 15 is formed.
  • the second semiconductor layer SE2 may be disposed on the sidewalls and the bottom wall of the first via hole, and on the surface of the fourth insulating layer 14 away from the substrate.
  • the second gate G2 may extend in a direction perpendicular to the substrate.
  • the second semiconductor layer SE2 contacts the common electrode layer CG and the read bit line R_BL, a portion of the common electrode layer CG serves as a fourth electrode P4 of the read transistor TR_R, and a portion of the read bit line R_BL serves as a third electrode P3 of the read transistor TR_R.
  • the orthographic projection of the first via hole may be a circle, but the embodiment of the present disclosure is not limited thereto, and may be a square or the like.
  • the read transistor TR_R including the third electrode P3, the fourth electrode P4, the second gate G2, the second gate dielectric layer GM2 and the second semiconductor layer SE2 is prepared.
  • the forming of the capacitor C may include: depositing a third conductive film on the substrate forming the aforementioned structure, patterning to form a second electrode C2, the second electrode C2 also serving as the storage node SN and the first electrode P1 of the write transistor TR_W; the second electrode C2 is in contact with the surface of the second gate G2 away from the substrate, and on a plane parallel to the substrate, the orthographic projection of the second gate G2 may be located within the orthographic projection of the second electrode C2, that is, the second electrode C2 covers the second gate G2 away from the substrate The surface on one side and a portion of the surface of the second gate dielectric layer GM2 away from the substrate.
  • a dielectric film is deposited on the substrate having the aforementioned structure to form a dielectric layer J; the dielectric layer J surrounds the side wall of the second electrode plate C2, covers the surface of the fifth insulating layer 15 away from the substrate and the surface of the second gate dielectric layer GM2 not covered by the second electrode plate C2, and exposes the surface of the second electrode plate C2 away from the substrate;
  • a fourth conductive film is deposited on the substrate forming the aforementioned structure to form a fourth conductive layer R_WL’, and a portion of the fourth conductive layer R_WL’ serves as a first electrode C1, as shown in FIGS. 14A and 14B , wherein FIG. 14A is a cross-sectional view along the AA direction in FIG. 14B , and FIG. 14B is a top view after the fourth conductive layer R_WL’ is formed.
  • the cross-section of the second electrode plate C2 may be circular, but the embodiments of the present disclosure are not limited thereto and may be other shapes, such as square.
  • the capacitor C including the first electrode plate 41, the dielectric layer J and the second electrode plate C2 is completed.
  • the forming of the read word line R_WL may include:
  • the fourth conductive layer R_WL' is patterned to form a read word line R_WL; a plurality of read word lines R_WL extending along the first direction X may be formed, and the first electrode plate C1 of the capacitor C connected to the read transistor TR_R in the same row is connected to form the read word line R_WL;
  • a sixth insulating film is deposited on the substrate forming the aforementioned structure to form a sixth insulating layer 16, as shown in Figures 15A and 15B, Figure 15A is a cross-sectional view along the AA direction in Figure 15B, and Figure 15B is a top view after the read word line R_WL is formed.
  • the sixth insulating layer 16 fills the etched area of the fourth conductive layer R_WL' to isolate multiple read word lines R_WL.
  • the forming of the write bit line W_BL may include:
  • a seventh insulating film is deposited on the substrate forming the aforementioned structure to form a seventh insulating layer 17; the seventh insulating layer 17 covers the dielectric layer J, the second electrode plate C2, the read word line R_WL and the sixth insulating layer 16;
  • FIG16A and FIG16B An eighth insulating film is deposited on the substrate forming the aforementioned structure to form an eighth insulating layer 18; as shown in FIG16A and FIG16B, where FIG16A is a cross-sectional view along the AA direction in FIG16B, and FIG16B is a top view after the write bit line W_BL is formed.
  • a portion of the write bit line W_BL can be used as the second electrode P2 of the write transistor TR_W.
  • the second electrodes P2 of the write transistors TR_W in the same column are connected to form a write bit line W_BL.
  • the forming of the write transistor TR_W and the write word line W_WL may include:
  • a second via hole is formed to expose the second electrode plate C2 and penetrate the write bit line W_BL, and the sidewall of the second via hole exposes the write bit line W_BL.
  • a first semiconductor film, a first gate dielectric film, and a first gate electrode film are sequentially deposited to form a first semiconductor layer SE1, a first gate dielectric layer GM1, and a first gate G1.
  • the first gate G1 can fill the second via hole.
  • the first gate dielectric layer GM1 is disposed between the first semiconductor layer SE1 and the first gate G1 to isolate the first semiconductor layer SE1 from the first gate G1.
  • An eleventh insulating film is deposited on the substrate having the aforementioned structure to form an eleventh insulating layer 21, as shown in Figures 17A and 17B, wherein Figure 17A is a cross-sectional view along the AA direction in Figure 17B, and Figure 17B is a top view after forming the write word line W_WL.
  • the eleventh insulating layer 21 isolates the plurality of write word lines W_WL.
  • the first semiconductor layer SE1 may be disposed on the sidewalls and the bottom wall of the second via hole, and on the surface of the eighth insulating layer 18 away from the substrate.
  • the first gate G1 may extend in a direction perpendicular to the substrate.
  • the first semiconductor layer SE1 contacts the second electrode plate C2 and the write bit line W_BL, a portion of the second electrode plate C2 serves as a first electrode P1 of the write transistor TR_W, and a portion of the write bit line W_BL serves as a second electrode P2 of the write transistor TR_W.
  • the positive The projection may be a circle, but the embodiment of the present disclosure is not limited thereto, and may be a square or the like.
  • the write transistor TR_W including the first electrode P1, the second electrode P2, the first gate G1, the first gate dielectric layer GM1 and the first semiconductor layer SE1 is prepared.
  • the embodiment of the present application further provides an electronic device 3, as shown in FIG. 18A and FIG. 18B, which may include the storage circuit 1, or the storage unit 2.
  • the electronic device may include any one or more of the following: a smart mobile terminal, a computer, a tablet computer, and a wearable device.
  • the smart mobile terminal may include but is not limited to smart phones, smart portable computers, etc.; it may also include any form of artificial robots; the wearable device may include but is not limited to smart watches, smart glasses, smart headphones, smart helmets, smart pocket watches, smart necklaces, smart rings, smart bracelets, etc.
  • Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium).
  • a computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data).
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer.
  • communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

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Abstract

L'invention concerne un circuit de stockage, une unité de stockage, un dispositif électronique et un procédé de lecture-écriture de données, se rapportant au domaine technique des semi-conducteurs. Le circuit de stockage comprend : un transistor d'écriture (TR_W), un transistor de lecture (TR_R) et un condensateur (C). Le transistor d'écriture (TR_W) comprend une première électrode (P1), une seconde électrode (P2) et une première grille (G1), la seconde électrode (P2) étant connectée à une ligne de bits d'écriture (W_BL), et la première grille (G1) étant connectée à une ligne de mots d'écriture (W_WL). Le transistor de lecture (TR_R) comprend une troisième électrode (P3), une quatrième électrode (P4) et une seconde grille (G2), la troisième électrode (P3) étant connectée à une ligne de bits de lecture (R_BL), la quatrième électrode (P4) étant connectée à une borne de tension de référence, et la seconde grille (G2) servant de nœud de stockage (SN) et étant connectée à la première électrode (P1). La première extrémité du condensateur (C) est connectée à une ligne de mots de lecture (R_WL), et la seconde extrémité est connectée au nœud de stockage (SN). Le condensateur (C) modifie la tension de grille du transistor de lecture au moyen d'un effet de couplage capacitif pendant une étape de lecture de données.
PCT/CN2023/092592 2022-11-15 2023-05-06 Circuit de stockage, unité de stockage, dispositif électronique et procédé de lecture-écriture de données WO2024103647A1 (fr)

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JP2001053164A (ja) * 1999-08-04 2001-02-23 Sony Corp 半導体記憶装置
JP2002093924A (ja) * 2000-09-20 2002-03-29 Sony Corp 半導体記憶装置
CN114709211A (zh) * 2022-04-02 2022-07-05 北京超弦存储器研究院 动态存储器及其制作、读写方法、电子设备、存储电路
CN114792735A (zh) * 2021-01-26 2022-07-26 华为技术有限公司 薄膜晶体管、存储器及制作方法、电子设备
WO2022241796A1 (fr) * 2021-05-21 2022-11-24 华为技术有限公司 Mémoire ferroélectrique et son procédé de commande, et dispositif électronique
WO2023102785A1 (fr) * 2021-12-08 2023-06-15 华为技术有限公司 Mémoire et procédé de fabrication de mémoire

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053164A (ja) * 1999-08-04 2001-02-23 Sony Corp 半導体記憶装置
JP2002093924A (ja) * 2000-09-20 2002-03-29 Sony Corp 半導体記憶装置
CN114792735A (zh) * 2021-01-26 2022-07-26 华为技术有限公司 薄膜晶体管、存储器及制作方法、电子设备
WO2022241796A1 (fr) * 2021-05-21 2022-11-24 华为技术有限公司 Mémoire ferroélectrique et son procédé de commande, et dispositif électronique
WO2023102785A1 (fr) * 2021-12-08 2023-06-15 华为技术有限公司 Mémoire et procédé de fabrication de mémoire
CN114709211A (zh) * 2022-04-02 2022-07-05 北京超弦存储器研究院 动态存储器及其制作、读写方法、电子设备、存储电路

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