CN116209248B - Dynamic memory, manufacturing method thereof, reading method thereof and storage device - Google Patents

Dynamic memory, manufacturing method thereof, reading method thereof and storage device Download PDF

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Publication number
CN116209248B
CN116209248B CN202210946203.4A CN202210946203A CN116209248B CN 116209248 B CN116209248 B CN 116209248B CN 202210946203 A CN202210946203 A CN 202210946203A CN 116209248 B CN116209248 B CN 116209248B
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electrode
substrate
layer
dynamic memory
accommodating hole
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CN116209248A (en
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朱正勇
康卜文
王桂磊
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the application provides a dynamic memory, a manufacturing method thereof, a reading and writing method thereof and a storage device. The dynamic memory includes: a device cell column on one side of the substrate and an isolation trench between adjacent device cell columns, the device cell column including a plurality of device cells including a drain electrode, a semiconductor layer, and a source electrode stacked in order in a direction away from the substrate, and first and second receiving holes between the device cells; a main gate electrode in the first receiving hole, electrically connected to the word line, and insulated from the source electrode and the drain electrode; the back grid electrode and the capacitor electrode are positioned in the second accommodating hole, the back grid electrode is electrically connected with the adjacent drain electrode, the capacitor electrode is electrically connected with the reference potential line, the back grid electrode and the capacitor electrode form a storage capacitor, and the back grid electrode and the source electrode form an auxiliary capacitor. The refresh frequency of the embodiment is lower, the noise immunity is strong, the peripheral detection circuit is convenient to design according to specific requirements, and the peripheral detection circuit has better adaptability.

Description

Dynamic memory, manufacturing method thereof, reading method thereof and storage device
Technical Field
The present application relates to the field of dynamic storage technologies, and in particular, to a dynamic memory, a manufacturing method, a reading method, and a storage device thereof.
Background
The dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory, and has the advantages of simpler structure, lower manufacturing cost and higher capacity density compared with the static memory.
DRAM memory typically includes a plurality of memory cells each including a transistor therein, which causes a gradual loss of charge stored in the memory cells due to leakage across the active layer, so that the stored data needs to be frequently refreshed to ensure the validity of the stored data.
In the current mainstream DRAM, in order to reduce the refresh rate, the conventional design is that the capacitor needs to be large enough, which makes the DRAM not compact in structure and low in integration level.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides a dynamic memory, a manufacturing method, a reading method and a storage device thereof, which are used for solving the technical problem that the refresh frequency and the integration level of the DRAM memory are difficult to be compatible in the prior art.
In a first aspect, embodiments of the present application provide a dynamic memory including a substrate, a plurality of word lines, a plurality of bit lines, a reference potential line, and a plurality of memory cells on the substrate, the dynamic memory including:
A plurality of device cell columns extending in a first direction and isolation grooves between adjacent device cell columns on one side of the substrate, the device cell columns including a plurality of device cells and accommodating holes between the device cells, the accommodating holes including first and second accommodating holes on both sides of the same device cell, the device cells including a drain electrode, a semiconductor layer, and a source electrode stacked in order in a direction away from the substrate;
a main gate electrode in the first receiving hole, electrically connected to the word line, and insulated from the source electrode and the drain electrode;
the back grid electrode is positioned on one side, close to the inner wall of the second accommodating hole, of the capacitor electrode, the back grid electrode is electrically connected with the adjacent drain electrode, the back grid electrode is insulated from the source electrode and the main grid electrode, the capacitor electrode is electrically connected with the reference potential line and is insulated from the main grid electrode, the back grid electrode, the source electrode and the drain electrode, wherein the back grid electrode and the capacitor electrode form a storage capacitor, and the back grid electrode and the source electrode form an auxiliary capacitor.
Optionally, two back gates are arranged in the second accommodating hole and distributed on two sides of the capacitor electrode; two adjacent memory cells in the same memory cell column share the same main gate and the same capacitor electrode.
Optionally, the device unit further includes a connection portion between the substrate and the drain electrode, and a first insulating layer located on a side of the source electrode away from the substrate, where the back gate and the drain electrode are both in contact with the connection portion; the dynamic memory further includes a first insulating structure filled in the isolation trench.
Optionally, the area where the substrate located right below the device unit is located is a first area, the area surrounding the first area is a second area, and the thickness of the substrate located in the first area is greater than the thickness of the substrate located in the second area.
Optionally, the dynamic memory further includes: and a third insulating structure positioned in the second accommodating hole and the second insulating structure, wherein the third insulating structure is contacted with the substrate and part of the side wall of the connecting part.
Optionally, the bit line extends along the first direction and is located on a side of the device unit away from the substrate, the word line extends along a second direction and is located on a side of the bit line away from the substrate, the reference potential line extends along the second direction and is arranged on the same layer as the bit line, and the second direction is perpendicular to the first direction.
Optionally, the substrate is made of a P-type silicon material, the connecting portion is made of an N-type heavily doped silicon material, the drain is made of an N-type silicon material, the source is made of an N-type silicon material, and the semiconductor layer is made of a silicon germanium material.
In a second aspect, an embodiment of the present application provides a storage device, where the storage device includes the dynamic memory described above.
In a third aspect, an embodiment of the present application provides a method for manufacturing a dynamic memory, where the method includes:
providing a substrate, and forming a device layer on the substrate by an epitaxial method;
forming a plurality of first accommodating holes penetrating through the device layer through a patterning process, and forming a main grid electrode in the first accommodating holes;
forming a plurality of second accommodating holes penetrating through the device layer through a patterning process, and sequentially forming a back grid electrode and a capacitor electrode in the second accommodating holes, wherein the first accommodating holes and the second accommodating holes are alternately arranged in a first direction;
forming a plurality of isolation trenches penetrating the device layer and extending in the first direction through a patterning process, the device layer being divided into a plurality of device units separated from each other by the first accommodating hole, the second accommodating hole and the isolation trenches, the device units including a drain electrode, a semiconductor layer and a source electrode stacked in sequence in a direction away from the substrate;
Forming a plurality of word lines, a plurality of bit lines and a plurality of reference potential lines through a composition process, wherein the main grid electrode is electrically connected with the word lines, the bit lines are electrically connected with the source electrode, and the capacitor electrode is electrically connected with the reference potential lines;
wherein the main gate is insulated from the source and the drain, the back gate is insulated from the source and the main gate, and the capacitor electrode is insulated from the main gate, the back gate, the source and the drain; the back gate and the capacitor electrode form a storage capacitor, and the back gate and the source electrode form an auxiliary capacitor.
Optionally, the device unit further includes a connection portion and a first insulating layer, a first receiving hole penetrating the device layer is formed through a patterning process, and a main gate is formed in the first receiving hole, including:
forming a spacer, a first sacrificial portion and a second sacrificial portion on the first insulating layer, wherein the orthographic projection of the first sacrificial portion on the substrate overlaps with the orthographic projection of the first accommodating hole on the substrate, and the orthographic projection of the second sacrificial portion on the substrate overlaps with the orthographic projection of the second accommodating hole on the substrate;
Removing the first sacrificial part and the device layer in the area where the first sacrificial part is located to form the first accommodating hole;
carrying out partial etching on the semiconductor material layer at the inner side wall of the first accommodating hole, and forming a first grid dielectric layer covering the inner wall of the first accommodating hole and the bottom of the first accommodating hole;
a second insulating structure is formed at the bottom in the first receiving hole, and the main gate is formed on the second insulating structure.
Optionally, forming a second accommodating hole penetrating through the device layer through a patterning process, and sequentially forming a back gate and a capacitor electrode in the second accommodating hole, including:
removing the second sacrificial part and the device layer in the area where the second sacrificial part is located to form the second accommodating hole;
forming a third insulating structure at the bottom in the second accommodating hole, and carrying out partial etching on the semiconductor material layer at the inner side wall of the second accommodating hole;
forming a second gate dielectric layer covering the inner wall of the second accommodating hole and the bottom of the second accommodating hole, and carrying out partial etching on the second gate dielectric layer to expose the third insulating structure and part of the connecting part;
Forming two back gates on the third insulating structure, wherein the two back gates are oppositely arranged in the first direction and are in contact with the connecting part and the second gate dielectric layer;
and forming a capacitance dielectric layer and a capacitance electrode in the second accommodating hole, wherein the capacitance dielectric layer is positioned between the back grid electrode and the capacitance electrode and covers the third insulation structure.
In a fourth aspect, an embodiment of the present application provides a method for reading and writing to and from the dynamic memory, where the method includes:
in a writing state, applying a first level to a main gate of a memory cell to be written through the word line to enable a transistor to be on, and transmitting a storage signal to a source of the memory cell to be written through a bit line to write the storage signal into the memory cell to be written as storage data;
in a read state, a second level is applied to the main gate of the memory cell to be read through the word line, so that the bit line senses the stored data of the memory cell to be read.
The beneficial technical effects that technical scheme that this application embodiment provided brought include:
1) The dynamic memory, the manufacturing method thereof, the reading and writing method thereof and the storage device provided by the embodiment have simple structure, wherein the back grid electrode and the source electrode form an auxiliary capacitor, so that the capacitance of the storage unit is increased, the storage node can be maintained for a longer time, and the refresh frequency of the dynamic memory is reduced while the integration level of the dynamic memory is ensured without increasing a film layer.
2) The dynamic memory, the manufacturing method thereof, the read-write method thereof and the storage device provided by the embodiment realize the patterning by utilizing the spacing part, the first sacrificial part and the second sacrificial part, so that the manufacturing method is simpler, and the subsequent transfer of the pattern is not needed, thereby improving the manufacturing precision.
3) According to the dynamic memory, the manufacturing method thereof, the reading and writing method thereof and the manufacturing method of the dynamic memory provided by the embodiment of the storage device, when a storage unit in the obtained dynamic memory is in a 1 state, a bit line can acquire a signal of a first node, and when the storage unit is in a 0 state, the bit line cannot acquire the signal of the first node, namely, the difference of data signals read by the bit line in the 1 state or the 0 state is large, so that the noise resistance of the dynamic memory is enhanced; compared with the prior art, the judgment of the '1' or '0' state of the memory unit can be realized only by detecting the output current of the transistor, and the embodiment can utilize current detection and voltage signal detection as no signal is detected in the '0' state, so that the peripheral detection circuit is conveniently designed according to specific requirements, and the method has better adaptability.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
The method comprises the following steps of
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic top view of a dynamic memory according to an embodiment of the present disclosure;
FIG. 2 is a schematic top view of another embodiment of a dynamic memory;
FIG. 3 is a schematic cross-sectional view of the dynamic memory of FIG. 2 along line A-A;
FIG. 4 is a schematic cross-sectional view of the dynamic memory of FIG. 2 along line A-A;
FIG. 5 is a schematic circuit diagram of a dynamic memory according to an embodiment of the present disclosure;
fig. 6 is a schematic circuit diagram of a memory cell in a dynamic memory according to an embodiment of the present application;
FIG. 7 is a graph of transfer characteristics of transistors in a dynamic memory when different data is written;
fig. 8 is a schematic diagram of a frame structure of a storage device according to an embodiment of the present disclosure;
FIG. 9 is a schematic flow chart of a method for fabricating a dynamic memory according to an embodiment of the present application;
Fig. 10 is a process schematic diagram of step S1 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 11 is a schematic flow chart of step S2 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 12 is a process schematic diagram of step S201 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 13 is a process schematic diagram of step S202 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 14 is a process schematic diagram of step S203 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 15 is a process schematic diagram of step S204 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 16 is a schematic flow chart of step S3 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 17 is a process schematic diagram of step S301 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 18 is a process schematic diagram of step S302 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 19 is a process schematic diagram of step S303 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 20 is a process schematic diagram of step S304 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
Fig. 21 is a process schematic diagram of step S305 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 22 is a flow chart of a method for reading and writing a dynamic memory according to an embodiment of the present application.
Reference numerals:
10-a memory cell; a T-transistor; c1-a storage capacitor; c2-auxiliary capacitance; BL-bit lines; WL-word line; vref—a reference potential line; an M-device layer;
101-a substrate; 102-a connection; 103-drain electrode; 104-a semiconductor layer; 105-source; 106-a first insulating layer; 107-spacers; 108-a first gate dielectric layer; 109-a second insulating structure; 110-a main gate; 111-a third insulating structure; 112-a second gate dielectric layer; 113-a back gate; 114-a capacitance dielectric layer; 115-capacitive electrode; 116-isolating the dielectric layer; 117-a first insulating structure; 118-a second insulating layer; 119-a first conductive layer; 120-a third insulating layer; 121-a second conductive layer;
102' -connecting layer; 103' -drain layer; a layer of 104' -semiconductor material; a 105' -source layer; 106' -a first layer of insulating material;
200-a first sacrificial portion; 300-a second sacrificial portion; 400-a first receiving hole; 500-a second receiving hole; 600-isolation trenches.
Detailed Description
Embodiments of the present application are described below with reference to the drawings in the present application. It should be understood that the embodiments described below with reference to the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and the technical solutions of the embodiments of the present application are not limited.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, information, data, steps, operations, elements, components, and/or groups thereof, etc. that may be implemented as desired in the art. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein refers to at least one of the items defined by the term, e.g., "a and/or B" may be implemented as "a", or as "B", or as "a and B".
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
DRAM memory typically includes a plurality of memory cells each including a transistor therein, which causes a gradual loss of charge stored in the memory cells due to leakage across the active layer, so that the stored data needs to be frequently refreshed to ensure the validity of the stored data. In the current mainstream DRAM, in order to reduce the refresh rate, the conventional design is that the capacitor needs to be large enough, which makes the DRAM not compact in structure and low in integration level.
The dynamic memory, the manufacturing method, the reading method and the storage device thereof aim to solve the technical problems in the prior art.
The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments. It should be noted that the following embodiments may be referred to, or combined with each other, and the description will not be repeated for the same terms, similar features, similar implementation steps, and the like in different embodiments.
The present application provides a dynamic memory, as shown in fig. 1 to 6, the dynamic memory provided in this embodiment includes a substrate 101, a plurality of word lines WL, a plurality of bit lines BL, a reference potential line Vref, and a plurality of memory cells 10 on the substrate 101. The dynamic memory includes:
A plurality of device cell columns 1000 extending in a first direction X and isolation grooves 600 between adjacent device cell columns on one side of the substrate 101, the device cell columns 1000 including a plurality of device cells 10 and receiving holes between the device cells, the receiving holes including first receiving holes 400 and second receiving holes 500 on both sides of the same device cell 10, the device cells 10 including a drain electrode 103, a semiconductor layer 104, and a source electrode 105 stacked in this order in a direction away from the substrate;
a main gate electrode 110 positioned in the first receiving hole 400, electrically connected to the word line WL, and insulated from the source electrode 105 and the drain electrode 103;
the back gate 113 and the capacitor electrode 115 are located in the second accommodating hole 500, the back gate 113 is located at one side of the capacitor electrode 115 close to the inner wall of the second accommodating hole 500, the back gate 113 is electrically connected with the adjacent drain 103, the back gate 113 is insulated from the source 105 and the main gate 110, the capacitor electrode 115 is electrically connected with the reference potential line Vref and insulated from the main gate 110, the back gate 113, the source 105 and the drain 103, wherein the back gate 113 and the capacitor electrode 115 form a storage capacitor C1, and the back gate 113 and the source 105 form an auxiliary capacitor C2.
Specifically, the isolation trench 600 is filled with a first insulation structure 117 for achieving insulation between adjacent device cell columns 1000. Specifically, in the implementation process, different arrangement modes can be selected according to specific storage capacity requirements and limitation on the space of the memory, namely, the optimal design of the storage capacity and the storage space can be realized by adjusting the number of the storage units 10 in each direction for design.
As shown in fig. 1 to 6, the source 105, the drain 103, the semiconductor layer 104, the main gate 110, the back gate 113, and the like provided in this embodiment form one transistor T, the capacitor electrode 115 and the back gate 113 form a storage capacitor C1, that is, each memory cell 10 includes one transistor T and one storage capacitor C1, and in this memory cell 10, the back gate 113 and the source 105 form an auxiliary capacitor C2, so that the capacitance of the memory cell 10 is increased, so that the storage node N1 can be maintained for a longer time, and thus the refresh frequency of the dynamic memory is reduced while the integration of the dynamic memory is ensured without increasing the film layer.
As shown in fig. 1 to 6, it is to be said that since the back gate 113 has a back gate effect, that is, the potential of the back gate 113 affects the threshold voltage of the transistor T, the magnitude of the voltage for turning on the transistor T when reading the stored data is between the threshold voltage when the transistor T stores "1" and the threshold voltage when the transistor T stores "0".
As shown in fig. 6 and 7, at the time of data writing, when a first level is applied to the main gate 110 through the word line WL, the transistor T is turned on, and a data signal inputted through the bit line BL is written to the first node N1, and when data writing is completed, the transistor T is turned off by adjusting the potential applied to the main gate 110 through the word line WL, and after the transistor T is turned off, the existence of the storage capacitor C1 and the auxiliary capacitor C2 can hold the potential of the first node N1 even though a leakage phenomenon is stored.
As shown in fig. 6 and 7, in the reading process, when the memory cell 10 is in the "1" state, the bit line BL can acquire the first node signal, and when the memory cell 10 is in the "0" state, the bit line BL cannot acquire the first node signal, that is, the difference between the data signals read by the bit line BL in the "1" or "0" states is large, so that the noise immunity of the dynamic memory is enhanced; compared with the prior art, the judgment of the "1" or "0" state of the memory cell 10 can be realized only by detecting the magnitude of the output current of the transistor T, and in this embodiment, the signal can be detected by using the current signal or the voltage signal because the signal cannot be detected in the "0" state, so that the peripheral detection circuit is conveniently designed according to specific requirements, and the peripheral detection circuit has better adaptability.
Optionally, as shown in fig. 3, in the dynamic memory provided in this embodiment, two back gates 113 are disposed in the second accommodating hole and distributed on two sides of the capacitor electrode 115; two memory cells 10 adjacent in the first direction X share the same main gate 110 and the same capacitor electrode 115.
Specifically, the main gate 110 and the capacitor electrode 115 in the dynamic memory provided in this embodiment can be shared by two adjacent memory cells 10, so that the integration level of the dynamic memory can be further improved.
Optionally, as shown in fig. 1 to 3, in the dynamic memory provided in this embodiment, the device unit further includes a connection portion 102 between the substrate 101 and the drain electrode 103, and a first insulating layer 106 located on a side of the source electrode 105 away from the substrate 101, where the back gate 113 and the drain electrode 103 are both in contact with the connection portion 102.
The main gate 110 and the capacitor electrode 115 in the dynamic memory provided in this embodiment can be shared by two adjacent memory cells 10, so that the electrical connection between the back gate 113 and the drain 103 by using the connection portion 102 can be further improved, and the connection portion 102 can be manufactured in the same etching process for manufacturing the source 105, the semiconductor layer 104 and the drain 103, so that the manufacturing method is simpler.
Alternatively, as shown in fig. 1 to 3, in the dynamic memory provided in this embodiment, the area where the substrate 101 located directly under the device unit is located is a first area, the area surrounding the first area is a second area, and the thickness of the substrate 101 located in the first area is greater than the thickness of the substrate 101 located in the second area. Specifically, the second area is the area where the first accommodation hole, the second accommodation hole and the isolation groove 600 are located.
In this embodiment, the substrate 101 in the area where the first accommodating hole, the second accommodating hole and the isolation trench 600 are located is partially etched, so that it can be ensured that the connection portion 102 on the substrate 101 is sufficiently etched, thereby preventing the connection portion 102 in the adjacent memory cell 10 from being connected by mistake, and reducing the risk of failure.
Optionally, as shown in fig. 1 to 3, the dynamic memory provided in this embodiment further includes a second insulating structure 109 located in the first accommodating hole and a third insulating structure 111 located in the second accommodating hole, where the third insulating structure 111 is in contact with the substrate 101 and a portion of the sidewall of the connection portion 102.
In the dynamic memory provided in this embodiment, the second insulating structure 109 and the third insulating structure 111 can further reduce the occurrence of erroneous connection of the connection portions 102102 in the adjacent memory cells 10, thereby further reducing the risk of failure.
Alternatively, as shown in fig. 1 to 3, in the dynamic memory provided in the present embodiment, the bit line BL extends along the second direction and is located on the side of the device unit away from the substrate 101, the word line WL extends along the first direction and is located on the side of the bit line BL away from the substrate 101, and the reference bit line Vref extends along the second direction and is disposed on the same layer as the bit line BL.
Specifically, the dynamic memory provided in this embodiment further includes a second insulating layer 118, a first conductive layer 119, a third insulating layer 120, and a second conductive layer 121. Wherein the second insulating layer 118 is located at a side of the spacer 107 away from the substrate 101, the first conductive layer 119 is located at a side of the second insulating layer 118 away from the substrate 101, and the first conductive layer 119 includes a plurality of bit lines BL and a plurality of reference potential lines Vref. The third insulating layer 120 is located on a side of the first conductive layer 119 away from the substrate 101, and is used for insulating the first conductive layer 119 from the second conductive layer 121. The second conductive layer 121 includes a plurality of word lines WL.
In the dynamic memory provided in this embodiment, the reference potential line Vref and the bit line BL are arranged in the same layer, which is beneficial to further simplifying the manufacturing method of the dynamic memory.
Alternatively, as shown in fig. 1 to 3, in the dynamic memory provided in this embodiment, the material of the substrate 101 is P-type silicon material, the material of the connection portion 102 is N-type heavily doped silicon material, the drain electrode 103 is N-type silicon material, the material of the source electrode 105 is N-type silicon material, and the material of the semiconductor layer 104 is silicon germanium material.
The transistor T of the semiconductor layer 104 made of the silicon germanium material can reduce the leakage current of the transistor T and reduce the loss speed of charges on the storage capacitor C1, so that the data storage time of the dynamic memory can be prolonged, and the refresh frequency and the power consumption of the dynamic memory can be reduced.
As shown in fig. 1 to 6, the dynamic memory provided in this embodiment further includes a first insulating layer 106 and a spacer 107, where the first insulating layer 106 is located on a side of the source 105 away from the substrate 101, and the spacer 107 is located on a side of the first insulating layer 106 away from the substrate 101. The spacer 107 is used as a mask to pattern the first insulating layer 106, the source electrode 105, the semiconductor layer 104, the drain electrode 103, and the like, and thus, it is not necessary to perform pattern transfer a plurality of times, which is advantageous in improving patterning accuracy.
As shown in fig. 1 to 6, the dynamic memory provided in this embodiment further includes a first gate dielectric layer 108, a second gate dielectric layer 112, a capacitor dielectric layer 114, and an isolation dielectric layer 116. The first gate dielectric layer 108 is located in the first accommodating hole 400 and covers the sidewall and the bottom of the first accommodating hole 400, so as to serve as an insulation function between the adjacent memory cells 10. The second gate dielectric layer 112 is located in the second accommodating hole 500 and covers the sidewalls of the second accommodating hole 500 that are disposed opposite to each other in the first direction X, and serves as an insulating material between the back gate 113 and the source 105, and also serves as a dielectric material between the back gate 113 and the auxiliary capacitor C2 formed by the source 105. The capacitor dielectric layer 114 is located in the second accommodating hole 500 and between the back gate 113 and the capacitor electrode 115, and is used as a dielectric material between the back gate 113 and the storage capacitor C1 formed by the capacitor electrode 115. Isolation dielectric layer 116 is located within isolation trench 600 and covers the sidewalls and bottom of isolation trench 600.
Based on the same inventive concept, the embodiment of the present application provides a storage device, as shown in fig. 8, where the storage device includes the dynamic memory in the foregoing embodiment, and has the beneficial effects of the dynamic memory in the foregoing embodiment, which is not described herein again. Specifically, the storage device in the embodiment of the present application may be a main memory of a computer, and may be specifically determined according to an actual situation.
Based on the same inventive concept, the embodiment of the present application provides a method for manufacturing a dynamic memory, as shown in fig. 9 to 21, including:
s1: a substrate 101 is provided, and a device layer M including a drain layer 103', a semiconductor material layer 104', and a source layer 105' stacked in this order in a direction away from the substrate 101 is formed on the substrate 101 by an epitaxial method.
Specifically, as shown in fig. 10, the device unit further includes a connection portion 102 and a first insulating layer 106', and step S1 includes: a connection layer 102', a drain layer 103', a semiconductor material layer 104', a source layer 105', and a first insulating material layer 106' are sequentially formed as a device layer M on a substrate 101 using an epitaxial growth method.
S2: the first receiving hole 400 penetrating the device layer M is formed through a patterning process, and the main gate electrode 110 is formed in the first receiving hole 400.
Specifically, as shown in fig. 11 to 15, taking an example based on the device layer M including the connection layer 102', the drain layer 103', the semiconductor material layer 104', the source layer 105', and the first insulating material layer 106', the step S2 includes:
s201: the spacer 107, the first sacrificial portion 200, and the second sacrificial portion 300 are formed on the first insulating layer 106, wherein an orthographic projection of the first sacrificial portion 200 on the substrate 101 overlaps an orthographic projection of the first receiving hole 400 on the substrate 101, and an orthographic projection of the second sacrificial portion 300 on the substrate 101 overlaps an orthographic projection of the second receiving hole 500 on the substrate 101. Specifically, the region corresponding to the spacer 107 is the region where the device unit is located.
S202: the first sacrificial portion 200 and the device layer M located in the region where the first sacrificial portion 200 is located are removed to form the first receiving hole 400. In order to avoid the situation that the connection layer 102' is not completely etched, the first receiving hole 400 needs to be etched to the substrate 101, that is, the substrate 101 in the area where the first sacrificial portion 200 is located is partially etched.
S203: the semiconductor material layer 104' layer at the inner sidewall of the first receiving hole 400 is partially etched, and then a first gate dielectric layer 108 is formed to cover the inner wall of the first receiving hole 400 and the bottom of the first receiving hole 400. The partial etching of the semiconductor material layer 104' enables the resulting semiconductor layer 104 to have corresponding dimensions, i.e. to achieve a design of the parameters of the semiconductor layer 104. The first gate dielectric layer 108 is used to isolate the main gate 110 from the source 105, the drain 103 and the semiconductor layer 104, such that the main gate 110 is insulated from the source 105, the drain 103.
S204: a second insulating structure 109 is formed at the bottom inside the first receiving hole 400, and a main gate 110 is formed on the second insulating structure 109. The second insulation structure 109 can further insulate the main gate 110 from the connection part 102.
S3: the second receiving hole 500 penetrating the device layer M is formed through a patterning process, and the back gate electrode 113 and the capacitor electrode 115 are sequentially formed in the second receiving hole 500.
Specifically, as shown in fig. 16 to 21, taking an example based on the device layer M including the connection layer 102', the drain layer 103', the semiconductor material layer 104', the source layer 105', and the first insulating material layer 106', the step S3 includes:
s301: the second sacrificial part 300 and the device layer M located in the region where the second sacrificial part 300 is located are removed to form the second receiving hole 500. In order to avoid the situation that the connection layer 102' is not completely etched, the second receiving hole 500 needs to be etched to the substrate 101, that is, the substrate 101 in the area where the second sacrificial portion 300 is located is partially etched.
S302: a third insulating structure 111 is formed at the bottom inside the second receiving hole 500, and the semiconductor material layer 104' at the inner sidewall of the second receiving hole 500 is partially etched. The local etching of the semiconductor material layer 104' enables the resulting semiconductor layer 104 to have corresponding dimensions, i.e. to achieve a design of the parameters of the semiconductor layer 104.
S303: a second gate dielectric layer 112 is formed to cover the inner wall of the second receiving hole 500 and the bottom of the second receiving hole 500, and the second gate dielectric layer 112 is partially etched to expose the third insulating structure 111 and a portion of the connection portion 102. The second gate dielectric layer 112 is used to isolate the back gate 113 from the source 105, the drain 103, and the semiconductor layer 104 such that the back gate 113 is insulated from the source 105.
S304: two back gates 113 are formed on the third insulating structure 111, and the two back gates 113 are disposed opposite to each other in the first direction and contact the connection portion 102 and the second gate dielectric layer 112. The two back gates 113 respectively belong to the transistors T in the adjacent two memory cells 10.
S305: a capacitive dielectric layer 114 and a capacitive electrode 115 are formed in the second accommodating hole 500, and the capacitive dielectric layer 114 is located between the back gate 113 and the capacitive electrode 115 and covers the third insulating structure 111. The capacitor dielectric layer 114 insulates the back gate electrode 113 and the capacitor electrode 115 and serves as a dielectric layer of the auxiliary capacitor C2 formed by the back gate electrode 113 and the capacitor electrode 115.
S4: a plurality of word lines WL, a plurality of bit lines BL, and a plurality of reference potential lines are formed through a patterning process, the main gate 110 is electrically connected to the word lines WL, the bit lines BL are electrically connected to the source 105, and the capacitor electrode 115 is electrically connected to the reference potential lines Vref.
Specifically, step S4 includes: forming a second insulating layer 118, forming a first conductive layer 119 on the second insulating layer 118, and performing patterning processing on the first conductive layer 119 to form a reference potential line Vref and a bit line BL; a third insulating layer 120 is formed, a second conductive layer 121 is formed on the third insulating layer 120, and the second conductive layer 121 is patterned to form word lines WL.
Specifically, the bit line BL extends in the second direction and is located on a side of the device cell away from the substrate 101, the word line WL extends in the first direction and is located on a side of the bit line BL away from the substrate 101, and the reference potential line Vref extends in the second direction and is disposed in the same layer as the bit line BL.
Specifically, the drain electrode 103' penetrated by the first and second receiving holes 400 and 500 forms the drain electrode 103, the semiconductor material layer 104' penetrated by the first and second receiving holes 400 and 500 forms the semiconductor layer 104, and the source electrode 105' penetrated by the first and second receiving holes 400 and 500 forms the source electrode 105; the main gate 110 is insulated from the source 104 and the drain 102, the back gate 113 is insulated from the source 104 and the main gate 110, and the capacitor electrode 115 is insulated from the main gate 110, the back gate 113, the source 104 and the drain 102; the back gate 113 and the capacitor electrode 115 constitute a storage capacitor C1, and the back gate 113 and the source 104 constitute an auxiliary capacitor C2.
The method for manufacturing the dynamic memory provided by the embodiment utilizes the spacer 107, the first sacrificial portion 200 and the second sacrificial portion 300 to realize patterning, so that the manufacturing method is simpler, and the subsequent transfer of the pattern is not needed, thereby improving the manufacturing precision.
According to the manufacturing method of the dynamic memory provided by the embodiment, the obtained dynamic memory has a simple structure, wherein the back gate 113 and the source 105 form the auxiliary capacitor C2, so that the capacitance of the memory cell 10 is increased, the storage node N1 can be maintained for a longer time, and the refresh frequency of the dynamic memory is reduced while the integration level of the dynamic memory is ensured without adding a film layer.
According to the manufacturing method of the dynamic memory, when the memory cell 10 in the obtained dynamic memory is in the 1 state, the bit line BL can acquire the signal of the first node N1, when the memory cell 10 is in the 0 state, the bit line BL can not acquire the signal of the first node N1, namely, the difference of data signals read by the bit line BL in the 1 state or the 0 state is huge, so that the noise resistance of the dynamic memory is enhanced; compared with the prior art, the judgment of the "1" or "0" state of the memory cell 10 can be realized only by detecting the magnitude of the output current of the transistor T, and in this embodiment, the signal can be detected by using the current signal or the voltage signal because the signal cannot be detected in the "0" state, so that the peripheral detection circuit is conveniently designed according to specific requirements, and the peripheral detection circuit has better adaptability.
Further, referring to fig. 1 to 3, the method for manufacturing a dynamic memory according to the present embodiment further includes: isolation trenches extending in the first direction X through the device layer M are formed by a patterning process, and the isolation trenches are filled with first insulating structures 117. Specifically, this step is located between step S3 and step S4.
Specifically, the isolation trenches extend along the first direction X to isolate two adjacent rows of memory cells 10, and in order to avoid the incomplete etching of the connection layer 102', the isolation trenches need to be etched to the substrate 101, i.e. the substrate 101 in the area where the isolation trenches are located is partially etched. To further enhance the isolation effect, an isolation dielectric layer is now formed in the isolation trench prior to filling the first insulating structure 117.
Based on the same inventive concept, the embodiments of the present application provide a read-write method for reading and writing the dynamic memory in the above embodiments, as shown in fig. 1 to 7 and 22, where the read-write method includes:
t1: in the writing state, a first level is applied to the main gate 110 of the memory cell 10 to be written through the word line WL to turn on the transistor T, and a storage signal is transmitted to the source 105 of the memory cell 10 to be written through the bit line BL to write the storage signal into the memory cell 10 to be written as storage data.
When the dynamic memory is in the writing operation mode, a first level (for example, 5V, a specific value may be adjusted according to the actual situation) is applied to the main gate 110 through the word line WL, so that the transistor T is in the on state, where the magnitude of the first level is related to factors such as the structure of the transistor T, the material of the active layer in the transistor T, and the like, and may be specifically adjusted according to the actual situation.
As shown in fig. 1 to 6, at the time of data writing, when a first level is applied to the main gate 110 through the word line WL, the transistor T is turned on, and a data signal inputted through the bit line BL is written to the first node N1, and when data writing is completed, the transistor T is turned off by adjusting the potential applied to the main gate 110 through the word line WL, and after the transistor T is turned off, the existence of the storage capacitor C1 and the auxiliary capacitor C2 can hold the potential of the first node N1 even though a leakage phenomenon is stored.
Since the back gate 114 and the source 105 constitute the auxiliary capacitance C2, even if the transistor TT is turned to an off state after the data writing is completed, the electric charge stored in the auxiliary capacitance C2 can enable the electric potential of the first node N1 (i.e., the back gate 114, the drain 103, and the second electrode of the storage capacitance C1) to be maintained for a longer time, thereby reducing the refresh frequency.
T2: in the read state, a second level is applied to the main gate 110 of the memory cell 10 to be read through the word line WL so that the bit line BL senses the stored data of the memory cell 10 to be read.
As shown in fig. 1 to 3, when the second level is applied to the main gate 110 during data reading, if the memory cell 10 is in the "1" state, the main gate 110 is turned on at the second level (for example, the main gate 110 potential vg=0.3v, and the source 105 potential vs=0) to acquire the signal of the first node; if the memory cell 10 is in the "0" state, the transistor T is not turned on under the same gate and source 105 bias, i.e., the signal of the first node cannot be detected.
During the read/write process of the dynamic memory, the reference potential is supplied to the reference potential line Vref. In one embodiment, the reference potential is a selected ground level.
The present embodiment provides a reading method, which can adopt either a current detection method or a voltage detection method. For example, when the memory cell 10 has previously stored data "1", the back gate 113 and the drain 103 have a higher potential, and the transistor T is turned on under the combined action of the second level, so that a more significant current can be measured through the bit line BL. When a more significant current is measured, the read data is judged to be "1". When the data "0" is stored in the memory cell 10 before, the transistor T is still in the off state after the second level is applied to the main gate 110, so that it can be considered that the bit line BL does not detect the current, and the read data is judged to be "0".
It should be noted that, in the N-type field effect transistor T (the carrier is an electron when the transistor T is turned on), the higher the voltage of the back gate 113 and the drain 103, the smaller the threshold voltage, i.e., the smaller the voltage difference between the main gate 110 and the source 105, the transistor T can be turned on; the lower the potential on the back gate 113 and drain 103, the greater the threshold voltage.
As shown in fig. 7, the abscissa in fig. 7 is the voltage (i.e., the second level) applied to the main gate 110, and the ordinate is the output current of the transistor T. When the second level applied to the main gate 110 is a specific value (indicated by the dotted line in fig. 7), the voltage on the back gate 113 and the drain 103 (i.e., whether the data written by the transistor T is "1" or "0") will significantly differ in the magnitude of the output current of the transistor T (i.e., the current measured through the bit line BL). Reading data from the memory cell 10 can be achieved by detecting the current on the bit line BL, and when the transistor T writes data "1", the output current of the transistor T is larger, so the read data is also "1"; when the data written by the transistor T is "0", the output current of the transistor T is extremely weak, and thus the read data is also "0".
The value of the second level may be determined according to the parameters of the transistor T and the magnitude of the voltage applied to the back gate 113 and the drain 103 when performing a write operation. It should be noted that, the value of the second level needs to be appropriate (between the threshold voltage when the transistor T stores "1" and the threshold voltage when the transistor T stores "0"), otherwise there may be a risk that the transistor T is turned on or off by mistake, which affects the performance of the dynamic memory. Specifically, the most suitable value of the second level may be determined by an experimental or analog method to ensure that the transistor T is correctly turned on or off in different states, so as to improve the reading performance.
As can be seen from the above description, in the dynamic memory provided in this embodiment, during the reading process, the bit line BL can acquire the first node signal when the memory cell 10 is in the "1" state, and the bit line BL cannot acquire the first node signal when the memory cell 10 is in the "0" state, that is, the difference between the data signals read by the bit line BL in the "1" or "0" states is large, so that the noise resistance of the dynamic memory is enhanced; compared with the prior art, the judgment of the "1" or "0" state of the memory cell 10 can be realized only by detecting the magnitude of the output current of the transistor T, and in this embodiment, the signal can be detected by using the current signal or the voltage signal because the signal cannot be detected in the "0" state, so that the peripheral detection circuit is conveniently designed according to specific requirements, and the peripheral detection circuit has better adaptability.
By applying the embodiment of the application, at least the following beneficial effects can be realized:
1) The dynamic memory, the manufacturing method thereof, the read-write method thereof and the storage device provided by the embodiment realize the patterning by utilizing the spacing part, the first sacrificial part and the second sacrificial part, so that the manufacturing method is simpler, and the subsequent transfer of the pattern is not needed, thereby improving the manufacturing precision.
2) The dynamic memory, the manufacturing method thereof, the reading and writing method thereof and the storage device provided by the embodiment have simple structure, wherein the back grid electrode and the source electrode form an auxiliary capacitor, so that the capacitance of the storage unit is increased, the storage node can be maintained for a longer time, and the refresh frequency of the dynamic memory is reduced while the integration level of the dynamic memory is ensured without increasing a film layer.
3) According to the dynamic memory, the manufacturing method thereof, the reading and writing method thereof and the manufacturing method of the dynamic memory provided by the embodiment of the storage device, when a storage unit in the obtained dynamic memory is in a 1 state, a bit line can acquire a signal of a first node, and when the storage unit is in a 0 state, the bit line cannot acquire the signal of the first node, namely, the difference of data signals read by the bit line in the 1 state or the 0 state is large, so that the noise resistance of the dynamic memory is enhanced; compared with the prior art, the judgment of the '1' or '0' state of the memory unit can be realized only by detecting the output current of the transistor, and the embodiment can utilize current detection and voltage signal detection as no signal is detected in the '0' state, so that the peripheral detection circuit is conveniently designed according to specific requirements, and the method has better adaptability.
The embodiments of the present application also provide a computer program product, which includes a computer program, where the computer program can implement the steps of the foregoing method embodiments and corresponding content when executed by a processor.
Those of skill in the art will appreciate that the various operations, methods, steps in the flow, actions, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed in this application may be alternated, altered, rearranged, split, combined, or eliminated. Further, steps, measures, schemes in the prior art with various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are based on the exemplary directions or positional relationships shown in the drawings, are for convenience of description or simplifying the description of the embodiments of the present application, and do not indicate or imply that the apparatus or components referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the order in which the steps are performed is not limited to the order indicated by the arrows. In some implementations of embodiments of the present application, the steps in each flow may be performed in other orders as desired, unless explicitly stated herein. Moreover, some or all of the steps in the flowcharts may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of the sub-steps or stages may be executed at the same time, or may be executed at different times, where the execution sequence of the sub-steps or stages may be flexibly configured according to the requirements, which is not limited by the embodiment of the present application.
The foregoing is only a part of the embodiments of the present application, and it should be noted that, for those skilled in the art, other similar implementation means based on the technical ideas of the present application are adopted without departing from the technical ideas of the solutions of the present application, and also belong to the protection scope of the embodiments of the present application.

Claims (12)

1. A dynamic memory comprising a substrate, a plurality of word lines, a plurality of bit lines, a reference potential line, and a plurality of memory cells on the substrate, the dynamic memory comprising:
a plurality of device cell columns extending in a first direction and isolation grooves between adjacent device cell columns on one side of the substrate, the device cell columns including a plurality of device cells and accommodating holes between the device cells, the accommodating holes including first and second accommodating holes on both sides of the same device cell, the device cells including a drain electrode, a semiconductor layer, and a source electrode stacked in order in a direction away from the substrate;
a main gate electrode in the first receiving hole, electrically connected to the word line, and insulated from the source electrode and the drain electrode;
the back grid electrode is positioned on one side, close to the inner wall of the second accommodating hole, of the capacitor electrode, the back grid electrode is electrically connected with the adjacent drain electrode, the back grid electrode is insulated from the source electrode and the main grid electrode, the capacitor electrode is electrically connected with the reference potential line and is insulated from the main grid electrode, the back grid electrode, the source electrode and the drain electrode, wherein the back grid electrode and the capacitor electrode form a storage capacitor, and the back grid electrode and the source electrode form an auxiliary capacitor.
2. The dynamic memory of claim 1, wherein two back gates are disposed in the second accommodating hole and distributed on both sides of the capacitor electrode; two adjacent memory cells in the same memory cell column share the same main gate and the same capacitor electrode.
3. The dynamic memory of claim 2, wherein,
the device unit further comprises a connecting part and a first insulating layer, wherein the connecting part is positioned between the substrate and the drain electrode, the first insulating layer is positioned on one side of the source electrode far away from the substrate, and the back grid electrode and the drain electrode are both contacted with the connecting part;
the dynamic memory further includes a first insulating structure filled in the isolation trench.
4. A dynamic memory as claimed in claim 3, wherein the area of the substrate directly under the device unit is a first area, the area surrounding the first area is a second area, and the thickness of the substrate in the first area is greater than the thickness of the substrate in the second area.
5. The dynamic memory of any one of claims 1-4, further comprising: and a third insulating structure positioned in the second accommodating hole and the second insulating structure, wherein the third insulating structure is contacted with the substrate and part of the side wall of the connecting part.
6. The dynamic memory of claim 5, wherein the bit line extends in the first direction and is located on a side of the device cell away from the substrate, the word line extends in a second direction and is located on a side of the bit line away from the substrate, and the reference bit line extends in the second direction and is co-located with the bit line, the second direction being perpendicular to the first direction.
7. The dynamic memory of claim 3, wherein,
the substrate is made of a P-type silicon material, the connecting portion is made of an N-type heavily doped silicon material, the drain electrode is made of an N-type silicon material, the source electrode is made of an N-type silicon material, and the semiconductor layer is made of a silicon germanium material.
8. A memory device comprising the dynamic memory of any one of claims 1-7.
9. A method for manufacturing a dynamic memory, comprising:
providing a substrate, and forming a device layer on the substrate by an epitaxial method, wherein the device layer comprises a drain electrode layer, a semiconductor material layer and a source electrode layer which are sequentially stacked in a direction away from the substrate;
forming a plurality of first accommodating holes penetrating through the device layer through a patterning process, and forming a main grid electrode in the first accommodating holes;
Forming a plurality of second accommodating holes penetrating through the device layer through a patterning process, and sequentially forming a back grid electrode and a capacitor electrode in the second accommodating holes, wherein the first accommodating holes and the second accommodating holes are alternately arranged in a first direction;
forming a plurality of isolation trenches penetrating the device layer and extending in the first direction through a patterning process, the device layer being divided into a plurality of device units separated from each other by the first accommodating hole, the second accommodating hole and the isolation trenches, the device units including a drain electrode, a semiconductor layer and a source electrode stacked in sequence in a direction away from the substrate;
forming a plurality of word lines, a plurality of bit lines and a plurality of reference potential lines through a composition process, wherein the main grid electrode is electrically connected with the word lines, the bit lines are electrically connected with the source electrode, and the capacitor electrode is electrically connected with the reference potential lines;
wherein the main gate is insulated from the source and the drain, the back gate is insulated from the source and the main gate, and the capacitor electrode is insulated from the main gate, the back gate, the source and the drain; the back gate and the capacitor electrode form a storage capacitor, and the back gate and the source electrode form an auxiliary capacitor.
10. The method of fabricating a dynamic memory of claim 9, wherein the device unit further comprises a connection portion and a first insulating material layer, a first receiving hole penetrating the device layer is formed through a patterning process, and a main gate is formed in the first receiving hole, comprising:
forming a spacer, a first sacrificial portion and a second sacrificial portion on the first insulating material layer, wherein an orthographic projection of the first sacrificial portion on the substrate overlaps an orthographic projection of the first accommodating hole on the substrate, and an orthographic projection of the second sacrificial portion on the substrate overlaps an orthographic projection of the second accommodating hole on the substrate;
removing the first sacrificial part and the device layer in the area where the first sacrificial part is located to form the first accommodating hole;
carrying out partial etching on the semiconductor material layer at the inner side wall of the first accommodating hole, and forming a first grid dielectric layer covering the inner wall of the first accommodating hole and the bottom of the first accommodating hole;
a second insulating structure is formed at the bottom in the first receiving hole, and the main gate is formed on the second insulating structure.
11. The method of claim 10, wherein forming a second accommodating hole through the device layer by patterning, and sequentially forming a back gate and a capacitor electrode in the second accommodating hole, comprises:
Removing the second sacrificial part and the device layer in the area where the second sacrificial part is located to form the second accommodating hole;
forming a third insulating structure at the bottom in the second accommodating hole, and carrying out partial etching on the semiconductor material layer at the inner side wall of the second accommodating hole;
forming a second gate dielectric layer covering the inner wall of the second accommodating hole and the bottom of the second accommodating hole, and carrying out partial etching on the second gate dielectric layer to expose the third insulating structure and part of the connecting part;
forming two back gates on the third insulating structure, wherein the two back gates are oppositely arranged in the first direction and are in contact with the connecting part and the second gate dielectric layer;
and forming a capacitance dielectric layer and a capacitance electrode in the second accommodating hole, wherein the capacitance dielectric layer is positioned between the back grid electrode and the capacitance electrode and covers the third insulation structure.
12. A method for reading from and writing to the dynamic memory of any one of claims 1-7, the method comprising:
in a writing state, applying a first level to a main gate of a memory cell to be written through the word line to enable a transistor to be on, and transmitting a storage signal to a source of the memory cell to be written through a bit line to write the storage signal into the memory cell to be written as storage data;
In a read state, a second level is applied to the main gate of the memory cell to be read through the word line, so that the bit line senses the stored data of the memory cell to be read.
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