WO2024032123A1

WO2024032123A1 - Memory cell and manufacturing method therefor, and dynamic memory, storage apparatus and read-write method

Info

Publication number: WO2024032123A1
Application number: PCT/CN2023/098858
Authority: WO
Inventors: 朱正勇; 康卜文; 王桂磊; 赵超
Original assignee: 北京超弦存储器研究院
Priority date: 2022-08-08
Filing date: 2023-06-07
Publication date: 2024-02-15
Also published as: CN116209247A; CN116209247B

Abstract

Provided in the embodiments of the present application are a memory cell and a manufacturing method therefor, and a dynamic memory, a storage apparatus and a read-write method. In the memory cell, a source electrode, a drain electrode, a semiconductor layer, a main gate electrode, a back gate electrode, etc. for a transistor, and a capacitor electrode and the back gate electrode form a storage capacitor. In the memory cell, the back gate electrode and the source electrode form an auxiliary capacitor for increasing the capacitance of the memory cell, thereby facilitating the reduction of the refresh frequency of a dynamic memory. During the process of reading the dynamic memory, data signals which are read by means of a bit line in a state "1" and a state "0" have a great difference, thereby enhancing the anti-noise performance of the dynamic memory; and no signal can be detected in the state "0", and therefore state determination can be realized by means of measuring a current or measuring a voltage, thereby facilitating the design of a peripheral measurement circuit according to specific requirements.

Description

存储单元及制作方法、动态存储器、存储装置、读写方法Storage unit and manufacturing method, dynamic memory, storage device, reading and writing method

本申请要求于2022年08月08日提交至中国国家知识产权局、申请号为202210945146.8、发明名称为“动态存储器、其制作方法、读取方法及存储装置”的专利申请的优先权。This application requests the priority of the patent application submitted to the State Intellectual Property Office of China on August 8, 2022, with the application number 202210945146.8 and the invention title "Dynamic Memory, Its Production Method, Reading Method and Storage Device".

技术领域Technical field

本申请涉及存储技术领域，具体而言，本申请涉及一种存储单元及制作方法、动态存储器、存储装置、读写方法。This application relates to the field of storage technology. Specifically, this application relates to a storage unit and a manufacturing method, a dynamic memory, a storage device, and a reading and writing method.

背景技术Background technique

动态随机存取存储器(Dynamic Random Access Memory，DRAM)是一种半导体存储器，和静态存储器相比，DRAM存储器具有结构较为简单、制造成本较低、容量密度较高的优点。Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared with static memory, DRAM memory has the advantages of simpler structure, lower manufacturing cost, and higher capacity density.

发明内容Contents of the invention

本申请提出一种存储单元及制作方法、动态存储器、存储装置、读写方法。This application proposes a storage unit and a manufacturing method, a dynamic memory, a storage device, and a reading and writing method.

第一个方面，本申请实施例提供了一种存储单元，包括：In a first aspect, embodiments of the present application provide a storage unit, including:

位于衬底上且呈柱状的电容电极，所述电容电极与参考电位线电连接；A columnar capacitance electrode located on the substrate, the capacitance electrode being electrically connected to the reference potential line;

位于所述电容电极与所述衬底之间且环绕所述电容电极的背栅极，所述背栅极与所述电容电极绝缘且与所述电容电极构成存储电容；a back gate located between the capacitor electrode and the substrate and surrounding the capacitor electrode, the back gate being insulated from the capacitor electrode and forming a storage capacitor with the capacitor electrode;

位于所述衬底的一侧且在远离所述衬底的方向上依次堆叠的漏极、半导体层和源极，所述漏极、所述半导体层和所述源极环绕所述电容电极且位于所述背栅极远离所述电容电极的一侧，所述漏极、半导体层和源极在平行于所述衬底的截面为环形，所述漏极与所述背栅极电连接，所述背栅极与所述源极构成辅助电容；A drain electrode, a semiconductor layer and a source electrode located on one side of the substrate and sequentially stacked in a direction away from the substrate, the drain electrode, the semiconductor layer and the source electrode surrounding the capacitor electrode and Located on the side of the back gate away from the capacitor electrode, the drain electrode, semiconductor layer and source electrode are annular in cross-section parallel to the substrate, and the drain electrode is electrically connected to the back gate electrode, The back gate and the source form an auxiliary capacitor;

环绕所述半导体层的外侧壁的主栅极，所述主栅极与字线电连接且与所述源极和所述漏极绝缘。A main gate surrounding the outer sidewall of the semiconductor layer, the main gate being electrically connected to the word line and insulated from the source and the drain.

可选地，所述存储单元还包括连接部，所述连接部位于所述衬底和所述漏极之间且位于所述衬底和所述背栅极之间，所述连接部直接与所述漏极接触同时与所述背栅极接触，所述连接部的材料为导电材料；所述连接部在所述衬底上的正投影所在的区域为第一区域，包围所述第一区域的区域为第二区域，位于所述第一区域的所述衬底的厚度大于位于所述第二区域的所述衬底的厚度。Optionally, the memory unit further includes a connection portion located between the substrate and the drain electrode and between the substrate and the back gate, and the connection portion is directly connected to The drain contact is in contact with the back gate at the same time, and the material of the connection part is a conductive material; the area where the orthographic projection of the connection part on the substrate is the first area, surrounding the first The area of the area is a second area, and the thickness of the substrate located in the first area is greater than the thickness of the substrate located in the second area.

可选地，所述存储单元还包括：Optionally, the storage unit also includes:

位于所述源极远离所述衬底一侧的第一绝缘层；a first insulating layer located on the side of the source electrode away from the substrate;

位于所述第一绝缘层远离所述衬底一侧的侧墙；Sidewalls located on the side of the first insulating layer away from the substrate;

所述侧墙、所述第一绝缘层、所述源极以及所述漏极在所述衬底上的正投影重合，所述半导体层在所述衬底上的正投影位于所述漏极在所述衬底上的正投影内，所述漏极在所述衬底上的正投影位于所述连接部在所述衬底上的正投影内。The orthographic projections of the sidewalls, the first insulating layer, the source electrode and the drain electrode on the substrate coincide with each other, and the orthographic projection of the semiconductor layer on the substrate is located on the drain electrode. Within the orthographic projection of the substrate, the orthographic projection of the drain on the substrate is located within the orthographic projection of the connection portion on the substrate.

可选地，所述侧墙、所述第一绝缘层、所述源极、所述半导体层以及所述漏极均为环形，所述半导体层的内径大于所述漏极的内径，且所述半导体层的外径小于所述漏极的外径。Optionally, the sidewalls, the first insulating layer, the source electrode, the semiconductor layer and the drain electrode are all annular, the inner diameter of the semiconductor layer is greater than the inner diameter of the drain electrode, and the The outer diameter of the semiconductor layer is smaller than the outer diameter of the drain electrode.

可选地，所述主栅极位于所述源极和所述漏极之间，所述字线与所述主栅极材料相同且与所述主栅极接触，所述字线在所述衬底上的正投影位于所述第二区域；所述参考电位线位于所述电容电极远离所述衬底的一侧且与所述电容电极接触；位线位于所述参考电位线远离所述衬底的一侧且通过过孔与所述源极电连接。Optionally, the main gate is located between the source and the drain, the word line is made of the same material as the main gate and is in contact with the main gate, and the word line is in the The orthographic projection on the substrate is located in the second area; the reference potential line is located on a side of the capacitor electrode away from the substrate and is in contact with the capacitor electrode; the bit line is located on the reference potential line away from the One side of the substrate is electrically connected to the source through a via hole.

可选地，所述衬底的材料为P型硅材料，所述连接部的材料为N型重掺杂硅材料，所述漏极为N型硅材料，所述源极的材料为N型硅材料，所述半导体层的材料为锗化硅材料。Optionally, the material of the substrate is P-type silicon material, and the material of the connection part is N-type heavily doped silicon material, The drain is made of N-type silicon material, the source electrode is made of N-type silicon material, and the semiconductor layer is made of silicon germanium material.

第一栅极介质层，位于所述连接部、所述漏极、所述半导体层、所述源极和所述第一绝缘层的外侧壁以及位于所述第二区域的所述衬底上；A first gate dielectric layer located on the connecting portion, the drain electrode, the semiconductor layer, the source electrode and the outer sidewalls of the first insulating layer and on the substrate in the second region ;

第二绝缘层，位于所述第二区域且位于所述第一栅极介质层远离所述衬底的一侧；a second insulating layer located in the second region and on the side of the first gate dielectric layer away from the substrate;

第二栅极介质层，位于所述连接部、所述漏极、所述半导体层、所述源极和所述第一绝缘层的内侧壁；A second gate dielectric layer is located on the inner sidewalls of the connection part, the drain electrode, the semiconductor layer, the source electrode and the first insulating layer;

电容介质层，位于所述背栅极和所述电容电极之间；A capacitive dielectric layer located between the back gate and the capacitive electrode;

第三绝缘层，位于所述字线远离所述衬底的一侧；A third insulating layer located on the side of the word line away from the substrate;

第四绝缘层，位于所述第二栅极介质层和所述电容介质层之间且位于所述背栅极远离所述衬底的一侧；A fourth insulating layer, located between the second gate dielectric layer and the capacitive dielectric layer and located on the side of the back gate away from the substrate;

第五绝缘层，填充所述字线以及所述第三绝缘层的侧面；A fifth insulating layer, filling the word lines and the sides of the third insulating layer;

第六绝缘层，位于所述参考电位线所在导电层和所述位线所在导电层之间。A sixth insulating layer is located between the conductive layer where the reference potential line is located and the conductive layer where the bit line is located.

第二个方面，本申请实施例提供了一种动态存储器，包括：衬底、位于所述衬底上的多条字线、多条位线、多条参考电位线和多个上述的存储单元；In a second aspect, embodiments of the present application provide a dynamic memory, including: a substrate, a plurality of word lines, a plurality of bit lines, a plurality of reference potential lines and a plurality of the above-mentioned memory cells located on the substrate. ;

多个所述存储单元分为多个存储单元组，多个所述存储单元组在垂直于所述衬底的方向上排布；A plurality of the memory cells are divided into a plurality of memory unit groups, and the plurality of memory unit groups are arranged in a direction perpendicular to the substrate;

每个所述存储单元组包括多个在平行于所述衬底的方向上呈阵列排布的存储单元，其中位于同一行的各所述存储单元与同一字线电连接，位于同一列的各所述存储单元与同一位线电连接。Each memory cell group includes a plurality of memory cells arranged in an array in a direction parallel to the substrate, wherein each memory cell located in the same row is electrically connected to the same word line, and each memory cell located in the same column is electrically connected to the same word line. The memory cells are electrically connected to the same bit line.

第三个方面，本申请实施例提供了一种存储装置，该存储装置包括上述的动态存储器。In a third aspect, embodiments of the present application provide a storage device, which includes the above-mentioned dynamic memory.

第四个方面，本申请实施例提供了一种存储单元的制作方法，所述制作方法包括：In a fourth aspect, embodiments of the present application provide a method of manufacturing a memory unit. The manufacturing method includes:

提供一衬底，通过构图工艺在所述衬底的一侧形成依次堆叠的漏极层、半导体材料层和源极层，所述漏极层、半导体材料层和源极层为圆柱形；Provide a substrate, and form a sequentially stacked drain layer, semiconductor material layer and source layer on one side of the substrate through a patterning process, where the drain layer, semiconductor material layer and source layer are cylindrical;

形成环绕所述半导体层的主栅极，所述主栅极与字线电连接且与所述源极层和所述漏极层绝缘；forming a main gate surrounding the semiconductor layer, the main gate being electrically connected to the word line and insulated from the source layer and the drain layer;

通过构图工艺形成贯穿所述漏极层、所述半导体材料层和所述源极层的容纳孔，其中，被所述容纳孔贯穿后的所述漏极层形成漏极，被所述容纳孔贯穿后的所述半导体材料层形成半导体层，被所述容纳孔贯穿后的所述源极层形成源极；A receiving hole penetrating the drain layer, the semiconductor material layer and the source layer is formed through a patterning process, wherein the drain layer penetrated by the receiving hole forms a drain electrode, and the receiving hole is The semiconductor material layer penetrated forms a semiconductor layer, and the source electrode layer penetrated by the accommodation hole forms a source electrode;

在所述容纳孔内依次形成背栅极和电容电极，所述电容电极与参考电位线电连接且与所述源极、所述漏极、所述主栅极和所述背栅极绝缘，其中，所述电容电极与所述背栅极构成存储电容，所述背栅极与所述源极构成辅助电容。A back gate and a capacitor electrode are sequentially formed in the accommodation hole, and the capacitor electrode is electrically connected to the reference potential line and insulated from the source, the drain, the main gate and the back gate, Wherein, the capacitor electrode and the back gate electrode form a storage capacitor, and the back gate electrode and the source electrode form a auxiliary capacitor.

可选地，所述存储单元还包括位于所述衬底和所述漏极之间的连接部以及位于所述源极远离所述衬底一侧的第一绝缘层，所述连接部直接与所述漏极接触同时与所述背栅极接触，所述连接部的材料为导电材料；Optionally, the memory unit further includes a connection portion between the substrate and the drain electrode and a first insulating layer located on a side of the source electrode away from the substrate, and the connection portion is directly connected to The drain contact is in contact with the back gate at the same time, and the material of the connection part is a conductive material;

通过构图工艺在所述衬底的一侧形成依次堆叠的漏极层、半导体材料层和源极层，包括：A sequentially stacked drain layer, semiconductor material layer and source layer are formed on one side of the substrate through a patterning process, including:

通过外延生长法在所述衬底上依次生长连接层、所述漏极层、半导体材料层、源极层和第一绝缘材料层；Sequentially grow the connection layer, the drain layer, the semiconductor material layer, the source layer and the first insulating material layer on the substrate through an epitaxial growth method;

通过构图工艺在所述第一绝缘材料层远离所述衬底的一侧形成多个侧墙和位于各所述侧墙内的牺牲部，其中，所述侧墙和所述牺牲部所在的区域为第一区域，包围所述第一区域的区域为第二区域； A plurality of sidewalls and sacrificial portions located in each sidewall are formed on the side of the first insulating material layer away from the substrate through a patterning process, wherein the area where the sidewalls and the sacrificial portion are located is the first area, and the area surrounding the first area is the second area;

依据所述侧墙对所述第一绝缘材料层、所述源极层、所述半导体材料层、所述漏极层进行刻蚀，以形成圆柱形的所述第一绝缘材料层、所述源极层、所述半导体材料层、所述漏极层，并且对位于第二区域的衬底进行刻蚀，以使位于所述第一区域的所述衬底的厚度大于位于所述第二区域的所述衬底的厚度。The first insulating material layer, the source layer, the semiconductor material layer, and the drain layer are etched according to the sidewalls to form the cylindrical first insulating material layer, the source layer, the semiconductor material layer, the drain layer, and etching the substrate located in the second region so that the thickness of the substrate located in the first region is greater than that located in the second region. area of the substrate thickness.

可选地，形成环绕所述半导体层的主栅极，所述主栅极与所述字线电连接且与所述源极层和所述漏极层绝缘，包括：Optionally, forming a main gate surrounding the semiconductor layer, the main gate being electrically connected to the word line and insulated from the source layer and the drain layer, including:

对所述半导体材料层进行第一局部刻蚀以使所述半导体材料层的外径小于所述漏极层的外径；Perform a first local etching on the semiconductor material layer to make the outer diameter of the semiconductor material layer smaller than the outer diameter of the drain layer;

在经过第一局部刻蚀之后的所述连接部、所述漏极层、所述半导体材料层、所述源极层和所述第一绝缘材料层的外侧壁以及位于所述第二区域的所述衬底上沉积第一栅极介质层；After the first local etching, the outer sidewalls of the connection portion, the drain layer, the semiconductor material layer, the source layer and the first insulating material layer, as well as those located in the second region depositing a first gate dielectric layer on the substrate;

在所述第一栅极介质层远离所述半导体材料层的一侧形成主栅极；Form a main gate on the side of the first gate dielectric layer away from the semiconductor material layer;

在位于所述第二区域的所述第一栅极介质层远离所述衬底的一侧依次形成第二绝缘层、第一导电层和第三绝缘层，所述第一导电层与所述主栅极接触。A second insulating layer, a first conductive layer and a third insulating layer are sequentially formed on the side of the first gate dielectric layer located in the second region away from the substrate. The first conductive layer and the main gate contact.

可选地，通过构图工艺形成贯穿所述漏极层、所述半导体材料层和所述源极层的容纳孔，包括：Optionally, a receiving hole penetrating the drain layer, the semiconductor material layer and the source layer is formed through a patterning process, including:

依据所述侧墙对所述第一绝缘材料层、所述源极层、所述半导体材料层、所述漏极层进行刻蚀，以形成贯穿所述第一绝缘材料层、所述源极层、所述半导体材料层和所述漏极层的容纳孔；Etch the first insulating material layer, the source layer, the semiconductor material layer, and the drain layer according to the sidewalls to form a layer that penetrates the first insulating material layer, the source layer, and the source layer. layer, the semiconductor material layer and the receiving hole of the drain layer;

对所述半导体层进行第二局部刻蚀以使所述半导体层的内径大于所述漏极的内径。A second local etching is performed on the semiconductor layer to make the inner diameter of the semiconductor layer larger than the inner diameter of the drain electrode.

可选地，在所述容纳孔内依次形成背栅极和电容电极，所述电容电极与所述参考电位线电连接且与所述源极、所述漏极、所述主栅极和所述背栅极绝缘，包括：Optionally, a back gate and a capacitor electrode are sequentially formed in the accommodation hole, and the capacitor electrode is electrically connected to the reference potential line and connected to the source, the drain, the main gate and all The back gate insulation includes:

在所述容纳孔内形成第二栅极介质层，并对位于所述容纳孔底部的所述第二栅极介质层进行刻蚀以使所述连接部暴露；Form a second gate dielectric layer in the accommodation hole, and etch the second gate dielectric layer located at the bottom of the accommodation hole to expose the connection portion;

在所述容纳孔内依次沉积背栅极、电容介质层和电容电极，所述背栅极与所述连接部以及所述第二栅极介质层接触；A back gate, a capacitor dielectric layer and a capacitor electrode are sequentially deposited in the accommodation hole, and the back gate is in contact with the connection part and the second gate dielectric layer;

去除位于所述第二栅极介质层和所述电容介质层之间的部分背栅极以形成环形凹槽，并在所述环形凹槽填充绝缘材料以形成第四绝缘层；Remove a portion of the back gate located between the second gate dielectric layer and the capacitor dielectric layer to form an annular groove, and fill the annular groove with an insulating material to form a fourth insulating layer;

对所述第三绝缘层和所述第一导电层进行刻蚀以去除刻蚀区域的所述第三绝缘层，并且去除所述刻蚀区域的所述第一导电层以形成所述字线，并在所述刻蚀区域沉积第五绝缘层；The third insulating layer and the first conductive layer are etched to remove the third insulating layer in the etched area, and the first conductive layer in the etched area is removed to form the word line , and deposit a fifth insulating layer in the etching area;

通过构图工艺在所述第四绝缘层上形成参考电位线，并在所述参考电位线上沉积第六绝缘层，所述参考电位线与所述电容电极接触；A reference potential line is formed on the fourth insulating layer through a patterning process, and a sixth insulating layer is deposited on the reference potential line, and the reference potential line is in contact with the capacitor electrode;

通过构图工艺在所述第六绝缘层上形成位线，所述位线通过过孔与所述源极电连接。A bit line is formed on the sixth insulating layer through a patterning process, and the bit line is electrically connected to the source electrode through a via hole.

第四个方面，本申请实施例提供一种读写方法，用于对上述的存储单元进行读写，所述读写方法包括：In a fourth aspect, embodiments of the present application provide a reading and writing method for reading and writing the above-mentioned storage unit. The reading and writing method includes:

在写入状态时，通过所述字线向待写入的存储单元的主栅极施加第一电平以使晶体管导通，并通过位线向所述待写入的存储单元的源极传输存储信号，以将所述存储信号写入所述待写入的存储单元作为存储数据；In the writing state, a first level is applied to the main gate of the memory cell to be written through the word line to turn on the transistor, and is transmitted to the source of the memory cell to be written through the bit line. store a signal to write the storage signal into the storage unit to be written as storage data;

在读取状态时，通过所述字线向待读取的存储单元的主栅极施加第二电平，以使所述位线感测所述待读取的存储单元的存储数据。In the read state, a second level is applied to the main gate of the memory cell to be read through the word line, so that the bit line senses the stored data of the memory cell to be read.

本申请实施例提供的技术方案带来的有益技术效果包括： The beneficial technical effects brought by the technical solutions provided by the embodiments of this application include:

1)本实施例提供的存储单元及制作方法、动态存储器、存储装置、读写方法，源极、漏极、半导体层、主栅极和背栅极等构成一个晶体管，电容电极和背栅极构成存储电容，也就是每个存储单元包括一个晶体管和一个存储电容，而在该存储单元中，背栅极和源极构成一个辅助电容，从而增加存储单元的电容量，使得存储节点能够维持更长的时间，从而在无需增加膜层以保证动态存储器的集成度的同时降低了动态存储器的刷新频率。1) In the memory unit and production method, dynamic memory, storage device, and reading and writing method provided in this embodiment, the source, drain, semiconductor layer, main gate, and back gate constitute a transistor, and the capacitor electrode and back gate are Constitute a storage capacitor, that is, each storage unit includes a transistor and a storage capacitor, and in the storage unit, the back gate and the source form an auxiliary capacitor, thus increasing the capacitance of the storage unit and allowing the storage node to maintain longer Therefore, there is no need to add film layers to ensure the integration of dynamic memory and at the same time reduce the refresh frequency of dynamic memory.

2)本实施例提供的存储单元及制作方法、动态存储器、存储装置、读写方法，在读取过程中，存储单元处于“1”状态则位线能够获取存储节点信号，存储单元处于“0”状态则位线不能获取存储节点信号，也就是“1”或“0”两种状态下位线读取的数据信号差异巨大，使得动态存储器的抗噪声性能增强；而且相对于现有技术中只能通过检测晶体管输出电流的大小来实现存储单元的“1”或“0”状态的判断而言，本实施例由于“0”状态下检测不到信号，则既可以利用电流信号进行检测也可以利用电压信号进行检测，从而便于根据具体需求设计***检测电路，具有更好地适应性。2) In the storage unit and production method, dynamic memory, storage device, and reading and writing method provided by this embodiment, during the reading process, if the storage unit is in the "1" state, the bit line can obtain the storage node signal, and the storage unit is in the "0" state. " state, the bit line cannot obtain the storage node signal, that is, the data signal read by the bit line in the two states of "1" or "0" is greatly different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, which only As far as the "1" or "0" state of the memory cell can be determined by detecting the output current of the transistor, in this embodiment, since no signal is detected in the "0" state, the current signal can be used for detection. Using voltage signals for detection makes it easier to design peripheral detection circuits according to specific needs and has better adaptability.

本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。Additional aspects and advantages of the invention will be set forth in part in the description which follows, and will be obvious from the description, or may be learned by practice of the invention.

附图说明Description of drawings

本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

图1为本申请实施例提供的一种动态存储器的一个局部截面示意图；Figure 1 is a partial cross-sectional schematic diagram of a dynamic memory provided by an embodiment of the present application;

图2为本申请实施例提供的一种动态存储器中的存储单元的电路结构示意图；Figure 2 is a schematic circuit structure diagram of a memory unit in a dynamic memory provided by an embodiment of the present application;

图3为在写入不同的数据时存储单元中晶体管的转移特性曲线图；Figure 3 is a graph of the transfer characteristics of the transistors in the memory cell when writing different data;

图4为本申请实施例提供的动态存储器的电路结构示意图；Figure 4 is a schematic circuit structure diagram of a dynamic memory provided by an embodiment of the present application;

图5为本申请实施例提供的动态存储器的另一局部截面示意图；Figure 5 is another partial cross-sectional schematic diagram of the dynamic memory provided by the embodiment of the present application;

图6为本申请实施例提供的一种存储装置的框架结构示意图；Figure 6 is a schematic diagram of the frame structure of a storage device provided by an embodiment of the present application;

图7为本申请实施例提供的一种存储单元的制作方法的流程示意图；Figure 7 is a schematic flowchart of a method of manufacturing a memory unit provided by an embodiment of the present application;

图8为本申请实施例提供的存储单元的制作方法中步骤S1的流程示意图；Figure 8 is a schematic flowchart of step S1 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图9为本申请实施例提供的存储单元的制作方法中步骤S101的侧视工艺示意图；Figure 9 is a schematic side view of step S101 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图10为本申请实施例提供的存储单元的制作方法中步骤S102的侧视工艺示意图；Figure 10 is a schematic side view of step S102 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图11为本申请实施例提供的存储单元的制作方法中步骤S102的俯视工艺示意图；Figure 11 is a top view process diagram of step S102 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图12为本申请实施例提供的存储单元的制作方法中步骤S103的侧视工艺示意图；Figure 12 is a schematic side view of step S103 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图13为本申请实施例提供的存储单元的制作方法中步骤S103的俯视工艺示意图；Figure 13 is a top view process diagram of step S103 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图14为本申请实施例提供的存储单元的制作方法中步骤S2的流程示意图；Figure 14 is a schematic flowchart of step S2 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图15为本申请实施例提供的存储单元的制作方法中步骤S201的侧视工艺示意图；Figure 15 is a schematic side view of step S201 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图16为本申请实施例提供的存储单元的制作方法中步骤S202至S203的侧视工艺示意图；Figure 16 is a schematic side view of steps S202 to S203 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图17为本申请实施例提供的存储单元的制作方法中步骤S202至S203的俯视工艺示意图；Figure 17 is a top view process diagram of steps S202 to S203 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图18为本申请实施例提供的存储单元的制作方法中步骤S203的侧视工艺示意图；Figure 18 is a schematic side view of step S203 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图19为本申请实施例提供的存储单元的制作方法中步骤S203的俯视工艺示意图；Figure 19 is a top view process diagram of step S203 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图20为本申请实施例提供的存储单元的制作方法中步骤S3的流程示意图；Figure 20 is a schematic flowchart of step S3 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图21为本申请实施例提供的存储单元的制作方法中步骤S301的侧视工艺示意图；Figure 21 is a schematic side view of step S301 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图22为本申请实施例提供的存储单元的制作方法中步骤S302的侧视工艺示意图； Figure 22 is a side view process diagram of step S302 in the method of manufacturing a memory unit provided by an embodiment of the present application;

图23为本申请实施例提供的存储单元的制作方法中步骤S4的流程示意图；Figure 23 is a schematic flowchart of step S4 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图24为本申请实施例提供的存储单元的制作方法中步骤S401的侧视工艺示意图；Figure 24 is a schematic side view of step S401 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图25为本申请实施例提供的存储单元的制作方法中步骤S401的俯视工艺示意图；Figure 25 is a top view process diagram of step S401 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图26为本申请实施例提供的存储单元的制作方法中步骤S402的侧视工艺示意图；Figure 26 is a schematic side view of step S402 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图27为本申请实施例提供的存储单元的制作方法中步骤S402的俯视工艺示意图；Figure 27 is a top view process diagram of step S402 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图28为本申请实施例提供的存储单元的制作方法中步骤S403的侧视工艺示意图；Figure 28 is a schematic side view of step S403 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图29为本申请实施例提供的存储单元的制作方法中步骤S403的俯视工艺示意图；Figure 29 is a top view process diagram of step S403 in the method for manufacturing a memory unit provided by an embodiment of the present application;

图30为本申请实施例提供的存储单元的制作方法中步骤S404的侧视工艺示意图；Figure 30 is a side view process diagram of step S404 in the method for manufacturing a memory unit provided by an embodiment of the present application;

图31为本申请实施例提供的存储单元的制作方法中步骤S404的俯视工艺示意图；Figure 31 is a top view process diagram of step S404 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图32为本申请实施例提供的存储单元的制作方法中步骤S405的侧视工艺示意图；Figure 32 is a side view process diagram of step S405 in the method of manufacturing a memory unit provided by an embodiment of the present application;

图33为本申请实施例提供的存储单元的制作方法中步骤S405的俯视工艺示意图；Figure 33 is a top view process diagram of step S405 in the manufacturing method of a memory unit provided by an embodiment of the present application;

图34为本申请实施例提供的读写方法的流程示意图。Figure 34 is a schematic flowchart of a reading and writing method provided by an embodiment of the present application.

附图标记：Reference signs:

10-存储单元；T-晶体管；C1-存储电容；C2-辅助电容；BL-位线；WL-字线；Vref-参考电位线；101-衬底；102-连接部；103-漏极；104-半导体层；105-源极；106-第一绝缘层；107-侧墙；108-第一栅极介质层；109-主栅极；110-第二绝缘层；111-第一导电层；112-第三绝缘层；113-第二栅极介质层；114-背栅极；115-电容介质层；116-电容电极；117-第四绝缘层；118-第五绝缘层；119-第二导电层；120-第六绝缘层；121-第三导电层；122-组间绝缘层；100-第一区域；200-第二区域。10-storage unit; T-transistor; C1-storage capacitor; C2-auxiliary capacitor; BL-bit line; WL-word line; Vref-reference potential line; 101-substrate; 102-connection portion; 103-drain; 104-semiconductor layer; 105-source; 106-first insulating layer; 107-side wall; 108-first gate dielectric layer; 109-main gate; 110-second insulating layer; 111-first conductive layer ; 112-third insulating layer; 113-second gate dielectric layer; 114-back gate; 115-capacitor dielectric layer; 116-capacitor electrode; 117-fourth insulating layer; 118-fifth insulating layer; 119- Second conductive layer; 120-sixth insulating layer; 121-third conductive layer; 122-inter-group insulating layer; 100-first region; 200-second region.

具体实施方式Detailed ways

下面结合本申请中的附图描述本申请的实施例。应理解，下面结合附图所阐述的实施方式，是用于解释本申请实施例的技术方案的示例性描述，对本申请实施例的技术方案不构成限制。The embodiments of the present application are described below with reference to the drawings in the present application. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not limit the technical solutions of the embodiments of the present application.

本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但不排除实现为本技术领域所支持其他特征、信息、数据、步骤、操作、元件、组件和/或它们的组合等。应该理解，当我们称一个元件被“连接”或“耦接”到另一元件时，该一个元件可以直接连接或耦接到另一元件，也可以指该一个元件和另一元件通过中间元件建立连接关系。此外，这里使用的“连接”或“耦接”可以包括无线连接或无线耦接。这里使用的术语“和/或”指该术语所限定的项目中的至少一个，例如“A和/或B”可以实现为“A”，或者实现为“B”，或者实现为“A和B”。Those skilled in the art will understand that, unless expressly stated otherwise, the singular forms "a", "an", "the" and "the" used herein may also include the plural form. It should be further understood that the word "comprising" used in the description of this application refers to the presence of the described features, integers, steps, operations, elements and/or components, but does not exclude the implementation of other features, information supported by the technical field. , data, steps, operations, elements, components and/or their combinations, etc. It should be understood that when we refer to an element being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or one element and the other element may be connected to the other element through intervening elements. Establish connections. Additionally, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and/or" used herein refers to at least one of the items defined by the term. For example, "A and/or B" can be realized as "A", or as "B", or as "A and B" ".

为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

DRAM存储器通常包括多个存储单元，每个存储单元中均包括晶体管，由于晶体管存在跨有源层泄漏现象，这会使得存储单元中存储的电荷逐渐流失，因此存储的数据需要频繁刷新才能保证存储数据的有效性。目前主流的DRAM中，为了降低刷新率，常规设计是电容需要做到足够大，这会使得DRAM的结构不紧凑、集成度较低。DRAM memory usually includes multiple memory cells, each of which includes a transistor. Since the transistor leaks across the active layer, the charge stored in the memory unit will gradually drain away. Therefore, the stored data needs to be refreshed frequently to ensure storage. Data validity. In current mainstream DRAM, in order to reduce the refresh rate, the conventional design requires the capacitor to be large enough, which will make the DRAM structure uncompact and low-integration.

本申请提供的存储单元及制作方法、动态存储器、存储装置、读写方法，旨在解决现有技术的如上技术问题。The storage unit and production method, dynamic memory, storage device, and reading and writing method provided by this application are intended to solve the above technical problems of the existing technology.

下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。需要指出的是，下述实施方式之间可以相互参考、借鉴或结合，对于不同实施方式中相同的术语、相似的特征以及相似的实施步骤等，不再重复描述。The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. It should be pointed out that the following embodiments may refer to, draw lessons from or combine with each other. Therefore, the same terms, similar features, and similar implementation steps in different implementations will not be described again.

本申请实施例提供了一种存储单元和动态存储器，如图1和图2所示，本实施例提供的动态存储器包括衬底101、位于衬底101上的多条字线WL、多条位线BL、多条参考电位线Vref和多个存储单元10。在本实施例中，存储单元10包括：An embodiment of the present application provides a memory unit and a dynamic memory. As shown in Figures 1 and 2, the dynamic memory provided by this embodiment includes a substrate 101, a plurality of word lines WL located on the substrate 101, and a plurality of bits. line BL, a plurality of reference potential lines Vref and a plurality of memory cells 10 . In this embodiment, the storage unit 10 includes:

位于衬底101上且呈柱状的电容电极116，电容电极116与参考电位线Vref电连接；A columnar capacitive electrode 116 is located on the substrate 101, and the capacitive electrode 116 is electrically connected to the reference potential line Vref;

位于电容电极116与衬底101之间且环绕电容电极116的背栅极114，背栅极114与电容电极116绝缘且与电容电极116构成存储电容C1；The back gate 114 is located between the capacitor electrode 116 and the substrate 101 and surrounds the capacitor electrode 116. The back gate 114 is insulated from the capacitor electrode 116 and forms a storage capacitor C1 with the capacitor electrode 116;

位于衬底101的一侧且在远离衬底101的方向上依次堆叠的漏极103、半导体层104和源极105，漏极103、半导体层104和源极105环绕电容电极116且位于背栅极114远离电容电极116的一侧，漏极103、半导体层104和源极105在平行于衬底101的截面为环形，漏极103与背栅极114电连接，背栅极114与源极105构成辅助电容C2；The drain electrode 103, the semiconductor layer 104 and the source electrode 105 are sequentially stacked on one side of the substrate 101 and in the direction away from the substrate 101. The drain electrode 103, the semiconductor layer 104 and the source electrode 105 surround the capacitor electrode 116 and are located on the back gate. The side of the electrode 114 away from the capacitor electrode 116. The drain electrode 103, the semiconductor layer 104 and the source electrode 105 are annular in cross-section parallel to the substrate 101. The drain electrode 103 is electrically connected to the back gate electrode 114, and the back gate electrode 114 is connected to the source electrode. 105 constitutes the auxiliary capacitor C2;

环绕半导体层104的外侧壁的主栅极109，主栅极109与字线WL电连接且与源极105和漏极103绝缘。The main gate 109 surrounding the outer side wall of the semiconductor layer 104 is electrically connected to the word line WL and is insulated from the source electrode 105 and the drain electrode 103 .

如图1和图2所示，源极105、漏极103、半导体层104、主栅极109和背栅极114等构成一个晶体管T，电容电极116和背栅极114构成存储电容C1，也就是每个存储单元10包括一个晶体管T和一个存储电容C1，而在该存储单元10中，背栅极114和源极105构成一个辅助电容C2，从而增加存储单元10的电容量，使得存储节点N1能够维持更长的时间，从而在无需增加膜层以保证动态存储器的集成度的同时降低了动态存储器的刷新频率。As shown in Figures 1 and 2, the source 105, the drain 103, the semiconductor layer 104, the main gate 109 and the back gate 114 constitute a transistor T, and the capacitor electrode 116 and the back gate 114 constitute the storage capacitor C1, also That is, each memory cell 10 includes a transistor T and a storage capacitor C1, and in the memory cell 10, the back gate 114 and the source 105 form an auxiliary capacitor C2, thereby increasing the capacitance of the memory cell 10, so that the storage node N1 can last longer, thus reducing the refresh frequency of dynamic memory without adding film layers to ensure the integration of dynamic memory.

需要说明的是，由于背栅极114存在背栅效应，即背栅极114的电位会对晶体管T的阈值电压产生影响，因此在读取存储数据时用于开启晶体管T的电压的大小位于晶体管T存储“1”时的阈值电压与晶体管T存储“0”时的阈值电压之间。It should be noted that since the back gate 114 has a back gate effect, that is, the potential of the back gate 114 will affect the threshold voltage of the transistor T, therefore when reading stored data, the voltage used to turn on the transistor T is located at the level of the transistor. Between the threshold voltage when T stores "1" and the threshold voltage when transistor T stores "0".

如图2和图3所示，在数据写入时，当通过字线WL向主栅极109施加第一电平则晶体管T导通，并通过位线BL输入的数据信号写入到存储节点N1，数据写入完成则通过调整字线WL施加到主栅极109的电位使得晶体管T关闭，在晶体管T关闭后，即使存在漏电现象，但存储电容C1和辅助电容C2的存在能够对存储节点N1的电位进行保持。As shown in FIGS. 2 and 3 , during data writing, when a first level is applied to the main gate 109 through the word line WL, the transistor T is turned on, and the data signal input through the bit line BL is written to the storage node. N1, after the data writing is completed, the potential applied to the main gate 109 by the word line WL is adjusted to turn off the transistor T. After the transistor T is turned off, even if there is leakage, the existence of the storage capacitor C1 and the auxiliary capacitor C2 can affect the storage node. The potential of N1 is maintained.

如图2和图3所示，在数据读取时，对主栅极109施加第二电平，若该存储单元10处于“1”状态，则主栅极109在第二电平(例如主栅极电位VG＝0.3V，此时源极电位VS＝0)下打开，能够获取存储节点N1的信号；若该存储单元10处于“0”状态，则在相同的栅极和源极105偏置下晶体管T并未导通，因此位线BL并未获取电信号。As shown in Figures 2 and 3, when data is read, a second level is applied to the main gate 109. If the memory cell 10 is in the "1" state, the main gate 109 is at the second level (for example, the main The gate potential VG=0.3V, at this time, the source potential VS=0) is turned on, and the signal of the storage node N1 can be obtained; if the memory cell 10 is in the "0" state, the same gate and source 105 bias When the transistor T is set down, it is not turned on, so the bit line BL does not obtain an electrical signal.

通过上述说明可知，本实施例提供的动态存储器，在读取过程中，存储单元10处于“1”状态则位线BL能够获取存储节点N1的信号，存储单元10处于“0”状态则位线BL不能获取存储节点N1的信号，也就是“1”或“0”两种状态下位线BL读取的数据信号差异巨大，使得动态存储器的抗噪声性能增强；而且相对于现有技术中只能通过检测晶体管T输出电流的大小来实现存储单元10的“1”或“0”状态的判断而言，本实施例由于“0”状态下检测不到信号，则既可以利用电流信号进行检测也可以利用电压信号进行检测，从而便于根据具体需求设计***检测电路，具有更好地适应性。It can be seen from the above description that in the dynamic memory provided by this embodiment, during the reading process, if the memory unit 10 is in the "1" state, the bit line BL can obtain the signal of the storage node N1, and if the memory unit 10 is in the "0" state, the bit line BL can obtain the signal of the storage node N1. BL cannot obtain the signal of storage node N1, that is, the data signal read by bit line BL in the two states of "1" or "0" is very different, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, which can only In terms of determining the “1” or “0” state of the memory cell 10 by detecting the output current of the transistor T, in this embodiment, since no signal is detected in the “0” state, the current signal can be used for detection. Voltage signals can be used for detection, which facilitates the design of peripheral detection circuits according to specific needs and has more Good adaptability.

具体的，如图4所示，该动态存储器包括第1至第n条字线WL，第1至第m条位线BL以及第1至第m条参考电位线Vref。通过向相应的字线WL和位线BL输入有效电平，能够实现数据的写入与读取。Specifically, as shown in FIG. 4 , the dynamic memory includes 1st to nth word lines WL, 1st to mth bit lines BL, and 1st to mth reference potential lines Vref. By inputting valid levels to the corresponding word lines WL and bit lines BL, data can be written and read.

如图5所示，本实施例提供的动态存储器中，多个存储单元10分为多个存储单元组，多个存储单元组在垂直于衬底101的方向上排布；每个存储单元组包括多个在平行于衬底101的方向上呈阵列排布的存储单元10，其中位于同一行的各存储单元10与同一字线WL电连接，位于同一列的各存储单元10与同一位线BL电连接。具体地，本实施例提供的动态存储器还包括组间绝缘层122，组间绝缘层122覆盖下侧的存储单元组中的位线BL。As shown in Figure 5, in the dynamic memory provided by this embodiment, multiple memory cells 10 are divided into multiple memory unit groups, and the multiple memory unit groups are arranged in a direction perpendicular to the substrate 101; each memory unit group It includes a plurality of memory cells 10 arranged in an array in a direction parallel to the substrate 101. Each memory cell 10 located in the same row is electrically connected to the same word line WL, and each memory cell 10 located in the same column is electrically connected to the same bit line. BL electrical connection. Specifically, the dynamic memory provided by this embodiment also includes an inter-group insulating layer 122 that covers the bit line BL in the lower memory cell group.

具体地，在实施过程中，可根据具体的存储容量的需求以及对存储器的空间的限制，选择不同的排布方式，即通过调整存储单元组的个数以及每个存储单元组中存储单元10的个数(包括调整每行和/或每列中存储单元10的个数)，实现存储容量与存储空间的优化设计。Specifically, during the implementation process, different arrangements can be selected according to specific storage capacity requirements and memory space limitations, that is, by adjusting the number of storage unit groups and the number of storage units 10 in each storage unit group. (including adjusting the number of storage units 10 in each row and/or column) to achieve optimal design of storage capacity and storage space.

可选地，如图1所示，本实施例提供的动态存储器中，存储单元10还包括连接部102，连接部102位于衬底101和漏极103之间且位于衬底101和背栅极114之间，连接部102直接与漏极103接触同时与背栅极114接触，连接部102的材料为导电材料；连接部102在衬底101上的正投影所在的区域为第一区域100，包围第一区域100的区域为第二区域200，位于第一区域100的衬底101的厚度大于位于第二区域200的衬底101的厚度。Optionally, as shown in Figure 1, in the dynamic memory provided by this embodiment, the memory unit 10 also includes a connection part 102. The connection part 102 is located between the substrate 101 and the drain electrode 103 and between the substrate 101 and the back gate. 114, the connection part 102 directly contacts the drain electrode 103 and the back gate 114. The material of the connection part 102 is a conductive material; the area where the orthographic projection of the connection part 102 on the substrate 101 is located is the first area 100. The area surrounding the first area 100 is the second area 200 , and the thickness of the substrate 101 located in the first area 100 is greater than the thickness of the substrate 101 located in the second area 200 .

在本实施例中，对衬底101的第二区域200进行部分刻蚀，能够保证位于衬底101上的连接部102被充分刻蚀从而防止相邻存储单元10中的连接部102发生误连接，降低故障风险。In this embodiment, partial etching of the second region 200 of the substrate 101 can ensure that the connection portion 102 on the substrate 101 is fully etched to prevent misconnection of the connection portions 102 in adjacent memory cells 10 , reduce the risk of failure.

可选地，如图1所示，衬底101的材料为P型硅材料，连接部102的材料为N型重掺杂硅材料，漏极103为N型硅材料，源极105的材料为N型硅材料，半导体层104的材料为锗化硅材料。Optionally, as shown in FIG. 1 , the material of the substrate 101 is P-type silicon material, the material of the connection part 102 is N-type heavily doped silicon material, the drain electrode 103 is made of N-type silicon material, and the material of the source electrode 105 is N-type silicon material, the material of the semiconductor layer 104 is silicon germanium material.

采用掺杂硅材料来制作连接部102、漏极103和源极105，便于利用外延生长法来制作动态存储器，有利于降低生产成本。Doped silicon materials are used to make the connection portion 102, the drain electrode 103 and the source electrode 105, which facilitates the use of epitaxial growth methods to produce dynamic memories and is beneficial to reducing production costs.

可选地，如图1所示，本实施例提供的动态存储器中，存储单元10还包括位于源极105远离衬底101一侧的第一绝缘层106和位于第一绝缘层106远离衬底101一侧的侧墙107；其中侧墙107、第一绝缘层106、源极105以及漏极103在衬底101上的正投影重合，半导体层104在衬底101上的正投影位于漏极103在衬底101上的正投影内，漏极103在衬底101上的正投影位于连接部102在衬底101上的正投影内。Optionally, as shown in FIG. 1 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes a first insulating layer 106 located on the side of the source 105 away from the substrate 101 and a first insulating layer 106 located away from the substrate. The spacers 107 on one side of 101; the orthographic projections of the spacers 107, the first insulating layer 106, the source 105 and the drain 103 on the substrate 101 coincide with each other, and the orthographic projection of the semiconductor layer 104 on the substrate 101 is located at the drain. 103 is within the orthographic projection on the substrate 101 , and the orthographic projection of the drain 103 on the substrate 101 is located within the orthographic projection of the connection portion 102 on the substrate 101 .

具体地，如图1所示，侧墙107、第一绝缘层106、源极105、半导体层104以及漏极103均为环形，半导体层104的内径大于漏极103的内径，且半导体层104的外径小于漏极103的外径。Specifically, as shown in FIG. 1 , the sidewalls 107 , the first insulating layer 106 , the source 105 , the semiconductor layer 104 and the drain 103 are all annular. The inner diameter of the semiconductor layer 104 is larger than the inner diameter of the drain 103 , and the semiconductor layer 104 The outer diameter is smaller than the outer diameter of the drain electrode 103 .

具体地，侧墙107为环形，通过对侧墙107的内径和外径的设计来确定源极105和漏极103的内外径，并且侧墙107的设计结合半导体层104的刻蚀工艺能够确定半导体层104的内外径，从而确定半导体层104的长宽比，进而使得存储单元10中的晶体管T具有所需的特性。Specifically, the spacer 107 is annular, and the inner and outer diameters of the source 105 and the drain 103 are determined by designing the inner and outer diameters of the spacer 107 , and the design of the spacer 107 can be determined by combining the etching process of the semiconductor layer 104 The inner and outer diameters of the semiconductor layer 104 determine the aspect ratio of the semiconductor layer 104 so that the transistor T in the memory unit 10 has required characteristics.

本实施例提供的动态存储器中，存储单元10设置有侧墙107，即以侧墙107作为位于侧墙107下方的源极105、漏极103等多个膜层的刻蚀掩膜，不仅制作方法较为简单，且侧墙107技术利于提升动态存储器的精度。In the dynamic memory provided by this embodiment, the memory unit 10 is provided with sidewalls 107, that is, the sidewalls 107 are used as etching masks for multiple film layers such as the source electrode 105 and the drain electrode 103 located under the sidewall 107. The method is relatively Simple, and the sidewall 107 technology helps improve the accuracy of dynamic memory.

可选地，如图1所示，本实施例提供的存储单元中，主栅极109位于源极105和漏极103之间(具体地，主栅极109位于源极105和漏极103之间的与半导体层104对应的区域)，字线WL与主栅极109材料相同且与主栅极109接触，字线WL在衬底101上的正投影位于第二区域200；参考电位线Vref位于电容电极116远离衬底101的一侧且与电容电极116接触；位线BL位于参考电位线Vref远离衬底101的一侧且通过过孔与源极105电连接。Optionally, as shown in Figure 1, in the memory cell provided by this embodiment, the main gate 109 is located between the source electrode 105 and the drain electrode 103 (specifically, the main gate 109 is located between the source electrode 105 and the drain electrode 103. (the area corresponding to the semiconductor layer 104), the word line WL is made of the same material as the main gate 109 and is in contact with the main gate 109. The orthographic projection of the word line WL on the substrate 101 is located in the second area 200; the reference potential line Vref The bit line BL is located on the side of the capacitor electrode 116 away from the substrate 101 and in contact with the capacitor electrode 116; the bit line BL is located on the side of the reference potential line Vref away from the substrate 101 and is electrically connected to the source electrode 105 through a via hole.

具体地，如图1所示，本实施例提供的动态存储器中，存储单元10还包括第一栅极介质层108。第一栅极介质层108位于连接部102、漏极103、半导体层104、源极105、第一绝缘层106和侧墙107的外侧壁以及位于第二区域200的衬底101上。第一栅极介质层108是为了使得主栅极109与源极105、漏极103、半导体层104绝缘。Specifically, as shown in FIG. 1 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes a first gate dielectric layer 108 . The first gate dielectric layer 108 is located on the connecting portion 102 , the drain electrode 103 , the semiconductor layer 104 , the source electrode 105 , the first insulating layer 106 and the outer sidewalls of the spacers 107 and on the substrate 101 in the second region 200 . The first gate dielectric layer 108 is used to insulate the main gate 109 from the source 105 , the drain 103 and the semiconductor layer 104 .

具体地，如图1所示，本实施例提供的动态存储器中，存储单元10还包括第二绝缘层110，第二绝缘层110位于第二区域200且位于第一栅极介质层108远离衬底101的一侧，第二绝缘层110进一步提升相邻存储单元10之间的绝缘性能。Specifically, as shown in FIG. 1 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes a second insulating layer 110 . The second insulating layer 110 is located in the second region 200 and is located away from the first gate dielectric layer 108 and the liner. On one side of the bottom 101 , the second insulating layer 110 further improves the insulation performance between adjacent memory cells 10 .

具体地，如图1所示，本实施例提供的动态存储器中，存储单元10还包括第三绝缘层112，第三绝缘层112位于字线WL远离衬底101的一侧，第三绝缘层112起到位线BL以及参考电位线Vref等与字线WL绝缘的作用。在制作时，在第二绝缘层110上依次沉积第一导电层111和第三绝缘层112，再在后续处理中，对第三绝缘层112和第一导电层111进行图形化处理，以形成图形化的第三绝缘层112和多条字线WL。可选地，第一导电层111的材料包括但不限于金属。Specifically, as shown in Figure 1, in the dynamic memory provided by this embodiment, the memory unit 10 also includes a third insulating layer 112. The third insulating layer 112 is located on the side of the word line WL away from the substrate 101. 112 serves to insulate the bit line BL, the reference potential line Vref, and the like from the word line WL. During production, the first conductive layer 111 and the third insulating layer 112 are sequentially deposited on the second insulating layer 110, and then in subsequent processing, the third insulating layer 112 and the first conductive layer 111 are patterned to form The patterned third insulating layer 112 and the plurality of word lines WL. Optionally, the material of the first conductive layer 111 includes but is not limited to metal.

具体地，如图1所示，本实施例提供的动态存储器中，存储单元10还包括第二栅极介质层113和电容介质层115。第二栅极介质层113位于连接部102、漏极103、半导体层104、源极105和第一绝缘层106的内侧壁，第二栅极介质层113使得背栅极114与源极105、漏极103绝缘，且第二栅极介质层113作为源极105与背栅极114之间的介质层以使源极105与背栅极114构成辅助电容C2。电容介质层115位于背栅极114和电容电极116之间，电容介质层115使得背栅极114和电容电极116绝缘，且电容介质层115作为背栅极114与电容电极116之间的介质以使背栅极114和电容电极116构成存储电容C1。Specifically, as shown in FIG. 1 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes a second gate dielectric layer 113 and a capacitive dielectric layer 115 . The second gate dielectric layer 113 is located on the inner sidewalls of the connection portion 102, the drain electrode 103, the semiconductor layer 104, the source electrode 105 and the first insulating layer 106. The second gate dielectric layer 113 connects the back gate electrode 114 with the source electrode 105, The drain electrode 103 is insulated, and the second gate dielectric layer 113 serves as a dielectric layer between the source electrode 105 and the back gate electrode 114 so that the source electrode 105 and the back gate electrode 114 form a auxiliary capacitor C2. The capacitive dielectric layer 115 is located between the back gate 114 and the capacitive electrode 116. The capacitive dielectric layer 115 insulates the back gate 114 and the capacitive electrode 116, and the capacitive dielectric layer 115 serves as a medium between the back gate 114 and the capacitive electrode 116. The back gate 114 and the capacitor electrode 116 form a storage capacitor C1.

具体地，如图1所示，本实施例提供的动态存储器中，存储单元10还包括第四绝缘层117、第五绝缘层118和第六绝缘层120。第四绝缘层117位于第二栅极介质层113和电容介质层115之间且位于背栅极114远离衬底101的一侧，起到使背栅极114与参考电位线Vref绝缘的作用。第五绝缘层118填充字线WL以及第三绝缘层112的侧面，也就是填充在对第三绝缘层112和第一导电层111进行图形化处理之后的刻蚀区。第六绝缘层120位于参考电位线Vref所在导电层(第二导电层119)和位线BL所在导电层(第三导电层121)之间。Specifically, as shown in FIG. 1 , in the dynamic memory provided by this embodiment, the memory unit 10 further includes a fourth insulating layer 117 , a fifth insulating layer 118 and a sixth insulating layer 120 . The fourth insulating layer 117 is located between the second gate dielectric layer 113 and the capacitive dielectric layer 115 and on the side of the back gate 114 away from the substrate 101 to insulate the back gate 114 from the reference potential line Vref. The fifth insulating layer 118 fills the word line WL and the side surfaces of the third insulating layer 112 , that is, fills the etched area after patterning the third insulating layer 112 and the first conductive layer 111 . The sixth insulating layer 120 is located between the conductive layer (the second conductive layer 119) where the reference potential line Vref is located and the conductive layer (the third conductive layer 121) where the bit line BL is located.

本实施例中，通过将字线WL与主栅极109接触来实现字线WL与主栅极109的电连接，将参考电位线Vref与电容电极116接触，不仅能够简化工艺而且能够进一步提升动态存储器的集成度。In this embodiment, the word line WL is electrically connected to the main gate 109 by contacting the word line WL with the main gate 109, and the reference potential line Vref is contacted with the capacitor electrode 116, which not only simplifies the process but also further improves the dynamics. Memory integration.

基于同一发明构思，本申请实施例提供了一种存储装置，如图6所示，该存储装置包括上述实施例中的动态存储器，具有上述实施例中的动态存储器的有益效果，在此不再赘述。具体地，本申请实施例中的存储装置可以为计算机的主存等，具体可根据实际情况进行确定。Based on the same inventive concept, an embodiment of the present application provides a storage device, as shown in Figure 6. The storage device includes the dynamic memory in the above embodiment and has the beneficial effects of the dynamic memory in the above embodiment, which will not be discussed here. Repeat. Specifically, the storage device in the embodiment of the present application can be the main memory of a computer, etc., and can be specifically based on Determine based on actual conditions.

基于同一发明构思，本申请实施例提供了一种存储单元的制作方法，动态存储器的一个局部截面示意图如图1所示，存储单元的制作方法的流程示意图如图7所示；本实施例提供的制作方法包括：Based on the same inventive concept, embodiments of the present application provide a method for manufacturing a memory unit. A partial cross-sectional schematic diagram of a dynamic memory is shown in Figure 1, and a schematic flow diagram of a method for manufacturing a memory unit is shown in Figure 7. This embodiment provides Production methods include:

S1：提供一衬底，通过构图工艺在衬底的一侧形成依次堆叠的漏极层103a、半导体材料层104a和源极层105a，漏极层103a、半导体材料层104a和源极层105a为圆柱形。S1: Provide a substrate, and form a sequentially stacked drain layer 103a, semiconductor material layer 104a, and source layer 105a on one side of the substrate through a patterning process. The drain layer 103a, semiconductor material layer 104a, and source layer 105a are Cylindrical shape.

具体地，如图8至图13所示，当存储单元10还包括连接部102和第一绝缘层106时，则步骤S1包括：Specifically, as shown in FIGS. 8 to 13 , when the memory unit 10 further includes the connection portion 102 and the first insulating layer 106 , step S1 includes:

S101：通过外延生长法在衬底101上依次生长连接层102a、漏极层103a、半导体材料层104a、源极层105a和第一绝缘材料层106a。S101: Sequentially grow the connection layer 102a, the drain layer 103a, the semiconductor material layer 104a, the source layer 105a and the first insulating material layer 106a on the substrate 101 through the epitaxial growth method.

具体地，如图9所示，在P型硅衬底101上依次生长N型重掺杂硅材料作为连接层102a，生长N型硅材料作为漏极层103a，生长锗化硅材料作为半导体材料层104a，生长N型硅材料作为源极层105a。当然，在本申请一些可选的实施方式中，还可以根据实际需要，通过沉积方式依次形成连接层102a、漏极层103a、半导体材料层104a、源极层105a和第一绝缘材料层106a。Specifically, as shown in Figure 9, N-type heavily doped silicon material is grown on the P-type silicon substrate 101 as the connection layer 102a, N-type silicon material is grown as the drain layer 103a, and silicon germanium material is grown as the semiconductor material. In layer 104a, N-type silicon material is grown as the source layer 105a. Of course, in some optional implementations of the present application, the connection layer 102a, the drain layer 103a, the semiconductor material layer 104a, the source layer 105a and the first insulating material layer 106a can also be formed sequentially through deposition according to actual needs.

S102：通过构图工艺在第一绝缘材料层106a远离衬底101的一侧形成多个侧墙107和位于各侧墙107内的牺牲部300，其中，侧墙107和牺牲部300所在的区域为第一区域100，包围第一区域100的区域为第二区域200。S102: Form a plurality of sidewalls 107 and sacrificial portions 300 located in each sidewall 107 on the side of the first insulating material layer 106a away from the substrate 101 through a patterning process, where the area where the sidewalls 107 and the sacrificial portion 300 are located is The first area 100, and the area surrounding the first area 100 is the second area 200.

具体地，如图10和图11所示，通过对侧墙107的内径和外径的设计来确定源极和漏极的内外径，并且侧墙107的设计结合半导体层的刻蚀工艺能够确定半导体层的内外径，从而确定半导体层的长宽比，进而使得存储单元10中的晶体管T具有所需的特性。Specifically, as shown in FIGS. 10 and 11 , the inner and outer diameters of the source and drain electrodes are determined by designing the inner and outer diameters of the sidewalls 107 , and the design of the sidewalls 107 can be determined by combining the etching process of the semiconductor layer. The inner and outer diameters of the semiconductor layer determine the aspect ratio of the semiconductor layer, so that the transistor T in the memory unit 10 has required characteristics.

S103：依据侧墙107对第一绝缘材料层106a、源极层105a、半导体材料层104a、漏极层103a进行刻蚀，以形成圆柱形的第一绝缘材料层106a、源极层105a、半导体材料层104a、漏极层103a，并且对位于第二区域200的衬底101进行刻蚀，以使位于第一区域100的衬底101的厚度大于位于第二区域200的衬底101的厚度。S103: Etch the first insulating material layer 106a, source layer 105a, semiconductor material layer 104a, and drain layer 103a according to the sidewalls 107 to form a cylindrical first insulating material layer 106a, source layer 105a, and semiconductor. The material layer 104a, the drain layer 103a, and the substrate 101 located in the second region 200 are etched so that the thickness of the substrate 101 located in the first region 100 is greater than the thickness of the substrate 101 located in the second region 200.

具体地，如图12和图13所示，对衬底101的第二区域200进行部分刻蚀，能够保证位于衬底101上的连接部102被充分刻蚀从而防止相邻存储单元10中的连接部102发生误连接，降低故障风险。Specifically, as shown in FIGS. 12 and 13 , partially etching the second region 200 of the substrate 101 can ensure that the connection portion 102 on the substrate 101 is fully etched to prevent the adjacent memory cells 10 from being damaged. Misconnection occurs in the connection part 102, thereby reducing the risk of failure.

S2：形成环绕半导体层的主栅极，主栅极与字线电连接且与源极层和漏极层绝缘。S2: Form a main gate surrounding the semiconductor layer. The main gate is electrically connected to the word line and insulated from the source layer and the drain layer.

具体地，如图14至图19所示，仍以存储单元10还包括连接部102和第一绝缘层106为例进行说明。此时，步骤S2包括：Specifically, as shown in FIGS. 14 to 19 , the memory unit 10 further includes a connection portion 102 and a first insulating layer 106 as an example. At this time, step S2 includes:

S201：对半导体材料层104a进行第一局部刻蚀以使半导体材料层104a的外径小于漏极层103a的外径。S201: Perform a first local etching on the semiconductor material layer 104a to make the outer diameter of the semiconductor material layer 104a smaller than the outer diameter of the drain layer 103a.

具体地，如图15所示，对半导体材料层104a的外侧壁进行第一局部刻蚀，不仅能够为主栅极109提供空间以提升存储单元10的集成度，而且能够实现对晶体管T的半导体材料层104a的参数(例如长宽比)的调整。Specifically, as shown in FIG. 15 , performing a first local etching on the outer sidewall of the semiconductor material layer 104 a can not only provide space for the main gate 109 to improve the integration of the memory unit 10 , but also enable semiconductor processing of the transistor T. Adjustment of parameters (eg aspect ratio) of material layer 104a.

S202：在经过第一局部刻蚀之后的连接部102、漏极层103a、半导体材料层104a、源极层105a、第一绝缘材料层106a和侧墙107的外侧壁以及位于第二区域200的衬底101上沉积第一栅极介质层108。S202: After the first local etching, the connection portion 102, the drain layer 103a, the semiconductor material layer 104a, the source layer 105a, the first insulating material layer 106a, the outer sidewalls of the spacers 107 and the sidewalls located in the second region 200 A first gate dielectric layer 108 is deposited on the substrate 101 .

具体地，如图16和图17所示，第一栅极介质层108是为了使得主栅极109与源极层105a、漏极层103a、半导体材料层104a绝缘。Specifically, as shown in FIGS. 16 and 17 , the first gate dielectric layer 108 is to connect the main gate 109 to the source. The electrode layer 105a, the drain layer 103a, and the semiconductor material layer 104a are insulated.

S203：在第一栅极介质层108远离半导体材料层104a的一侧形成主栅极109，并在位于第二区域200的第一栅极介质层108远离衬底101的一侧依次形成第二绝缘层110、第一导电层111和第三绝缘层112，第一导电层111与主栅极109接触。S203: Form the main gate 109 on the side of the first gate dielectric layer 108 away from the semiconductor material layer 104a, and sequentially form a second gate electrode 109 on the side of the first gate dielectric layer 108 located in the second region 200 away from the substrate 101. The insulating layer 110 , the first conductive layer 111 and the third insulating layer 112 , and the first conductive layer 111 is in contact with the main gate 109 .

具体地，请参照图16和图17，主栅极109位于源极层105a和漏极层103a之间且环绕半导体材料层104a。如图18和图19所示，第二绝缘层110能够起到进一步增强相邻存储单元10之间均匀性的作用；第一导电层111用于制作字线WL，字线WL直接与主栅极109接触有利于提升动态存储器的集成度，第三绝缘层112起到后续导电层与第一导电层111绝缘的作用。Specifically, referring to Figures 16 and 17, the main gate 109 is located between the source layer 105a and the drain layer 103a and surrounds the semiconductor material layer 104a. As shown in Figures 18 and 19, the second insulating layer 110 can further enhance the uniformity between adjacent memory cells 10; the first conductive layer 111 is used to make the word line WL, which is directly connected to the main gate. The contact between the poles 109 is beneficial to improving the integration level of the dynamic memory, and the third insulating layer 112 serves to insulate the subsequent conductive layer from the first conductive layer 111 .

S3：通过构图工艺形成贯穿漏极层、半导体材料层和源极层的容纳孔，其中，被容纳孔贯穿后的漏极层形成漏极，被容纳孔贯穿后的半导体材料层形成半导体层，被容纳孔贯穿后的源极层形成源极。S3: Form an accommodation hole penetrating the drain layer, semiconductor material layer and source layer through a patterning process, wherein the drain layer penetrated by the accommodation hole forms a drain electrode, and the semiconductor material layer penetrated by the accommodation hole forms a semiconductor layer, The source layer penetrated by the receiving hole forms a source electrode.

具体地，如图20至图22所示，仍以存储单元10还包括连接部102和第一绝缘层106为例进行说明。此时，步骤S3包括：Specifically, as shown in FIGS. 20 to 22 , the memory unit 10 further includes a connection portion 102 and a first insulating layer 106 as an example. At this time, step S3 includes:

S301：依据侧墙107对第一绝缘材料层106a、源极层105a、半导体材料层104a、漏极层103a进行刻蚀，以形成贯穿第一绝缘材料层106a、源极层105a、半导体材料层104a、漏极层103a的容纳孔400，被容纳孔400贯穿的第一绝缘材料层106a即为第一绝缘层106，被容纳孔400贯穿的源极层105a即为源极105，被容纳孔400贯穿的半导体材料层104a即为半导体层104，被容纳孔400贯穿的漏极层103a即为漏极103。可选地，在依据侧墙107对第一绝缘材料层106a、源极层105a、半导体材料层104a、漏极层103a进行刻蚀之前，去除位于侧墙107内的牺牲部300。S301: Etch the first insulating material layer 106a, the source layer 105a, the semiconductor material layer 104a, and the drain layer 103a according to the sidewalls 107 to form a layer that penetrates the first insulating material layer 106a, the source layer 105a, and the semiconductor material layer. 104a. The receiving hole 400 of the drain layer 103a. The first insulating material layer 106a penetrated by the receiving hole 400 is the first insulating layer 106. The source layer 105a penetrated by the receiving hole 400 is the source 105. The receiving hole The semiconductor material layer 104a penetrated by the receiving hole 400 is the semiconductor layer 104, and the drain electrode layer 103a penetrated by the receiving hole 400 is the drain electrode 103. Optionally, before etching the first insulating material layer 106a, the source layer 105a, the semiconductor material layer 104a, and the drain layer 103a according to the spacers 107, the sacrificial portion 300 located in the spacers 107 is removed.

S302：对半导体层104进行第二局部刻蚀以使半导体层104的内径大于漏极103的内径。S302: Perform a second local etching on the semiconductor layer 104 to make the inner diameter of the semiconductor layer 104 larger than the inner diameter of the drain electrode 103.

具体地，如图22所示，通过对侧墙107的内径和外径的设计来确定源极105和漏极103的内外径，并且侧墙107的设计结合半导体层104的刻蚀工艺能够确定半导体层104的内外径，从而确定半导体层104的长宽比，进而使得存储单元10中的晶体管T具有所需的特性。Specifically, as shown in FIG. 22 , the inner and outer diameters of the source electrode 105 and the drain electrode 103 are determined by designing the inner diameter and outer diameter of the spacer 107 , and the design of the spacer 107 can be determined by combining the etching process of the semiconductor layer 104 The inner and outer diameters of the semiconductor layer 104 determine the aspect ratio of the semiconductor layer 104 so that the transistor T in the memory unit 10 has required characteristics.

S4：在容纳孔400内依次形成背栅极114和电容电极116，电容电极116与参考电位线Vref电连接且与源极105、漏极103、主栅极109和背栅极114绝缘，其中，电容电极116与背栅极114构成存储电容C1，背栅极114与源极105构成辅助电容C2。S4: The back gate 114 and the capacitor electrode 116 are sequentially formed in the receiving hole 400. The capacitor electrode 116 is electrically connected to the reference potential line Vref and is insulated from the source electrode 105, the drain electrode 103, the main gate electrode 109 and the back gate electrode 114, wherein , the capacitor electrode 116 and the back gate electrode 114 form the storage capacitor C1, and the back gate electrode 114 and the source electrode 105 form the auxiliary capacitor C2.

具体地，如图23至图33所示，仍以存储单元10还包括连接部102和第一绝缘层106为例进行说明。此时，步骤S4包括：Specifically, as shown in FIGS. 23 to 33 , the memory unit 10 further includes a connection portion 102 and a first insulating layer 106 as an example. At this time, step S4 includes:

S401：在容纳孔400内沉积第二栅极介质层113，并对位于容纳孔400底部的第二栅极介质层113进行刻蚀以使连接部102暴露。S401: Deposit the second gate dielectric layer 113 in the accommodation hole 400, and etch the second gate dielectric layer 113 located at the bottom of the accommodation hole 400 to expose the connection portion 102.

具体地，如图24和图25所示，第二栅极介质层113使得后续制作的背栅极114与源极105、漏极103绝缘，且第二栅极介质层113作为源极105与背栅极114之间的介质层以使源极105与背栅极114构成辅助电容C2。暴露的连接部102可与后续制作的背栅极114直接接触从而实现背栅极114和漏极103的电连接。Specifically, as shown in FIGS. 24 and 25 , the second gate dielectric layer 113 insulates the subsequently produced back gate 114 from the source 105 and the drain 103 , and the second gate dielectric layer 113 serves as the source electrode 105 and the drain electrode 103 . The dielectric layer between the back gate electrodes 114 allows the source electrode 105 and the back gate electrode 114 to form a auxiliary capacitor C2. The exposed connection portion 102 can be in direct contact with the subsequently fabricated back gate 114 to achieve electrical connection between the back gate 114 and the drain 103 .

S402：在容纳孔400内依次沉积背栅极114、电容介质层115和电容电极116，背栅极114与连接部102以及第二栅极介质层113接触。S402: sequentially deposit the back gate 114, the capacitor dielectric layer 115 and the capacitor electrode 116 in the accommodation hole 400, and the back gate 114 is in contact with the connection part 102 and the second gate dielectric layer 113.

具体地，如图26和图27所示，电容介质层115使得背栅极114和电容电极116 绝缘，且电容介质层115作为背栅极114与电容电极116之间的介质以使背栅极114和电容电极116构成存储电容C1。Specifically, as shown in FIGS. 26 and 27 , the capacitive dielectric layer 115 makes the back gate 114 and the capacitive electrode 116 Insulation, and the capacitive dielectric layer 115 serves as a medium between the back gate 114 and the capacitive electrode 116 so that the back gate 114 and the capacitive electrode 116 form a storage capacitor C1.

S403：去除位于第二栅极介质层113和电容介质层115之间的部分背栅极114以形成环形凹槽，并在环形凹槽填充绝缘材料以形成第四绝缘层117。S403: Remove part of the back gate 114 between the second gate dielectric layer 113 and the capacitor dielectric layer 115 to form an annular groove, and fill the annular groove with insulating material to form the fourth insulating layer 117.

具体地，如图28和图29所示，第四绝缘层117是为了使得后续制作的参考电位线Vref与背栅极114绝缘。Specifically, as shown in FIGS. 28 and 29 , the fourth insulating layer 117 is used to insulate the reference potential line Vref produced later from the back gate 114 .

S404：对第三绝缘层112和第一导电层111进行刻蚀以去除刻蚀区域的第三绝缘层112，并且去除刻蚀区域的第一导电层111以形成字线WL，并在刻蚀区域沉积第五绝缘层118。S404: Etch the third insulating layer 112 and the first conductive layer 111 to remove the third insulating layer 112 in the etching area, and remove the first conductive layer 111 in the etching area to form the word line WL, and etching A fifth insulating layer 118 is deposited in the area.

具体地，如图30和图31所示，在制作过程中，先制作图形化光刻胶层500，再利用图形化光刻胶层500作为掩膜进行刻蚀以去除刻蚀区域的第三绝缘层112，并且去除刻蚀区域的第一导电层111以形成字线WL。Specifically, as shown in Figures 30 and 31, during the production process, a patterned photoresist layer 500 is first produced, and then etching is performed using the patterned photoresist layer 500 as a mask to remove the third layer of the etched area. The insulating layer 112 is removed, and the first conductive layer 111 in the etched area is removed to form the word line WL.

S405：通过构图工艺在第四绝缘层117上形成参考电位线Vref，并在参考电位线Vref上沉积第六绝缘层120，参考电位线Vref与电容电极116接触。S405: Form a reference potential line Vref on the fourth insulating layer 117 through a patterning process, and deposit the sixth insulating layer 120 on the reference potential line Vref. The reference potential line Vref is in contact with the capacitor electrode 116.

具体地，如图32和图33所示，先在第四绝缘层117上形成第二导电层119并进行刻蚀以获得参考电位线Vref。参考电位线Vref用于为存储单元10提供参考电位，并且参考电位线Vref直接与电容电极116接触也有利于减少膜层，降低生产成本。Specifically, as shown in FIGS. 32 and 33 , the second conductive layer 119 is first formed on the fourth insulating layer 117 and etched to obtain the reference potential line Vref. The reference potential line Vref is used to provide a reference potential for the memory cell 10, and the reference potential line Vref being in direct contact with the capacitor electrode 116 is also beneficial to reducing film layers and reducing production costs.

S406：通过构图工艺在第六绝缘层120上形成位线BL，位线BL通过过孔与源极105电连接。S406: Form a bit line BL on the sixth insulating layer 120 through a patterning process, and the bit line BL is electrically connected to the source electrode 105 through a via hole.

具体地，形成的结构请参照图1，在具体制作时，先在第六绝缘层120上形成第三导电层121并进行刻蚀以获得位线BL。形成的动态存储器的存储单元10中的源极105、漏极103、半导体层104、主栅极109和背栅极114等构成一个晶体管T，电容电极116和背栅极114构成存储电容C1，也就是每个存储单元10包括一个晶体管T和一个存储电容C1，而在该存储单元10中，背栅极114和源极105构成一个辅助电容C2，从而增加存储单元10的电容量，使得存储节点N1能够维持更长的时间，从而在无需增加膜层以保证动态存储器的集成度的同时降低了动态存储器的刷新频率；采用外延生长以及侧墙107技术来制作，制作方法较为简单，且侧墙107技术利于提升动态存储器的精度。Specifically, please refer to FIG. 1 for the structure formed. During specific fabrication, the third conductive layer 121 is first formed on the sixth insulating layer 120 and etched to obtain the bit line BL. The source 105, drain 103, semiconductor layer 104, main gate 109 and back gate 114 in the memory cell 10 of the formed dynamic memory constitute a transistor T, and the capacitor electrode 116 and the back gate 114 constitute the storage capacitor C1. That is, each memory cell 10 includes a transistor T and a storage capacitor C1, and in the memory cell 10, the back gate 114 and the source 105 form an auxiliary capacitor C2, thereby increasing the capacitance of the memory cell 10, so that the storage Node N1 can be maintained for a longer time, thereby reducing the refresh frequency of dynamic memory without adding film layers to ensure the integration of dynamic memory; it is produced using epitaxial growth and sidewall 107 technology, the production method is relatively simple, and the sidewall Wall 107 technology helps improve the accuracy of dynamic memory.

基于同一发明构思，本申请实施例提供了一种读写方法，用于对上述实施例中的存储单元进行读写，如图1至图5以及图34所示，该读写方法包括：Based on the same inventive concept, embodiments of the present application provide a reading and writing method for reading and writing the storage unit in the above embodiment, as shown in Figures 1 to 5 and Figure 34. The reading and writing method includes:

T1：在写入状态时，通过字线WL向待写入的存储单元10的主栅极109施加第一电平以使晶体管T导通，并通过位线BL向待写入的存储单元10的源极105传输存储信号，以将存储信号写入待写入的存储单元10作为存储数据。T1: In the writing state, the first level is applied to the main gate 109 of the memory cell 10 to be written through the word line WL to turn on the transistor T, and the first level is applied to the memory cell 10 to be written through the bit line BL. The source 105 transmits the storage signal to write the storage signal into the storage unit 10 to be written as storage data.

在动态存储器处于写入工作模式时，通过字线WL向主栅极109施加第一电平(例如5V，具体数值可根据实际情况进行调整)，以使晶体管T处于导通状态，第一电平的大小与晶体管T的结构、晶体管T中半导体层的材料等因素相关，具体可根据实际情况进行调整。When the dynamic memory is in the write operation mode, a first level (for example, 5V, the specific value can be adjusted according to the actual situation) is applied to the main gate 109 through the word line WL, so that the transistor T is in a conductive state, and the first voltage The size of the flat is related to factors such as the structure of the transistor T and the material of the semiconductor layer in the transistor T, and can be adjusted according to the actual situation.

如图1至图4所示，在数据写入时，当通过字线WL向主栅极109施加第一电平则晶体管T导通，并通过位线BL输入的数据信号写入到存储节点N1，数据写入完成则通过调整字线WL施加到主栅极109的电位使得晶体管T关闭，在晶体管T关闭后，即使存在漏电现象，但存储电容C1和辅助电容C2的存在能够对存储节点N1的电位进行保持。 As shown in FIGS. 1 to 4 , during data writing, when a first level is applied to the main gate 109 through the word line WL, the transistor T is turned on, and the data signal input through the bit line BL is written to the storage node. N1, after the data writing is completed, the potential applied to the main gate 109 by the word line WL is adjusted to turn off the transistor T. After the transistor T is turned off, even if there is leakage, the existence of the storage capacitor C1 and the auxiliary capacitor C2 can affect the storage node. The potential of N1 is maintained.

由于背栅极114与源极105构成辅助电容C2，因此，即使在完成数据写入之后晶体管T转变为关断状态，辅助电容C2中存储的电荷也能够使得存储节点N1(即背栅极114、漏极103以及存储电容C1的电容电极116)的电位能够维持更长的时间，从而降低刷新频率。Since the back gate 114 and the source 105 form the auxiliary capacitor C2, even if the transistor T transitions to the off state after completing the data writing, the charge stored in the auxiliary capacitor C2 can make the storage node N1 (ie, the back gate 114 , the potential of the drain electrode 103 and the capacitor electrode 116 of the storage capacitor C1) can be maintained for a longer period of time, thereby reducing the refresh frequency.

T2：在读取状态时，通过字线WL向待读取的存储单元10的主栅极109施加第二电平，以使位线BL感测待读取的存储单元10的存储数据。T2: In the read state, the second level is applied to the main gate 109 of the memory cell 10 to be read through the word line WL, so that the bit line BL senses the storage data of the memory cell 10 to be read.

如图1至图3所示，在数据读取时，对主栅极109施加第二电平，若该存储单元10处于“1”状态，则主栅极109在第二电平(例如主栅极电位VG＝0.3V，此时源极电位VS＝0)下打开，能够获取存储节点的信号；若该存储单元10处于“0”状态，则在相同的栅极和源极偏置下晶体管T未导通，即无法检测到存储节点的信号。As shown in Figures 1 to 3, when data is read, a second level is applied to the main gate 109. If the memory cell 10 is in the "1" state, the main gate 109 is at the second level (for example, the main The gate potential VG=0.3V, at this time, the source potential VS=0) is turned on, and the signal of the storage node can be obtained; if the memory cell 10 is in the "0" state, then under the same gate and source bias The transistor T is not turned on, that is, the signal from the storage node cannot be detected.

需要说明的是，在动态存储器的读写过程中，均向参考电位线Vref提供参考电位。在一个具体的实施例中，参考电位为地电平。It should be noted that during the reading and writing process of the dynamic memory, the reference potential is provided to the reference potential line Vref. In a specific embodiment, the reference potential is ground level.

本实施例提供的读写方法，既能够采用电流检测方式也可以采用电压检测方式。以电流检测为例，当存储单元10之前存储的是数据“1”时，背栅极114和漏极103上具有一较高的电位，在第二电平的共同作用下，晶体管T处于导通的状态，因此可通过位线BL测得较为明显的电流。当测得较为明显的电流时，判断读取的数据为“1”。当存储单元10之前存储的是数据“0”时，主栅极109上施加第二电平后，晶体管T仍处于关断的状态，因此可以认为位线BL并未检测到电流，此时判断读取的数据为“0”。The reading and writing method provided in this embodiment can adopt either the current detection method or the voltage detection method. Taking current detection as an example, when the memory cell 10 previously stored data "1", the back gate 114 and the drain 103 had a higher potential. Under the joint action of the second level, the transistor T was in conductive state. On state, therefore a relatively obvious current can be measured through the bit line BL. When a relatively obvious current is measured, the read data is judged to be "1". When the memory cell 10 previously stored data "0", after the second level is applied to the main gate 109, the transistor T is still in the off state, so it can be considered that the bit line BL has not detected current. At this time, it is judged The data read is "0".

需要说明的是，晶体管T的阈值电压的大小和背栅极114以及漏极103上电位的大小相关，对于N型场效应晶体管(晶体管导通时载流子为电子)，背栅极114以及漏极103的电位越高，阈值电压越小，即主栅极109和源极105之间的压差较小时，晶体管T也能被导通；背栅极114以及漏极103上的电位越低，阈值电压越大。It should be noted that the threshold voltage of the transistor T is related to the potential on the back gate 114 and the drain 103. For an N-type field effect transistor (carriers are electrons when the transistor is turned on), the back gate 114 and The higher the potential of the drain 103, the smaller the threshold voltage, that is, when the voltage difference between the main gate 109 and the source 105 is small, the transistor T can also be turned on; the higher the potential on the back gate 114 and the drain 103 The lower, the greater the threshold voltage.

如图3所示，图3中的横坐标为施加在主栅极109上的电压(即第二电平)，纵坐标为晶体管T的输出电流。当施加在主栅极109上的第二电平为某一特定值(图3中虚线位置)时，背栅极114和漏极103上电压的高低(即晶体管T写入的数据是“1”还是“0”)会使晶体管T的输出电流(即通过位线BL所测的电流)的大小具有显著的差别。通过检测位线BL上电流即可实现将数据从存储单元10中读出，当晶体管T写入数据“1”时，晶体管T的输出电流较大，因此读取的数据也是“1”；当晶体管T写入的数据是“0”时，晶体管T的输出电流极为微弱，因此读取的数据也是“0”。As shown in FIG. 3 , the abscissa in FIG. 3 is the voltage applied to the main gate 109 (ie, the second level), and the ordinate is the output current of the transistor T. When the second level applied to the main gate 109 is a certain value (the dotted line position in Figure 3), the voltage on the back gate 114 and the drain 103 (that is, the data written by the transistor T is "1") ” or “0”) will make a significant difference in the size of the output current of transistor T (that is, the current measured through bit line BL). Data can be read from the memory cell 10 by detecting the current on the bit line BL. When the transistor T writes data "1", the output current of the transistor T is large, so the read data is also "1"; When the data written by transistor T is "0", the output current of transistor T is extremely weak, so the data read is also "0".

第二电平的数值可根据晶体管T的参数以及在进行写操作时施加给背栅极114和漏极103上电压的大小确定。需要说明的是，第二电平的数值需要是合适的(需要位于晶体管T存储“1”时的阈值电压与晶体管T存储“0”时的阈值电压之间)，否则可能存在晶体管T误导通或者误断开的风险，影响动态存储器的性能。具体地，可通过实验或者模拟的方法确定最合适的第二电平的值，以保证晶体管T在不同的状态下的正确导通或断开，以提高读取性能。The value of the second level can be determined according to the parameters of the transistor T and the magnitude of the voltage applied to the back gate 114 and the drain 103 during the writing operation. It should be noted that the value of the second level needs to be appropriate (it needs to be between the threshold voltage when the transistor T stores "1" and the threshold voltage when the transistor T stores "0"), otherwise the transistor T may be misdirected. Or there is the risk of mistaken disconnection, which affects the performance of dynamic memory. Specifically, the most appropriate value of the second level can be determined through experiments or simulations to ensure that the transistor T is correctly turned on or off in different states to improve reading performance.

通过上述说明可知，本实施例提供的存储单元，在读取过程中，存储单元10处于“1”状态则位线BL能够获取存储节点信号，存储单元10处于“0”状态则位线BL不能获取存储节点信号，也就是“1”或“0”两种状态下位线BL读取的数据信号差异巨大，使得动态存储器的抗噪声性能增强；而且相对于现有技术中只能通过检测晶体管T输出电流的大小来实现存储单元10的“1”或“0”状态的判断而言，本实施例由于“0”状态下检测不到信号，则既可以利用电流信号进行检测也可以利用电压信号进行检测，从而便于根据具体需求设计***检测电路，具有更好地适应性。 It can be seen from the above description that in the memory unit provided by this embodiment, during the reading process, if the memory unit 10 is in the "1" state, the bit line BL can obtain the storage node signal, and if the memory unit 10 is in the "0" state, the bit line BL cannot. Obtaining the storage node signal, that is, the data signal read by the bit line BL in the two states of "1" or "0" has a huge difference, which enhances the anti-noise performance of the dynamic memory; and compared with the existing technology, which can only be detected by the detection transistor T In terms of determining the “1” or “0” state of the memory cell 10 by the size of the output current, in this embodiment, since no signal is detected in the “0” state, either the current signal or the voltage signal can be used for detection. Detection is carried out to facilitate the design of peripheral detection circuits according to specific needs and have better adaptability.

应用本申请实施例，至少能够实现如下有益效果：By applying the embodiments of this application, at least the following beneficial effects can be achieved:

1)本实施例提供的存储单元及制作方法、动态存储器、存储装置、读写方法，源极、漏极、半导体层、主栅极和背栅极等构成一个晶体管，电容电极和背栅极构成存储电容，也就是每个存储单元包括一个晶体管和一个存储电容，而在该存储单元中，背栅极和源极构成一个辅助电容，从而增加存储单元的电容量，使得存储节点能够维持更长的时间，从而在无需增加膜层以保证动态存储器的集成度的同时降低了动态存储器的刷新频率。1) In the memory unit and manufacturing method, dynamic memory, storage device, and reading and writing method provided in this embodiment, the source, drain, semiconductor layer, main gate, and back gate constitute a transistor, and the capacitor electrode and back gate are To form a storage capacitor, that is, each storage unit includes a transistor and a storage capacitor, and in the storage unit, the back gate and the source form an auxiliary capacitor, thus increasing the capacitance of the storage unit and allowing the storage node to maintain a longer Therefore, there is no need to add film layers to ensure the integration of dynamic memory and at the same time reduce the refresh frequency of dynamic memory.

本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。Those skilled in the art can understand that the steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Furthermore, the steps, measures, and solutions in the prior art with various operations, methods, and processes disclosed in this application can also be replaced, changed, rearranged, decomposed, combined, or deleted.

在本申请的描述中，词语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方向或位置关系，为基于附图所示的示例性的方向或位置关系，是为了便于描述或简化描述本申请的实施例，而不是指示或暗示所指的装置或部件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。In the description of this application, the words "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", " The directions or positional relationships indicated by "bottom", "inner", "outer", etc. are based on the exemplary directions or positional relationships shown in the drawings, and are for convenience of describing or simplifying the description of the embodiments of the present application, rather than indicating or It is implied that the device or component referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore is not to be construed as a limitation on the application.

术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。The terms “first” and “second” are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, "plurality" means two or more.

在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。In the description of this specification, specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

应该理解的是，虽然附图的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤的实施顺序并不受限于箭头所指示的顺序。除非本文中有明确的说明，否则在本申请实施例的一些实施场景中，各流程中的步骤可以按照需求以其他的顺序执行。而且，各流程图中的部分或全部步骤基于实际的实施场景，可以包括多个子步骤或者多个阶段。这些子步骤或者阶段中的部分或全部可以在同一时刻被执行，也可以在不同的时刻被执行在执行时刻不同的场景下，这些子步骤或者阶段的执行顺序可以根据需求灵活配置，本申请实施例对此不限制。It should be understood that although various steps in the flowchart of the accompanying drawings are shown in sequence as indicated by arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated in this article, in some implementation scenarios of the embodiments of this application, the steps in each process may be executed in other orders according to requirements. Moreover, some or all of the steps in each flowchart are based on actual implementation scenarios and may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time or at different times. In scenarios with different execution times, the execution order of these sub-steps or stages can be flexibly configured according to needs. This application implements There is no limit to this.

以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请的方案技术构思的前提下，采用基于本申请技术思想的其他类似实施手段，同样属于本申请实施例的保护范畴。 The above are only some implementations of the present application. It should be pointed out that for those of ordinary skill in the technical field, other similar implementation means based on the technical ideas of the present application may be adopted without departing from the technical concept of the present application. , also belongs to the protection scope of the embodiments of this application.

Claims

一种存储单元，其特征在于，包括：A storage unit, characterized by including:

位于衬底上且呈柱状的电容电极，所述电容电极与参考电位线电连接；A columnar capacitance electrode located on the substrate, the capacitance electrode being electrically connected to the reference potential line;

位于所述电容电极与所述衬底之间且环绕所述电容电极的背栅极，所述背栅极与所述电容电极绝缘且与所述电容电极构成存储电容；a back gate located between the capacitor electrode and the substrate and surrounding the capacitor electrode, the back gate being insulated from the capacitor electrode and forming a storage capacitor with the capacitor electrode;

位于所述衬底的一侧且在远离所述衬底的方向上依次堆叠的漏极、半导体层和源极，所述漏极、所述半导体层和所述源极环绕所述电容电极且位于所述背栅极远离所述电容电极的一侧，所述漏极、半导体层和源极在平行于所述衬底的截面为环形，所述漏极与所述背栅极电连接，所述背栅极与所述源极构成辅助电容；A drain electrode, a semiconductor layer and a source electrode located on one side of the substrate and sequentially stacked in a direction away from the substrate, the drain electrode, the semiconductor layer and the source electrode surrounding the capacitor electrode and Located on the side of the back gate away from the capacitor electrode, the drain electrode, semiconductor layer and source electrode are annular in cross-section parallel to the substrate, and the drain electrode is electrically connected to the back gate electrode, The back gate and the source form an auxiliary capacitor;

环绕所述半导体层的外侧壁的主栅极，所述主栅极与字线电连接且与所述源极和所述漏极绝缘。A main gate surrounding the outer sidewall of the semiconductor layer, the main gate being electrically connected to the word line and insulated from the source and the drain.
根据权利要求1所述的存储单元，其特征在于，还包括连接部，所述连接部位于所述衬底和所述漏极之间且位于所述衬底和所述背栅极之间，所述连接部直接与所述漏极接触同时与所述背栅极接触，所述连接部的材料为导电材料；The memory cell of claim 1, further comprising a connection portion located between the substrate and the drain and between the substrate and the back gate, The connecting part is directly in contact with the drain and the back gate, and the material of the connecting part is a conductive material;

所述连接部在所述衬底上的正投影所在的区域为第一区域，包围所述第一区域的区域为第二区域，位于所述第一区域的所述衬底的厚度大于位于所述第二区域的所述衬底的厚度。The area where the orthographic projection of the connecting portion on the substrate is located is the first area, the area surrounding the first area is the second area, and the thickness of the substrate located in the first area is greater than that located in the first area. The thickness of the substrate in the second region.
根据权利要求2所述的存储单元，其特征在于，还包括：The storage unit according to claim 2, further comprising:

位于所述源极远离所述衬底一侧的第一绝缘层；a first insulating layer located on the side of the source electrode away from the substrate;

位于所述第一绝缘层远离所述衬底一侧的侧墙；Sidewalls located on the side of the first insulating layer away from the substrate;

所述侧墙、所述第一绝缘层、所述源极以及所述漏极在所述衬底上的正投影重合，所述半导体层在所述衬底上的正投影位于所述漏极在所述衬底上的正投影内，所述漏极在所述衬底上的正投影位于所述连接部在所述衬底上的正投影内。The orthographic projections of the sidewalls, the first insulating layer, the source electrode and the drain electrode on the substrate coincide with each other, and the orthographic projection of the semiconductor layer on the substrate is located on the drain electrode. Within the orthographic projection of the substrate, the orthographic projection of the drain on the substrate is located within the orthographic projection of the connection portion on the substrate.
根据权利要求3所述的存储单元，其特征在于，所述侧墙、所述第一绝缘层、所述源极、所述半导体层以及所述漏极均为环形，所述半导体层的内径大于所述漏极的内径，且所述半导体层的外径小于所述漏极的外径。The memory unit of claim 3, wherein the sidewalls, the first insulating layer, the source, the semiconductor layer and the drain are all annular, and the inner diameter of the semiconductor layer is larger than the inner diameter of the drain electrode, and the outer diameter of the semiconductor layer is smaller than the outer diameter of the drain electrode.
根据权利要求4所述的存储单元，其特征在于，The storage unit according to claim 4, characterized in that:

所述主栅极位于所述源极和所述漏极之间，所述字线与所述主栅极材料相同且与所述主栅极接触，所述字线在所述衬底上的正投影位于所述第二区域；The main gate is located between the source and the drain. The word line is made of the same material as the main gate and is in contact with the main gate. The word line is on the substrate. The orthographic projection is located in the second area;

所述参考电位线位于所述电容电极远离所述衬底的一侧且与所述电容电极接触；The reference potential line is located on a side of the capacitor electrode away from the substrate and is in contact with the capacitor electrode;

位线位于所述参考电位线远离所述衬底的一侧且通过过孔与所述源极电连接。A bit line is located on a side of the reference potential line away from the substrate and is electrically connected to the source electrode through a via hole.
根据权利要求2-5中任一项所述的存储单元，其特征在于，所述衬底的材料为P型硅材料，所述连接部的材料为N型重掺杂硅材料，所述漏极为N型硅材料，所述源极的材料为N型硅材料，所述半导体层的材料为锗化硅材料。The memory unit according to any one of claims 2 to 5, characterized in that the material of the substrate is P-type silicon material, the material of the connection part is N-type heavily doped silicon material, and the drain The electrode is made of N-type silicon material, the source electrode is made of N-type silicon material, and the semiconductor layer is made of silicon germanium material.
根据权利要求3所述的存储单元，其特征在于，还包括：The storage unit according to claim 3, further comprising:

第一栅极介质层，位于所述连接部、所述漏极、所述半导体层、所述源极和所述第一绝缘层的外侧壁以及位于所述第二区域的所述衬底上；A first gate dielectric layer located on the connecting portion, the drain electrode, the semiconductor layer, the source electrode and the outer sidewalls of the first insulating layer and on the substrate in the second region ;

第二绝缘层，位于所述第二区域且位于所述第一栅极介质层远离所述衬底的一侧；a second insulating layer located in the second region and on the side of the first gate dielectric layer away from the substrate;

第二栅极介质层，位于所述连接部、所述漏极、所述半导体层、所述源极和所述第一绝缘层的内侧壁；A second gate dielectric layer is located on the inner sidewalls of the connection part, the drain electrode, the semiconductor layer, the source electrode and the first insulating layer;

电容介质层，位于所述背栅极和所述电容电极之间； A capacitive dielectric layer located between the back gate and the capacitive electrode;

第三绝缘层，位于所述字线远离所述衬底的一侧；A third insulating layer located on the side of the word line away from the substrate;

第四绝缘层，位于所述第二栅极介质层和所述电容介质层之间且位于所述背栅极远离所述衬底的一侧；A fourth insulating layer, located between the second gate dielectric layer and the capacitive dielectric layer and located on the side of the back gate away from the substrate;

第五绝缘层，填充所述字线以及所述第三绝缘层的侧面；A fifth insulating layer, filling the word lines and the sides of the third insulating layer;

第六绝缘层，位于所述参考电位线所在导电层和所述位线所在导电层之间。A sixth insulating layer is located between the conductive layer where the reference potential line is located and the conductive layer where the bit line is located.
一种动态存储器，其特征在于，包括：衬底、位于所述衬底上的多条字线、多条位线、多条参考电位线和多个权利要求1至7中任一项所述的存储单元；A dynamic memory, characterized by comprising: a substrate, a plurality of word lines, a plurality of bit lines, a plurality of reference potential lines located on the substrate and a plurality of claims 1 to 7. storage unit;

多个所述存储单元分为多个存储单元组，多个所述存储单元组在垂直于所述衬底的方向上排布；A plurality of the memory cells are divided into a plurality of memory unit groups, and the plurality of memory unit groups are arranged in a direction perpendicular to the substrate;

每个所述存储单元组包括多个在平行于所述衬底的方向上呈阵列排布的存储单元，其中位于同一行的各所述存储单元与同一字线电连接，位于同一列的各所述存储单元与同一位线电连接。Each memory cell group includes a plurality of memory cells arranged in an array in a direction parallel to the substrate, wherein each memory cell located in the same row is electrically connected to the same word line, and each memory cell located in the same column is electrically connected to the same word line. The memory cells are electrically connected to the same bit line.
一种存储装置，其特征在于，包括权利要求8所述的动态存储器。A storage device, characterized by comprising the dynamic memory according to claim 8.
一种存储单元的制作方法，其特征在于，所述制作方法包括：A method of manufacturing a storage unit, characterized in that the manufacturing method includes:

提供一衬底，通过构图工艺在所述衬底的一侧形成依次堆叠的漏极层、半导体材料层和源极层，所述漏极层、半导体材料层和源极层为圆柱形；Provide a substrate, and form a sequentially stacked drain layer, semiconductor material layer and source layer on one side of the substrate through a patterning process, where the drain layer, semiconductor material layer and source layer are cylindrical;

形成环绕所述半导体层的主栅极，所述主栅极与字线电连接且与所述源极层和所述漏极层绝缘；forming a main gate surrounding the semiconductor layer, the main gate being electrically connected to the word line and insulated from the source layer and the drain layer;

通过构图工艺形成贯穿所述漏极层、所述半导体材料层和所述源极层的容纳孔，其中，被所述容纳孔贯穿后的所述漏极层形成漏极，被所述容纳孔贯穿后的所述半导体材料层形成半导体层，被所述容纳孔贯穿后的所述源极层形成源极；A receiving hole penetrating the drain layer, the semiconductor material layer and the source layer is formed through a patterning process, wherein the drain layer penetrated by the receiving hole forms a drain electrode, and the receiving hole is The semiconductor material layer penetrated forms a semiconductor layer, and the source electrode layer penetrated by the accommodation hole forms a source electrode;

在所述容纳孔内依次形成背栅极和电容电极，所述电容电极与参考电位线电连接且与所述源极、所述漏极、所述主栅极和所述背栅极绝缘，其中，所述电容电极与所述背栅极构成存储电容，所述背栅极与所述源极构成辅助电容。A back gate and a capacitor electrode are sequentially formed in the accommodation hole, and the capacitor electrode is electrically connected to the reference potential line and insulated from the source, the drain, the main gate and the back gate, Wherein, the capacitor electrode and the back gate electrode form a storage capacitor, and the back gate electrode and the source electrode form a auxiliary capacitor.
根据权利要求10所述的存储单元的制作方法，其特征在于，所述存储单元还包括位于所述衬底和所述漏极之间的连接部以及位于所述源极远离所述衬底一侧的第一绝缘层，所述连接部直接与所述漏极接触同时与所述背栅极接触，所述连接部的材料为导电材料；The method of manufacturing a memory unit according to claim 10, wherein the memory unit further includes a connection portion between the substrate and the drain electrode and a connection portion between the source electrode and the source electrode away from the substrate. The first insulating layer on the side, the connecting portion is directly in contact with the drain and the back gate, and the material of the connecting portion is a conductive material;

通过构图工艺在所述衬底的一侧形成依次堆叠的漏极层、半导体材料层和源极层，包括：A sequentially stacked drain layer, semiconductor material layer and source layer are formed on one side of the substrate through a patterning process, including:

通过外延生长法在所述衬底上依次生长连接层、所述漏极层、半导体材料层、源极层和第一绝缘材料层；Sequentially grow the connection layer, the drain layer, the semiconductor material layer, the source layer and the first insulating material layer on the substrate through an epitaxial growth method;

通过构图工艺在所述第一绝缘材料层远离所述衬底的一侧形成多个侧墙和位于各所述侧墙内的牺牲部，其中，所述侧墙和所述牺牲部所在的区域为第一区域，包围所述第一区域的区域为第二区域；A plurality of sidewalls and sacrificial portions located in each sidewall are formed on the side of the first insulating material layer away from the substrate through a patterning process, wherein the area where the sidewalls and the sacrificial portion are located is the first area, and the area surrounding the first area is the second area;

依据所述侧墙对所述第一绝缘材料层、所述源极层、所述半导体材料层、所述漏极层进行刻蚀，以形成圆柱形的所述第一绝缘材料层、所述源极层、所述半导体材料层、所述漏极层，并且对位于第二区域的衬底进行刻蚀，以使位于所述第一区域的所述衬底的厚度大于位于所述第二区域的所述衬底的厚度。The first insulating material layer, the source layer, the semiconductor material layer, and the drain layer are etched according to the sidewalls to form the cylindrical first insulating material layer, the source layer, the semiconductor material layer, the drain layer, and etching the substrate located in the second region so that the thickness of the substrate located in the first region is greater than that located in the second region. area of the substrate thickness.
根据权利要求11所述的存储单元的制作方法，其特征在于，形成环绕所述半导体层的主栅极，所述主栅极与所述字线电连接且与所述源极层和所述漏极层绝缘，包括： The method of manufacturing a memory cell according to claim 11, wherein a main gate is formed surrounding the semiconductor layer, the main gate is electrically connected to the word line and is connected to the source layer and the Drain layer insulation, including:

对所述半导体材料层进行第一局部刻蚀以使所述半导体材料层的外径小于所述漏极层的外径；Perform a first local etching on the semiconductor material layer to make the outer diameter of the semiconductor material layer smaller than the outer diameter of the drain layer;

在经过第一局部刻蚀之后的所述连接部、所述漏极层、所述半导体材料层、所述源极层和所述第一绝缘材料层的外侧壁以及位于所述第二区域的所述衬底上沉积第一栅极介质层；After the first local etching, the outer sidewalls of the connection portion, the drain layer, the semiconductor material layer, the source layer and the first insulating material layer, as well as those located in the second region depositing a first gate dielectric layer on the substrate;

在所述第一栅极介质层远离所述半导体材料层的一侧形成主栅极；Form a main gate on the side of the first gate dielectric layer away from the semiconductor material layer;

在位于所述第二区域的所述第一栅极介质层远离所述衬底的一侧依次形成第二绝缘层、第一导电层和第三绝缘层，所述第一导电层与所述主栅极接触。A second insulating layer, a first conductive layer and a third insulating layer are sequentially formed on the side of the first gate dielectric layer located in the second region away from the substrate. The first conductive layer and the Main gate contact.
根据权利要求12所述的存储单元的制作方法，其特征在于，通过构图工艺形成贯穿所述漏极层、所述半导体材料层和所述源极层的容纳孔，包括：The method of manufacturing a memory cell according to claim 12, wherein a receiving hole penetrating the drain layer, the semiconductor material layer and the source layer is formed through a patterning process, including:

依据所述侧墙对所述第一绝缘材料层、所述源极层、所述半导体材料层、所述漏极层进行刻蚀，以形成贯穿所述第一绝缘材料层、所述源极层、所述半导体材料层和所述漏极层的容纳孔；Etch the first insulating material layer, the source layer, the semiconductor material layer, and the drain layer according to the sidewalls to form a layer that penetrates the first insulating material layer, the source layer, and the source layer. layer, the semiconductor material layer and the receiving hole of the drain layer;

对所述半导体层进行第二局部刻蚀以使所述半导体层的内径大于所述漏极的内径。A second local etching is performed on the semiconductor layer to make the inner diameter of the semiconductor layer larger than the inner diameter of the drain electrode.
根据权利要求13所述的存储单元的制作方法，其特征在于，在所述容纳孔内依次形成背栅极和电容电极，所述电容电极与所述参考电位线电连接且与所述源极、所述漏极、所述主栅极和所述背栅极绝缘，包括：The method of manufacturing a memory cell according to claim 13, wherein a back gate and a capacitor electrode are sequentially formed in the accommodation hole, and the capacitor electrode is electrically connected to the reference potential line and to the source electrode. , the drain, the main gate and the back gate insulation, including:

在所述容纳孔内形成第二栅极介质层，并对位于所述容纳孔底部的所述第二栅极介质层进行刻蚀以使所述连接部暴露；Form a second gate dielectric layer in the accommodation hole, and etch the second gate dielectric layer located at the bottom of the accommodation hole to expose the connection portion;

在所述容纳孔内依次沉积背栅极、电容介质层和电容电极，所述背栅极与所述连接部以及所述第二栅极介质层接触；A back gate, a capacitor dielectric layer and a capacitor electrode are sequentially deposited in the accommodation hole, and the back gate is in contact with the connection part and the second gate dielectric layer;

去除位于所述第二栅极介质层和所述电容介质层之间的部分背栅极以形成环形凹槽，并在所述环形凹槽填充绝缘材料以形成第四绝缘层；Remove a portion of the back gate located between the second gate dielectric layer and the capacitor dielectric layer to form an annular groove, and fill the annular groove with an insulating material to form a fourth insulating layer;

对所述第三绝缘层和所述第一导电层进行刻蚀以去除刻蚀区域的所述第三绝缘层，并且去除所述刻蚀区域的所述第一导电层以形成所述字线，并在所述刻蚀区域沉积第五绝缘层；The third insulating layer and the first conductive layer are etched to remove the third insulating layer in the etched area, and the first conductive layer in the etched area is removed to form the word line , and deposit a fifth insulating layer in the etching area;

通过构图工艺在所述第四绝缘层上形成参考电位线，并在所述参考电位线上沉积第六绝缘层，所述参考电位线与所述电容电极接触；A reference potential line is formed on the fourth insulating layer through a patterning process, and a sixth insulating layer is deposited on the reference potential line, and the reference potential line is in contact with the capacitor electrode;

通过构图工艺在所述第六绝缘层上形成位线，所述位线通过过孔与所述源极电连接。A bit line is formed on the sixth insulating layer through a patterning process, and the bit line is electrically connected to the source electrode through a via hole.
一种读写方法，其特征在于，用于对权利要求1-7中任一项所述的存储单元进行读写，所述读写方法包括：A reading and writing method, characterized in that it is used to read and write the storage unit according to any one of claims 1 to 7, and the reading and writing method includes:

在写入状态时，通过所述字线向待写入的存储单元的主栅极施加第一电平以使晶体管导通，并通过位线向所述待写入的存储单元的源极传输存储信号，以将所述存储信号写入所述待写入的存储单元作为存储数据；In the writing state, a first level is applied to the main gate of the memory cell to be written through the word line to turn on the transistor, and is transmitted to the source of the memory cell to be written through the bit line. store a signal to write the storage signal into the storage unit to be written as storage data;

在读取状态时，通过所述字线向待读取的存储单元的主栅极施加第二电平，以使所述位线感测所述待读取的存储单元的存储数据。 In the read state, a second level is applied to the main gate of the memory cell to be read through the word line, so that the bit line senses the stored data of the memory cell to be read.