WO2024026966A1 - 流水线型模数转换器 - Google Patents

流水线型模数转换器 Download PDF

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Publication number
WO2024026966A1
WO2024026966A1 PCT/CN2022/116673 CN2022116673W WO2024026966A1 WO 2024026966 A1 WO2024026966 A1 WO 2024026966A1 CN 2022116673 W CN2022116673 W CN 2022116673W WO 2024026966 A1 WO2024026966 A1 WO 2024026966A1
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analog
digital
switched capacitor
terminal
output
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PCT/CN2022/116673
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English (en)
French (fr)
Inventor
刘涛
王健安
邓民明
刘璐
付东兵
张正平
俞宙
王旭
陈光炳
吴雪美
周晓丹
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重庆吉芯科技有限公司
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Publication of WO2024026966A1 publication Critical patent/WO2024026966A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array

Definitions

  • the present invention relates to the technical field of analog integrated circuits, and in particular to a pipeline type analog-to-digital converter.
  • Pipelined ADC is one of the commonly used analog-to-digital converter structure types.
  • the pipelined ADC is a multi-stage low-precision and high-sampling-rate analog-to-digital converter pipeline (hereinafter referred to as the pipeline stage). They are cascaded in turn, and the digital output of each pipeline stage is processed according to a certain algorithm to obtain the final encoded output, which makes it have the characteristics of high speed and high precision.
  • each pipeline stage is mainly composed of a sub-analog converter (Sub ADC), a sub-digital-to-analog converter (Sub DAC), a subtraction unit and a multiplication unit.
  • the sub-analog converter quantizes and encodes the analog input signal to obtain a digital signal.
  • the sub-digital-to-analog converter performs digital-to-analog conversion on the digital signal to obtain an analog output voltage.
  • the analog input signal is subtracted from the analog output voltage and amplified to obtain the residual output signal.
  • sub-digital-to-analog converters, subtractors and multiplication units are all implemented with switched capacitors, and this switched capacitor circuit is called a multiplying digital-to-analog converter (MDAC).
  • MDAC multiplying digital-to-analog converter
  • a typical implementation is a switched capacitor DAC array.
  • the switched capacitor DAC array has a 2 N relationship with the resolution N. As the resolution N increases, the switched capacitor DAC array grows exponentially, causing the area overhead and power consumption overhead of the switched capacitor circuit to continue to increase. And the increase in capacitance will also limit the increase in speed.
  • the purpose of the present invention is to provide a technical solution for a pipelined analog-to-digital converter to simplify the structure of the switched capacitor circuit in the pipelined analog-to-digital converter and reduce its area and power consumption. And improve its analog-to-digital conversion speed.
  • a pipeline analog-to-digital converter including multiple pipeline stages cascaded in sequence, at least one of the pipeline stages includes:
  • the N-bit analog-to-digital conversion module receives analog input signals and performs analog-to-digital conversion on the analog input signals to obtain and output 2 N digital signals;
  • the first sub-digital-to-analog conversion module receives 2 N-1 digital signals and performs digital-to-analog conversion on 2 N-1 digital signals to obtain and output a first analog signal;
  • the second sub-digital-to-analog conversion module receives another 2 N-1 digital signals and performs digital-to-analog conversion on another 2 N-1 digital signals to obtain and output a second analog signal;
  • the switched capacitor amplification module receives the first analog signal and the second analog signal, performs a difference operation on the first analog signal and the second analog signal, and performs an amplification operation on the result of the difference operation to obtain And output analog output signal;
  • N is an integer greater than or equal to 1.
  • the N-bit sub-analog-to-digital conversion module includes:
  • the first resistor voltage dividing unit divides the initial reference voltage and outputs 2 N in-phase reference voltages to the outside;
  • the second resistor voltage dividing unit divides the initial reference voltage and outputs 2 N inverted reference voltages to the outside;
  • the comparator array unit is respectively connected to the first resistor voltage dividing unit and the second resistor voltage dividing unit, receives the analog input signal, and compares the analog input signal with 2 N reference voltages respectively, 2 N digital signals are obtained, and the 2 N digital signals include 2 N-1 first digital signals and 2 N-1 second digital signals, wherein the 2 N in-phase reference voltages are the same as 2 N
  • the inverted reference voltages correspond one to one, forming 2 N reference voltages.
  • the first resistor voltage dividing unit includes a first input port, a second input port and 2 N +1 first resistors, and the 2 N +1 first resistors are connected in series to the first input port. and the second input port, the first input port is connected to the positive terminal of the initial reference voltage, the second input port is connected to the negative terminal of the initial reference voltage, two adjacent first The common terminal of the resistor outputs one of the non-inverting reference voltages.
  • the second resistor voltage dividing unit includes a third input port, a fourth input port and 2 N +1 second resistors, and the 2 N +1 second resistors are connected in series to the third input port. and the fourth input port, the third input port is connected to the negative terminal of the initial reference voltage, the fourth input port is connected to the positive terminal of the initial reference voltage, two adjacent second The common terminal of the resistor outputs one of the inverted reference voltages.
  • the comparator array unit includes:
  • 2 N comparators which compare and quantify the analog input signals with the 2 N reference voltages one by one, and output 2 N-1 first initial digital signals and 2 N-1 second initial digital signals;
  • 2 N drivers the input terminals of 2 N drivers are connected to the output terminals of 2 N comparators in a one-to-one correspondence, and the output terminals of 2 N drivers externally output 2 N signals controlled by the first clock signal. -1 said first digital signal and 2 N-1 said second digital signal.
  • 2 N comparators are arranged in parallel.
  • the first input terminal of the comparator is connected to the positive terminal of the analog input signal
  • the second input terminal of the comparator is connected to the positive terminal of the analog input signal.
  • the input terminal is connected to the negative terminal of the analog input signal
  • the third input terminal of the comparator is connected to the i-th in-phase reference voltage
  • the fourth input terminal of the comparator is connected to the i-th inverting reference voltage.
  • the first input terminal of the driver is connected to the first output terminal of the i-th comparator, and the second input terminal of the driver is connected to the i-th comparator.
  • i second output terminals of the comparators, and a third input terminal of the driver connected to the first clock signal;
  • the output terminal of the mth comparator outputs a first initial digital signal
  • the output terminal of the mth driver outputs a first digital signal
  • the output terminal of the nth comparator outputs a first digital signal.
  • a second initial digital signal is output
  • the output terminal of the n-th driver outputs a second digital signal
  • m is an odd number between 1 and 2 N
  • n is an even number between 1 and 2 N.
  • the driver includes a first NAND gate, a first NOR gate, a first NOT gate, a second NOT gate and a third NOT gate, and the first input end of the first NAND gate serves as the The first input terminal of the driver, the second input terminal of the first NAND gate is connected to the output terminal of the first NOT gate, and the output terminal of the first NAND gate is connected to the input terminal of the second NOT gate.
  • the output terminal of the second NOT gate serves as the second output terminal of the driver
  • the input terminal of the first NOT gate serves as the third input terminal of the driver
  • the first input terminal of the first NOR gate The input terminal of the first NOR gate is connected to the input terminal of the first NOR gate.
  • the second input terminal of the first NOR gate serves as the second input terminal of the driver.
  • the output terminal of the first NOR gate is connected to the third NOT gate.
  • the input terminal of the gate and the output terminal of the third NOT gate serve as the first output terminal of the driver.
  • the first sub-digital-to-analog conversion module includes 2 N-1 first switched capacitor units arranged in parallel, the first input terminal of the jth first switched capacitor unit is connected to the second clock signal, and the jth first switched capacitor unit is connected to the second clock signal.
  • the second input terminal of the jth first switched capacitor unit is connected to the positive terminal of the analog input signal, and the third input terminal of the jth first switched capacitor unit is connected to the positive terminal of the initial reference voltage.
  • the fourth input terminal of the jth first switched capacitor unit is connected to the negative terminal of the initial reference voltage, and the fifth input terminal of the jth first switched capacitor unit is connected to the jth first digital signal.
  • the second sub-digital-to-analog conversion module includes 2 N-1 second switched capacitor units arranged in parallel.
  • the first input terminal of the j-th second switched capacitor unit is connected to the second clock signal, and the j-th second switched capacitor unit is connected to the second clock signal.
  • the second input terminal of the second switched capacitor unit is connected to the negative terminal of the analog input signal
  • the third input terminal of the jth second switched capacitor unit is connected to the positive terminal of the initial reference voltage
  • the jth second switched capacitor unit is connected to the positive terminal of the initial reference voltage.
  • the fourth input terminal of the second switched capacitor unit is connected to the negative terminal of the initial reference voltage
  • the fifth input terminal of the jth second switched capacitor unit is connected to the positive terminal of the jth second digital signal.
  • the sixth input terminal of the j-th second switched capacitor unit is connected to the negative terminal of the j-th second digital signal
  • the output terminals of 2 N-1 second switched capacitor units are connected in parallel and externally Output the second analog signal.
  • the first switched capacitor unit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a switched capacitor, and the gate of the first NMOS transistor serves as the first capacitor of the first switched capacitor unit.
  • Input terminal, the drain of the first NMOS transistor serves as the second input terminal of the first switched capacitor unit, and the gate of the second NMOS transistor serves as the sixth input terminal of the first switched capacitor unit, so
  • the drain of the second NMOS transistor serves as the fourth input terminal of the first switched capacitor unit, and the gate of the first PMOS transistor serves as the fifth input terminal of the first switched capacitor unit.
  • the source of the tube serves as the third input terminal of the first switched capacitor unit.
  • the source of the first NMOS tube, the source of the second NMOS tube and the drain of the first PMOS tube are connected respectively.
  • One end of the switched capacitor and the other end of the switched capacitor serve as the output end of the first switched capacitor unit.
  • the switched capacitor amplification module includes a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first capacitor, a second capacitor and a fully differential operational amplifier.
  • the third NMOS tube The gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor are respectively connected to the third clock signal, and the drain of the third NMOS transistor and the drain of the fifth NMOS transistor are respectively connected to the third clock signal.
  • the source, the source of the fourth NMOS transistor, the inverting input terminal of the fully differential operational amplifier, the output terminal of the second sub-digital-to-analog conversion module and one terminal of the second capacitor are connected together, so The other end of the second capacitor, the non-inverting output terminal of the fully differential operational amplifier and the source of the sixth NMOS tube are connected together, and the gate of the sixth NMOS tube is connected to the fourth clock signal.
  • the non-inverting output end of the differential operational amplifier serves as the positive output end of the switched capacitor amplification module, and the inverting output end of the fully differential operational amplifier serves as the negative output end of the switched capacitor amplification module.
  • the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.
  • the pipeline analog-to-digital converter provided by the present invention has at least the following beneficial effects:
  • At least one pipeline stage is based on the structure of "N-bit sub-analog-to-digital conversion module + first sub-digital-to-analog conversion module + second sub-digital-to-analog conversion module + switched capacitor amplification module".
  • the first The sub-digital-to-analog conversion module and the second sub-digital-to-analog conversion module respectively accept and process 2 N-1 digital signals, corresponding to the need for 2*2 N-1 switched capacitors.
  • the non-inverting input and the inverting input of the differential input comparison are completely symmetrical, correspondingly requiring 2*2 N switching capacitors. Therefore, compared with the pipeline stage with the traditional structure, this The invention can effectively reduce the number of sub-digital-analog conversion switching capacitors in the pipeline stage, reduce the area of the switched capacitor array, reduce the power consumption of the switched capacitor array, and improve the processing speed of the pipeline stage.
  • Figure 1 shows a schematic structural diagram of the pipeline stages of a pipeline analog-to-digital converter in the prior art.
  • FIG. 2 shows a circuit diagram of the pipeline stages of a pipelined analog-to-digital converter according to an embodiment of the present invention.
  • Figure 3 shows the circuit diagram of the N-bit sub-analog-to-digital conversion module 1 in Figure 2.
  • FIG. 4 shows a circuit diagram of the first resistor voltage dividing unit 11 in FIG. 3 .
  • FIG. 5 shows a circuit diagram of the second resistor voltage dividing unit 12 in FIG. 3 .
  • FIG. 6 shows a circuit diagram of the comparator array unit 13 in FIG. 3 .
  • Figure 7 shows the circuit diagram of the driver in Figure 6.
  • FIG. 8 shows a circuit diagram of the first sub-digital-to-analog conversion module 2 in FIG. 2 .
  • FIG. 9 shows a circuit diagram of the second sub-digital-to-analog conversion module 3 in FIG. 2 .
  • FIG. 10 shows a circuit diagram of the first switched capacitor unit in FIG. 8 .
  • FIG. 11 shows a timing state diagram of the first clock signal ⁇ 1, the second clock signal ⁇ 2, the third clock signal ⁇ 3 and the fourth clock signal ⁇ 4 in FIG. 2 .
  • Figure 12 shows a schematic diagram of the transmission curve of the pipeline stage of the pipeline type analog-to-digital converter in Figure 2.
  • the inventor found through research that: for the pipeline stage shown in Figure 1, it mainly consists of a sub-analog-to-digital converter (Sub ADC), a sub-digital-to-analog converter (Sub DAC), a subtraction unit and It consists of a multiplication unit.
  • the sub-analog-to-digital converter quantizes and encodes the analog input signal VIN to obtain a digital signal.
  • the sub-digital-to-analog converter performs digital-to-analog conversion on the digital signal to obtain the analog output voltage D (VIN).
  • the sub-digital-to-analog converter, subtractor and multiplication unit are all implemented with switched capacitors, and this switched capacitor circuit is called multiplicative digital-to-analog conversion. converter (MDAC), and the typical implementation of the switched capacitor circuit is a switched capacitor array.
  • the switched capacitor array has a 2 N relationship with the resolution N. As the resolution N increases, the switched capacitor array (especially the corresponding sub-digital-to-analog converter) Switched capacitor arrays, pipeline-level neutron digital-to-analog converters with N-bit resolution require 2*2 N switched capacitors) grow exponentially, causing the area overhead and power consumption overhead of switched capacitor circuits to continue to increase, and the increase in capacitance also Will limit the speed increase.
  • the present invention proposes a new design solution for a pipeline analog-to-digital converter: based on "N-bit sub-analog-to-digital conversion module + first sub-digital-to-analog conversion module + second sub-digital-to-analog conversion module + switched capacitor amplification module"
  • the pipeline-level structure splits the digital output of the N-bit sub-analog-to-digital conversion module into two parts, and correspondingly splits the sub-digital-to-analog conversion module into two parts, and controls them one by one through the digital output of the two parts of the N-bit sub-analog-to-digital conversion module.
  • Two different sub-digital-to-analog conversion modules to simplify the number of switched capacitors in the sub-digital-to-analog conversion module, reduce power consumption and increase processing speed.
  • the present invention proposes a pipeline analog-to-digital converter, which includes multiple pipeline stages cascaded in sequence. As shown in Figure 2, at least one pipeline stage includes:
  • N-bit analog-to-digital conversion module 1 receives the analog input signal VIN and performs analog-to-digital conversion on the analog input signal VIN to obtain and output 2 N digital signals, that is, 2 N-1 first digital signals DO ⁇ 2 N-1 : 1> and 2 N-1 second digital signals DE ⁇ 2 N-1 :1>;
  • the first sub-digital-to-analog conversion module 2 receives 2 N-1 digital signals (i.e., the first digital signal DO ⁇ 2 N-1 :1>) and performs digital-to-analog conversion on the 2 N-1 digital signals to obtain and output first analog signal V1;
  • the second sub-digital-to-analog conversion module 3 receives another 2 N-1 digital signals (i.e., the second digital signal DE ⁇ 2 N-1 :1>) and performs digital-to-analog conversion on the other 2 N-1 digital signals to obtain And output the second analog signal V2;
  • the switched capacitor amplification module 4 receives the first analog signal V1 and the second analog signal V2, performs a difference operation on the first analog signal V1 and the second analog signal V2, and amplifies the result of the difference operation to obtain and output the analog signal.
  • N is an integer greater than or equal to 1.
  • the N-bit sub-analog-to-digital conversion module 1 includes:
  • the first resistor voltage dividing unit 11 divides the initial reference voltage VREF and outputs 2 N in-phase reference voltages, that is, the in-phase reference voltage Vrefp ⁇ 2 N-1 :1>;
  • the second resistor voltage dividing unit 12 divides the initial reference voltage VREF and outputs 2 N inverted reference voltages, that is, the inverted reference voltage Vrefn ⁇ 2 N-1 :1>;
  • the comparator array unit 13 is respectively connected to the first resistor voltage dividing unit 11 and the second resistor voltage dividing unit 12, receives the analog input signal VIN, and compares the analog input signal VIN with 2 N reference voltages respectively to obtain 2 N digital signals
  • 2 N digital signals include 2 N-1 first digital signals (i.e., first digital signals DO ⁇ 2 N-1 :1>) and 2 N-1 second digital signals (i.e., second digital signals DO ⁇ 2 N-1:1>) Signal DE ⁇ 2 N-1 :1>), where 2 N in-phase reference voltages correspond to 2 N inverting reference voltages one-to-one, forming 2 N reference voltages, that is, the non-phase reference voltage Vrefp ⁇ 2 N-1 > It forms a reference voltage with the inverting reference voltage Vrefn ⁇ 2 N-1 >, and the non-inverting reference voltage Vrefp ⁇ 2 N-1 -1> and the inverting reference voltage Vrefn ⁇ 2 N-1 -1> form a reference voltage,..., The non-inverting
  • the first resistor voltage dividing unit 11 includes a first input port VRP01, a second input port VRN01 and 2 N +1 first resistors, that is, first resistors R(1) 1 , The first resistor R(2) 1 , the first resistor R(3) 1 , ..., the first resistor R(2 N -1) 1 , the first resistor R(2 N ) 1 and the first resistor R(2 N + 1) 1 , 2 N +1 first resistors are connected in series between the first input port VRP01 and the second input port VRN01, that is, the first resistor R(2 N +1) 1 , the first resistor R(2 N ) 1 , first resistor R(2 N -1) 1 ,..., first resistor R(3) 1 , first resistor R(2) 1 and first resistor R(1) 1 are connected in series to the first input Between the port VRP01 and the second input port VRN01, the first input port VRP01 is connected to the positive terminal VRP of
  • the second resistor voltage dividing unit 12 includes a third input port VRP02, a fourth input port VRN02 and 2 N +1 second resistors, that is, second resistors R(1) 2 , The second resistor R(2) 2 , the second resistor R(3) 2 , ..., the second resistor R(2 N -1) 2 , the second resistor R(2 N ) 2 and the second resistor R(2 N + 1) 2 , 2 N +1 second resistors are connected in series between the third input port VRP02 and the fourth input port VRN02, that is, the second resistor R(2 N +1) 2 , the second resistor R(2 N ) 2 , the second resistor R(2 N -1) 2 ,..., the second resistor R(3) 2 , the second resistor R(2) 2 and the second resistor R(1) 2 are connected in series to the third input Between the port VRP02 and the fourth input port VRN02, the third input port VRP02 is connected to the negative
  • R(1) 1 R(2 N +1) 1
  • R( 2) 1 2 ⁇ R(1) 1
  • R(1) 2 R(2 N +1) 2
  • R(2) 2 2 ⁇ R(1) 2 .
  • the comparator array unit 13 includes:
  • 2 N comparators namely comparator U(2 N ) 131 , comparator U(2 N -1) 131 ,..., comparator U(2) 131 and comparator U(1) 131 , convert the analog input signal VIN Compare and quantify with 2 N reference voltages one by one, and output 2 N-1 first initial digital signals (i.e., first initial digital signal DO ⁇ 2 N :1>0) and 2 N-1 second initial digital signals. (i.e. the second initial digital signal DE ⁇ 2 N :1>0);
  • 2 N drivers namely driver U(2 N ) 132 , driver U(2 N -1) 132 ,..., driver U(2) 132 and driver U(1) 132
  • the input terminals of 2 N drivers are connected with 2 N
  • the output terminals of the two comparators are connected in a one-to-one correspondence.
  • the input terminal of the driver U(2 N ) 132 is connected to the output terminal of the comparator U(2 N ) 131.
  • the input terminal of the driver U(2 N -1) 132 is connected to the comparator U.
  • 2 N comparators are set up in parallel.
  • the first input terminal Vin+ of the comparator is connected to the positive terminal VIN(+) of the analog input signal VIN.
  • the second input terminal Vin- of the comparator is connected to the negative terminal VIN(-) of the analog input signal VIN
  • the third input terminal Vref+ of the comparator is connected to the i-th non-inverting reference voltage Vrefp ⁇ i>
  • the first input terminal A1 of the driver is connected to the first output terminal OP of the i-th comparator, and the second input terminal A2 of the driver is connected to the i-th comparator.
  • the second output terminals of i comparators are ON, and the third input terminal CK of the driver is connected to the first clock signal ⁇ 1;
  • the output terminal of the mth comparator U(m) 131 outputs a first initial digital signal
  • the output terminal of the mth driver U(m) 132 outputs a first digital signal
  • the nth comparator U(n) ) The output terminal of 131 outputs a second initial digital signal
  • the output terminal of the n-th driver U(n) 132 outputs a second digital signal.
  • first digital signals DO ⁇ 2 N :1> are obtained at the odd-numbered output ports of the comparator array unit 13 and 2 N are obtained at the even-numbered output ports of the comparator array unit 13.
  • second digital signal ie, the second digital signal DE ⁇ 2 N :1>
  • the output first digital signal and the second digital signal are controlled by the first clock signal ⁇ 1.
  • N drivers have the same structure.
  • Each driver includes a first NAND gate U1, a first NOR gate U2, a first NOT gate U3, a second NOT gate U4 and a third NOT gate U5, the first input terminal of the first NAND gate U1 serves as the first input terminal A1 of the driver, the second input terminal of the first NAND gate U1 is connected with the output terminal of the first NOT gate U3, and the first NAND gate
  • the output terminal of U1 is connected to the input terminal of the second NOT gate U4.
  • the output terminal of the second NOT gate U4 is used as the second output terminal Y2 of the driver.
  • the input terminal of the first NOT gate U3 is used as the third input terminal CK of the driver.
  • the first input terminal of the NOR gate U2 is connected to the input terminal of the first NOR gate U3, the second input terminal of the first NOR gate U2 serves as the second input terminal A2 of the driver, and the output terminal of the first NOR gate U2 is connected to the second input terminal A2 of the driver.
  • the input terminal of the three NOT gate U5 and the output terminal of the third NOT gate U5 serve as the first output terminal Y1 of the driver.
  • the first sub-digital-to-analog conversion module 2 includes 2 N-1 first switched capacitor units arranged in parallel, that is, first switched capacitor units U(2 N-1 ) 2 ,..., The first switched capacitor unit U(2) 2 and the first switched capacitor unit U(1) 2.
  • first switched capacitor units U(2 N-1 ) 2 For the j-th first switched capacitor unit U(j) 2 , its first input terminal CKS1 is connected to the second clock signal ⁇ 2, Its second input terminal VI1 is connected to the positive terminal VIN(+) of the analog input signal VIN, its third input terminal VRP1 is connected to the positive terminal VRP of the initial reference voltage VREF, and its fourth input terminal VRN1 is connected to the negative terminal VRN of the initial reference voltage VREF.
  • the second sub-digital-to-analog conversion module 3 includes 2 N-1 second switched capacitor units arranged in parallel, that is, the second switched capacitor unit U(2 N-1 ) 3 ,..., The second switched capacitor unit U(2) 3 and the second switched capacitor unit U(1) 3.
  • its first input terminal CKS2 is connected to the second clock signal ⁇ 2
  • Its second input terminal VI2 is connected to the negative terminal VIN(-) of the analog input signal VIN
  • its third input terminal VRP2 is connected to the positive terminal VRP of the initial reference voltage VREF
  • its fourth input terminal VRN2 is connected to the negative terminal VRN of the initial reference voltage VREF.
  • the j-th first switched capacitor unit U(j) 2 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1 and a switched capacitor C U.
  • the first NMOS transistor The gate of MN1 serves as the first input terminal CKS1 of the first switched capacitor unit U(j) 2
  • the drain of the first NMOS transistor MN1 serves as the second input terminal VI1 of the first switched capacitor unit U(j) 2 .
  • the gate of the NMOS transistor MN2 serves as the sixth input terminal CK22 ⁇ j> of the first switched capacitor unit U(j) 2
  • the drain of the second NMOS transistor MN2 serves as the fourth input of the first switched capacitor unit U(j) 2 .
  • the gate of the first PMOS transistor MP1 serves as the fifth input terminal CK21 ⁇ j> of the first switched capacitor unit U(j) 2
  • the source of the first PMOS transistor MP1 serves as the first switched capacitor unit U(j)
  • the third input terminal VRP1 of 2 , the source of the first NMOS transistor MN1, the source of the second NMOS transistor MN2 and the drain of the first PMOS transistor MP1 are respectively connected to one end of the switched capacitor C U , and the other end of the switched capacitor C U As the output terminal D of the first switched capacitor unit U(j) 2.
  • the structure of the second switched capacitor unit is the same as that of the first switched capacitor unit, and will not be described again here.
  • the switched capacitor amplification module 4 includes a third NMOS transistor N1, a fourth NMOS transistor N2, a fifth NMOS transistor N3, a sixth NMOS transistor N4, a first capacitor C FP and a second capacitor C FN.
  • the gate of the third NMOS transistor N1, the gate of the fourth NMOS transistor N2 and the gate of the fifth NMOS transistor N3 are respectively connected to the third clock signal ⁇ 3, the drain of the third NMOS transistor N1 and The drain of the fifth NMOS transistor N3 is respectively connected to the basic signal VB, the source of the fifth NMOS transistor N3, the drain of the fourth NMOS transistor N2, the non-inverting input terminal IN+ of the fully differential operational amplifier OTA, and the first sub-digital-to-analog conversion module.
  • the output terminal of 2 and one terminal of the first capacitor C FP are connected together.
  • the other terminal of the first capacitor C FP , the inverting output terminal VO- of the fully differential operational amplifier OTA and the drain of the sixth NMOS transistor N4 are connected together.
  • the source of the third NMOS transistor N1, the source of the fourth NMOS transistor N2, the inverting input terminal IN- of the fully differential operational amplifier OTA, the output terminal of the second sub-digital-to-analog conversion module 3 and the second capacitor C FN One end is connected together, the other end of the second capacitor C FN , the non-inverting output terminal VO+ of the fully differential operational amplifier OTA and the source of the sixth NMOS transistor N4 are connected together, and the gate of the sixth NMOS transistor N4 is connected to the fourth clock signal.
  • the non-inverting output terminal VO+ of the fully differential operational amplifier OTA is used as the output positive terminal VOUT(+) of the switched capacitor amplification module 4
  • the inverting output terminal VO- of the fully differential operational amplifier OTA is used as the output negative terminal VOUT of the switched capacitor amplification module 4.
  • the capacitance value of the first capacitor C FP is equal to the capacitance value of the second capacitor CFN .
  • the timing state diagram of the first clock signal ⁇ 1, the second clock signal ⁇ 2, the third clock signal ⁇ 3 and the fourth clock signal ⁇ 4 is as shown in Figure 11, and The phases of the first clock signal ⁇ 1, the second clock signal ⁇ 2, the third clock signal ⁇ 3 and the fourth clock signal ⁇ 4 are the same.
  • the first sub-digital-to-analog conversion module 2 and the second sub-digital-to-analog conversion module 3 Both are in sampling mode: the gate voltage of the second NMOS transistor MN2 in each first switched capacitor unit and the second switched capacitor unit is low level, the second NMOS transistor MN2 is in the off mode, and the gate voltage of the first PMOS transistor MP1 The gate voltage of the first PMOS transistor MP1 is high level, the gate voltage of the first NMOS transistor MN1 is high level, and the first NMOS transistor MN1 is in the conduction mode; the third NMOS in the switched capacitor amplification module 4 The gate voltage of the tube N1, the gate voltage of the fourth NMOS tube N2 and the gate voltage of the fifth NMOS tube N3 are all high level; the switched capacitance of each first switched capacitor unit in the first sub-digital-to-analog
  • C U collects the input basic signal.
  • Signal VB the other end collects the negative terminal VIN(-) of the analog input signal VIN;
  • the gate voltage of the sixth NMOS transistor N4 in the switched capacitor amplification module 4 is high level, the sixth NMOS transistor N4 is turned on, and the switched capacitor amplification module
  • the first output terminal VOUT(+) and the second output terminal VOUT(-) of 4 are short-circuited together; therefore, the output of the pipeline stage in sampling mode is:
  • the first clock signal ⁇ 1, the second clock signal ⁇ 2, the third clock signal ⁇ 3 and the fourth clock signal ⁇ 4 are all low level
  • the first sub-digital-to-analog conversion module 2 and the second sub-digital-to-analog conversion module 3 All are in the hold mode: the gate voltage of the third NMOS transistor N1, the gate voltage of the fourth NMOS transistor N2 and the gate voltage of the fifth NMOS transistor N3 in the switched capacitor amplification module 4 are all low level
  • the third NMOS transistor N1, the fourth NMOS transistor N2 and the fifth NMOS transistor N3 are all turned off, and the non-inverting input terminal IN+ and the inverting input terminal IN- of the fully differential operational amplifier OTA are in a high impedance state
  • the sixth NMOS transistor N4 in the switched capacitor amplification module 4 The gate voltage is low level, and the sixth NMOS transistor N4 is turned off; the second NMOS transistor MN2 of each first switched capacitor unit in the first sub-digital-
  • each first switched capacitor unit (or second The second NMOS transistor MN2 and the first PMOS transistor MP1 in the switched capacitor unit) can only maintain one conduction, and the conduction and shutdown modes are determined by the output of the corresponding comparator, and the output of the comparator is determined by the analog input signal VIN and Determined by the size of the reference voltage; according to the principle of charge conservation, the output of the pipeline stage at this time is:
  • C U,1i represents the capacitance value of the switching capacitor (or sampling capacitor) C U in the i-th first switched capacitor unit in the first sub-digital-to-analog converter module
  • C U,2i represents the second The capacitance value of the switched capacitor C U in the i-th second switched capacitor unit in the sub-digital-to-analog converter module
  • Capacitor C U is connected to VRN.
  • At least one pipeline stage is based on "N-bit sub-analog conversion module + first sub-digital-to-analog conversion module + second sub-digital-to-analog conversion module + switch
  • the structure of "Capacitive Amplification Module”, the first sub-digital-to-analog conversion module and the second sub-digital-to-analog conversion module respectively accept and process 2 N-1 digital signals, that is, the output sum of the odd-numbered comparison drive structure in the N-bit sub-analog-to-digital conversion module
  • the output of the even-numbered comparison drive structure controls the first sub-digital-to-analog conversion module and the second sub-digital-to-analog conversion module respectively, which requires 2*2 N-1 switching capacitors.
  • the traditional pipeline stage with the structure of "analog conversion module + subtractor + multiplier” has a completely symmetrical non-inverting input and inverting input of the differential input comparison, which requires 2*2 N switched capacitors.
  • this The invention reduces the number of sub-digital-to-analog conversion switch capacitors at the pipeline level by 50%, corresponding to a 50% reduction in power consumption and a 1-2 times increase in processing speed. Therefore, the invention can effectively reduce the number of sub-digital-to-analog conversion switch capacitors at the pipeline level.
  • the area of the switched capacitor array is reduced, the power consumption of the switched capacitor array is reduced, and the processing speed of the pipeline level is improved.

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Abstract

本发明提供一种流水线型模数转换器，在流水线型模数转换器中，至少一级流水级包括N位子模数转换模块、第一子数模转换模块、第二子数模转换模块及开关电容放大模块，第一子数模转换模块及第二子数模转换模块分别接受处理2 N-1个数字信号，对应需要2*2 N-1个开关电容，而基于"N位子模数转换模块+子数模转换模块+减法器+乘法器"结构的传统流水级，其差分输入比较的同相输入与反相输入完全对称，对应需要2*2 N个开关电容，因此，相比于传统结构的流水级，本发明能有效减少流水级的子数模转换开关电容的数量，减少了开关电容阵列的面积，降低了开关电容阵列的功耗，并提升了流水级的处理速度。

Description

流水线型模数转换器 技术领域
本发明涉及模拟集成电路技术领域，特别是涉及一种流水线型模数转换器。
背景技术
流水线型模数转换器(Pipelined ADC)是常用的模数转换器结构类型之一，流水线型模数转换器就是将多级低精度高采样速率的模数转换器流水级(以下简称流水级)依次级联起来，并将每级流水级的数字输出按照一定算法进行处理以得到最终的编码输出，进而使得其具有高速、高精度的特点。
其中，每级流水级主要由子模数转换器(Sub ADC)、子数模转换器(Sub DAC)、减法单元和乘法单元组成，子模数转换器对模拟输入信号进行量化并编码得到数字信号，子数模转换器对数字信号进行数模转换得到模拟输出电压，模拟输入信号减去模拟输出电压并放大得到残差输出信号。在当代混合信号集成电路设计中，子数模转换器、减法器和乘法单元都是用开关电容实现，并将此开关电容电路称之为乘法数模转换器(MDAC)，而开关电容电路的典型实现方式是开关电容DAC阵列，开关电容DAC阵列与分辨率N成2 N关系，随分辨率N的增加，开关电容DAC阵列指数增长，导致开关电容电路的面积开销和功耗开销不断增加，且电容的增大也会限制速度的增加。
因此，目前亟需一种流水线型模数转换器中开关电容电路的精简方案。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种流水线型模数转换器的技术方案，以精简流水线型模数转换器中开关电容电路的结构，减少其面积和功耗，并提升其模数转换速度。
为实现上述目的及其他相关目的，本发明提供的技术方案如下。
一种流水线型模数转换器，包括多级依次级联的流水级，至少一级所述流水级包括：
N位子模数转换模块，接收模拟输入信号并对所述模拟输入信号进行模数转换，得到并输出2 N个数字信号；
第一子数模转换模块，接收2 N-1个所述数字信号并对2 N-1个所述数字信号进行数模转换，得到并输出第一模拟信号；
第二子数模转换模块，接收另外2 N-1个所述数字信号并对另外2 N-1个所述数字信号进行 数模转换，得到并输出第二模拟信号；
开关电容放大模块，接收所述第一模拟信号和所述第二模拟信号，对所述第一模拟信号和所述第二模拟信号进行求差运算并对求差运算的结果进行放大运算，得到并输出模拟输出信号；
其中，N为大于等于1的整数。
可选地，所述N位子模数转换模块包括：
第一电阻分压单元，对初始参考电压进行分压处理，对外输出2 N个同相参考电压；
第二电阻分压单元，对初始参考电压进行分压处理，对外输出2 N个反相参考电压；
比较器阵列单元，与所述第一电阻分压单元及所述第二电阻分压单元分别连接，接收所述模拟输入信号，并将所述模拟输入信号与2 N个参考电压分别进行比较，得到2 N个所述数字信号，2 N个所述数字信号包括2 N-1个第一数字信号和2 N-1个第二数字信号，其中，2 N个所述同相参考电压与2 N个所述反相参考电压一一对应，构成2 N个所述参考电压。
可选地，所述第一电阻分压单元包括第一输入端口、第二输入端口和2 N+1个第一电阻，2 N+1个第一电阻依次串接在所述第一输入端口和所述第二输入端口之间，所述第一输入端口接所述初始参考电压的正端，所述第二输入端口接所述初始参考电压的负端，相邻两个所述第一电阻的公共端输出一个所述同相参考电压。
可选地，所述第二电阻分压单元包括第三输入端口、第四输入端口和2 N+1个第二电阻，2 N+1个第二电阻依次串接在所述第三输入端口和所述第四输入端口之间，所述第三输入端口接所述初始参考电压的负端，所述第四输入端口接所述初始参考电压的正端，相邻两个所述第二电阻的公共端输出一个所述反相参考电压。
可选地，所述比较器阵列单元包括：
2 N个比较器，将所述模拟输入信号与2 N个所述参考电压一一进行比较量化，输出2 N-1个第一初始数字信号和2 N-1个第二初始数字信号；
2 N个驱动器，2 N个所述驱动器的输入端与2 N个所述比较器的输出端一一对应连接，2 N个所述驱动器的输出端对外输出受第一时钟信号控制的2 N-1个所述第一数字信号和2 N-1个所述第二数字信号。
可选地，2 N个所述比较器并行设置，在第i个所述比较器中，所述比较器的第一输入端接所述模拟输入信号的正端，所述比较器的第二输入端接所述模拟输入信号的负端，所述比较器的第三输入端接第i个所述同相参考电压，所述比较器的第四输入端接第i个所述反相参考电压，i＝1、2、…、2 N；
2 N个所述驱动器并行设置，在第i个所述驱动器中，所述驱动器的第一输入端接第i个所述比较器的第一输出端，所述驱动器的第二输入端接第i个所述比较器的第二输出端，所述驱动器的第三输入端接所述第一时钟信号；
其中，第m个所述比较器的输出端输出一个所述第一初始数字信号，第m个所述驱动器的输出端输出一个所述第一数字信号，第n个所述比较器的输出端输出一个所述第二初始数字信号，第n个所述驱动器的输出端输出一个所述第二数字信号，m为1～2 N的奇数，n为1～2 N的偶数。
可选地，所述驱动器包括第一与非门、第一或非门、第一非门、第二非门及第三非门，所述第一与非门的第一输入端作为所述驱动器的第一输入端，所述第一与非门的第二输入端接所述第一非门的输出端，所述第一与非门的输出端接所述第二非门的输入端，所述第二非门的输出端作为所述驱动器的第二输出端，所述第一非门的输入端作为所述驱动器的第三输入端，所述第一或非门的第一输入端接所述第一非门的输入端，所述第一或非门的第二输入端作为所述驱动器的第二输入端，所述第一或非门的输出端接所述第三非门的输入端，所述第三非门的输出端作为所述驱动器的第一输出端。
可选地，所述第一子数模转换模块包括2 N-1个并行设置的第一开关电容单元，第j个所述第一开关电容单元的第一输入端接第二时钟信号，第j个所述第一开关电容单元的第二输入端接所述模拟输入信号的正端，第j个所述第一开关电容单元的第三输入端接所述初始参考电压的正端，第j个所述第一开关电容单元的第四输入端接所述初始参考电压的负端，第j个所述第一开关电容单元的第五输入端接第j个所述第一数字信号的负端，第j个所述第一开关电容单元的第六输入端接第j个所述第一数字信号的正端，2 N-1个所述第一开关电容单元的输出端并联在一起并对外输出所述第一模拟信号，j＝1、2、…、2 N-1；
所述第二子数模转换模块包括2 N-1个并行设置的第二开关电容单元，第j个所述第二开关电容单元的第一输入端接所述第二时钟信号，第j个所述第二开关电容单元的第二输入端接所述模拟输入信号的负端，第j个所述第二开关电容单元的第三输入端接所述初始参考电压的正端，第j个所述第二开关电容单元的第四输入端接所述初始参考电压的负端，第j个所述第二开关电容单元的第五输入端接第j个所述第二数字信号的正端，第j个所述第二开关电容单元的第六输入端接第j个所述第二数字信号的负端，2 N-1个所述第二开关电容单元的输出端并联在一起并对外输出所述第二模拟信号。
可选地，所述第一开关电容单元包括第一NMOS管、第二NMOS管、第一PMOS管及开关电容，所述第一NMOS管的栅极作为所述第一开关电容单元的第一输入端，所述第一 NMOS管的漏极作为所述第一开关电容单元的第二输入端，所述第二NMOS管的栅极作为所述第一开关电容单元的第六输入端，所述第二NMOS管的漏极作为所述第一开关电容单元的第四输入端，所述第一PMOS管的栅极作为所述第一开关电容单元的第五输入端，所述第一PMOS管的源极作为所述第一开关电容单元的第三输入端，所述第一NMOS管的源极、所述第二NMOS管的源极及所述第一PMOS管的漏极分别接所述开关电容的一端，所述开关电容的另一端作为所述第一开关电容单元的输出端。
可选地，所述开关电容放大模块包括第三NMOS管、第四NMOS管、第五NMOS管、第六NMOS管、第一电容、第二电容及全差分运算放大器，所述第三NMOS管的栅极、所述第四NMOS管的栅极及所述第五NMOS管的栅极分别接第三时钟信号，所述第三NMOS管的漏极及所述第五NMOS管的漏极分别接基础信号，所述第五NMOS管的源极、所述第四NMOS管的漏极、所述全差分运算放大器的同相输入端、所述第一子数模转换模块的输出端及所述第一电容的一端接在一起，所述第一电容的另一端、所述全差分运算放大器的反相输出端及所述第六NMOS管的漏极接在一起，所述第三NMOS管的源极、所述第四NMOS管的源极、所述全差分运算放大器的反相输入端、所述第二子数模转换模块的输出端及所述第二电容的一端接在一起，所述第二电容的另一端、所述全差分运算放大器的同相输出端及所述第六NMOS管的源极接在一起，所述第六NMOS管的栅极接第四时钟信号，所述全差分运算放大器的同相输出端作为所述开关电容放大模块的输出正端，所述全差分运算放大器的反相输出端作为所述开关电容放大模块的输出负端。
可选地，所述第一电容的电容值等于所述第二电容的电容值。
如上所述，本发明提供的流水线型模数转换器，至少具有以下有益效果：
在流水线型模数转换器中，至少一级流水级为基于“N位子模数转换模块+第一子数模转换模块+第二子数模转换模块+开关电容放大模块”的结构，第一子数模转换模块及第二子数模转换模块分别接受处理2 N-1个数字信号，对应需要2*2 N-1个开关电容，而基于“N位子模数转换模块+子数模转换模块+减法器+乘法器”结构的传统流水级，其差分输入比较的同相输入与反相输入完全对称，对应需要2*2 N个开关电容，因此，相比于传统结构的流水级，本发明能有效减少流水级的子数模转换开关电容的数量，减少了开关电容阵列的面积，降低了开关电容阵列的功耗，并提升了流水级的处理速度。
附图说明
图1显示为现有技术中流水线型模数转换器流水级的结构示意图。
图2显示为本发明一实施例中流水线型模数转换器流水级的电路图。
图3显示为图2中N位子模数转换模块1的电路图。
图4显示为图3中第一电阻分压单元11的电路图。
图5显示为图3中第二电阻分压单元12的电路图。
图6显示为图3中比较器阵列单元13的电路图。
图7显示为图6中驱动器的电路图。
图8显示为图2中第一子数模转换模块2的电路图。
图9显示为图2中第二子数模转换模块3的电路图。
图10显示为图8中第一开关电容单元的电路图。
图11显示为图2中第一时钟信号Ф1、第二时钟信号Ф2、第三时钟信号Ф3及第四时钟信号Ф4的时序状态图。
图12显示为图2中流水线型模数转换器的流水级的传输曲线示意图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图12。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
如前述在背景技术中所述的，发明人研究发现：针对如图1所示的流水级，其主要由子模数转换器(Sub ADC)、子数模转换器(Sub DAC)、减法单元和乘法单元组成，子模数转换器对模拟输入信号VIN进行量化并编码得到数字信号，子数模转换器对数字信号进行数模转换得到模拟输出电压D(VIN)，模拟输入信号VIN减去模拟输出电压D(VIN)并放大G倍得到残差输出信号VRES，其中，子数模转换器、减法器和乘法单元都是用开关电容实现，并将此 开关电容电路称之为乘法数模转换器(MDAC)，而开关电容电路的典型实现方式是开关电容阵列，开关电容阵列与分辨率N成2 N关系，随分辨率N的增加，开关电容阵列(尤其是子数模转换器对应的开关电容阵列，N位分辨率的流水级中子数模转换器需要2*2 N个开关电容)呈指数增长，导致开关电容电路的面积开销和功耗开销不断增加，且电容的增大也会限制速度的增加。
基于此，本发明提出一种流水线型模数转换器的新型设计方案：基于“N位子模数转换模块+第一子数模转换模块+第二子数模转换模块+开关电容放大模块”的流水级结构，将N位子模数转换模块的数字输出拆分成两部分，对应地将子数模转换模块拆分成两部分，通过N位子模数转换模块中两部分数字输出一一对应控制两个不同的子数模转换模块，以精简子数模转换模块中的开关电容数量，降低功耗并提升处理速度。
详细地，本发明提出一种流水线型模数转换器，其包括多级依次级联的流水级，如图2所示，至少一级流水级包括：
N位子模数转换模块1，接收模拟输入信号VIN并对模拟输入信号VIN进行模数转换，得到并输出2 N个数字信号，即2 N-1个第一数字信号DO<2 N-1:1>和2 N-1个第二数字信号DE<2 N-1:1>；
第一子数模转换模块2，接收2 N-1个数字信号(即第一数字信号DO<2 N-1:1>)并对2 N-1个数字信号进行数模转换，得到并输出第一模拟信号V1；
第二子数模转换模块3，接收另外2 N-1个数字信号(即第二数字信号DE<2 N-1:1>)并对另外2 N-1个数字信号进行数模转换，得到并输出第二模拟信号V2；
开关电容放大模块4，接收第一模拟信号V1和第二模拟信号V2，对第一模拟信号V1和第二模拟信号V2进行求差运算并对求差运算的结果进行放大运算，得到并输出模拟输出信号VOUT；
其中，N为大于等于1的整数。
更详细地，如图3所示，N位子模数转换模块1包括：
第一电阻分压单元11，对初始参考电压VREF进行分压处理，对外输出2 N个同相参考电压，即同相参考电压Vrefp<2 N-1:1>；
第二电阻分压单元12，对初始参考电压VREF进行分压处理，对外输出2 N个反相参考电压，即反相参考电压Vrefn<2 N-1:1>；
比较器阵列单元13，与第一电阻分压单元11及第二电阻分压单元12分别连接，接收模拟输入信号VIN，并将模拟输入信号VIN与2 N个参考电压分别进行比较，得到2 N个数字信 号，2 N个数字信号包括2 N-1个第一数字信号(即第一数字信号DO<2 N-1:1>)和2 N-1个第二数字信号(即第二数字信号DE<2 N-1:1>)，其中，2 N个同相参考电压与2 N个反相参考电压一一对应，构成2 N个参考电压，即同相参考电压Vrefp<2 N-1>与反相参考电压Vrefn<2 N-1>构成一个参考电压，同相参考电压Vrefp<2 N-1-1>与反相参考电压Vrefn<2 N-1-1>构成一个参考电压，…，同相参考电压Vrefp<i>与反相参考电压Vrefn<i>构成一个参考电压，…，同相参考电压Vrefp<2>与反相参考电压Vrefn<2>构成一个参考电压，同相参考电压Vrefp<1>与反相参考电压Vrefn<1>构成一个参考电压，i＝1、2、…、2 N。
更详细地，如图4所示，第一电阻分压单元11包括第一输入端口VRP01、第二输入端口VRN01和2 N+1个第一电阻，即为第一电阻R(1) 1、第一电阻R(2) 1、第一电阻R(3) 1、…、第一电阻R(2 N-1) 1、第一电阻R(2 N) 1及第一电阻R(2 N+1) 1，2 N+1个第一电阻依次串接在第一输入端口VRP01和第二输入端口VRN01之间，即第一电阻R(2 N+1) 1、第一电阻R(2 N) 1、第一电阻R(2 N-1) 1、…、第一电阻R(3) 1、第一电阻R(2) 1及第一电阻R(1) 1依次串接在第一输入端口VRP01和第二输入端口VRN01之间，第一输入端口VRP01接初始参考电压VREF的正端VRP，第二输入端口VRN01接初始参考电压VREF的负端VRN，相邻两个第一电阻的公共端输出一个同相参考电压，即第一电阻R(2) 1与第一电阻R(1) 1的公共端V 1<1>输出同相参考电压Vrefp<1>，第一电阻R(3) 1与第一电阻R(2) 1的公共端V 1<2>输出同相参考电压Vrefp<2>，…，第一电阻R(2 N-1) 1与第一电阻R(2 N) 1的公共端V 1<2 N-1>输出同相参考电压Vrefp<2 N-1>，第一电阻R(2 N+1) 1与第一电阻R(2 N) 1的公共端V 1<2 N>输出同相参考电压Vrefp<2 N>。
更详细地，如图5所示，第二电阻分压单元12包括第三输入端口VRP02、第四输入端口VRN02和2 N+1个第二电阻，即为第二电阻R(1) 2、第二电阻R(2) 2、第二电阻R(3) 2、…、第二电阻R(2 N-1) 2、第二电阻R(2 N) 2及第二电阻R(2 N+1) 2，2 N+1个第二电阻依次串接在第三输入端口VRP02和第四输入端口VRN02之间，即第二电阻R(2 N+1) 2、第二电阻R(2 N) 2、第二电阻R(2 N-1) 2、…、第二电阻R(3) 2、第二电阻R(2) 2及第二电阻R(1) 2依次串接在第三输入端口VRP02和第四输入端口VRN02之间，第三输入端口VRP02接初始参考电压VREF的负端VRN，第四输入端口VRN02接初始参考电压VREF的正端VRP，相邻两个第二电阻的公共端输出一个反相参考电压，即第二电阻R(2) 2与第二电阻R(1) 2的公共端V 2<1>输出反相参考电压Vrefn<1>，第二电阻R(3) 2与第二电阻R(2) 2的公共端V 2<2>输出反相参考电压Vrefn<2>，…，第二电阻R(2 N-1) 2与第二电阻R(2 N) 2的公共端V 2<2 N-1>输出反相参考电压Vrefn<2 N-1>，第二电阻R(2 N+1) 2与第二电阻R(2 N) 2的公共端V 2<2 N>输出反相参考电压 Vrefn<2 N>。
其中，R(1) 1＝R(2 N+1) 1，R(2) 1＝R(3) 1＝…＝R(2 N-1) 1＝R(2 N) 1，且R(2) 1＝2×R(1) 1；R(1) 2＝R(2 N+1) 2，R(2) 2＝R(3) 2＝…＝R(2 N-1) 2＝R(2 N) 2，且R(2) 2＝2×R(1) 2。
更详细地，如图6所示，比较器阵列单元13包括：
2 N个比较器，即比较器U(2 N) 131、比较器U(2 N-1) 131、…、比较器U(2) 131及比较器U(1) 131，将模拟输入信号VIN与2 N个参考电压一一进行比较量化，输出2 N-1个第一初始数字信号(即第一初始数字信号DO<2 N:1>0)和2 N-1个第二初始数字信号(即第二初始数字信号DE<2 N:1>0)；
2 N个驱动器，即驱动器U(2 N) 132、驱动器U(2 N-1) 132、…、驱动器U(2) 132及驱动器U(1) 132，2 N个驱动器的输入端与2 N个比较器的输出端一一对应连接，驱动器U(2 N) 132的输入端接比较器U(2 N) 131的输出端，驱动器U(2 N-1) 132的输入端接比较器U(2 N-1) 131的输出端，…，驱动器U(2) 132的输入端接比较器U(2) 131的输出端，驱动器U(1) 132的输入端接比较器U(1) 131的输出端，2 N个驱动器的输出端对外输出受第一时钟信号Φ1控制的2 N-1个第一数字信号(即第一数字信号DO<2 N:1>)和2 N-1个第二数字信号(即第二数字信号DE<2 N:1>)。
进一步地，如图6所示，2 N个比较器并行设置，在第i个比较器U(i) 131中，比较器的第一输入端Vin+接模拟输入信号VIN的正端VIN(+)，比较器的第二输入端Vin-接模拟输入信号VIN的负端VIN(-)，比较器的第三输入端Vref+接第i个同相参考电压Vrefp<i>，比较器的第四输入端Vref-接第i个反相参考电压Vrefn<i>，i＝1、2、…、2 N；
同时，2 N个驱动器并行设置，在第i个驱动器U(i) 132中，驱动器的第一输入端A1接第i个比较器的第一输出端OP，驱动器的第二输入端A2接第i个比较器的第二输出端ON，驱动器的第三输入端CK接第一时钟信号Φ1；
其中，第m个比较器U(m) 131的输出端输出一个第一初始数字信号，第m个驱动器U(m) 132的输出端输出一个第一数字信号，第n个比较器U(n) 131的输出端输出一个第二初始数字信号，第n个驱动器U(n) 132的输出端输出一个第二数字信号，m为1～2 N的奇数，n为1～2 N的偶数；最终，在比较器阵列单元13的奇数输出端口得到2 N-1个第一数字信号(即第一数字信号DO<2 N:1>)，在比较器阵列单元13的偶数输出端口得到2 N-1个第二数字信号(即第二数字信号DE<2 N:1>)，且输出的第一数字信号和第二数字信号受第一时钟信号Φ1控制。
更进一步地，如图7所示，2 N个驱动器的结构相同，每个驱动器包括第一与非门U1、第一或非门U2、第一非门U3、第二非门U4及第三非门U5，第一与非门U1的第一输入端作为驱动器的第一输入端A1，第一与非门U1的第二输入端接第一非门U3的输出端，第一与 非门U1的输出端接第二非门U4的输入端，第二非门U4的输出端作为驱动器的第二输出端Y2，第一非门U3的输入端作为驱动器的第三输入端CK，第一或非门U2的第一输入端接第一非门U3的输入端，第一或非门U2的第二输入端作为驱动器的第二输入端A2，第一或非门U2的输出端接第三非门U5的输入端，第三非门U5的输出端作为驱动器的第一输出端Y1。
更详细地，如图8所示，第一子数模转换模块2包括2 N-1个并行设置的第一开关电容单元，即第一开关电容单元U(2 N-1) 2、…、第一开关电容单元U(2) 2及第一开关电容单元U(1) 2，针对第j个第一开关电容单元U(j) 2，其第一输入端CKS1接第二时钟信号Φ2，其第二输入端VI1接模拟输入信号VIN的正端VIN(+)，其第三输入端VRP1接初始参考电压VREF的正端VRP，其第四输入端VRN1接初始参考电压VREF的负端VRN，其第五输入端CK21<j>接第j个第一数字信号DO<j>的负端，其第六输入端CK22<j>接第j个第一数字信号DO<j>的正端，2 N-1个第一开关电容单元的输出端D并联在一起并对外输出第一模拟信号V1，j＝1、2、…、2 N-1。
更详细地，如图9所示，第二子数模转换模块3包括2 N-1个并行设置的第二开关电容单元，即第二开关电容单元U(2 N-1) 3、…、第二开关电容单元U(2) 3及第二开关电容单元U(1) 3，针对第j个第二开关电容单元U(j) 3，其第一输入端CKS2接第二时钟信号Φ2，其第二输入端VI2接模拟输入信号VIN的负端VIN(-)，其第三输入端VRP2接初始参考电压VREF的正端VRP，其第四输入端VRN2接初始参考电压VREF的负端VRN，其第五输入端CK31<j>接第j个第二数字信号DE<j>的正端，其第六输入端CK32<j>接第j个第二数字信号DE<j>的负端，2 N-1个第二开关电容单元的输出端D并联在一起并对外输出所述第二模拟信号V2。
详细地，如图10所示，第j个第一开关电容单元U(j) 2包括第一NMOS管MN1、第二NMOS管MN2、第一PMOS管MP1及开关电容C U，第一NMOS管MN1的栅极作为第一开关电容单元U(j) 2的第一输入端CKS1，第一NMOS管MN1的漏极作为第一开关电容单元U(j) 2的第二输入端VI1，第二NMOS管MN2的栅极作为第一开关电容单元U(j) 2的第六输入端CK22<j>，第二NMOS管MN2的漏极作为第一开关电容单元U(j) 2的第四输入端VRN1，第一PMOS管MP1的栅极作为第一开关电容单元U(j) 2的第五输入端CK21<j>，第一PMOS管MP1的源极作为第一开关电容单元U(j) 2的第三输入端VRP1，第一NMOS管MN1的源极、第二NMOS管MN2的源极及第一PMOS管MP1的漏极分别接开关电容C U的一端，开关电容C U的另一端作为第一开关电容单元U(j) 2的输出端D。其中，第二开关电容单元的结构与第一开关电容单元的结构相同，在此不再赘述。
详细地，如图2所示，开关电容放大模块4包括第三NMOS管N1、第四NMOS管N2、 第五NMOS管N3、第六NMOS管N4、第一电容C FP、第二电容C FN及全差分运算放大器OTA，第三NMOS管N1的栅极、第四NMOS管N2的栅极及第五NMOS管N3的栅极分别接第三时钟信号Φ3，第三NMOS管N1的漏极及第五NMOS管N3的漏极分别接基础信号VB，第五NMOS管N3的源极、第四NMOS管N2的漏极、全差分运算放大器OTA的同相输入端IN+、第一子数模转换模块2的输出端及第一电容C FP的一端接在一起，第一电容C FP的另一端、全差分运算放大器OTA的反相输出端VO-及第六NMOS管N4的漏极接在一起，第三NMOS管N1的源极、所第四NMOS管N2的源极、全差分运算放大器OTA的反相输入端IN-、第二子数模转换模块3的输出端及第二电容C FN的一端接在一起，第二电容C FN的另一端、全差分运算放大器OTA的同相输出端VO+及第六NMOS管N4的源极接在一起，第六NMOS管N4的栅极接第四时钟信号Φ4，全差分运算放大器OTA的同相输出端VO+作为开关电容放大模块4的输出正端VOUT(+)，全差分运算放大器OTA的反相输出端VO-作为开关电容放大模块4的输出负端VOUT(-)。
其中，第一电容C FP的电容值等于第二电容C FN的电容值。
详细地，在本发明中，流水级处于工作模式下时，第一时钟信号Ф1、第二时钟信号Ф2、第三时钟信号Ф3及第四时钟信号Ф4的时序状态图如图11所示，且第一时钟信号Ф1、第二时钟信号Ф2、第三时钟信号Ф3及第四时钟信号Ф4的相位相同。
更详细地，如图2-图11所示的流水级的工作原理如下：
1)、当第一时钟信号Ф1、第二时钟信号Ф2、第三时钟信号Ф3及第四时钟信号Ф4均为高电平时，第一子数模转换模块2及第二子数模转换模块3均处于采样模式：各个第一开关电容单元及第二开关电容单元中的第二NMOS管MN2的栅极电压为低电平，第二NMOS管MN2处于关断模式，第一PMOS管MP1的栅极电压为高电平，第一PMOS管MP1处于关断模式，第一NMOS管MN1的栅极电压为高电平，第一NMOS管MN1处于导通模式；开关电容放大模块4中第三NMOS管N1的栅极电压、第四NMOS管N2的栅极电压及第五NMOS管N3的栅极电压均为高电平；第一子数模转换模块2中各个第一开关电容单元的开关电容C U一端采集输入的基础信号VB、另一端采集模拟输入信号VIN的正端VIN(+)，第二子数模转换模块3中各个第二开关电容单元的开关电容C U一端采集输入的基础信号VB、另一端采集模拟输入信号VIN的负端VIN(-)；开关电容放大模块4中第六NMOS管N4的栅极电压为高电平，第六NMOS管N4导通，开关电容放大模块4的第一输出端VOUT(+)与第二输出端VOUT(-)短接在一起；因此，采样模式下流水级的输出为：
VOUT(+)-VOUT(-)＝0              (1)
2)、当第一时钟信号Ф1、第二时钟信号Ф2、第三时钟信号Ф3及第四时钟信号Ф4均为低电平时，第一子数模转换模块2及第二子数模转换模块3均处于保持模式：开关电容放大模块4中第三NMOS管N1的栅极电压、第四NMOS管N2的栅极电压及第五NMOS管N3的栅极电压均为低电平，第三NMOS管N1、第四NMOS管N2及第五NMOS管N3均关断，全差分运算放大器OTA同相输入端IN+和反相输入端IN-处于高阻抗状态；开关电容放大模块4中第六NMOS管N4的栅极电压为低电平，第六NMOS管N4关断；第一子数模转换模块2中各个第一开关电容单元的第二NMOS管MN2与比较器阵列单元13中对应驱动器的第二输出端Y2连接、第一PMOS管MP1与比较器阵列单元13中驱动器的第一输出端Y1连接；第二子数模转换模块3中各个第二开关电容单元中的第二NMOS管MN2与比较器阵列单元13中对应驱动器的第一输出端Y1连接、第一PMOS管MP1与比较器阵列单元13中对应驱动器的第二输出端Y2连接；此模式下，各个第一开关电容单元(或者第二开关电容单元)中的第二NMOS管MN2和第一PMOS管MP1只能保持1个导通，且导通与关闭模式由对应比较器的输出决定，而比较器的输出由模拟输入信号VIN与参考电压的大小决定；根据电荷守恒原理，此时流水级的输出为：
Figure PCTCN2022116673-appb-000001
在式(2)中，C U,1i表示第一子数模转换器模块中第i个第一开关电容单元中开关电容(或者采样电容)C U的电容值，C U,2i表示第二子数模转换器模块中第i个第二开关电容单元中开关电容C U的电容值，D i +＝1表示第一子数模转换器模块中第i个第一开关电容单元中开关电容C U连接VRP(即VREFP)，D i +＝0表示第一子数模转换器模块中第i个第一开关电容单元中开关电容C U连接VRN(即VREFN)，D i -＝1表示第二子数模转换器模块中第i个第二开关电容单元中开关电容C U连接VRP，D i -＝0表示第二子数模转换器模块中第i个第二开关电容单元中开关电容C U连接VRN。
在理想情况下，C U,1i＝C U,2i＝C FP＝C FN，式(2)简化为：
Figure PCTCN2022116673-appb-000002
根据式(3)可知，在本发明提供的流水线型模数转换器中，基于如图2所示的流水级结 构，实现了增益为2N-1的残差信号放大，其对应的传输曲线如图12所示。
综上所述，在本发明提供的流水线型模数转换器中，至少一级流水级为基于“N位子模数转换模块+第一子数模转换模块+第二子数模转换模块+开关电容放大模块”的结构，第一子数模转换模块及第二子数模转换模块分别接受处理2 N-1个数字信号，即N位子模数转换模块中奇数编号的比较驱动结构的输出和偶数编号的比较驱动结构的输出分别控制第一子数模转换模块及第二子数模转换模块，对应需要2*2 N-1个开关电容，而基于“N位子模数转换模块+子数模转换模块+减法器+乘法器”结构的传统流水级，其差分输入比较的同相输入与反相输入完全对称，对应需要2*2 N个开关电容，相比于传统结构的流水级，本发明流水级中子数模转换开关电容的数量减少50％，对应功耗降低50％，处理速度提升1-2倍，因此，本发明能有效减少流水级的子数模转换开关电容的数量，减少了开关电容阵列的面积，降低了开关电容阵列的功耗，并提升了流水级的处理速度。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (11)

  1. 一种流水线型模数转换器，其特征在于，包括多级依次级联的流水级，至少一级所述流水级包括：
    N位子模数转换模块，接收模拟输入信号并对所述模拟输入信号进行模数转换，得到并输出2 N个数字信号；
    第一子数模转换模块，接收2 N-1个所述数字信号并对2 N-1个所述数字信号进行数模转换，得到并输出第一模拟信号；
    第二子数模转换模块，接收另外2 N-1个所述数字信号并对另外2 N-1个所述数字信号进行数模转换，得到并输出第二模拟信号；
    开关电容放大模块，接收所述第一模拟信号和所述第二模拟信号，对所述第一模拟信号和所述第二模拟信号进行求差运算并对求差运算的结果进行放大运算，得到并输出模拟输出信号；
    其中，N为大于等于1的整数。
  2. 根据权利要求1所述的流水线型模数转换器，其特征在于，所述N位子模数转换模块包括：
    第一电阻分压单元，对初始参考电压进行分压处理，对外输出2 N个同相参考电压；
    第二电阻分压单元，对初始参考电压进行分压处理，对外输出2 N个反相参考电压；
    比较器阵列单元，与所述第一电阻分压单元及所述第二电阻分压单元分别连接，接收所述模拟输入信号，并将所述模拟输入信号与2 N个参考电压分别进行比较，得到2 N个所述数字信号，2 N个所述数字信号包括2 N-1个第一数字信号和2 N-1个第二数字信号，其中，2 N个所述同相参考电压与2 N个所述反相参考电压一一对应，构成2 N个所述参考电压。
  3. 根据权利要求2所述的流水线型模数转换器，其特征在于，所述第一电阻分压单元包括第一输入端口、第二输入端口和2 N+1个第一电阻，2 N+1个第一电阻依次串接在所述第一输入端口和所述第二输入端口之间，所述第一输入端口接所述初始参考电压的正端，所述第二输入端口接所述初始参考电压的负端，相邻两个所述第一电阻的公共端输出一个所述同相参考电压。
  4. 根据权利要求2所述的流水线型模数转换器，其特征在于，所述第二电阻分压单元包括第三输入端口、第四输入端口和2 N+1个第二电阻，2 N+1个第二电阻依次串接在所述第三输入端口和所述第四输入端口之间，所述第三输入端口接所述初始参考电压的负端，所述第 四输入端口接所述初始参考电压的正端，相邻两个所述第二电阻的公共端输出一个所述反相参考电压。
  5. 根据权利要求4所述的流水线型模数转换器，其特征在于，所述比较器阵列单元包括：
    2 N个比较器，将所述模拟输入信号与2 N个所述参考电压一一进行比较量化，输出2 N-1个第一初始数字信号和2 N-1个第二初始数字信号；
    2 N个驱动器，2 N个所述驱动器的输入端与2 N个所述比较器的输出端一一对应连接，2 N个所述驱动器的输出端对外输出受第一时钟信号控制的2 N-1个所述第一数字信号和2 N-1个所述第二数字信号。
  6. 根据权利要求5所述的流水线型模数转换器，其特征在于，
    2 N个所述比较器并行设置，在第i个所述比较器中，所述比较器的第一输入端接所述模拟输入信号的正端，所述比较器的第二输入端接所述模拟输入信号的负端，所述比较器的第三输入端接第i个所述同相参考电压，所述比较器的第四输入端接第i个所述反相参考电压，i＝1、2、…、2 N；
    2 N个所述驱动器并行设置，在第i个所述驱动器中，所述驱动器的第一输入端接第i个所述比较器的第一输出端，所述驱动器的第二输入端接第i个所述比较器的第二输出端，所述驱动器的第三输入端接所述第一时钟信号；
    其中，第m个所述比较器的输出端输出一个所述第一初始数字信号，第m个所述驱动器的输出端输出一个所述第一数字信号，第n个所述比较器的输出端输出一个所述第二初始数字信号，第n个所述驱动器的输出端输出一个所述第二数字信号，m为1～2 N的奇数，n为1～2 N的偶数。
  7. 根据权利要求6所述的流水线型模数转换器，其特征在于，所述驱动器包括第一与非门、第一或非门、第一非门、第二非门及第三非门，所述第一与非门的第一输入端作为所述驱动器的第一输入端，所述第一与非门的第二输入端接所述第一非门的输出端，所述第一与非门的输出端接所述第二非门的输入端，所述第二非门的输出端作为所述驱动器的第二输出端，所述第一非门的输入端作为所述驱动器的第三输入端，所述第一或非门的第一输入端接所述第一非门的输入端，所述第一或非门的第二输入端作为所述驱动器的第二输入端，所述第一或非门的输出端接所述第三非门的输入端，所述第三非门的输出端作为所述驱动器的第一输出端。
  8. 根据权利要求6所述的流水线型模数转换器，其特征在于，
    所述第一子数模转换模块包括2 N-1个并行设置的第一开关电容单元，第j个所述第一开关电容单元的第一输入端接第二时钟信号，第j个所述第一开关电容单元的第二输入端接所述模拟输入信号的正端，第j个所述第一开关电容单元的第三输入端接所述初始参考电压的正端，第j个所述第一开关电容单元的第四输入端接所述初始参考电压的负端，第j个所述第一开关电容单元的第五输入端接第j个所述第一数字信号的负端，第j个所述第一开关电容单元的第六输入端接第j个所述第一数字信号的正端，2 N-1个所述第一开关电容单元的输出端并联在一起并对外输出所述第一模拟信号，j＝1、2、…、2 N-1；
    所述第二子数模转换模块包括2 N-1个并行设置的第二开关电容单元，第j个所述第二开关电容单元的第一输入端接所述第二时钟信号，第j个所述第二开关电容单元的第二输入端接所述模拟输入信号的负端，第j个所述第二开关电容单元的第三输入端接所述初始参考电压的正端，第j个所述第二开关电容单元的第四输入端接所述初始参考电压的负端，第j个所述第二开关电容单元的第五输入端接第j个所述第二数字信号的正端，第j个所述第二开关电容单元的第六输入端接第j个所述第二数字信号的负端，2 N-1个所述第二开关电容单元的输出端并联在一起并对外输出所述第二模拟信号。
  9. 根据权力要求8所述的流水线型模数转换器，其特征在于，所述第一开关电容单元包括第一NMOS管、第二NMOS管、第一PMOS管及开关电容，所述第一NMOS管的栅极作为所述第一开关电容单元的第一输入端，所述第一NMOS管的漏极作为所述第一开关电容单元的第二输入端，所述第二NMOS管的栅极作为所述第一开关电容单元的第六输入端，所述第二NMOS管的漏极作为所述第一开关电容单元的第四输入端，所述第一PMOS管的栅极作为所述第一开关电容单元的第五输入端，所述第一PMOS管的源极作为所述第一开关电容单元的第三输入端，所述第一NMOS管的源极、所述第二NMOS管的源极及所述第一PMOS管的漏极分别接所述开关电容的一端，所述开关电容的另一端作为所述第一开关电容单元的输出端。
  10. 根据权力要求1或9所述的流水线型模数转换器，其特征在于，所述开关电容放大模块包括第三NMOS管、第四NMOS管、第五NMOS管、第六NMOS管、第一电容、第二电容及全差分运算放大器，所述第三NMOS管的栅极、所述第四NMOS管的栅极及所述第 五NMOS管的栅极分别接第三时钟信号，所述第三NMOS管的漏极及所述第五NMOS管的漏极分别接基础信号，所述第五NMOS管的源极、所述第四NMOS管的漏极、所述全差分运算放大器的同相输入端、所述第一子数模转换模块的输出端及所述第一电容的一端接在一起，所述第一电容的另一端、所述全差分运算放大器的反相输出端及所述第六NMOS管的漏极接在一起，所述第三NMOS管的源极、所述第四NMOS管的源极、所述全差分运算放大器的反相输入端、所述第二子数模转换模块的输出端及所述第二电容的一端接在一起，所述第二电容的另一端、所述全差分运算放大器的同相输出端及所述第六NMOS管的源极接在一起，所述第六NMOS管的栅极接第四时钟信号，所述全差分运算放大器的同相输出端作为所述开关电容放大模块的输出正端，所述全差分运算放大器的反相输出端作为所述开关电容放大模块的输出负端。
  11. 根据权力要求10所述的流水线型模数转换器，其特征在于，所述第一电容的电容值等于所述第二电容的电容值。
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CN1499730A (zh) * 2002-11-08 2004-05-26 尹登庆 流水线结构的高速高精度模数转换器
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CN200997595Y (zh) * 2006-12-07 2007-12-26 深圳艾科创新微电子有限公司 新型模数转换器结构
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