WO2024012430A1 - 沟槽型双扩散金属氧化物半导体器件及其制造方法 - Google Patents

沟槽型双扩散金属氧化物半导体器件及其制造方法 Download PDF

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Publication number
WO2024012430A1
WO2024012430A1 PCT/CN2023/106711 CN2023106711W WO2024012430A1 WO 2024012430 A1 WO2024012430 A1 WO 2024012430A1 CN 2023106711 W CN2023106711 W CN 2023106711W WO 2024012430 A1 WO2024012430 A1 WO 2024012430A1
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Prior art keywords
trench
source region
gate
metal oxide
oxide semiconductor
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PCT/CN2023/106711
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English (en)
French (fr)
Inventor
许超奇
陈淑娴
张仪
林峰
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无锡华润上华科技有限公司
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Publication of WO2024012430A1 publication Critical patent/WO2024012430A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the present application relates to the field of semiconductor manufacturing, in particular to a trench-type double-diffused metal oxide semiconductor device, and also relates to a manufacturing method of a trench-type double-diffused metal oxide semiconductor device.
  • CMOS Complementary Metal Oxide Semiconductor
  • DMOS double-diffused Metal Oxide Semiconductor
  • NLDMOSFET N-channel Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor
  • the drift region of LDMOS is horizontal, and the drift region of vertical double-diffused Metal Oxide Semiconductor (VDMOS) devices is vertical, so the drift region of LDMOS The device area is still at a higher level compared to vertical VDMOS.
  • VDMOS is led out from the back and is not compatible with the CMOS process, so VDMOS is rarely used in BCD process development. Therefore, it is difficult to further reduce the chip area of chips obtained based on the existing BCD process platform.
  • SGT MOSFET Shield Gate Trench Metal Oxide Semiconductor Field Effect Transistor
  • TrenchDMOS lateral trench type double diffused metal oxide
  • the device structure allows the device performance of extremely small on-resistance (Rdson) to be achieved by taking advantage of the small area of VDMOS. And because the drain and source ends of the device are both on the front side, it can theoretically be compatible with the CMOS process and further reduce the circuit area.
  • a method for manufacturing a trench-type double-diffused metal oxide semiconductor device including: using an active area photoresist to form a hard mask layer on a substrate; using the hard mask layer as an etching barrier layer to form an etching barrier A first trench, one side of the first trench is a source region; wherein the active area photoresist plate includes a source region pattern, a drain region pattern, and a source region located between the source region pattern and the drain region.
  • the first trench pattern between patterns, the first trench pattern in the corresponding area of the substrate is the first trench, and the source region is the source region pattern in the substrate.
  • Corresponding areas forming a bottom gate and an insulating isolation structure on the bottom gate in the first trench; forming an opening above the source region through photolithography, the width of the opening being larger than the source region
  • the width of the insulating isolation structure in the first trench is etched to form a third trench, and the remaining insulating isolation structure is at least between the third trench and the bottom gate; to the The third trench is filled with the first gate material as a top gate; the hard mask layer is removed; a source region and a drain region are formed by doping; wherein the first trench is located between the source region and the Between the drain regions, the source region is located on one side of the first trench where the top gate is provided, and the drain region is located on the other side of the first trench.
  • the above-mentioned manufacturing method of a trench-type double-diffused metal oxide semiconductor device uses a first photoresist to etch an insulating isolation structure to form a top gate. There is no need to make a separate photoresist for etching the top gate, so manufacturing costs can be saved. , reduce process complexity. The drain region of the device can be led from the front, so it is compatible with the CMOS process.
  • the above-mentioned manufacturing method of trench-type double-diffused metal oxide semiconductor devices can be applied to the BCD process platform, which can effectively reduce the chip area while optimizing device performance. .
  • the light transmittance of the source region pattern and the drain region pattern of the active area photoresist plate is opposite to the light transmittance of the first trench pattern.
  • the width of the source region pattern is greater than the width of the drain region pattern.
  • the active area photoresist includes a plurality of first trench patterns, the source area is located between two adjacent first trenches, and the width of the source area Greater than or equal to 0.45 microns.
  • the width of the source region is less than or equal to 0.6 microns.
  • the width of the source region is greater than or equal to 0.45 microns and less than or equal to 0.6 microns.
  • the width of the third trench ranges from 0.05 to 0.1 microns.
  • the active area photoresist plate further includes a second trench pattern, one end of the first trench pattern is directly connected to the second trench pattern; the hard mask
  • the step of etching the film layer to serve as the etching barrier layer to form the first trench includes: etching the hard mask layer as the etching barrier layer to form the first trench and the second trench;
  • Two groove pattern The corresponding area of the substrate is the second trench;
  • the step of forming a bottom gate and the insulating isolation structure on the bottom gate in the first trench includes: The inner surface of the trench and the inner surface of the second trench form a gate dielectric layer; the first trench and the second trench are filled with a second gate material; and a third gate material is formed on the second trench by photolithography.
  • the method further includes: using the second gate material in the third trench as a lead-out structure.
  • the forming the second photoresist layer on the second trench by photolithography includes: using a second photoresist plate to form the second photoresist layer on the second trench. and etching the second gate material in the first trench to form the bottom gate, including: etching the first trench using the second photoresist layer as an etching barrier layer of second gate material to form the bottom gate.
  • the step of forming an insulating isolation structure on the bottom gate includes: forming an insulating isolation layer in the first trench and on the hard mask layer; Chemical mechanical polishing is performed to obtain the insulating isolation structure, and the hard mask layer is a polished barrier layer.
  • forming an insulating isolation structure on the bottom gate includes: removing the second photoresist layer; and depositing an insulating dielectric on the front side of the substrate as the insulating isolation structure.
  • the method before using an active area photoresist to form the hard mask layer on the substrate, the method further includes: forming a first well region in the substrate, and the first well region is formed in the substrate.
  • the conductivity type of the well region is the same as that of the source region and the drain region, and the first trench and the second trench are formed in the first well region.
  • the method before using an active area photoresist to form the hard mask layer on the substrate, the method further includes: forming an oxide layer on the substrate, and the material of the oxide layer is is silicon oxide.
  • forming the opening above the source region by photolithography includes: coating a photoresist on the front side of the substrate; using a first photoresist to pattern the photoresist After exposure and development, a first photoresist layer having the opening is obtained, and the opening is located above the source region.
  • the step of forming an insulating isolation structure on the bottom gate further includes forming a shallow layer between the trench-type double-diffused metal oxide semiconductor device and the CMOS device.
  • the hard mask layer serves as a polished barrier layer for the shallow trench isolation structure.
  • the step of forming a second well region in the substrate is further included.
  • the source region is located in the second well region, and the third well region is
  • the second well region has a second conductivity type well region, the source region and the drain region have a first conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the trench-type double-diffusion metal oxide semiconductor device includes: a bottom gate , insulating isolation structure, top gate, source region and drain region.
  • a bottom gate is provided at the lower part of the first trench, and the bottom and sides of the bottom gate are surrounded by a gate dielectric layer located on the inner surface of the first trench; an insulating isolation structure is provided at the first trench middle, on the bottom gate; a top gate is disposed in the first trench and close to one side of the first trench, the top gate is located above the bottom gate, and the top gate is connected to the The bottom gates are separated by the insulating isolation structure; the source region is provided in the substrate on the side of the first trench where the top gate is provided; the drain region is provided on the side of the first trench is located in the substrate on the other side and close to the front surface of the substrate. The width of the source region is greater than the width of the drain region, and the drain region and the top gate are separated by the insulating isolation structure.
  • the width of the source region of the trench-type double-diffused metal oxide semiconductor device is greater than the width of the drain region, which can prevent the hard mask used for etching the trench from peeling off and affecting the device yield.
  • the drain region of the device can be led from the front, so it is compatible with the CMOS process and can be applied to the BCD process platform, which can effectively reduce the chip area while optimizing the device performance.
  • Figure 1 is a flow chart of a manufacturing method of a trench-type double-diffused metal oxide semiconductor device in an embodiment of the present application
  • Figure 2 is a schematic diagram of the layout of the active area photoresist plate in an embodiment of the present application
  • Figures 3a-3f are schematic cross-sectional views of the device during the process of manufacturing a TrenchDMOS device using the method shown in Figure 1 according to an embodiment of the present application;
  • Figure 4 is a flow chart of forming a bottom gate and an insulating isolation structure on the bottom gate in the first trench according to an embodiment of the present application;
  • Figure 5a is a partial schematic diagram of the layout of the active area photoresist plate in another embodiment of the present application.
  • Figure 5b shows the corresponding position of the first photoresist layer in Figure 5a;
  • Figure 6 is a schematic cross-sectional structural diagram of a TrenchDMOS device when etching the insulating medium in the trench in an embodiment of the present application;
  • FIG. 7 is a microscope image of the hard mask peeling off according to an embodiment of the present application.
  • Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. Thus, variations from the shapes shown may be anticipated due, for example, to manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant occurs. Therefore, the regions shown in the figures are schematic in nature and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present application.
  • P+ type simply represents P type with heavy doping concentration
  • P type represents medium doping concentration
  • P-type with doping concentration P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type N-type with medium doping concentration
  • N-type represents lightly doped concentration.
  • An exemplary manufacturing method of TrenchDMOS with drain terminal front lead in the related art is to form a bottom gate in a trench, then deposit an insulating dielectric on the bottom gate, photolithography and etching the insulating dielectric to form an insulating dielectric on the bottom gate.
  • Insulating isolation structure the gate material in the trench used to form the lead-out structure needs to be protected by photoresist
  • fill the gate material on the insulating isolation structure and then use photolithography and etching to remove the gate electrode at the drain end. Material is removed, then the trench is filled with an insulating medium, and finally CMP (Chemical Mechanical Polishing) is performed.
  • CMP Chemical Mechanical Polishing
  • FIG. 1 is a flow chart of a manufacturing method of a trench-type double-diffused metal oxide semiconductor device in an embodiment of the present application, including the following steps S110 to S180.
  • the active area photoresist plate includes a source area pattern 204, a drain area pattern 202, and a first trench pattern 201 located between the source area pattern 204 and the drain area pattern 202.
  • FIG. 2 is a schematic diagram of the layout of the active area photoresist plate in an embodiment of the present application.
  • the active area photoresist plate further includes a second trench pattern 203.
  • the source area pattern 204, the drain area pattern 202 and the first trench pattern 201 are located in the device area, and the second trench pattern 203 is located in the lead-out area.
  • One end of the first groove pattern 201 is directly connected to the second groove pattern 203 .
  • Figure 3a is a schematic diagram of the cross-sectional structure of the wafer after step S110 is completed.
  • the left side of the dotted line is the lead-out area structure (corresponding to the AA' section in Figure 2), and the large-width structure of the lead-out area is reduced to a small-width structure so that In terms of patterning, the right side of the dotted line is the device area structure (corresponding to the BB' section in Figure 2).
  • the hard mask layer 230 is made of nitride silicon.
  • a photoresist is coated on the hard mask material, and then the active area photoresist is used to expose the photoresist. After development, the photoresist forms an etching window, and then the hard mask material is etched to obtain the hard mask layer 230 .
  • the light transmittance of the source region pattern and the drain region pattern is opposite to the light transmittance of the first trench pattern. That is, the first trench pattern on the active area photoresist plate is light-transmitting, but the source area pattern and the drain area pattern are opaque; or the source area pattern and the drain area pattern are light-transmitting, but the first trench pattern is opaque. .
  • the step of forming the first well region 212 is also included before step S110.
  • the first well region 212 is a high-voltage well.
  • the first well region 212 is a first conductivity type well
  • the substrate 210 is a second conductivity type substrate.
  • the first conductivity type is N-type
  • the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type.
  • an oxide layer 220 may also be formed on the substrate 210.
  • the oxide layer 220 is a pad oxide layer, and its material is silicon oxide, such as silicon dioxide.
  • etching the hard mask layer 230 as an etching barrier layer to form the first trench 211 includes: etching the hard mask layer 230 as an etching barrier layer to form the first trench 211 and the second trench. 213.
  • the corresponding area is the second trench 213.
  • a shallow trench 215 also needs to be formed in the substrate 210 to form a shallow trench isolation structure (shallow trench isolation, STI) between TrenchDMOS and CMOS.
  • the active area photoresist includes a plurality of first trench patterns 201 (as shown in FIG. 2), and the source region 254 is located between two adjacent first trenches 211. time (as shown in Figure 3f). S130, form a bottom gate 242 and an insulating isolation structure 224 on the bottom gate in the first trench.
  • a bottom gate 242 and an insulating isolation structure 224 on the bottom gate 242 are formed in the first trench 211 (not labeled in FIG. 3 c ).
  • the bottom gate 242 is a shield gate.
  • step S130 also includes forming a lead-out structure 248 in the second trench 213 (not labeled in FIG. 3c). The first trench 211 and the second trench 213 are connected, so the bottom gate 242 in the first trench 211 is in direct contact with the lead-out structure 248 in the second trench 213. The bottom gate 242 can be removed from the substrate through the lead-out structure 248. The front of 210 leads out.
  • step S130 includes:
  • silicon dioxide may be formed on the inner surfaces of the first trench 211 and the second trench 213 as the gate dielectric layer 222 through thermal oxidation.
  • the gate material is polysilicon material. In other embodiments, metal, metal nitride, metal silicide or similar compounds can also be used as the gate material.
  • the first trench and the second trench may be filled with gate material through a deposition process. In one embodiment of the present application, excess gate material can be removed through CMP, leaving only the gate material in the first trench 211 and the second trench 213 . The gate material in the second trench 213 forms the lead structure 248 .
  • photoresist is coated on the front side of the substrate 210, and then the photoresist is exposed using a lead-out structure photoresist. After development, the remaining photoresist layer covers the second trench 213, so as to The gate material in the second trench is protected.
  • etching the gate material in the first trench to form the bottom gate includes:
  • step S139 forms an insulating isolation structure on the bottom gate, including forming an insulating isolation layer in the first trench and on the hard mask layer; performing chemical mechanical polishing on the insulating isolation layer, The insulating isolation structure is obtained, and the hard mask layer is a polished barrier layer.
  • step S139 further includes forming a shallow trench isolation structure 228 in the shallow trench 215 .
  • step S130 it also includes:
  • S140 form an opening 291 above the source region 254 by photolithography, and the width of the opening 291 is greater than the width of the source region 254.
  • photoresist is coated on the front side of the substrate 210, and then the photoresist is exposed using a first photoresist plate.
  • the first photoresist layer 292 obtained after development is An opening 291 is formed above the source area (that is, the source area pattern 204 of the active area photoresist plate corresponds to the area of the substrate 210).
  • the width of the opening 291 is greater than the width of the source region, thereby partially exposing the first trench 211 .
  • step S150 is a two-step etching process, in which dry etching is performed first and then the remaining insulating isolation structure 224 on the sidewall of the source region 254 is removed by wet bleaching.
  • the remaining insulation isolation structure is at least between the third trench 217 and the bottom gate 242 .
  • a step of forming a gate dielectric layer is also included, that is, in step S150, the exposed first trench sidewall is etched to form a gate dielectric layer.
  • the material of the gate dielectric layer may be silicon oxide, such as silicon dioxide.
  • the filled gate material may be the same as the gate material filled in step S133, or may be different. That is, the top gate 244 may be made of the same material as the bottom gate 242 , or may be different. In the embodiment shown in FIG. 3e , both the top gate 244 and the bottom gate 242 are made of polysilicon.
  • the first photoresist layer 292 before filling the gate material into the third trench 217 in step S160, the first photoresist layer 292 must first be removed. After filling the third trench 217 with the gate material, the excess gate material can be removed by etching back or CMP.
  • the hard mask layer 230 may be removed through an etching process.
  • the source region 254 and the drain region 252 are formed by implanting ions of the first conductivity type through an ion implantation process.
  • the source region 254 is located on one side of the first trench 211 (not labeled in FIG. 3 f ) where the top gate 244 is located, and the drain region 252 is located on the other side of the first trench 211 .
  • the step S170 is followed by the step of forming the second well region 258 .
  • the second well region 258 serves as a channel region
  • the source region 254 is located in the second well region 258, and the second well region 258 has the second conductivity type.
  • the above-mentioned manufacturing method of a trench-type double-diffused metal oxide semiconductor device uses a first photoresist to etch an insulating isolation structure to form a top gate. There is no need to make a separate photoresist for etching the top gate, so manufacturing costs can be saved. , reduce process complexity. The drain region of the device can be led from the front, so it is compatible with the CMOS process.
  • the above-mentioned manufacturing method of trench-type double-diffused metal oxide semiconductor devices can be applied to the BCD process platform, which can effectively reduce the chip area while optimizing device performance. .
  • a shallow trench isolation structure needs to be provided between TrenchDMOS and CMOS (refer to the shallow trench isolation structure 228 in the previous embodiment).
  • the STI is usually completed before the CMOS process, and the hard mask (usually SiN film) serves as a barrier layer for CMP structures such as STI, so in the wet etching trench of insulating dielectric, the hard mask remains. Therefore, when the width of the active area pattern is small, peeling is easy to occur, that is, the wet etching liquid enters the oxide layer between the hard mask and silicon, causing the hard mask to peel off, see Figure 7.
  • Figure 5a is a partial schematic diagram of the layout of the active area photoresist plate in another embodiment (the second trench pattern is omitted).
  • the active area photoresist includes a source area pattern 304, a drain area pattern 302 and a source area pattern 304. and the first trench pattern 301 between the drain region pattern 302.
  • the opening 291 is located above the source region 254, and the drain region 252 is covered by the first photoresist layer 292 (the first photoresist layer 292 Refer to FIG. 5b) for the position corresponding to the photoresist layout of the active area, that is, the opening 291 exposes the source area and part of the first trench 211 around the source area.
  • the drain region 252 will not have the problem of hard mask peeling off.
  • the width of the source region pattern 304 is greater than the width of the drain region pattern 302.
  • the width of the drain region pattern 302 can be correspondingly reduced.
  • the source region width a ⁇ 0.45 microns. The applicant has discovered through creative research that hard mask peeling is less likely to occur when the corresponding width is greater than or equal to 0.5 microns, while hard mask peeling is prone to occur when the corresponding width is less than or equal to 0.4 microns.
  • the width of the source region is less than or equal to 0.6 microns. In one embodiment of the present application, the width a of the source region is 0.45 microns ⁇ a ⁇ 0.6 microns, and the width of the drain region is correspondingly reduced to 0.3 microns ⁇ a ⁇ 0.45 microns.
  • the width of the third trench 217 is 0.05-0.1 microns, that is, the width b of the opening 291 (shown in Figure 3c) is 0.1 larger than the width a of the source region (shown in Figure 3d). ⁇ 0.2 microns.
  • the first photoresist layer 292 cuts off the first trench pattern 301 and the second trench pattern, thereby cutting off the top gate 244. This is to prevent the top gate 244 from being electrically connected to the lead-out structure 248 .
  • the present application also provides a trench-type double-diffused metal oxide semiconductor device, which can be formed using the manufacturing method of a trench-type double-diffused metal oxide semiconductor device described in any of the previous embodiments.
  • the structure of the trench-type double-diffusion metal oxide semiconductor device can be referred to FIG. 3f, which is provided with a first trench 211 (not labeled in FIG. 3f) extending from the front of the substrate 210 to the substrate 210.
  • the trench-type double-diffusion The metal oxide semiconductor device also includes a bottom gate 242, an insulating isolation structure 224, a top gate 244, a source region 254, and a drain region 252.
  • the bottom gate 242 is disposed under the first trench 211 .
  • the bottom and side surfaces of the bottom gate 242 are surrounded by the gate dielectric layer 222 located on the inner surface of the first trench 211 .
  • the insulation isolation structure 224 is provided in the first trench 211 and on the bottom gate 242 .
  • the top gate 244 is disposed in the first trench 211 and is disposed close to one side of the first trench 211 .
  • the top gate 244 is located above the bottom gate 242 .
  • the top gate 244 and the bottom gate 242 are separated by an insulation isolation structure 224 .
  • the source region 254 is disposed in the substrate 210 on the side of the first trench 211 where the top gate 244 is disposed (the source region 254 and the top gate 244 are also isolated by a thin gate dielectric layer 222), and disposed close to the front surface of the substrate 210 .
  • the drain region 252 is disposed in the substrate 210 on the other side of the first trench 211 and is disposed close to the front surface of the substrate 210 .
  • the drain region 252 and the top gate 244 are separated by an insulating isolation structure 224 .
  • Source region 254 is wider than drain region 252 width.
  • the width of the source region 254 of the trench-type double-diffused metal oxide semiconductor device is greater than the width of the drain region 252, which can prevent the hard mask used for etching the trench from peeling off and affecting the device yield.
  • the drain region 252 of the SGT device can be led out from the front, so it is compatible with the CMOS process and can be applied to the BCD process platform, which can effectively reduce the chip area while optimizing the device performance.
  • TrenchDMOS mainly withstands voltage in the longitudinal drift region, and its lateral size becomes smaller. Compared with traditional LDMOS devices, when the breakdown voltage (BV) is consistent, the area becomes smaller, and Rdson will have a great advantage. At the same time, because it is compatible with CMOS technology, the TrenchDMOS part does not need to be separated in the circuit, and a lot of area on the circuit can be reduced.
  • the trench type double-diffused metal oxide semiconductor device further includes a first well region 212 .
  • the first well region 212 serves as the drift region of TrenchDMOS, and the source region 254 and the drain region 252 are located in the first well region 212, thus forming a U-shaped drift region.
  • the first well region 212 has the same doping type as the source region 254 and the drain region 252 .
  • the first well region 212, the source region 254 and the drain region 252 have a first conductivity type
  • the substrate 210 has a second conductivity type.
  • the trench-type double-diffused metal oxide semiconductor device is also provided with a second trench 213 (not labeled in Figure 3f) connected to the first trench 211.
  • a second trench 213 (not labeled in Figure 3f) connected to the first trench 211.
  • Conductive material is provided, and the bottom gate 242 in the first trench 211 is in direct contact with the lead-out structure 248 in the second trench 213.
  • the bottom gate 242 can be led out from the front side of the substrate 210 through the lead-out structure 248.
  • the bottom gate 242 and the lead structure 248 are made of the same material.
  • a shallow trench isolation structure 228 is also provided on the front side of the substrate 210 as an isolation between TrenchDMOS and CMOS.
  • a second well region 258 is also provided in the substrate 210 on the side of the first trench 211 where the top gate 244 is disposed.
  • the second well region 258 has the second conductivity type, and the source region 254 is disposed in the second well region 258 .
  • each step in the flow chart of the present application is shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flow chart of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution of these steps or stages The sequence is not necessarily sequential, but may be performed in turn or alternately with other steps or at least part of steps or stages in other steps.

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Abstract

一种沟槽型双扩散金属氧化物半导体器件及其制造方法，所述方法包括：使用有源区光刻版在衬底(210)上形成硬掩膜层(230)；以所述硬掩膜层(230)为刻蚀阻挡层刻蚀形成第一沟槽(211)，所述第一沟槽(211)的一侧为源极区(254)；在第一沟槽(211)中形成底栅(242)和底栅(242)上的绝缘隔离结构(224)；通过光刻在所述源极区(254)上方形成开口(291)所述开口(291)的宽度大于源极区(254)的宽度；刻蚀露出的所述第一沟槽(211)中的所述绝缘隔离结构(224)形成第三沟槽(217)，剩余的绝缘隔离结构(224)至少位于所述第三沟槽(217)和所述底栅(242)之间；向第三沟槽(217)中填充第一栅极材料作为顶栅；去除所述硬掩膜层(230)；通过掺杂形成源极区(254)和漏极区(252)。

Description

沟槽型双扩散金属氧化物半导体器件及其制造方法
相关申请
本申请要求2022年7月12日申请的，申请号为202210813484.6，名称为“沟槽型双扩散金属氧化物半导体器件及其制造方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及半导体制造领域，特别是涉及一种沟槽型双扩散金属氧化物半导体器件，还涉及一种沟槽型双扩散金属氧化物半导体器件的制造方法。
背景技术
在BCD工艺开发中，涉及双极性(Bipolar)晶体管/互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)器件/双扩散金属氧化物半导体(Double-diffused Metal Oxide Semiconductor,DMOS)器件等多项器件共同开发，其中应用最广泛的器件是N沟道横向双扩散金属氧化物半导体场效应管(N-channel Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor,NLDMOSFET)，因此在一般BCD工艺开发过程中，首先是将NLDMOS集成在CMOS工艺平台中。在器件开发中常用降低表面电场(REduced SURface Field,RESURF)技术来降低LDMOS漂移区的表面电场，提高LDMOS的耐压性能。但在达到耐压要求的情况下需要一定漂移区长度才能实现，LDMOS漂移区为横向，垂直双扩散金属氧化物半导体(Vertical Double-diffused Metal Oxide Semiconductor,VDMOS)器件漂移区为纵向，因此LDMOS的器件面积相比纵向VDMOS仍处于较高水平。一般地，VDMOS都是背面引出，无法兼容CMOS工艺，因此VDMOS很少用于BCD工艺开发中。故，基于已有的BCD工艺平台获得的芯片的芯片面积难以进一步缩小。
申请人提出将屏蔽栅沟槽金属氧化物半导体场效应管(Shield Gate Trench MOSFET，简称SGT MOSFET)中的漏端从正面引出，变成一种横向的沟槽型双扩散金属氧化物(TrenchDMOS)器件结构，因此可以利用VDMOS面积小的优势达到极小导通电阻(Rdson)的器件性能。又因为器件的漏端和源端都在正面，理论上可以兼容CMOS工艺制程，进一步缩小电路面积。
发明内容
基于此，有必要提供一种沟槽型双扩散金属氧化物半导体器件以及沟槽型双扩散金属氧化物半导体器件的制造方法。
一种沟槽型双扩散金属氧化物半导体器件的制造方法，包括：使用有源区光刻版在衬底上形成硬掩膜层；以所述硬掩膜层为刻蚀阻挡层刻蚀形成第一沟槽，所述第一沟槽的一侧为源极区；其中所述有源区光刻版包括源极区图形、漏极区图形及位于所述源极区图形和漏极区图形之间的第一沟槽图形，所述第一沟槽图形在所述衬底对应的区域为所述第一沟槽，所述源极区为所述源极区图形在所述衬底对应的区域；在所述第一沟槽中形成底栅和所述底栅上的绝缘隔离结构；通过光刻在所述源极区上方形成开口，所述开口的宽度大于所述源极区的宽度；刻蚀露出的所述第一沟槽中的所述绝缘隔离结构形成第三沟槽，剩余的绝缘隔离结构至少位于所述第三沟槽和所述底栅之间；向所述第三沟槽中填充第一栅极材料作为顶栅；去除所述硬掩膜层；通过掺杂形成源极区和漏极区；其中所述第一沟槽位于所述源极区和所述漏极区之间，所述源极区位于所述第一沟槽设有所述顶栅的一侧，所述漏极区位于所述第一沟槽的另一侧。
上述沟槽型双扩散金属氧化物半导体器件的制造方法，利用第一光刻版刻蚀绝缘隔离结构来形成顶栅，无需为顶栅的刻蚀单独做一块光刻版，因此可以节省制造成本，降低工艺复杂度。器件的漏极区可以从正面引出，因此能够兼容CMOS工艺，可以将上述沟槽型双扩散金属氧化物半导体器件的制造方法应用于BCD工艺平台，在优化器件性能的同时还能有效降低芯片面积。
在其中一个实施例中，所述有源区光刻版的所述源极区图形和漏极区图形的透光性与所述第一沟槽图形的透光性相反。
在其中一个实施例中，所述源极区图形的宽度大于所述漏极区图形的宽度。
在其中一个实施例中，所述有源区光刻版包括多个所述第一沟槽图形，所述源极区位于两相邻的第一沟槽之间，所述源极区的宽度大于或等于0.45微米。
在其中一个实施例中，所述源极区的宽度小于或等于0.6微米。
在其中一个实施例中，所述源极区的宽度大于或等于0.45微米，且小于或等于0.6微米。
在其中一个实施例中，所述第三沟槽的宽度范围为0.05～0.1微米。
在其中一个实施例中，所述有源区光刻版还包括第二沟槽图形，所述第一沟槽图形的一端与所述第二沟槽图形直接连接；所述以所述硬掩膜层为所述刻蚀阻挡层刻蚀形成所述第一沟槽的步骤包括：以所述硬掩膜层为刻蚀阻挡层刻蚀形成第一沟槽和第二沟槽；所述第二沟槽图形 在所述衬底对应的区域为所述第二沟槽；所述在所述第一沟槽中形成底栅和所述底栅上的所述绝缘隔离结构的步骤包括：在所述第一沟槽的内表面和第二沟槽的内表面形成栅介电层；在第一沟槽和第二沟槽中填充第二栅极材料；通过光刻在所述第二沟槽上形成第二光刻胶层；刻蚀所述第一沟槽中的所述第二栅极材料，形成所述底栅；在所述底栅上形成绝缘隔离结构。
在其中一个实施例中，在第一沟槽和第二沟槽中填充栅极材料步骤之后，还包括:将所述第三沟槽中的第二栅极材料作为引出结构。所述通过光刻在所述第二沟槽上形成所述第二光刻胶层，包括：使用第二光刻版在所述第二沟槽上形成所述第二光刻胶层。以及所述刻蚀第一沟槽中的所述第二栅极材料，形成所述底栅，包括：以所述第二光刻胶层为刻蚀阻挡层刻蚀所述第一沟槽中的第二栅极材料，形成所述底栅。
在其中一个实施例中，所述在所述底栅上形成绝缘隔离结构的步骤包括：在所述第一沟槽中和所述硬掩膜层上形成绝缘隔离层；对所述绝缘隔离层进行化学机械抛光，得到所述绝缘隔离结构，所述硬掩膜层为抛光的阻挡层。
在其中一个实施例中，所述在所述底栅上形成绝缘隔离结构，包括：去除所述第二光刻胶层；在所述衬底正面淀积绝缘介质作为所述绝缘隔离结构。
在其中一个实施例中，所述使用有源区光刻版在所述衬底上形成所述硬掩膜层之前，还包括：在所述衬底中形成第一阱区，所述第一阱区的导电类型与所述源极区和所述漏极区的导电类型相同，所述第一沟槽和所述第二沟槽形成于所述第一阱区中。
在其中一个实施例中，所述使用有源区光刻版在所述衬底上形成所述硬掩膜层之前，还包括：在所述衬底上形成氧化层，所述氧化层的材质为硅氧化物。
在其中一个实施例中，所述通过光刻在所述源极区上方形成所述开口，包括：在所述衬底正面涂覆光刻胶；使用第一光刻版对所述光刻胶进行曝光，显影后得到具有所述开口的第一光刻胶层，所述开口位于所述源极区的上方。
在其中一个实施例中，应用于BCD工艺平台，所述在所述底栅上形成绝缘隔离结构的步骤还包括形成位于所述沟槽型双扩散金属氧化物半导体器件与CMOS器件之间的浅沟槽隔离结构，所述硬掩膜层作为所述浅沟槽隔离结构的抛光的阻挡层。
在其中一个实施例中，所述去除所述硬掩膜层之后还包括在所述衬底中形成第二阱区的步骤，所述源极区位于所述第二阱区中，所述第二阱区具有第二导电类型阱区，所述源极区和漏极区具有第一导电类型，所述第一导电类型和第二导电类型为相反的导电类型。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型。
还有必要提供一种沟槽型双扩散金属氧化物半导体器件，通过前述任一实施例所述的沟槽型双扩散金属氧化物半导体器件的制造方法制造形成。
还有必要提供一种沟槽型双扩散金属氧化物半导体器件，设有从衬底正面向衬底中延伸的第一沟槽，所述沟槽型双扩散金属氧化物半导体器件包括：底栅，绝缘隔离结构，顶栅，源极区和漏极区。底栅设于所述第一沟槽的下部，所述底栅的底部和侧面被位于所述第一沟槽的内表面的栅介电层包围；绝缘隔离结构设于所述第一沟槽中、所述底栅上；顶栅设于所述第一沟槽中且靠近所述第一沟槽的一侧设置，所述顶栅位于所述底栅上方，所述顶栅与所述底栅之间被所述绝缘隔离结构隔开；源极区设于所述第一沟槽的设置所述顶栅的一侧的衬底中；漏极区设于所述第一沟槽的另一侧的所述衬底中，且靠近所述衬底的正面设置。所述源极区的宽度大于所述漏极区的宽度，所述漏极区与所述顶栅之间被所述绝缘隔离结构隔开。
上述沟槽型双扩散金属氧化物半导体器件的源极区宽度大于漏极区宽度，能够避免用于刻蚀沟槽的硬掩膜剥落而影响器件良率的情况。且器件的漏极区可以从正面引出，因此能够兼容CMOS工艺，可以应用于BCD工艺平台，在优化器件性能的同时还能有效降低芯片面积。
附图说明
为了更好地描述和说明本公开的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对本公开目前描述的实施例和/或示例以及目前理解的本公开的最佳模式中的任何一者的范围的限制。
图1是本申请一实施例中沟槽型双扩散金属氧化物半导体器件的制造方法的流程图；
图2是本申请一实施例中有源区光刻版的版图的示意图；
图3a-图3f是本申请一实施例采用图1所示的方法制造TrenchDMOS器件的过程中器件的剖面示意图；
图4是本申请一实施例中在第一沟槽中形成底栅和底栅上的绝缘隔离结构的流程图；
图5a是本申请另一实施例中有源区光刻版的版图的局部示意图，图5b示出了第一光刻胶层在图5a中对应的位置；
图6是本申请一实施例中在刻蚀沟槽内的绝缘介质时TrenchDMOS器件的剖面结构示意图；
图7是本申请一实施例硬掩膜发生剥落时的显微镜图像。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述申请的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本申请的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
相关技术中的一种示例性的漏端正面引出的TrenchDMOS的制造方法是，在沟槽中形成底栅，然后在底栅上淀积绝缘介质，光刻并刻蚀绝缘介质形成底栅上的绝缘隔离结构(需要通过光刻胶对用于形成引出结构的沟槽中的栅极材料进行保护)，然后在绝缘隔离结构上填充栅极材料，再通过光刻及刻蚀将漏端的栅极材料去除，然后通过绝缘介质将沟槽填满，最后进行CMP(化学机械抛光)。这种方案刻蚀沟槽中漏端的栅极材料需要单独准备一张光刻版，并且刻蚀绝缘隔离结构也需要使用一块光刻版，以对引出结构进行保护。
图1是本申请一实施例中一种沟槽型双扩散金属氧化物半导体器件的制造方法的流程图，包括下列步骤S110至S180。
S110，使用有源区光刻版在衬底210上形成硬掩膜层230。
有源区光刻版包括源极区图形204、漏极区图形202及位于源极区图形204和漏极区图形202之间的第一沟槽图形201。图2是本申请一实施例中有源区光刻版的版图的示意图，在该实施例中，有源区光刻版还包括第二沟槽图形203。源极区图形204、漏极区图形202及第一沟槽图形201位于器件区，第二沟槽图形203位于引出区。第一沟槽图形201的一端与第二沟槽图形203直接连接。
图3a是步骤S110完成后晶圆的剖面结构示意图，其中点划线左侧为引出区结构(对应图2中的AA’截面)，并且将引出区的大宽度结构缩小为一个小宽度结构以便于构图，点划线右侧为器件区结构(对应图2中的BB’截面)。在本申请的一个实施例中，硬掩膜层230的材质为氮化 硅。在本申请的一个实施例中，在衬底210上淀积硬掩膜材料后，再于硬掩膜材料上涂覆光刻胶，然后使用有源区光刻版对光刻胶进行曝光，显影后光刻胶形成刻蚀窗口，然后刻蚀硬掩膜材料得到硬掩膜层230。
在本申请的一个实施例中，源极区图形和漏极区图形的透光性与第一沟槽图形的透光性相反。即有源区光刻版上第一沟槽图形透光，源极区图形和漏极区图形不透光；或者源极区图形和漏极区图形透光，第一沟槽图形不透光。
在图3a所示的实施例中，在步骤S110之前还包括形成第一阱区212的步骤。在本申请的一个实施例中，第一阱区212为高压阱。在本申请的一个实施例中，第一阱区212为第一导电类型阱，衬底210为第二导电类型衬底。在本申请的一个实施例中，第一导电类型是N型，第二导电类型是P型；在其他实施例中，也可以是第一导电类型为P型，第二导电类型为N型。
在图3a所示的实施例中，在形成硬掩膜层230之前，还可以先在衬底210上形成氧化层220。在本申请的一个实施例中，氧化层220为衬垫氧化层，其材质为硅氧化物，例如二氧化硅。
S120，以硬掩膜层230为刻蚀阻挡层刻蚀形成第一沟槽211，第一沟槽的一侧为源极区254。
参照图3b，第一沟槽图形201转移到衬底210后对应的区域为第一沟槽211第一沟槽211的一侧为源极区254。步骤S120所述硬掩膜层230为刻蚀阻挡层刻蚀形成第一沟槽211包括：以所述硬掩膜层230为刻蚀阻挡层刻蚀形成第一沟槽211和第二沟槽213。第二沟槽图形203转移到衬底210后对应的区域为第二沟槽213。在图3b所示的实施例中，还需要在衬底210中形成浅沟槽215，以形成TrenchDMOS与CMOS之间的浅沟槽隔离结构(shallow trench isolation，STI)。在一些实施例中，所述有源区光刻版包括多个所述第一沟槽图形201(如图2所示)，所述源极区254位于两相邻的第一沟槽211之间(如图3f所示)。S130，在第一沟槽中形成底栅242和底栅上的绝缘隔离结构224。
在第一沟槽211(图3c中未标示)中形成底栅242和底栅242上的绝缘隔离结构224。在本申请一个实施例中，底栅242为屏蔽栅(Shield Gate)。在本申请一个实施例中，步骤S130还包括在第二沟槽213(图3c中未标示)中形成引出结构248。第一沟槽211和第二沟槽213连通，因此第一沟槽211中的底栅242与第二沟槽213中的引出结构248直接接触，可以通过引出结构248将底栅242从衬底210的正面引出。
参见图4，在本申请的一个实施例中，步骤S130包括：
S131，在第一沟槽211的内表面和第二沟槽213的内表面形成栅介电层222。
在本申请的一个实施例中，可以通过热氧化在第一沟槽211和第二沟槽213的内表面形成二氧化硅，作为栅介电层222。
S133，在第一沟槽和第二沟槽中填充栅极材料。
在本申请的一个实施例中，栅极材料为多晶硅材料，在其他实施例中也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极材料。可以通过淀积工艺在第一沟槽和第二沟槽中填充栅极材料。在本申请的一个实施例中，可以通过CMP去除多余的栅极材料，只保留第一沟槽211和第二沟槽213内的栅极材料。第二沟槽213中的栅极材料构成引出结构248。
S135，通过光刻在第二沟槽上形成光刻胶层。
在本申请的一个实施例中，在衬底210正面涂覆光刻胶，然后使用引出结构光刻版对光刻胶进行曝光，显影后剩余的光刻胶层覆盖第二沟槽213，以对第二沟槽中的栅极材料进行保护。
S137，刻蚀第一沟槽中的栅极材料，形成底栅。
以步骤S135形成的刻胶层为刻蚀阻挡层，刻蚀第一沟槽211中的栅极材料至所需的底栅厚度，形成底栅242。在一些实施例中，刻蚀第一沟槽中的栅极材料形成底栅包括：
S139，在底栅上形成绝缘隔离结构。
在本申请的一个实施例中，去除光刻胶层，然后在衬底210正面淀积绝缘介质作为绝缘隔离结构。在本申请的一个实施例中，绝缘介质可以是硅氧化物，例如二氧化硅。在一些实施例中，步骤S139在底栅上形成绝缘隔离结构，包括在所述第一沟槽中和所述硬掩膜层上形成绝缘隔离层；对所述绝缘隔离层进行化学机械抛光，得到所述绝缘隔离结构，所述硬掩膜层为抛光的阻挡层。在本申请的一个实施例中，步骤S139还包括在浅沟槽215中形成浅沟槽隔离结构228。
请继续参照图1，步骤S130之后还包括：
S140，通过光刻在源极区254上方形成开口291，开口291宽度大于源极区254的宽度。
参照图3c，在本申请的一个实施例中，在衬底210正面涂覆光刻胶，然后使用第一光刻版对光刻胶进行曝光，显影后得到的第一光刻胶层292在源极区(即有源区光刻版的源极区图形204在衬底210对应的区域)的上方形成开口291。开口291的宽度大于源极区的宽度，从而将第一沟槽211部分露出。
S150，刻蚀露出的第一沟槽211中的绝缘隔离结构224形成第三沟槽217，剩余的绝缘隔离结构至少位于所述第三沟槽和所述底栅之间。
参见图3d，刻蚀形成第三沟槽217，第一光刻胶层292和硬掩膜层230作为刻蚀阻挡层。 在本申请的一个实施例中，步骤S150为两步刻蚀，先进行干法刻蚀再湿法漂除源极区254侧壁残留的绝缘隔离结构224。剩余的绝缘隔离结构至少位于所述第三沟槽217和所述底栅242之间。
S160，向第三沟槽217中填充栅极材料作为顶栅。
在本申请的一个实施例中，向第三沟槽217中填充栅极材料之前还包括形成栅介质层的步骤，即在步骤S150刻蚀露出的第一沟槽侧壁，形成栅介质层，栅介质层的材质可以是硅氧化物，例如二氧化硅。填充的栅极材料可以与步骤S133中填充的栅极材料相同，也可以不同。即顶栅244的材料可以与底栅242相同，也可以不同。在图3e所示的实施例中，顶栅244和底栅242的材料均为多晶硅。在本申请的一个实施例中，步骤S160向第三沟槽217中填充栅极材料之前，先要将第一光刻胶层292去除。在第三沟槽217中填充栅极材料后可以通过回刻或CMP将多余的栅极材料去除。
S170，去除硬掩膜层230。
在本申请的一个实施例中，可以通过刻蚀工艺去除硬掩膜层230。
S180，通过掺杂形成源极区254和漏极区252。
通过离子注入工艺注入第一导电类型的离子形成源极区254和漏极区252。源极区254位于第一沟槽211(图3f中未标示)设有顶栅244的一侧，漏极区252位于第一沟槽211的另一侧。在图3f所示的实施例中，步骤S170之后还包括形成第二阱区258的步骤。第二阱区258作为沟道区，源极区254位于第二阱区258中，第二阱区258具有第二导电类型。
上述沟槽型双扩散金属氧化物半导体器件的制造方法，利用第一光刻版刻蚀绝缘隔离结构来形成顶栅，无需为顶栅的刻蚀单独做一块光刻版，因此可以节省制造成本，降低工艺复杂度。器件的漏极区可以从正面引出，因此能够兼容CMOS工艺，可以将上述沟槽型双扩散金属氧化物半导体器件的制造方法应用于BCD工艺平台，在优化器件性能的同时还能有效降低芯片面积。
对于BCD工艺平台，需要在TrenchDMOS与CMOS之间设置浅沟槽隔离结构(参照前述实施例中的浅沟槽隔离结构228)。参照图6，由于要兼容CMOS工艺，通常在进行CMOS工艺前就将STI做完，而硬掩膜(通常为SiN膜)作为STI等结构CMP的阻挡层，因此在湿法刻蚀沟槽内的绝缘介质时，硬掩膜仍然保留。所以在有源区图形的宽度较小时，很容易出现剥落(peeling)，即湿法腐蚀液进入硬掩膜和硅中间的氧化层，导致硬掩膜剥落，参照图7。
图5a是另一实施例中有源区光刻版的版图的局部示意图(省略了第二沟槽图形)。在图5a所示的实施例中，有源区光刻版包括源极区图形304、漏极区图形302及位于源极区图形304 和漏极区图形302之间的第一沟槽图形301。根据前述，有源区图形的宽度较小时容易出现硬掩膜剥落，但加大有源区宽度又会增加大器件面积，并且增大Rdson(导通电阻)。参照图3d，前述实施例中刻蚀绝缘隔离结构224时开口291位于源极区254的位置上方，漏极区252的位置则被第一光刻胶层292覆盖(第一光刻胶层292对应有源区光刻版版图的位置参照图5b)，也即开口291露出源极区以及源极区周围的部分第一沟槽211。回刻开口291露出的源极区254周围的部分第一沟槽211内的绝缘隔离结构过程中，漏极区252不会出现硬掩膜剥落的问题。因此，在本申请的一个实施例中，源极区图形304的宽度大于漏极区图形302的宽度，通过只增大源极区图形304的宽度，从而避免硬掩膜剥落；同时为了避免器件面积增大或保持器件的节距(pitch)整体不变，可以相应减小漏极区图形302的宽度。在本申请的一个实施例中，参照图3d，源极区宽度a≥0.45微米。申请人经创造性研究发现在相应的宽度大于或等于0.5微米时不易出现硬掩膜剥落，而小于或等于0.4微米时易出现硬掩膜剥落。在本申请的一个实施例中，所述源极区的宽度小于或等于0.6微米。在本申请的一个实施例中，源极区宽度a为0.45微米≤a≤0.6微米，漏极区宽度相应缩小至0.3微米≤a≤0.45微米。
在本申请的一个实施例中，第三沟槽217的宽度为0.05～0.1微米，即开口291的宽度b(如图3c所示)比源极区宽度a(如图3d所示)大0.1～0.2微米。
请一并参照图5a和图5b，在本申请的一个实施例中，第一光刻胶层292将第一沟槽图形301与第二沟槽图形之间截断，从而将顶栅244截断，以避免顶栅244与引出结构248电性连接。
本申请还提供一种沟槽型双扩散金属氧化物半导体器件，其可以采用前述任一实施例所述的沟槽型双扩散金属氧化物半导体器件制造方法形成。沟槽型双扩散金属氧化物半导体器件的结构可以参照图3f，其设有从衬底210正面向衬底210中延伸的第一沟槽211(图3f中未标示)，沟槽型双扩散金属氧化物半导体器件还包括底栅242、绝缘隔离结构224、顶栅244、源极区254及漏极区252。底栅242设于第一沟槽211的下部，底栅242的底部和侧面被位于第一沟槽211的内表面的栅介电层222包围。绝缘隔离结构224设于第一沟槽211中、底栅242上。顶栅244设于第一沟槽211中且靠近第一沟槽211的一侧设置，顶栅244位于底栅242上方，顶栅244与底栅242之间被绝缘隔离结构224隔开。源极区254设于第一沟槽211的设置顶栅244的一侧的衬底210中(源极区254与顶栅244之间也被一层薄的栅介电层222隔离)，且靠近衬底210的正面设置。漏极区252设于第一沟槽211的另一侧的衬底210中，且靠近衬底210的正面设置，漏极区252与顶栅244之间被绝缘隔离结构224隔开。源极区254的宽度大于漏极区252 的宽度。
上述沟槽型双扩散金属氧化物半导体器件的源极区254的宽度大于漏极区252的宽度，能够避免用于刻蚀沟槽的硬掩膜剥落而影响器件良率的情况。且SGT器件的漏极区252可以从正面引出，因此能够兼容CMOS工艺，可以应用于BCD工艺平台，在优化器件性能的同时还能有效降低芯片面积。TrenchDMOS主要由纵向漂移区耐压，横向尺寸变小，相对于传统LDMOS器件，在击穿电压(BV)一致的情况下，面积变小，Rdson会有很大优势。同时，由于可以兼容CMOS工艺，TrenchDMOS部分在电路中无需独立出来，电路上可以减少很多面积。
在图3f所示的实施例中，沟槽型双扩散金属氧化物半导体器件还包括第一阱区212。第一阱区212作为TrenchDMOS的漂移区，源极区254和漏极区252位于第一阱区212中，从而构成U型漂移区。第一阱区212的掺杂类型与源极区254和漏极区252相同。在本申请的一个实施例中，第一阱区212、源极区254及漏极区252具有第一导电类型，衬底210具有第二导电类型。
在图3f所示的实施例中，沟槽型双扩散金属氧化物半导体器件还设有与第一沟槽211连通的第二沟槽213(图3f中未标示)，第二沟槽213中设有导电材料，第一沟槽211中的底栅242与第二沟槽213中的引出结构248直接接触，可以通过引出结构248将底栅242从衬底210的正面引出。在本申请的一个实施例中，底栅242与引出结构248的材料相同。
在图3f所示的实施例中，在衬底210正面还设置有浅沟槽隔离结构228，作为TrenchDMOS与CMOS之间的隔离。
在图3f所示的实施例中，第一沟槽211的设置顶栅244的一侧的衬底210中还设有第二阱区258。第二阱区258具有第二导电类型，源极区254设于第二阱区258中。
应该理解的是，虽然本申请的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且本申请的流程图中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种沟槽型双扩散金属氧化物半导体器件的制造方法，包括：
    使用有源区光刻版在衬底上形成硬掩膜层；
    以所述硬掩膜层为刻蚀阻挡层刻蚀形成第一沟槽，所述第一沟槽的一侧为源极区；其中所述有源区光刻版包括源极区图形、漏极区图形及位于所述源极区图形和漏极区图形之间的第一沟槽图形，所述第一沟槽图形在所述衬底对应的区域为所述第一沟槽，所述源极区为所述源极区图形在所述衬底对应的区域；
    在所述第一沟槽中形成底栅和所述底栅上的绝缘隔离结构；
    通过光刻在所述源极区上方形成开口，所述开口的宽度大于所述源极区的宽度；
    刻蚀露出的所述第一沟槽中的所述绝缘隔离结构形成第三沟槽，剩余的绝缘隔离结构至少位于所述第三沟槽和所述底栅之间；
    向所述第三沟槽中填充第一栅极材料作为顶栅；
    去除所述硬掩膜层；
    通过掺杂形成源极区和漏极区；其中所述第一沟槽位于所述源极区和所述漏极区之间，所述源极区位于所述第一沟槽设有所述顶栅的一侧，所述漏极区位于所述第一沟槽的另一侧。
  2. 根据权利要求1所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于，所述源极区图形的宽度大于所述漏极区图形的宽度。
  3. 根据权利要求2所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于，所述有源区光刻版包括多个所述第一沟槽图形，所述源极区位于两相邻的第一沟槽之间，所述源极区的宽度大于或等于0.45微米。
  4. 根据权利要求3所述的沟槽型双扩散金属氧化物半导体器件的制造方法，所述源极区的宽度小于或等于0.6微米。
  5. 根据权利要求2所述的沟槽型双扩散金属氧化物半导体器件的制造方法，所述源极区的宽度大于或等于0.45微米，且小于或等于0.6微米。
  6. 根据权利要求1-5中任一项所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于，所述第三沟槽的宽度范围为0.05～0.1微米。
  7. 根据权利要求1所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于，所述有源区光刻版还包括第二沟槽图形，所述第一沟槽图形的一端与所述第二沟槽图形直接连 接；
    所述以所述硬掩膜层为所述刻蚀阻挡层刻蚀形成所述第一沟槽的步骤包括：以所述硬掩膜层为刻蚀阻挡层刻蚀形成第一沟槽和第二沟槽；所述第二沟槽图形在所述衬底对应的区域为所述第二沟槽；
    所述在所述第一沟槽中形成底栅和所述底栅上的所述绝缘隔离结构的步骤包括：
    在所述第一沟槽的内表面和第二沟槽的内表面形成栅介电层；
    在第一沟槽和第二沟槽中填充第二栅极材料；
    通过光刻在所述第二沟槽上形成第二光刻胶层；
    刻蚀所述第一沟槽中的所述第二栅极材料，形成所述底栅；
    在所述底栅上形成绝缘隔离结构。
  8. 根据权利要求7所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于：
    在第一沟槽和第二沟槽中填充栅极材料步骤之后，还包括:将所述第三沟槽中的第二栅极材料作为引出结构；
    所述通过光刻在所述第二沟槽上形成所述第二光刻胶层，包括：使用第二光刻版在所述第二沟槽上形成所述第二光刻胶层；以及
    所述刻蚀第一沟槽中的所述第二栅极材料，形成所述底栅，包括：以所述第二光刻胶层为刻蚀阻挡层刻蚀所述第一沟槽中的第二栅极材料，形成所述底栅。
  9. 根据权利要求7所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于，所述在所述底栅上形成绝缘隔离结构的步骤包括：
    在所述第一沟槽中和所述硬掩膜层上形成绝缘隔离层；
    对所述绝缘隔离层进行化学机械抛光，得到所述绝缘隔离结构，所述硬掩膜层为抛光的阻挡层。
  10. 根据权利要求7所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于，所述在所述底栅上形成绝缘隔离结构，包括：
    去除所述第二光刻胶层；
    在所述衬底正面淀积绝缘介质作为所述绝缘隔离结构。
  11. 根据权利要求7所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于，所述使用有源区光刻版在所述衬底上形成所述硬掩膜层之前，还包括：在所述衬底中形成第一 阱区，所述第一阱区的导电类型与所述源极区和所述漏极区的导电类型相同，所述第一沟槽和所述第二沟槽形成于所述第一阱区中。
  12. 根据权利要求1所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于，所述使用有源区光刻版在所述衬底上形成所述硬掩膜层之前，还包括：在所述衬底上形成氧化层，所述氧化层的材质为硅氧化物。
  13. 根据权利要求1所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于，所述通过光刻在所述源极区上方形成所述开口，包括：
    在所述衬底正面涂覆光刻胶；
    使用第一光刻版对所述光刻胶进行曝光，显影后得到具有所述开口的第一光刻胶层，所述开口位于所述源极区的上方。
  14. 根据权利要求9所述的沟槽型双扩散金属氧化物半导体器件的制造方法，其特征在于，应用于BCD工艺平台，所述在所述底栅上形成绝缘隔离结构的步骤还包括形成位于所述沟槽型双扩散金属氧化物半导体器件与CMOS器件之间的浅沟槽隔离结构，所述硬掩膜层作为所述浅沟槽隔离结构的抛光的阻挡层。
  15. 一种沟槽型双扩散金属氧化物半导体器件，设有从衬底正面向衬底中延伸的第一沟槽，其特征在于，包括：
    底栅，设于所述第一沟槽的下部，所述底栅的底部和侧面被位于所述第一沟槽的内表面的栅介电层包围；
    绝缘隔离结构，设于所述第一沟槽中、所述底栅上；
    顶栅，设于所述第一沟槽中且靠近所述第一沟槽的一侧设置，所述顶栅位于所述底栅上方，所述顶栅与所述底栅之间被所述绝缘隔离结构隔开；
    源极区，设于所述第一沟槽的设置所述顶栅的一侧的衬底中；
    漏极区，设于所述第一沟槽的另一侧的所述衬底中，且靠近所述衬底的正面设置；
    其中，所述源极区的宽度大于所述漏极区的宽度，所述漏极区与所述顶栅之间被所述绝缘隔离结构隔开。
PCT/CN2023/106711 2022-07-12 2023-07-11 沟槽型双扩散金属氧化物半导体器件及其制造方法 WO2024012430A1 (zh)

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