CN103489901A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN103489901A
CN103489901A CN201210190898.4A CN201210190898A CN103489901A CN 103489901 A CN103489901 A CN 103489901A CN 201210190898 A CN201210190898 A CN 201210190898A CN 103489901 A CN103489901 A CN 103489901A
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gate
epitaxial loayer
layer
groove
contact hole
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娄翠红
刘厚超
唐翠
陈宇
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BYD Co Ltd
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Abstract

本发明提供一种利用沟槽工艺形成的半导体结构及其形成方法,通过设置与栅极沟槽连接的栅极引出沟槽,该栅极引出沟槽通过栅极接触孔与栅极金属电极接触,替代传统的栅极接触沟槽与栅极金属电极直接接触的结构,形成该半导体结构仅需要使用三次掩膜:沟槽掩膜、接触孔掩膜、金属层掩膜。相对于传统的五次掩膜工艺,在不降低器件性能的同时,大大减少MOSFET器件制造过程中的掩膜次数,降低工艺复杂度,降低成本,减少器件的制造时间,提供生产效率。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体设计和制造技术领域,特别涉及一种半导体结构及其形成方法。
背景技术
MOSFET功率器件的制造工艺包括:传统的平面工艺和当前的沟槽工艺。以沟槽工艺为例,图1所示为通过沟槽工艺形成的N沟道的MOSFET器件的结构剖面图。如图1所示,其工艺步骤通常是在N+半导体衬底9’上形成N-型外延层8’;在外延层8’上形成二氧化硅层,使用P阱(P-well)掩膜板(mask)定义P阱区;在硅片表面生长一层厚的二氧化硅层,使用沟槽掩膜板定义沟槽区域,并在N-外延层上形成多个沟槽,通过热氧化在沟槽中生长栅氧化层7’,在栅氧化层7’上淀积多晶硅层,然后对多晶硅层进行回刻,形成栅电极6’;接着在所定义的P阱区内,进行P型杂质离子注入和扩散,形成P阱区5’;再使用N+掩膜板,在P阱区内定N+源极接触区域,进行N型杂质离子的注入和扩散,形成N+源极接触区域4’;随后在芯片表面淀积绝缘介质层3’,使用接触孔掩膜板定义接触孔图形,光刻源极孔2’,在孔内填充阻挡层金属;在芯片表面形成金属层;然后使用金属层掩膜板,定义栅极金属区域和源极金属区域,并采用干法刻蚀形成栅极金属电极11’和源极金属电极1’;最后在半导体衬底9’的背面淀积金属层形成漏极金属电极10’。
从以上制造流程可以看出,现有的沟槽工艺制程至少包括五层光刻掩膜版:P阱掩膜板、沟槽掩膜层、N+掩膜板、接触孔掩膜板和金属层掩膜板。即在器件制造过程中,需要经过5次光刻,而每次光刻需要经过至少8个工艺步骤,包括气相成膜、旋转涂胶、烘焙、曝光、曝光后烘陪、显影、固膜烘陪和显影检查,这些步骤在芯片制造过程中占有非常大的机台比例和时间比例。
因此,需要一种能够减少MOSFET器件制造过程中的掩膜次数的沟槽工艺,以大幅度降低成本,减少器件的制造时间,提供生产效率。
发明内容
本发明的目的旨在至少解决上述技术缺陷之一,特别是提供一种利用沟槽工艺形成的MOSFET器件结构及其形成方法,通过减少MOSFET器件制造过程中的掩膜次数,从而大幅度降低成本,减少器件的制造时间,提供生产效率。
为达到上述目的,本发明一方面提出了一种半导体结构,包括:
半导体衬底,所述半导体衬底的第一表面依次形成有外延层和绝缘层;
源极区,形成在所述半导体衬底的所述第一表面,所示源极区包括:多条相互连通的栅极沟槽,形成在所述外延层中,分别沿第一方向和第二方向平行设置,所述多条栅极沟槽将所述源极区划分为多个元胞区;源极金属电极,形成在所述绝缘层上;和多个源极接触孔,每个所述源极接触孔分别位于每个所述元胞区,贯通所述源极金属电极和绝缘层到达所述外延层;
栅极区,形成在所述半导体衬底的所述第一表面,所述栅极区包括:至少一条栅极引出沟槽,形成在所述外延层中,且与所述栅极沟槽连接,栅极金属电极,形成在所述绝缘层上,和至少一个栅极接触孔,每条所述栅极引出沟槽分别通过每个所述栅极接触孔与所述栅极金属电极连接;和
漏极,形成在所述半导体衬底的第二表面。
在本发明的一个实施例中,所述半导体结构还包括形成在所述半导体衬底上的所述源极区和栅极区两侧的至少一条隔离沟槽,所述隔离沟槽形成在所述外延层中作为截止环,一方面用于隔离各个器件,另一方面用于使电场均匀分布在各个截止环上,防止电击穿。本发明实施例中隔离沟槽设计具有较好的电场截止效果,并且高温漏电小,高温可靠性好。
在本发明的一个实施例中,所述隔离沟槽的宽大于所述栅极沟槽的宽度,以增强隔离效果。
在本发明的一个实施例中,所述栅极沟槽、栅极引出沟槽和隔离沟槽中形成有栅介质层,所述栅介质层上形成有栅极层。
在本发明的一个实施例中,所述外延层从下至上依次包括:第一类型轻掺杂外延层、第二类型阱层、第一类型重掺杂外延层。
在本发明的一个实施例中,所述源极区的边界处形成有至少一个边界接触孔,所述边界接触孔贯通所述源极金属电极和绝缘层到达所述外延层。通过设置边界接触孔,使元胞区***的外延层的第二类型阱层和第一类型重掺杂外延层与源极等电位,以避免由于第二类型阱层和第一类型重掺杂外延层的悬空而造成表面漏电。
在本发明的一个实施例中,所述源极接触孔、栅极接触孔和边界接触孔分别到达所述外延层的第二类型阱层。
本发明另一方面还提出了一种上述半导体结构的形成方法,包括以下步骤:
S01:提供所述半导体衬底;
S02:在所述半导体衬底的所述第一表面上形成所述第一类型轻掺杂外延层;
S03:刻蚀所述第一类型轻掺杂外延层形成沟槽,所述沟槽包括所述栅极沟槽和栅极引出沟槽,在所述沟槽中形成所述栅介质层,在所述栅介质层上形成所述栅极层;
S04:在所述第一类型轻掺杂外延层内的上部区域形成所述第二类型阱层,在所述第二类型阱层内的上部区域形成所述第一类型重掺杂外延层;
S05:在所述第一类型重掺杂外延层上形成所述绝缘层;
S06:刻蚀所述绝缘层和部分所述第二类型阱层形成所述源极接触孔和栅极接触孔;
S07:在所述绝缘层表面形成第一金属层,刻蚀所述第一金属层形成所述源极金属电极和栅极金属电极;和
S08:在所述半导体衬底的所述第二表面上形成作为漏极的第二金属层。
在本发明的一个实施例中,步骤S02中形成所述第一类型轻掺杂外延层之后,还包括:在所述第一类型轻掺杂外延层上形成氧化层,以防止步骤S03中刻蚀沟槽时对半导体衬底造成损伤。
在本发明的一个实施例中,步骤S03进一步包括:S031:刻蚀所述氧化层和第一类型轻掺杂外延层形成所述沟槽;S032:去除所述氧化层,并在所述沟槽中形成牺牲氧化层;S033:去除所述牺牲氧化层,并在所述沟槽中形成所述栅介质层;和S034:在所述栅介质层上形成所述栅极层。通过在沟槽中形成牺牲氧化层的方式,可以去除沟槽内壁的晶格棱角,形成平滑的暴露表面。
在本发明的一个实施例中,步骤S03中形成的所述沟槽还包括:至少一条所述隔离沟槽。所述隔离沟槽形成在所述外延层中,用于隔离各个器件。本发明实施例中隔离沟槽设计具有较好的电场截止效果,并且高温漏电小,高温可靠性好。
在本发明的一个实施例中,所述隔离沟槽的宽度大于所述栅极沟槽的宽度,以增强隔离效果。
在本发明的一个实施例中,步骤S06包括:刻蚀所述绝缘层和部分所述第二类型阱层形成至少一个所述边界接触孔。通过设置边界接触孔,使元胞区***的外延层的第二类型阱层和第一类型重掺杂外延层与源极等电位,以避免由于第二类型阱层和第一类型重掺杂外延层的悬空而造成表面漏电。
本发明提供一种利用沟槽工艺形成的MOSFET器件结构及其形成方法,通过设置与栅极沟槽连接的栅极引出沟槽,该栅极引出沟槽通过栅极接触孔与栅极金属电极接触,替代传统的栅极接触沟槽与栅极金属电极直接接触的结构。并且,通过对整个器件表面进行注入,以形成阱区和源极接触区域,故形成该器件结构仅需要使用三次掩膜:沟槽掩膜、接触孔掩膜、金属层掩膜。相对于传统的五次掩膜工艺,节省了阱区掩膜和源极接触区域掩膜,在不降低器件性能的同时,大大减少MOSFET器件制造过程中的掩膜次数,降低工艺复杂度,降低成本,减少器件的制造时间,提供生产效率。
本发明附加的方面和优点将在下面的描述中部分给出,部分将从下面的描述中变得明显,或通过本发明的实践了解到。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解,其中:
图1为通过现有的沟槽工艺形成的N沟道的MOSFET器件的结构剖面图;
图2为本发明实施例的半导体结构的俯视图;
图3为沿图2所示的半导体结构的线AA’的剖面图;
图4为图2所示的半导体结构的栅极接触孔的局部剖面图;
图5-11为本发明实施例的半导体结构的形成方法的中间步骤的结构剖面图。
具体实施方式
下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。
在本发明的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。
需要说明的是,此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。进一步地,在本发明的描述中,除非另有说明,“多个”的含义是两个或两个以上。
在本发明的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通。对于本领域的普通技术人员而言,可以具体情况理解上述术语在本发明中的具体含义。
需指出的是,本发明实施例以N沟道的MOSFET器件为例描述本发明提供的半导体结构及其形成方法,对于P沟道的MOSFET器件可以参照本实施例对应改变掺杂状态,在此不再赘述。对于与本实施例所描述的MOSFET器件具有相同或相似结构的半导体结构,均落在本发明的保护范围之内。
图2为本发明实施例的半导体结构的俯视图,图3为沿图2所示的半导体结构的线AA’的剖面图。如图2和图3所示,该半导体结构包括:半导体衬底9、形成在半导体衬底9的第一表面的源极区100和栅极区200,形成在半导体衬底9的第二表面的漏极10。其中,第一表面和第二表面分别为半导体衬底9的顶面和底面。
其中,半导体衬底9可以是制备MOS器件的任何半导体衬底,具体可以是但不限于硅、锗硅、锗、砷化镓、砷化镓、砷化铟或者磷化铟等半导体材料。半导体衬底9可以可选地包括外延层,可以被应力改变以增强其性能,以及也可以包括绝缘体上半导体(SOI)结构。在本实施例中,半导体衬底9可以为N型重掺杂的硅衬底,其第一表面形成有外延层8。其中,外延层8自下至上依次包括N型轻掺杂的外延层12、P型阱层5、N型重掺杂外延层4。在外延层8上形成有绝缘层3,绝缘层3可以是硼磷硅玻璃(BPSG),也可以是正硅酸乙脂(TEOS)或者其他绝缘介质。
源极区100包括:多条栅极沟槽13、源极金属电极1和源极接触孔2。其中,多条栅极沟槽13形成在外延层8中、分别沿第一方向(横向,即图2中W方向)和第二方向(纵向,即图2中L方向)平行设置且相互连通;源极金属电极1形成在绝缘层3上;多条栅极沟槽13将源极区100划分为多个元胞区14,每个源极接触孔2分别位于每个元胞区14,且贯通源极金属电极1和绝缘层3到达外延层8的P型阱层5。
栅极区200包括:至少一条栅极引出沟槽15、栅极金属电极11、至少一个栅极接触孔16。其中,图2中所示为两条栅极引出沟槽15形成在外延层8中、沿第一方向设置,且与横向的栅极沟槽13连接;栅极金属电极11形成在在绝缘层3上;栅极接触孔16贯通栅极金属电极11和绝缘层3到达外延层8的P型阱层5;每条栅极引出沟槽15分别通过每个栅极接触孔16与栅极金属电极11连接,请参见如图4所示的栅极接触孔局部剖面图。
需指出的是,在本实施例中,为了清楚显示该半导体结构的元胞区结构,在图2中未显示绝缘层3以及覆盖在栅极沟槽13上的栅极金属电极11和覆盖在栅极引出沟槽15上的源极金属电极1。并且,为清楚简洁起见,图2中的栅极沟槽13和栅极引出沟槽15中未显示栅介质层7和栅极层6。
在本发明实施例中,该半导体结构还可以包括形成在半导体衬底9上的源极区100和栅极区200两侧的至少一条隔离沟槽17作为截止环,一方面用于隔离各个器件,另一方面用于使电场均匀分布在各个截止环上,防止电击穿。图2示出形成在栅极区200一侧的4条隔离沟槽17作为示例,需指出的是,图中所示的隔离沟槽17的形状和数量仅用于描述方便起见,并不用于限制本发明。四条隔离沟槽17平行设置在外延层8中,且隔离沟槽17的上沿与形成在外延层8上的绝缘层3相接,隔离沟槽17的深度可以与栅极沟槽13、栅极引出沟槽15相当,从而可以利用同一块沟槽掩膜板一体化形成。本发明实施例中隔离沟槽设计可以配合其3mask的制造方法,具有较好的电场截止效果,较小的高温漏电,以及较好的高温可靠性。优选地,隔离沟槽17的宽度大于栅极沟槽13的宽度,以增强隔离效果。
在本发明实施例中,栅极沟槽13、栅极引出沟槽15和隔离沟槽17中形成有栅介质层7,栅介质层7上形成有栅极层6。如图3所示,栅介质层7形成在隔离沟槽17的内壁,栅极层6进一步形成在栅介质层7上,且栅介质层7和栅极层6的上表面与形成在外延层8上的绝缘层3相接。其中,栅介质层7的材料可以是常规的二氧化硅等绝缘介质,栅极层6的材料可以是多晶硅。
在本发明实施例中,优选地,源极区100的边界处形成有至少一个边界接触孔18。图2所示为三个边界接触孔18贯通源极金属电极1和绝缘层3到达外延层8的P型阱层5。通过设置边界接触孔18,使元胞区14***的外延层8的P型阱层5、N型重掺杂外延层4与源极等电位,以避免由于P型阱层5和N型重掺杂外延层4的悬空而造成表面漏电。
在本发明实施例中,源极接触孔2、栅极接触孔16和边界接触孔18的深度可以相当,从而可以利用同一块接触孔掩膜板一体化形成。在各个接触孔中形成有金属阻挡层,从而与孔壁和孔底形成欧姆接触。例如金属阻挡层可以包括金属钛(Ti)粘结层和氮化钛(TiN)阻挡层。
本发明实施例进一步提供一种上述半导体结构的形成方法,下面参照图5-11具体描述该形成方法的具体步骤。该方法包括以下步骤:
步骤S01:提供半导体衬底9。半导体衬底9可以是制备MOS器件的任何半导体衬底,具体可以是但不限于硅、锗硅、锗、砷化镓、砷化镓、砷化铟或者磷化铟等半导体材料。半导体衬底9可以可选地包括外延层,可以被应力改变以增强其性能,以及也可以包括绝缘体上半导体(SOI)结构。在本实施例中,半导体衬底9可以为N型重掺杂的硅衬底。
步骤S02:在半导体衬底9的第一表面上形成N型轻掺杂的外延层12,如图5所示。优选地,形成N型轻掺杂的外延层12之后,还可以在N型轻掺杂的外延层12上形成厚氧化层,以防止步骤S03中刻蚀沟槽时对半导体衬底9造成损伤。该厚氧化层的厚度可以大于或等于2000A。
步骤S03:刻蚀N型轻掺杂的外延层12形成沟槽19,沟槽19包括栅极沟槽13和栅极引出沟槽15(图5中未示出),如图6所示。优选地,沟槽19还包括:至少一条隔离沟槽17,用于隔离各个器件。本发明实施例中隔离沟槽设计可以配合其3mask的制造方法,具有较好的电场截止效果,较小的高温漏电,以及较好的高温可靠性。优选地,隔离沟槽17的宽度大于栅极沟槽13的宽度,以增强隔离效果。在本实施例中,步骤S03可以包括以下步骤:S031:刻蚀厚氧化层和N型轻掺杂的外延层12形成沟槽19,具体地,使用沟槽掩膜板进行光刻,通过涂胶、曝光、显影和去胶步骤,在芯片表面形成图案化的第一掩膜层,然后通过干法刻蚀厚氧化层,接着通过反应离子刻蚀法(Reactive IonEtching)刻蚀外延层12,在外延层12上形成具有预定深宽比的沟槽19;S032:去除厚氧化层,并在沟槽19中形成牺牲氧化层,具体地,可以采用湿法刻蚀去除剩余厚氧化层,采用热氧化法在沟槽19形成牺牲氧化层;S033:去除牺牲氧化层,并在沟槽19中形成栅介质层7,栅介质层7的厚度小于牺牲氧化层的厚度;和S034:在栅介质层7上形成栅极层6,具体地,栅介质层7的材料可以是常规的二氧化硅等绝缘介质,在栅氧化层7上用低压化学气相淀积(LPCVD)淀积多晶硅形成栅电极层6。优选地,根据需要,步骤S034之后还可以包括:根据沟槽19的深度采用干法回刻多晶硅层6。通过在沟槽中形成牺牲氧化层的方式,可以去除沟槽内壁的晶格棱角,形成平滑的暴露表面。
步骤S04:在N型轻掺杂的外延层12内的上部区域形成P型阱层5,在P型阱层5内的上部区域形成N型重掺杂外延层4。在本实施例中,具体地,可以采用大束流注入机在N型轻掺杂的外延层12内的上部区域注入P型本体区离子,在高温炉管中退火,以激活本体区杂质离子,如图7所示;然后采用大束流注入机在P型阱层5内的上部区域注入N型源区离子,在高温炉管中退火,激活源区的杂质离子,如图7所示。
步骤S05:在N型重掺杂外延层4上形成绝缘层3,如图9所示。绝缘层3可以采用例如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)及/或其他合适的工艺等方法形成。绝缘层3的材料可以是硼磷硅玻璃(BPSG),也可以是正硅酸乙脂(TEOS)或者其他绝缘介质。
步骤S06:刻蚀绝缘层3和部分P型阱层5形成源极接触孔2和栅极接触孔16。优选地,刻蚀绝缘层3和部分P型阱层5可以同时形成至少一个边界接触孔18,如图10所示。通过设置边界接触孔18,使元胞区14***的外延层8的P型阱层5、N型重掺杂外延层4与源极等电位,以避免由于P型阱层5和N型重掺杂外延层4的悬空而造成表面漏电。在本实施例中,具体地,使用接触孔掩膜板进行光刻,通过涂胶、曝光、显影和去胶步骤,在芯片表面形成图案化的第二掩膜层,然后采用湿法刻蚀绝缘层3,打开接触孔窗口,再采用等离子体刻蚀部分P型阱层5,以形成具有预定深宽比的源极接触孔2、栅极接触孔16和边界接触孔18。接着,在各个接触孔中形成有金属阻挡层,从而与孔壁和孔底形成欧姆接触。具体可以包括:在接触孔中注入重搀杂的P型离子;在接触孔中用化学气相淀积法(CVD)淀积金属钛(Ti)粘结层和氮化钛(TiN)阻挡层,在高温炉中快速热退火,使金属阻挡层与孔壁和孔底形成欧姆接触。在覆盖有TiN阻挡层的通孔中用低压化学气相淀积法(LPCVD)形成钨塞,采用干法等离子体回刻刻蚀掉多余的钨覆盖层。
步骤S07:在绝缘层3表面形成第一金属层,刻蚀第一金属层形成源极金属电极1和栅极金属电极11,如图11所示。在本实施例中,具体地,可以采用物理气相淀积(PVD)工艺在器件表面淀积第一金属层,使用金属层掩膜板光刻,通过涂胶、曝光、显影和去胶步骤,在芯片表面形成图案化的第三掩膜层,然后干法刻蚀刻掉不需要的金属覆盖层,剩下的第一金属层即为MOS器件的栅极金属电极1和源极金属电极11。步骤S07之后还包括将晶圆减薄的步骤。
步骤S08:在半导体衬底9的第二表面上形成作为漏极10的第二金属层,如图2所示。具体地,可以采用背晶工艺在半导体衬底9的第二表面淀积第二金属层(如1K/2K/10K的Ti/Ni/Ag金属)。
本发明提供一种利用沟槽工艺形成的MOSFET器件结构及其形成方法,通过设置与栅极沟槽连接的栅极引出沟槽,该栅极引出沟槽通过栅极接触孔与栅极金属电极接触,替代传统的栅极接触沟槽与栅极金属电极直接接触的结构,形成该器件结构仅需要使用三次掩膜:沟槽掩膜、接触孔掩膜、金属层掩膜。相对于传统的五次掩膜工艺,在不降低器件性能的同时,大大减少MOSFET器件制造过程中的掩膜次数,降低工艺复杂度,降低成本,减少器件的制造时间,提供生产效率。
在本说明书的描述中,参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中,对上述术语的示意性表述不一定指的是相同的实施例或示例。而且,描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
尽管已经示出和描述了本发明的实施例,对于本领域的普通技术人员而言,可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型,本发明的范围由所附权利要求及其等同限定。

Claims (13)

1.一种半导体结构,其特征在于,包括:
半导体衬底,所述半导体衬底的第一表面依次形成有外延层和绝缘层;
源极区,形成在所述半导体衬底的所述第一表面,包括:
多条相互连通的栅极沟槽,形成在所述外延层中,分别沿第一方向和第二方向平行设置,所述多条栅极沟槽将所述源极区划分为多个元胞区,
源极金属电极,形成在所述绝缘层上,和
多个源极接触孔,每个所述源极接触孔分别位于每个所述元胞区,贯通所述源极金属电极和绝缘层到达所述外延层;
栅极区,形成在所述半导体衬底的所述第一表面,包括:
至少一条栅极引出沟槽,形成在所述外延层中,与所述栅极沟槽连接,
栅极金属电极,形成在所述绝缘层上,和
至少一个栅极接触孔,每条所述栅极引出沟槽分别通过每个所述栅极接触孔与所述栅极金属电极连接;和
漏极,形成在所述半导体衬底的第二表面。
2.如权利要求1所述的半导体结构,其特征在于,还包括形成在所述半导体衬底上的所述源极区和栅极区两侧的至少一条隔离沟槽,所述隔离沟槽形成在所述外延层中。
3.如权利要求2所述的半导体结构,其特征在于,所述隔离沟槽的宽度大于所述栅极沟槽的宽度。
4.如权利要求2所述的半导体结构,其特征在于,所述栅极沟槽、栅极引出沟槽和隔离沟槽中形成有栅介质层,所述栅介质层上形成有栅极层。
5.如权利要求1所述的半导体结构,其特征在于,所述外延层从下至上依次包括:第一类型轻掺杂外延层、第二类型阱层、第一类型重掺杂外延层。
6.如权利要求5所述的半导体结构,其特征在于,所述源极区的边界处形成有至少一个边界接触孔,所述边界接触孔贯通所述源极金属电极和绝缘层到达所述外延层的第二类型阱层。
7.如权利要求5所述的半导体结构,其特征在于,所述源极接触孔、栅极接触孔分别到达所述外延层的第二类型阱层。
8.如权利要求1-7任一项所述的半导体结构的形成方法,其特征在于,包括以下步骤:
S01:提供所述半导体衬底;
S02:在所述半导体衬底的所述第一表面上形成所述第一类型轻掺杂外延层;
S03:刻蚀所述第一类型轻掺杂外延层形成沟槽,所述沟槽包括所述栅极沟槽和栅极引出沟槽,在所述沟槽中形成所述栅介质层,在所述栅介质层上形成所述栅极层;
S04:在所述第一类型轻掺杂外延层内的上部区域形成所述第二类型阱层,在所述第二类型阱层内的上部区域形成所述第一类型重掺杂外延层;
S05:在所述第一类型重掺杂外延层上形成所述绝缘层;
S06:刻蚀所述绝缘层和部分所述第二类型阱层形成所述源极接触孔和栅极接触孔;
S07:在所述绝缘层表面形成第一金属层,刻蚀所述第一金属层形成所述源极金属电极和栅极金属电极;和
S08:在所述半导体衬底的所述第二表面上形成作为漏极的第二金属层。
9.如权利要求8所述的半导体结构的形成方法,其特征在于,步骤S02中形成所述第一类型轻掺杂外延层之后,还包括:在所述第一类型轻掺杂外延层上形成氧化层。
10.如权利要求9所述的半导体结构的形成方法,其特征在于,步骤S03进一步包括:
S031:刻蚀所述氧化层和第一类型轻掺杂外延层形成所述沟槽;
S032:去除所述氧化层,并在所述沟槽中形成牺牲氧化层;
S033:去除所述牺牲氧化层,并在所述沟槽中形成所述栅介质层;和
S034:在所述栅介质层上形成所述栅极层。
11.如权利要求8所述的半导体结构的形成方法,其特征在于,步骤S03中形成的所述沟槽还包括:至少一条所述隔离沟槽。
12.如权利要求11所述的半导体结构的形成方法,其特征在于,所述隔离沟槽的宽度大于所述栅极沟槽的宽度。
13.如权利要求8所述的半导体结构的形成方法,其特征在于,步骤S06包括:刻蚀所述绝缘层和部分所述第二类型阱层形成至少一个所述边界接触孔。
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WO2024012430A1 (zh) * 2022-07-12 2024-01-18 无锡华润上华科技有限公司 沟槽型双扩散金属氧化物半导体器件及其制造方法

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