WO2023279485A1 - 一种封装方法及其封装结构 - Google Patents

一种封装方法及其封装结构 Download PDF

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Publication number
WO2023279485A1
WO2023279485A1 PCT/CN2021/113188 CN2021113188W WO2023279485A1 WO 2023279485 A1 WO2023279485 A1 WO 2023279485A1 CN 2021113188 W CN2021113188 W CN 2021113188W WO 2023279485 A1 WO2023279485 A1 WO 2023279485A1
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Prior art keywords
adhesive
substrate
chip
groove
conductive
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PCT/CN2021/113188
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English (en)
French (fr)
Inventor
庄凌艺
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长鑫存储技术有限公司
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Priority to US17/668,724 priority Critical patent/US20230010585A1/en
Publication of WO2023279485A1 publication Critical patent/WO2023279485A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item

Definitions

  • the present application relates to but is not limited to a packaging method and its packaging structure.
  • Flip-chip technology is not only a chip interconnection technology. At present, flip-chip technology has become a frequently used packaging form in the field of high-end devices and high-density packaging.
  • an adhesive is used to fixedly connect the chip and the substrate.
  • An embodiment of the present application provides a packaging method, including: providing a substrate with a groove on the surface, the substrate includes at least one pad, and the groove exposes the pad;
  • a chip having a first surface and a second surface opposite to each other, at least one conductive bump being disposed on the first surface of the chip;
  • the chip is mounted on the substrate, and the conductive bump is connected to the pad through the first adhesive and the second adhesive.
  • the embodiment of the present application also provides a packaging structure, including:
  • a substrate having a groove on its surface, the substrate including at least one pad, the groove exposing the pad;
  • the first adhesive is disposed in the groove
  • a chip having opposite first and second surfaces, at least one conductive bump is disposed on the first surface of the chip;
  • a second adhesive located between the first surface of the chip and the first adhesive, the conductive bump passing through the second adhesive and the first adhesive and The pads are connected.
  • FIG. 1 is a schematic diagram of a packaging method provided in the related art
  • FIG. 2 is a block flow diagram of the encapsulation method provided by the embodiment of the present application.
  • 3a-3g are process flow charts of the packaging method provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a packaging structure provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a packaging method provided in the related art. As shown in the figure, a substrate 1 with a groove 14 on the surface is provided, the substrate 1 includes at least one pad 13, and the groove 14 exposes the pad 13 .
  • a chip 2 is provided, the chip 2 includes a first surface 2a and a second surface 2b oppositely disposed, and at least one conductive bump 22 is formed on the first surface 2a.
  • An adhesive 3 is applied on the first surface 2 a of the chip 2 and the conductive bumps 22 .
  • a thermal pressing device 4 is provided on the second surface 2b of the chip 2, the thermal pressing device 4 mounts the chip 2 on the substrate 1, the conductive bump 22 passes through the adhesive 3 and the The aforementioned pad 13 is connected.
  • the adhesive 3 cannot completely fill the groove 14, so that air often remains around the pad 13, resulting in Due to the existence of voids, during the subsequent reflow soldering process, the residual air is likely to cause bridging between the pads 13 , affecting the reliability of the package.
  • the embodiment of the present application provides a packaging method, as shown in Figure 2, the packaging method includes the following steps:
  • Step 201 providing a substrate with a groove on its surface, the substrate includes at least one pad, and the groove exposes the pad;
  • Step 202 providing a chip, the chip has a first surface and a second surface opposite to each other, and at least one conductive bump is provided on the first surface of the chip;
  • Step 203 filling the first adhesive in the groove
  • Step 204 applying a second adhesive on the first surface of the chip and the conductive bumps
  • Step 205 mounting the chip on the substrate, and connecting the conductive bump to the pad through the first adhesive and the second adhesive.
  • the first adhesive is filled in the groove of the substrate, which can solve the problem that the chip is mounted to the substrate only through the second adhesive.
  • the air cannot be completely discharged from the groove, which greatly reduces the probability of bridging between the conductive bumps in the subsequent reflow process, and improves the reliability of the package.
  • step 201 is performed, as shown in FIG. 3 a , a substrate 1 having a groove 14 on the surface is provided, the substrate 1 includes at least one pad 13 , and the groove 14 exposes the pad 13 .
  • the substrate 1 further includes a carrier board 11 and a solder resist layer 12; the step of providing the substrate 1 with grooves 14 on the surface includes: providing the carrier board 11, forming a solder mask on the carrier board 11. The solder resist layer 12 of a first opening constituting the groove 14 on the surface of the substrate.
  • the substrate may be a PCB board or a BT board
  • the solder resist layer may be green paint
  • step 202 is performed, as shown in FIG. 3b, a chip 2 is provided, the chip 2 has a first surface 2a and a second surface 2b opposite to each other, and the first surface 2a of the chip 2 is provided with at least A conductive bump 22 .
  • the first surface 2a of the chip 2 is further provided with an under bump metal layer 21, the under bump metal layer 21 is located on the first surface 2a and the conductive bump 22 between.
  • the chip 2 is an active device, such as a dynamic random access memory (DRAM). But not limited thereto, the chip 2 may also be a passive device.
  • DRAM dynamic random access memory
  • step 203 is executed, as shown in FIG. 3 c , filling the first adhesive 31 in the groove 14 .
  • the first adhesive 31 includes non-conductive glue (NCP), and the non-conductive glue is in paste form, and the first adhesive 31 in paste form fills the groove 14 .
  • the first adhesive 31 includes a thermosetting resin.
  • filling the first adhesive 31 in the groove 14 includes: filling the first adhesive 31 into the groove 14 until the groove 14 is filled , planarize the first adhesive 31 so that the upper surface of the first adhesive 31 is flush with the surface of the substrate 1 .
  • filling the first adhesive 31 in the groove 14 of the substrate 1 can solve the problem that the air cannot be completely discharged from the groove 14 and a gap appears. problem, greatly reducing the probability of bridging between the conductive bumps 22 in the subsequent reflow soldering process, and improving the reliability of the package.
  • the packaging method further includes: forming a second opening 311 in the first adhesive 31, the second opening 311 exposes the pad 13, as shown in FIG. 3d.
  • the second opening 311 can facilitate the inflow of other adhesives (such as the second adhesive 32 described later) when the subsequent chip 2 is installed, and can increase the contact between the first adhesive 31 and other adhesives. area, increasing the binding force.
  • the second opening 211 can be formed selectively, and in other embodiments, the step of forming the second opening 211 can be omitted.
  • step 204 is executed, as shown in FIG. 3 e , applying a second adhesive 32 on the first surface 2 a of the chip 2 and the conductive bump 22 .
  • the second adhesive 32 includes a non-conductive film (NCF), that is, the second adhesive 32 is in the form of a film.
  • the second adhesive 32 includes a thermosetting resin.
  • the thickness of the second adhesive 32 is greater than that of the first adhesive 31 .
  • the second adhesive 32 can cover part of the side surface of the chip 2, so as to reduce the gap between the subsequent molding material (EMC) and the side surface of the chip 2. The contact area between them can reduce the risk of delamination caused by the large difference in thermal expansion coefficient between the molding material and the chip 2 .
  • step 205 is executed, as shown in FIG. 3f and FIG. 3g, the chip 2 is mounted on the substrate 1, and the conductive bump 22 passes through the first adhesive 31 and the second adhesive.
  • the agent 32 is connected to the pad 13.
  • the mounting of the chip 2 on the substrate 1 includes:
  • thermocompression bonding device (TCB) 4 is provided, which is in contact with the second surface 2b of the chip 2 and heats and pressurizes the chip 2 to mount the chip 2 on The substrate 1.
  • the second adhesive 32 is in contact with the first adhesive 31 and the surface of the substrate 1 at the same time.
  • the conductive bumps 22 include solder; after the chip 2 is mounted on the substrate 1 , a solder reflow process is performed on the conductive bumps 22 .
  • the conductive bumps may also be other suitable metal materials.
  • the packaging method further includes a step of curing the first adhesive 31 and the second adhesive 32 .
  • the embodiment of the present application also provides a packaging structure, including: a substrate with a groove on the surface, the substrate includes at least one pad, and the groove exposes the pad; a first adhesive, the first An adhesive is disposed in the groove; a chip, the chip has an opposite first surface and a second surface, and at least one conductive bump is arranged on the first surface of the chip; a second adhesive , located between the first surface of the chip and the first adhesive, the conductive bump is connected to the pad through the second adhesive and the first adhesive .
  • the packaging structure provided by the embodiment of the present application is provided with a first adhesive in the groove, which greatly improves the reliability of the packaging structure compared with the packaging structure in the related art that only includes the second adhesive .
  • the package structure includes a substrate 1, a first adhesive 31, a second adhesive 32, and mounted on the first adhesive 31 and the second adhesive 32.
  • the chip 2 on the substrate 1, the surface of the substrate 1 has a groove 14, the substrate 1 is provided with a pad 13, the groove 14 exposes the pad 13, and the groove 14 is provided with First adhesive 31;
  • the chip 2 has a first surface 2a and a second surface 2b opposite to the first surface 2a, the first surface 2a is provided with conductive bumps 22, the conductive bumps 22 is connected to the pad 13 through the first adhesive 31 and the second adhesive 32 .
  • the first adhesive 31 includes non-conductive glue (NCP); in a specific embodiment, the first adhesive 31 includes thermosetting resin.
  • the first adhesive 31 is filled into the groove 14 before the chip 2 is mounted on the substrate 1 .
  • the problem that the air cannot be completely discharged from the groove 14 during the process of mounting the chip 2 to the substrate 1 only through the second adhesive 32 can be solved, and the conductive bumps in the subsequent reflow soldering process are greatly reduced.
  • the probability of bridging between blocks 22 improves the reliability of encapsulation.
  • the surface where the first adhesive 31 is connected to the second adhesive 32 is flush with the surface of the substrate.
  • the substrate 1 further includes a carrier board 11 and a solder resist layer 12 formed on the carrier board, the solder resist layer 12 has a first opening exposing the surface of the carrier board 11, so The first opening constitutes the groove 14 on the surface of the substrate.
  • the substrate 1 includes a PCB board, and the solder resist layer 12 includes green paint.
  • the second adhesive 32 includes a non-conductive film (NCF). In a specific embodiment, the second adhesive 32 includes a thermosetting resin.
  • the second adhesive 32 is applied to the first surface 2 a of the chip 2 and the conductive bumps 22 before the chip 2 is mounted on the substrate 1 .
  • the second adhesive 32 covers the first surface 2 a of the chip 2 and part of the side surface of the chip 2 .
  • the second adhesive 32 covers part of the side surface of the chip 2, which can reduce the contact area between the subsequent molding material (EMC) and the side surface of the chip 2, thereby reducing the The risk of delamination caused by the large difference in thermal expansion coefficient of chip 2.
  • the second adhesive 32 is simultaneously in contact with the first adhesive 31 and the surface of the substrate.
  • the conductive bump 22 includes solder. But not limited thereto, the conductive bump 22 may also include other metal materials.
  • the first surface 2a of the chip 2 is further provided with an under bump metal layer 21, and the under bump metal layer 21 is located on the first surface 2a and the conductive Between the bumps 22.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本申请实施例提供了一种封装方法，包括：提供表面具有凹槽的基板，所述基板包括至少一个焊盘，所述凹槽暴露所述焊盘；提供芯片，所述芯片具有彼此相对的第一表面和第二表面，所述芯片的所述第一表面上设置有至少一个导电凸块；在所述凹槽内填充第一粘结剂；在所述芯片的所述第一表面及所述导电凸块上施加第二粘结剂；将所述芯片安装至所述基板，所述导电凸块穿过所述第一粘结剂和所述第二粘结剂与所述焊盘连接。

Description

一种封装方法及其封装结构
相关申请的交叉引用
本申请基于申请号为202110776998.4、申请日为2021年07月09日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及但不限于一种封装方法及其封装结构。
背景技术
倒装芯片技术既是一种芯片互联技术。目前，倒装芯片技术已成为高端器件及高密度封装领域中经常采用的封装形式。
现有的倒装芯片技术中，采用粘结剂将芯片和基板固定连接。
然而，当所述基板上的焊盘周围具有凹槽时，芯片在倒装的过程中容易在所述凹槽内残留空气，影响芯片和基板的连接可靠性。
发明内容
本申请实施例提供了一种封装方法，包括：提供表面具有凹槽的基板，所述基板包括至少一个焊盘，所述凹槽暴露所述焊盘；
提供芯片，所述芯片具有彼此相对的第一表面和第二表面，所述芯片的所述第一表面上设置有至少一个导电凸块；
在所述凹槽内填充第一粘结剂；
在所述芯片的所述第一表面及所述导电凸块上施加第二粘结剂；
将所述芯片安装至所述基板，所述导电凸块穿过所述第一粘结剂和所 述第二粘结剂与所述焊盘连接。
本申请实施例还提供了一种封装结构，包括：
表面具有凹槽的基板，所述基板包括至少一个焊盘，所述凹槽暴露所述焊盘；
第一粘结剂，所述第一粘结剂设置于所述凹槽内；
芯片，所述芯片具有相对的第一表面和第二表面，所述芯片的所述第一表面上设置有至少一个导电凸块；
第二粘结剂，位于所述芯片的所述第一表面和所述第一粘结剂之间，所述导电凸块穿过所述第二粘结剂和所述第一粘结剂与所述焊盘连接。
附图说明
图1为相关技术中提供的封装方法的示意图；
图2为本申请实施例提供的封装方法的流程框图；
图3a-3g为本申请实施例提供的封装方法的工艺流程图。
图4为本申请实施例提供的封装结构的示意图。
具体实施方式
下面将参照附图更详细地描述本申请公开的示例性实施方式。虽然附图中显示了本申请的示例性实施方式，然而应当理解，可以以各种形式实现本申请，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本申请，并且能够将本申请公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实 际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本申请必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形 式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
图1为相关技术中提供的封装方法的示意图，如图所示，提供表面具有凹槽14的基板1，所述基板1包括至少一个焊盘13，所述凹槽14暴露所述焊盘13。
提供芯片2，所述芯片2包括相对设置的第一表面2a和第二表面2b，所述第一表面2a上形成有至少一个导电凸块22。
在所述芯片2的第一表面2a和所述导电凸块22上施加粘结剂3。
在所述芯片2的第二表面2b设置热压装置4，所述热压装置4将所述芯片2安装至所述基板1，所述导电凸块22穿过所述粘结剂3与所述焊盘13连接。
然而，在上述封装方法中，当所述芯片2安装至所述基板1后，所述粘结剂3并不能完全填充所述凹槽14，使得所述焊盘13周围常残留有空气而导致空隙的存在，在后续回流焊工艺时，所述残留的空气容易使所述焊盘13之间发生桥接，影响封装的可靠性。
基于此，提出了本申请实施例的以下技术方案。
本申请实施例提供了一种封装方法，如图2所示，所述封装方法包括如下步骤：
步骤201、提供表面具有凹槽的基板，所述基板包括至少一个焊盘，所述凹槽暴露所述焊盘；
步骤202、提供芯片，所述芯片具有彼此相对的第一表面和第二表面，所述芯片的所述第一表面上设置有至少一个导电凸块；
步骤203、在所述凹槽内填充第一粘结剂；
步骤204、在所述芯片的所述第一表面及所述导电凸块上施加第二粘结剂；
步骤205、将所述芯片安装至所述基板，所述导电凸块穿过所述第一粘结剂和所述第二粘结剂与所述焊盘连接。
本申请实施例在将所述芯片安装至所述基板之前，在所述基板的所述凹槽内填充第一粘结剂，可以解决所述芯片仅通过第二粘结剂安装至所述基板的过程中，空气无法从所述凹槽完全排出的问题，大幅度降低了后续回流焊工艺中导电凸块之间出现桥接的概率，提高了封装的可靠性。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合图3a-3g对本申请实施例提供的封装方法做进一步的详述。
首先，执行步骤201，如图3a，提供表面具有凹槽14的基板1，所述基板1包括至少一个焊盘13，所述凹槽14暴露所述焊盘13。
在一实施例中，所述基板1还包括载板11和阻焊层12；所述提供表面具有凹槽14的基板1的步骤包括：提供载板11，在所述载板11上形成具有第一开口的阻焊层12，所述第一开口构成所述基板表面的所述凹槽14。
在一实施例中，所述基板可以为PCB板或BT板，所述阻焊层为绿漆。
接下来，执行步骤202，如图3b所示，提供芯片2，所述芯片2具有彼此相对的第一表面2a和第二表面2b，所述芯片2的所述第一表面2a上设置有至少一个导电凸块22。
在一实施例中，所述芯片2的所述第一表面2a上还设置有凸块下金属层21，所述凸块下金属层21位于所述第一表面2a和所述导电凸块22之间。
在一实施例中，所述芯片2为有源器件，例如，动态随机存储器(DRAM)。但不限于此，所述芯片2还可以为无源器件。
接着，执行步骤203，如图3c所示，在所述凹槽14内填充第一粘结剂 31。
在一实施例中，所述第一粘结剂31包括非导电胶(NCP)，所述非导电胶呈膏状，所述呈膏状的第一粘结剂31填充所述凹槽14。在一具体实施例中，所述第一粘结剂31包含热固性树脂。
在一实施例中，在所述凹槽14内填充所述第一粘结剂31，包括：将所述第一粘结剂31填入所述凹槽14至所述凹槽14被填满，平坦化所述第一粘结剂31，使所述第一粘结剂31的上表面与所述基板1的所述表面齐平。
在所述芯片2安装至所述基板1之前，在所述基板1的所述凹槽14内填充第一粘结剂31，可以解决空气无法从所述凹槽14内完全排出而出现空隙的问题，大幅度降低了后续回流焊工艺中导电凸块22之间出现桥接的概率，提高了封装的可靠性。
在一实施例中，在所述凹槽14内填充第一粘结剂31之后，所述封装方法还包括：在所述第一粘结剂31内形成第二开口311，所述第二开口311暴露所述焊盘13，如图3d所示。所述第二开口311可以方便后续芯片2安装时，其他粘结剂(如后续描述的第二粘结剂32)的流入，可以增加所述第一粘结剂31与其他粘结剂的接触面积，增大结合力。
需要说明的是，所述第二开口211是可选择性地形成的，在其他实施例中，形成所述第二开口211的步骤可省略。
接下来，执行步骤204，如图3e所示，在所述芯片2的所述第一表面2a及所述导电凸块22上施加第二粘结剂32。
在一实施例中，所述第二粘结剂32包括非导电膜(NCF)，即所述第二粘结剂32呈膜状。在一具体的实施例中，所述第二粘结剂32包含热固性树脂。
在一实施例中，所述第二粘结剂32的厚度大于所述第一粘结剂31的厚度。如此，在所述芯片2安装至所述基板1后，所述第二粘结剂32能够 包覆所述芯片2的部分侧表面，以减少后续模封材料(EMC)与芯片2侧表面之间的接触面积，从而可以降低因所述模封材料与所述芯片2的热膨胀系数差异过大而引起的剥离风险。
接着，执行步骤205，如图3f及图3g所示，将所述芯片2安装至所述基板1，所述导电凸块22穿过所述第一粘结剂31和所述第二粘结剂32与所述焊盘13连接。
在一实施例中，所述将所述芯片2安装至所述基板1，包括：
提供热压粘合设备(TCB)4，所述热压粘合设备4与所述芯片2的所述第二表面2b接触并对所述芯片2加热、加压以将所述芯片2安装至所述基板1。
如图3g所示，在将所述芯片安装至所述基板1后，所述第二粘结剂32同时与所述第一粘结剂31和所述基板1的表面接触连接。
在一实施例中，所述导电凸块22包括焊料；在将所述芯片2安装至所述基板1后，对所述导电凸块22执行回流焊工艺。但不限于此，所述导电凸块还可以是其他合适的金属材料。
在将所述芯片2安装至所述基板1后，所述封装方法还包括固化所述第一粘结剂31和所述第二粘结剂32的步骤。
本申请实施例还提供了一种封装结构，包括：表面具有凹槽的基板，所述基板包括至少一个焊盘，所述凹槽暴露所述焊盘；第一粘结剂，所述第一粘结剂设置于所述凹槽内；芯片，所述芯片具有相对的第一表面和第二表面，所述芯片的所述第一表面上设置有至少一个导电凸块；第二粘结剂，位于所述芯片的所述第一表面和所述第一粘结剂之间，所述导电凸块穿过所述第二粘结剂和所述第一粘结剂与所述焊盘连接。
本申请实施例提供的封装结构在所述凹槽内设置有第一粘结剂，与相关技术中仅包括第二粘结剂的封装结构相比，极大程度的提高了封装结构 的可靠性。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合图4对本申请实施例提供的封装结构做一步的详述。
如图4所示，所述封装结构包括基板1、第一粘结剂31、第二粘结32、和通过所述第一粘结剂31和所述第二粘结剂32安装在所述基板1上的芯片2，所述基板1的表面具有凹槽14，所述基板1上设置有焊盘13，所述凹槽14暴露出所述焊盘13，所述凹槽14内设置有第一粘结剂31；所述芯片2具有第一表面2a和与所述第一表面2a相对的第二表面2b，所述第一表面2a上设置有导电凸块22，所述导电凸块22穿过所述第一粘结剂31和所述第二粘结剂32与所述焊盘13连接。
在一实施例中，所述第一粘结剂31包括非导电胶(NCP)；在一具体的实施例中，所述第一粘结剂31包括热固性树脂。
在一实施例中，所述第一粘结剂31是在所述芯片2安装至所述基板1之前，被填入至所述凹槽14内。如此，可以解决所述芯片2仅通过第二粘结剂32安装至所述基板1的过程中，空气无法完全从所述凹槽14排出的问题，大幅度降低了后续回流焊工艺中导电凸块22之间出现桥接的概率，提高了封装的可靠性。
在一实施例中，所述第一粘结剂31与所述第二粘结剂32连接的表面与所述基板表面齐平。
在一实施例中，所述基板1还包括载板11和形成在所述载板上的阻焊层12，所述阻焊层12具有一暴露所述载板11表面的第一开口，所述第一开口构成所述基板表面的所述凹槽14。在一具体的实施例中，所述基板1包括PCB板，所述阻焊层12包括绿漆。
在一实施例中，所述第二粘结剂32包括非导电膜(NCF)。在一具体的实施例中，所述第二粘结剂32包含热固性树脂。
在一实施例中，所述第二粘结剂32是在所述芯片2安装至所述基板1之前，施加至所述芯片2的所述第一表面2a及导电凸块22上。
在一实施例中，所述第二粘结剂32覆盖所述芯片2的所述第一表面2a以及所述芯片2的部分侧表面。所述第二粘结剂32覆盖所述芯片2的部分侧表面，可以减少后续模封材料(EMC)与芯片2侧表面之间的接触面积，从而可以降低因所述模封材料与所述芯片2的热膨胀系数差异过大而引起的剥离风险。
在一实施例中，所述第二粘结剂32同时与所述第一粘结剂31和所述基板表面接触连接。
在一实施例中，所述导电凸块22包括焊料。但不限于此，所述导电凸块22也可以包括其他金属材料。
在一实施例中，参见图4，所述芯片2的所述第一表面2a还设置有凸块下金属层21，所述凸块下金属层21位于所述第一表面2a和所述导电凸块22之间。
以上所述，仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种封装方法，包括：
    提供表面具有凹槽的基板，所述基板包括至少一个焊盘，所述凹槽暴露所述焊盘；
    提供芯片，所述芯片具有彼此相对的第一表面和第二表面，所述芯片的所述第一表面上设置有至少一个导电凸块；
    在所述凹槽内填充第一粘结剂；
    在所述芯片的所述第一表面及所述导电凸块上施加第二粘结剂；
    将所述芯片安装至所述基板，所述导电凸块穿过所述第一粘结剂和所述第二粘结剂与所述焊盘连接。
  2. 根据权利要求1所述的封装方法，其中，所述第一粘结剂包括非导电胶(NCP)，所述第二粘结剂包括非导电膜(NCF)。
  3. 根据权利要求1所述的封装方法，其中，所述第二粘结剂的厚度大于所述第一粘结剂的厚度。
  4. 根据权利要求1所述的封装方法，其中，在所述凹槽内填充第一粘结剂，包括：
    将所述第一粘结剂填入所述凹槽至所述凹槽被填满，平坦化所述第一粘结剂，使所述第一粘结剂的上表面与所述基板的所述表面齐平。
  5. 根据权利要求1所述的封装方法，其中，所述第一粘结剂为非导电的粘结剂，所述第一粘结剂包含热固性树脂；所述第二粘结剂为非导电的粘结剂，所述第二粘结剂包含热固性树脂。
  6. 根据权利要求1所述的封装方法，所述基板还包括载板和阻焊层；所述提供表面具有凹槽的基板的步骤包括：提供载板，在所述载板上形成具有第一开口的阻焊层，所述第一开口构成所述基板表面的所述凹槽。
  7. 根据权利要求1所述的封装方法，在所述凹槽内填充第一粘结剂之 后，所述封装方法还包括：
    在所述第一粘结剂内形成第二开口，所述第二开口暴露所述焊盘。
  8. 根据权利要求1所述的封装方法，在将所述芯片安装至所述基板后，所述第二粘结剂同时与所述第一粘结剂和所述基板的表面接触连接。
  9. 根据权利要求1所述的封装方法，其中，所述将所述芯片安装至所述基板的步骤包括：提供热压粘合设备，所述热压粘合设备与所述芯片的所述第二表面接触并对所述芯片加热、加压以将所述芯片安装至所述基板。
  10. 根据权利要求1所述的封装方法，所述导电凸块包括焊料；在将所述芯片安装至所述基板后，对所述导电凸块执行回流焊工艺。
  11. 根据权利要求1所述的封装方法，在将所述芯片安装至所述基板后，所述封装方法还包括固化所述第一粘结剂和所述第二粘结剂的步骤。
  12. 一种封装结构，包括：
    表面具有凹槽的基板，所述基板包括至少一个焊盘，所述凹槽暴露所述焊盘；
    第一粘结剂，所述第一粘结剂设置于所述凹槽内；
    芯片，所述芯片具有相对的第一表面和第二表面，所述芯片的所述第一表面上设置有至少一个导电凸块；
    第二粘结剂，位于所述芯片的所述第一表面和所述第一粘结剂之间，所述导电凸块穿过所述第二粘结剂和所述第一粘结剂与所述焊盘连接。
  13. 根据权利要求12所述的封装结构，其中，所述第一粘结剂包括非导电胶(NCP)，所述第二粘结剂包括非导电膜(NCF)。
  14. 根据权利要求12所述的封装结构，其中，所述第一粘结剂与所述第二粘结剂连接的表面与所述基板表面齐平。
  15. 根据权利要求12所述的封装结构，其中，所述第一粘结剂为非导电的粘结剂，所述第一粘结剂包含热固性树脂；所述第二粘结剂为非导电 的粘结剂，所述第二粘结剂包含热固性树脂。
  16. 根据权利要求12所述的封装结构，所述基板还包括载板和形成在所述载板上的阻焊层，所述阻焊层具有一暴露所述载板表面的第一开口，所述第一开口构成所述基板表面的所述凹槽。
  17. 根据权利要求12所述的封装结构，其中，所述第二粘结剂覆盖所述芯片的所述第一表面以及所述芯片的部分侧表面。
  18. 根据权利要求12所述的封装结构，其中，所述第二粘结剂同时与所述第一粘结剂和所述基板表面接触连接。
  19. 根据权利要求12所述的封装结构，其中，所述导电凸块包括焊料。
PCT/CN2021/113188 2021-07-09 2021-08-18 一种封装方法及其封装结构 WO2023279485A1 (zh)

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US20140098507A1 (en) * 2012-10-05 2014-04-10 Samsung Electro-Mechanics Co., Ltd. Printed circuit board, semiconductor package using the same, and method for manufacturing the printed circuit board and the semiconductor package
CN104701289A (zh) * 2013-12-06 2015-06-10 三星电子株式会社 半导体封装及其制造方法
CN111433907A (zh) * 2017-11-17 2020-07-17 美光科技公司 具有多层囊封剂的半导体装置及相关联***、装置与方法

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Publication number Priority date Publication date Assignee Title
US6297560B1 (en) * 1996-10-31 2001-10-02 Miguel Albert Capote Semiconductor flip-chip assembly with pre-applied encapsulating layers
US20140098507A1 (en) * 2012-10-05 2014-04-10 Samsung Electro-Mechanics Co., Ltd. Printed circuit board, semiconductor package using the same, and method for manufacturing the printed circuit board and the semiconductor package
CN104701289A (zh) * 2013-12-06 2015-06-10 三星电子株式会社 半导体封装及其制造方法
CN111433907A (zh) * 2017-11-17 2020-07-17 美光科技公司 具有多层囊封剂的半导体装置及相关联***、装置与方法

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