TWI239609B - Method for manufacturing multi package module - Google Patents
Method for manufacturing multi package module Download PDFInfo
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- TWI239609B TWI239609B TW093107355A TW93107355A TWI239609B TW I239609 B TWI239609 B TW I239609B TW 093107355 A TW093107355 A TW 093107355A TW 93107355 A TW93107355 A TW 93107355A TW I239609 B TWI239609 B TW I239609B
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- Prior art keywords
- module structure
- package
- item
- package module
- viscous
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 229910000679 solder Inorganic materials 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 13
- 239000000084 colloidal system Substances 0.000 claims description 37
- 239000003292 glue Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 3
- 230000004907 flux Effects 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 3
- 238000012360 testing method Methods 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 238000003466 welding Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 19
- 238000010586 diagram Methods 0.000 description 8
- 239000005022 packaging material Substances 0.000 description 4
- 239000000499 gel Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
1239609 五、發明說明（1) ^ ------ 【發明所屬之技術領域】 本發明係有關於一種多封裝件模組構造（Mu丨t 土 Package Module，MPM)之製造方法，特別係有關於—種在 小基板尺寸上點膠之多封裝件模組構造之製造方法。 【先前技術】 ' 隨著半導體封裝技術之演進發展，半導體封裝構造之 尺寸可以接近晶片尺寸而製造出晶片尺寸封裝件（chi S二P:ckage，CSP)，更在一般尺寸之封褒基板上可以 整a復數個晶片尺寸封裝件與其它晶片，以組合成且 整電性功能之多封裝件模組構造（Multi Package八1239609 V. Description of the invention (1) ^ ------ [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a multi-package module structure (Mu 丨 t Package Module, MPM). It is related to a manufacturing method of a multi-package module structure for dispensing on a small substrate size. [Prior technology] '' With the evolution and development of semiconductor packaging technology, the size of the semiconductor package structure can be close to the wafer size to produce chip-size packages (chi S2P: ckage, CSP), and more on the general-sized package substrate Multiple chip-size packages and other chips can be integrated into a multi-package module structure (Multi Package
Module，MPM)(MPM)，在未來趨勢中， 人 Γ, ^;ΛΘΘΛ, gystem In Package，SIp)，不需要整合系統單晶片 需:太〇:⑴p，soc)之多道製程且尺寸上已能符合所 ί於ίϊί:且良率高，故目前多封裝件模組構造係能運 裝置腦之繪圖卡、中央處理器與其它可攜式電子 有一2ί利ΐ告第557520號「封裝模組及其製程」揭示 習知ΐί 夕晶片封裝模組，依該前案之第1圖所示， α 土板上係封裝有一晶片並表面接合有一 ^牛係以凸塊或料結合至該基板之上表面，ς於^= (1:=該晶片而不密封該封裝件，-底部填充膠體 以#固4 j lnlmater ia 1)係填滿於該封I件與該基板， 亥封裝件’由晶片尺寸封裝件本身即有保護措施，Module (MPM) (MPM), in the future, people Γ, ^; ΛΘΘΛ, gystem In Package (SIp), do not need to integrate the system single chip (multiple processes: too 0: ⑴p, soc) and the size has been It can meet the requirements of the United Nations and has a high yield, so the current multi-package module structure is the graphics card, central processing unit and other portable electronics of the mobile device. And its process "reveals the conventional chip packaging module. As shown in Figure 1 of the previous case, a chip is packaged on the α soil plate and a surface is bonded to the substrate by bumps or materials. The upper surface is filled with ^ = (1: = the wafer without sealing the package,-the underfill gel is filled with #solid 4 j lnlmater ia 1) system to fill the package and the substrate. Chip-size packages are inherently protected,
1239609 五、發明說明1 (2) 當該封裝材料填滿而包覆在該晶片尺寸封裝件與該基板間 之忒些凸塊（或銲球）時，會導致該封裝材料耗用量過大且 不恰當’此外為了達到該封裝材料之填滿形成，該基板之 尺寸要設計得更大，以供在表面接合該封裝件之後點注形 成該封裝材料，但若無膠體固定該封裝件，則該封裝件^ 基板周邊之凸塊（或銲球）將會承受聚集之應力，且隨著該 封裝件之運算發熱，該些凸塊（或銲球）會軟化而易使該= 裝件掉脫，亦可能造成該封裝件之傾斜。 【發明内容】1239609 V. Description of the invention 1 (2) When the packaging material is filled and covered with bumps (or solder balls) between the chip-size package and the substrate, it will cause excessive consumption of the packaging material and Inappropriate 'In addition, in order to achieve the full formation of the packaging material, the size of the substrate should be designed to be larger, so as to form the packaging material after the surface bonding of the package, but if the package is not glued, then The package ^ The bumps (or solder balls) around the substrate will withstand the stress of aggregation, and as the operation of the package heats up, the bumps (or solder balls) will soften and make the = component drop Detachment may also cause the package to tilt. [Summary of the Invention]
，本發明之主要目的係在於提供一種多封裝件模組構造 之製造方法，一基板之上表面係包含複數個接合區，在結 合複數個晶片尺寸封裝件於該些接合區之前，係將複數^ 黏稍狀膠體對稱點塗於每一接合區之局部周緣，在結合複 數個晶片尺寸封裝件之後，回銲該些晶片尺寸封裝件之銲 球與固化該些黏稠狀膠體，以使該些固化之黏稠狀膠體得 以在不需填滿在該些晶片尺寸封裝件與該基板間之間隙便 能穩固該些晶片尺寸封裝件。The main object of the present invention is to provide a method for manufacturing a multi-package module structure. The upper surface of a substrate includes a plurality of bonding areas. Before combining a plurality of wafer-size packages to the bonding areas, a plurality of bonding areas are combined. ^ The sticky colloids are symmetrically applied to the local periphery of each bonding area. After combining a plurality of chip size packages, the solder balls of the chip size packages are re-soldered and the viscous colloids are cured to make the The cured viscous colloid can stabilize the chip-size packages without filling the gap between the chip-size packages and the substrate.
•本發明之次一目的係在於提供一種多封裝件模組構造 之製造方法，複數個黏稠狀膠體係對稱點塗於每一接合區 之周緣，例如將該些黏稠狀膠體對稱點塗成L形、團狀"或 直條狀，且該些黏稠狀膠體係可不填滿該些晶片尺寸封裝 件與該基板間之間隙，以節省該些黏稠狀膠體之耗用量: •本發明之再一目的係在於提供一種多封裝件模組構造 之製造方法，該些對稱點塗之黏稠狀膠體係包含有助銲• A second object of the present invention is to provide a method for manufacturing a multi-package module structure. A plurality of viscous colloidal systems are symmetrically coated on the periphery of each bonding region, for example, the viscous colloidal symmetrical points are coated as L. Shape, lumps " or straight bars, and the viscous glue system may not fill the gap between the chip-size packages and the substrate to save the consumption of the viscous glue: Another object is to provide a method for manufacturing a multi-package module structure. The symmetrical spot-coated viscous glue system includes soldering aid.
1239609 五、發明說明（3) h\ 以利在結合晶片尺寸封裝件之步驟中，避免冷銲點之 $成’並在回銲該些晶片尺寸封裝件之銲球同時固化該些 黏祠狀膠體’達到簡化製程步驟之功效，並且該基板不需 要預留點膠區’使得該些接合區距離該基板之上表面側邊 之最小寬度係可不大於1 · 〇min，以縮小基板之尺寸。 4t發明之另一目的係在於提供一種多封裝件模組構 7 ’ 一基板之上表面係包含有複數個接合區，以供結合複 個晶片尺寸封裝件，每一接合區之周緣點塗形成有複數 個黏稠狀膠體，該些黏稠狀膠體係可不填滿在該些晶片尺 寸封裝件與該基板之間而形成空隙，以低成本並固定該些 ，片尺寸封裝#，使得職板可供小尺寸之多封裝件模^ 配置。 、 一依本發明之多封裝件模組構造之製造方法，首先提供 一基板，該基板之上表面係包含有複數個接合區，每一接 有複數個連接塾，較佳地，可不預留點膠區而使 Γη妾二區距離該基板之上表面側邊之最小寬度係不大於 1. 0mm，接者，將複數個黏稠狀膠體對稱點塗於每一接合 緣’如將該些黏稍狀膠體對稱點塗成[形、團狀二 區，使得每一晶片尺寸封；於該些接合^ 接塾；最後，回銲該= ; =球連接對應之連1 一砰艰並固化该些黏稠狀膠體，該此 S稠該些晶片尺寸封裝件與該基板之 ‘ & M &二i 1 # r·封裝件與該基板之間形成有空隙， 故此低成本並有效地穩固該些晶片尺寸封裝件。 第8頁 1239609 五、發明說明（4) 【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 依據本發明之多封裝件模組構造之製造方法，第1 A至 1D圖係為一基板在製程中之截面示意圖，第2圖係為所提 供之基板之上表面示意圖，請參閱第1A及2圖，首先，提 供一基板11 0，該基板11 〇係為一種多層印刷電路板或陶瓷 電路板，其係具有一上表面lu及一對應之下表面112，該 上表面111係包含有複數個接合區11 3，每一接合區11 3係 設有複數個連接墊11 4，用以接合複數個晶片尺寸封裝件 140 (Chip Scale Package，CSP)(如第1D 圖所示），較佳 地，該基板1 1 0之上表面111係不需預留點膠區而使該些接零 合區11 3距離該基板11 〇之上表面丨丨1侧邊之最小寬度不大 於1 · 0mm，在本實施例中，該基板丨丨〇在該上表面11 1係可 結合有一覆晶晶片1 20或其它打線晶片，該覆晶晶片1 20係_ 可為繪圖處理晶片或其它晶片，該覆晶晶片1 20係具有一 -主動面121及一背面122，在該主動面121設有複數個凸塊 123、以覆晶接合至該基板丨1()之上表面丨“，較佳地，在 該覆晶晶片1 20之主動面121與該基板110之上表面1 11之間 填充有一底部填充材124。 接著，請參閱第1B圖，在結合該些晶片尺寸封裝件 $ 140之前，係將複數個黏稠狀膠體13 0對稱點塗於每一接合 區11 3之局部周緣，其中以形成在該接合區丨丨3之角隅為較 佳’但不局限該些黏稠狀膠體1 3 0之位置，該些黏網狀膠 體130係可以形狀、數量或用量擇一對稱方式點塗於在每1239609 V. Description of the invention (3) h \ In order to avoid the cost of cold solder joints in the step of combining chip-size packages, and to re-solder the solder balls of these chip-size packages while curing the sticky temples The colloid 'achieves the effect of simplifying the process steps, and the substrate does not need to reserve a dispensing area' so that the minimum width of the bonding areas from the upper surface side of the substrate may not be greater than 1.0 mm to reduce the size of the substrate. Another object of the 4t invention is to provide a multi-package module structure 7 '. The upper surface of a substrate includes a plurality of bonding areas for bonding a plurality of chip-size packages, and the peripheral edges of each bonding area are formed by dot coating. There are a plurality of viscous colloids. The viscous gel systems may not fill the gaps between the chip-size packages and the substrate, and fix them at a low cost. The chip-size package # makes the board available. Small package size configuration. 1. A method for manufacturing a multi-package module structure according to the present invention, firstly, a substrate is provided. The upper surface of the substrate includes a plurality of bonding areas, each of which is connected with a plurality of connection pads. Preferably, it may not be reserved. Dispense the region so that the minimum width of the two regions from the upper surface side of the substrate is not greater than 1.0 mm. Then, apply a plurality of viscous colloidal symmetrical points to each bonding edge. The slightly colloidal symmetrical points are coated in two areas of [shape and lump shape, so that each wafer size is sealed; the joints ^ are connected; finally, the solder joints are reconnected =; = the ball connection corresponds to 1 and it is hard to cure the These viscous colloids are thicker than the chip size package and the substrate, and a gap is formed between the package and the substrate, so the cost is effectively and stably fixed. Some chip-size packages. Page 8 1239609 V. Description of the invention (4) [Embodiment] Referring to the attached drawings, the present invention will enumerate the following embodiments. According to the manufacturing method of the multi-package module structure of the present invention, the first 1 to 1D diagrams are schematic cross-sectional views of a substrate in the manufacturing process, and the second diagram is a schematic diagram of the upper surface of the substrate provided, please refer to 1A and 1D. In FIG. 2, first, a substrate 110 is provided, which is a multilayer printed circuit board or a ceramic circuit board, which has an upper surface lu and a corresponding lower surface 112, and the upper surface 111 includes a plurality of Each bonding area 11 3 is provided with a plurality of connection pads 11 4 for bonding a plurality of chip scale packages (Chip Scale Packages, CSP) (as shown in FIG. 1D). Ground, the top surface 111 of the substrate 1 1 0 does not need to reserve the dispensing area, so that the junction area 11 3 is away from the top surface of the substrate 11 0. The minimum width of the side is not greater than 1.0 mm In this embodiment, the substrate 丨 丨 can be combined with a flip chip wafer 120 or other wire-bonded wafer on the upper surface 11 1. The flip chip wafer 1 20 can be a graphics processing wafer or other wafer. The flip-chip wafer 1 20 has an active surface 121 and a back surface 122. The surface 121 is provided with a plurality of bumps 123, which are bonded to the substrate with a flip chip 丨 1 (). Preferably, the active surface 121 of the flip-chip wafer 1 20 and the upper surface 1 of the substrate 110 11 is filled with an underfill material 124. Next, referring to FIG. 1B, before combining the chip size packages of $ 140, a plurality of viscous colloids 130 are symmetrically coated on each of the bonding areas 11 3 Local peripheries, in which the corners formed at the junction area 3 are preferred, but are not limited to the positions of the viscous colloids 130. The viscous colloids 130 can be selected in shape, quantity or amount Symmetrical way to paint on each
12396091239609
一接合區11 3之周緣且不相互連接，以作為該些晶片尺寸 封裝件1 40之角隅接合劑（corner bond)，請參閱第3圖， 在一具體點塗方式中，該些黏稠狀膠體丨3〇係為兩兩對稱 之L形地點塗在每一接合區丨丨3之周緣，或者是請參閱第4 圖，在另一具體點塗方式中，該些黏稠狀膠體丨3〇係以數 量或用量對稱方式點塗在每一接合區1 1 3之周緣，其點塗 圖案係為團狀或其它任意形狀，或者是請參閱第5圖，在 又一具體點塗方式中，該些黏稠狀膠體丨3〇係以例如對稱 直條狀方式點塗在每一接合區113之周緣，因此該些 狀膠體130係不需要全面覆蓋該些接合區113，較佳地，該 些黏稠狀膠體130係為一種無流動底膠材（n〇n —f 1〇w underfilling material)，其包含有熱固性樹脂及助銲 劑，此外，由於該些黏稠狀膠體13〇係預先點塗在該 \10之接=區113上，該基板11〇之周緣不需要預留點膠 二電二Ϊ T基板11 〇具有更小尺寸，以供裝設於各式可攜 之後，請參閱第1C圖，複數個晶片尺寸封裝件14〇The peripheral edge of a bonding area 11 3 is not connected to each other, and serves as a corner bond of the chip-size packages 1 40. Please refer to FIG. 3. In a specific spot coating method, the sticky The colloids 丨 30 are two symmetrical L-shaped spots painted on each of the joint areas 丨 丨 3 around the periphery, or refer to Figure 4, in another specific point coating method, these viscous colloids 丨 3 〇 The dots are symmetrically applied to the periphery of each bonding area 1 1 3 in a quantity or quantity manner, and the dot painting pattern is a ball shape or any other shape, or please refer to FIG. 5. In another specific spot coating method, The viscous colloids 30 are spot-coated on the periphery of each bonding region 113 in a symmetrical straight strip manner, so the colloidal gels 130 do not need to completely cover the bonding regions 113. Preferably, the The viscous colloid 130 is a non-flowing underfilling material (non-f 10w underfilling material), which contains a thermosetting resin and a flux. In addition, since the viscous colloid 13 is previously spot-coated on the \ 10 的 接 = Area 113, the periphery of the substrate 11 does not need to be prepared Dispensing after two electrical two Ϊ T square substrate 11 having smaller dimensions, for mounting to a variety of portable, see FIG. 1C, a plurality of chip size package 14〇
ϋ = ΐ接合區113 ’每一晶片尺寸封裝件“0係包含、 半導體Β曰片141，在該晶片141之主動面係形成有一封用 層142及複數個錫鉛銲球143，該封膠層142掸 - 141之保護與該些録球143之勃度，使得該半導曰體^片= 不需要將習知底部填充材填滿在該些晶片尺寸封裝件丨4〇 之ίί私在表面接合之過程，由於該些黏稠狀膠體130會 受”、、版動，以使該些晶片尺寸封裝件14〇之該些銲球143道ϋ = ΐJunction area 113 'Each wafer size package "0 contains, semiconductor B chip 141, an active layer 142 and a plurality of tin-lead solder balls 143 are formed on the active surface of the wafer 141, the sealing compound The protection of the layers 142 掸 -141 and the robustness of the recording balls 143 make the semiconducting body ^ film = it is not necessary to fill the conventional underfill material in the chip-size packages 丨 4〇 the private In the process of surface bonding, since the viscous colloids 130 will be affected, the 143 tracks of the solder balls of the chip size package 14 will be made.
回銲該些銲球143並固化該些黏稠狀膠體130，以製作一多 封裝件模組構造1 0 0，使得該些銲球1 43將更加穩固連接該 些連接墊11 4，且該些固化後黏稠狀膠體1 3 〇係黏著該些晶 之電性測試步驟，在回銲該些銲球丨43並固化該些黏稠狀 膠體130之前，先電性測試該多封裝件模組構造1〇()及該些 1239609 五、發明說明（6) 接對應之連接墊1 1 4以電性導通。最後，請參閱第i D圖， 片尺寸封裝件1 4 0之對稱側邊於該基板11 〇，即使再升高溫 度’該些固化後黏稠狀膠體1 30仍具有良好黏著性，以穩 固該些晶片尺寸封裝件1 40，不致傾斜或掉脫」且該些固 化後黏稠狀膠體1 3 0係可不填滿在該些晶片尺寸封裝件丨4 〇 與該基板110之間而形成空隙？1，故能低成本與有效地穩 固該些晶片尺寸封裝件14〇。而本發明可另包含有一具體 晶片尺寸封裝件140，若有不良之晶片尺寸封裝件14〇則能 在固化該些黏稠狀膠體丨3〇之前仍可被重工拔除。 因此，依據本發明之多封裝件模組構造之製造方法， 能夠在有限尺寸基板11 〇上高密度地結合複數個晶片尺寸 封裝件140以及至少一晶片12〇，而該些晶片尺寸封裝件 140係以該些由對稱點塗形成之黏稠狀膠體130加以固定， 在該些黏稠狀膠體130之固化過程中，由於該歧 細之用量係被預定在不足以填滿對應晶片忒 140與該基板110之間隙，因此即使該些黏稠狀膠體13〇在 未固化，有些微流動，而導致該些黏稠狀膠體13〇之形狀 產生些f變化，但該些黏稍狀膠體130仍不會相互連接， 以防止氣/包内包，此外在基板丨丨〇設計上不需要預留該基The solder balls 143 are re-soldered and the viscous colloids 130 are cured to make a multi-package module structure 100, so that the solder balls 143 will be more firmly connected to the connection pads 11 and After curing, the viscous colloid 130 is an electrical test step for sticking the crystals. Before re-soldering the solder balls 43 and curing the viscous colloid 130, the multi-package module structure 1 is electrically tested. 〇 () and these 1239609 V. Description of the invention (6) Connect the corresponding connection pads 1 1 4 to be electrically conductive. Finally, referring to FIG. ID, the symmetrical sides of the chip-size package 1 40 are on the substrate 11. Even if the temperature is increased, the viscous colloids 1 30 after curing still have good adhesion to stabilize the These chip-size packages 1 40 will not tilt or fall off "and the viscous colloids 130 after curing can not form a gap between the chip-size packages 410 and the substrate 110? 1. Therefore, these wafer-size packages 14 can be stabilized at low cost and effectively. The present invention may further include a specific wafer size package 140. If there is a defective wafer size package 140, it can be removed by rework before curing the viscous colloids 30. Therefore, according to the manufacturing method of the multi-package module structure of the present invention, a plurality of wafer-size packages 140 and at least one wafer 120 can be combined with high density on a limited-size substrate 110, and the wafer-size packages 140 The viscous colloids 130 formed by symmetrical point coating are used for fixing. During the curing process of the viscous colloids 130, the amount of the miscellaneous amount is predetermined to be insufficient to fill the corresponding wafers 140 and the substrate. The gap of 110, so even though the viscous colloids 13 are uncured and slightly flowing, which causes some changes in the shape of the viscous colloids 130, the viscous colloids 130 will not be connected to each other. In order to prevent the gas / inner package, in addition, the substrate does not need to be reserved in the design of the substrate.
第11頁 1239609_ 五、發明說明（7) 板11 0之點膠區，以得到具體可行之多封裝件模，組構，造 100 〇 本發明之保護範圍當視後附之申請專利範圍所界定者 為準，任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。Page 11 1239609_ V. Description of the invention (7) Dispensing area of board 110, to obtain concrete and feasible multi-package molds, structures, and build 100. The scope of protection of the present invention shall be defined by the scope of the attached patent application In case, any changes and modifications made by anyone skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention.
第12頁 1239609 圖式簡單說明 【圖式簡單說明】 第1A至ID® :依據本發明之多封裝件模組構造之製造方 法’一基板在製程中之截面示意圖； 第2圖·依據本發明之多封裝件模組構造之製造方 法’所提供之基板之上表面示意圖； 第3·圖·依據本發明之一實施例，對稱點塗有複數個 黏稠狀膠體之基板之上表面示意圖，· 第4 圖··依據本發明之另一實施例，對稱點塗有複數 個黏稠狀膠體之基板之上表面示意圖；及 第 5 圖：依據本發明之再一實施例，對稱點塗有複數 個黏稠狀膠體之基板之上表面示意圖。 元件符號簡單說明： 10 0多封裝件模組構造 112下表面 1 2 2背面 1 4 3銲球 11 0基板 111上表面 11 3接合區 114連接墊 120覆晶晶片 121主動面 1 2 3凸塊 1 2 4底部填充材 1 3 0 黏稠狀膠體 1 4 0晶片尺寸封裝4牛 141晶片 142封膠層 P1 空隙 第13頁Page 1239609 Brief description of the drawings [Simplified description of the drawings] Sections 1A to ID®: Manufacturing method of a multi-package module structure according to the present invention 'A cross-sectional view of a substrate in the manufacturing process; Figure 2 according to the present invention Schematic diagram of the upper surface of the substrate provided by the manufacturing method of the multi-package module structure; Figure 3 · Diagram · According to one embodiment of the present invention, a schematic diagram of the upper surface of a substrate coated with a plurality of viscous colloids symmetrically, Figure 4: A schematic diagram of the upper surface of a substrate coated with a plurality of viscous colloids at symmetrical points according to another embodiment of the present invention; and Figure 5: a plurality of symmetrical points coated at a symmetrical point according to another embodiment of the present invention Schematic diagram of the upper surface of a substrate with a viscous colloid. Simple explanation of component symbols: 10 0 multi-package module structure 112 lower surface 1 2 2 back surface 1 4 3 solder ball 11 0 substrate 111 upper surface 11 3 bonding area 114 connection pad 120 chip wafer 121 active surface 1 2 3 bump 1 2 4 Underfill material 1 3 0 Viscous colloid 1 4 0 Wafer size package 4 Cow 141 Wafer 142 Sealant layer P1 Gap Page 13
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW093107355A TWI239609B (en) | 2004-03-18 | 2004-03-18 | Method for manufacturing multi package module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW093107355A TWI239609B (en) | 2004-03-18 | 2004-03-18 | Method for manufacturing multi package module |
Publications (2)
| Publication Number | Publication Date |
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| TWI239609B true TWI239609B (en) | 2005-09-11 |
| TW200532867A TW200532867A (en) | 2005-10-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI452661B (en) * | 2007-01-30 | 2014-09-11 | Package structure with circuit directly connected to chip |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7608921B2 (en) * | 2006-12-07 | 2009-10-27 | Stats Chippac, Inc. | Multi-layer semiconductor package |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI452661B (en) * | 2007-01-30 | 2014-09-11 | Package structure with circuit directly connected to chip |
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| TW200532867A (en) | 2005-10-01 |
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