CN111433907A - 具有多层囊封剂的半导体装置及相关联***、装置与方法 - Google Patents
具有多层囊封剂的半导体装置及相关联***、装置与方法 Download PDFInfo
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Abstract
本发明提供一种半导体装置,所述半导体装置包含:衬底,其包含迹线,其中所述迹线突出在所述衬底的顶表面上方;预填充材料,其在所述衬底上方且在所述迹线之间,其中所述预填充材料直接接触所述迹线的***表面;裸片,其经附接在所述衬底上方;及晶片级底部填充物,其在所述预填充材料与所述裸片之间。
Description
技术领域
本技术涉及半导体装置囊封剂,例如接触金属迹线的底部填充物。
背景技术
半导体装置裸片,其包含存储器芯片、微处理器芯片及成像器芯片,通常包含安装在衬底上且包装在塑料保护罩中的半导体裸片。所述裸片包含例如存储器单元、处理器电路及成像器装置的功能特征,以及电连接到功能特征的接合焊盘。接合焊盘可电连接到保护罩外部的端子以将裸片连接到更高级电路。
形成半导体装置可包含形成衬底102,其中迹线104经暴露在衬底102上。如图1中所说明,可基于移除焊料掩模开口区域中的焊料掩模106来暴露迹线104,由此也暴露衬底顶部的顶表面及迹线104的***表面。
如图1中进一步说明,单独组装结构可经对准且经附接到衬底102及迹线104,所述单独组装结构包含具有支柱112的裸片110以及囊封支柱112及裸片110上的表面的晶片级底部填充物130。附接工艺可包含使晶片级底部填充物130重整或回流(举例来说,例如通过控制其温度以改变其粘度水平),晶片级底部填充物130如图1中所说明那样向下行进以填充裸片110与衬底102之间的空间。
如图2中进一步说明,所得半导体装置202(例如,在使晶片级底部填充物130回流且固化晶片级底部填充物130以形成囊封剂之后)可包含填充裸片110与衬底102之间的空间的晶片级底部填充物130。晶片级底部填充物130可进一步囊封迹线104。然而,由于各种因素(例如,晶片级底部填充物130的粘度水平、陷留空气/气体、晶片级底部填充物130的不均匀流动、所述迹线之间的空间),因此回流工艺可能直接邻近于一些迹线104留下空隙204(例如,其中迹线104的部分未能直接接触晶片级底部填充物130)。迹线104之间的空隙204可能致使迹线104之间的短接及泄漏,从而致使半导体装置202的电故障。
附图说明
图1是根据现存技术的在制造方法中的选定阶段的半导体装置的横截面图。
图2是根据现存技术配置的半导体装置的横截面图。
图3是根据本技术的实施例配置的半导体装置的横截面图。
图4到7是说明根据本技术的实施例的在制造方法中的选定阶段的半导体装置的横截面图。
图8到11是说明根据本技术的实施例的在进一步制造方法中的选定阶段的半导体装置的横截面图。
图12到14是说明根据本技术的实施例的在进一步制造方法中的选定阶段的半导体装置的横截面图。
图15是说明根据本技术的实施例的制造半导体装置的实例方法的流程图。
图16是说明根据本技术的实施例的并入半导体装置的***的框图。
具体实施方式
本文中所揭示的技术涉及半导体装置、具有半导体装置的***及用于制造半导体装置的相关方法。术语“半导体装置”通常是指包含一或多种半导体材料的固态装置。半导体装置的实例包含逻辑装置、存储器装置及二极管等等。此外,术语“半导体装置”可指成品装置或指在变为成品装置之前的各个处理阶段的组合件或其它结构。取决于使用半导体装置的上下文,术语“衬底”可指支撑电子组件(例如,裸片)的结构(例如晶片级衬底)或指单片化、晶片级衬底,或用于裸片堆叠应用的另一裸片。所属领域的一般技术人员将认识到,本文中所描述的方法的合适步骤可以晶片级或以裸片级执行。此外,除非上下文另有指示,否则可使用常规半导体制造技术来形成本文中所揭示的结构。可例如使用化学气相沉积、物理气相沉积、原子层沉积、旋涂、镀覆及/或其它合适技术来沉积材料。类似地,可例如使用等离子体蚀刻、湿法蚀刻、化学机械平坦化或其它合适技术来移除材料。
下文在囊封半导体装置或其部分的上下文中描述本技术的许多实施例,例如用于晶片级底部填充物。在制造半导体装置(例如,硅通孔(TSV)裸片封装)时,可将裸片结构(例如,包含具有晶片级底部填充物的TSV裸片,所述晶片级底部填充物囊封TSV裸片的部分及其上的金属支柱)附接到衬底(例如,裸片堆叠应用中的另一裸片、印刷电路板、裸片级或晶片级衬底等)。在附接工艺之前(例如,包含使用焊料连接金属支柱与衬底上的迹线及使晶片级底部填充物回流或重整),可将预填充材料(例如,具有低于晶片级底部填充物的粘度水平的非导电材料,例如非导电液体囊封剂或非导电膏(NCP))形成为(举例来说,例如通过沉积工艺、喷射工艺、施配工艺、移除工艺等)直接接触衬底的部分及迹线的***侧。因而,预填充材料可在附接工艺期间直接接触且附接到晶片级底部填充物,其中组合材料填充裸片与衬底之间的空间。通过在附接工艺之前在衬底上形成预填充材料,制造工艺可减少陷留空隙(例如,迹线的部分及/或不与晶片级底部填充物直接接触的衬底)在金属迹线之间的形成且增加半导体装置的可靠性。
如本文中所使用,鉴于图中所展示的定向,术语“垂直”、“横向”、“上”及“下”可指半导体裸片组合件中的特征的相对方向或位置。例如,“上”或“最上”可指比另一特征更靠近页面顶部定位的特征。然而,这些术语应广义地被解释为包含具有其它定向的半导体装置,例如倒置或倾斜定向,其中可取决于所述定向互换顶部/底部、上面/下面、上方/下方、上/下及左/右。
图3是根据本技术的实施例的半导体装置300的横截面图。半导体装置300(例如,半导体裸片组合件,包含TSV裸片封装)包含其上具有金属或导电迹线304(“迹线304”)的衬底302,及安装到衬底302的半导体裸片310(“裸片310”)。
半导体裸片310上的导电或金属支柱312(“支柱312”)可通过焊料316连接到迹线304以在裸片310与衬底302之间提供电连接件。已至少部分地移除在衬底302上可定位焊料掩模306(例如,阻焊层或涂层)的电连接件以形成掩模开口区域308且从焊料掩模304暴露迹线304的顶表面326(“迹线顶表面326”)。例如,焊料掩模306可具有的掩模开口区域308外部的部分的外部高度大于掩模开口区域308内部的部分的内部高度,其中内部高度等于或小于迹线324的高度。而且例如,焊料掩模306可在掩模开口区域308中完全移除且暴露衬底302的顶表面322(“衬底顶表面322”)及迹线304的***表面324(“迹线***表面324”)。
半导体装置300进一步包含裸片310与衬底302之间的空间中的晶片级底部填充物330(举例来说,例如在晶片级工艺期间施加到裸片310的电绝缘囊封剂或粘合剂材料)及预填充材料332(例如,在处理步骤(例如在特定温度下或基于不同固化剂)具有低于晶片级底部填充物的粘度水平的电绝缘材料,例如非导电液体囊封剂或非导电膏(NCP))。如图3中所说明,晶片级底部填充物330可在预填充材料332上方,其中晶片级底部填充物330直接接触支柱312,且预填充材料332可直接接触迹线304(举例来说,例如在迹线***表面324上)。此外,晶片级底部填充物330可直接接触裸片310的底表面,且预填充材料332可直接接触衬底顶表面322。而且,晶片级底部填充物330可直接接触预填充材料332,例如其中底部填充物底表面334直接接触预填充物顶表面336。
在制造半导体装置300时,可在将中间结构(例如,包含裸片310、支柱312、焊料316(例如,焊料凸块)及晶片级底部填充物330)附接到包含迹线304的衬底302之前将预填充材料332形成或施加在衬底顶表面322上。例如,在附接工艺之前,可在掩模开口区域308中的迹线304之间喷射或施配非导电液体囊封剂或NCP(例如,使用高精度工艺来控制预填充材料332的位置及/或体积)。可直接在衬底顶表面322、残留在掩模开口区域308中的焊料掩模306、迹线***表面324或其组合上喷射或施配非导电液体囊封剂或NCP。在一些实施例中,预填充材料332可包含或直接接触未从掩模开口区域308完全移除的焊料掩模306。
在制造工艺期间,可根据预填充材料332的组合物或特性来施加不同量或体积的预填充材料332。因而,预填充物顶表面336及底部填充物底表面334可与迹线顶表面326共面,在其上方或下方。
迹线304之间的预填充材料332为半导体装置300提供增大的可靠性。预填充材料332可减少在制造工艺期间晶片级底部填充物330向下流动。此外,由于预填充材料332具有低于晶片级底部填充物330的粘度水平,因此预填充材料332可减少在金属迹线之间形成陷留空隙(例如,基于留下从焊料掩模306及晶片级底部填充物330两者暴露的迹线***表面324的部分、衬底顶表面322的部分或其组合)。因此,可基于减少陷留空隙来降低半导体装置300的故障率。
图4到7是说明根据本技术的实施例的在制造方法中的一系列选定步骤的的半导体装置的横截面图。如图4中所说明,所述方法可包含提供衬底302,例如印刷电路板(PCB)、层压材料或陶瓷材料。衬底302可包含突出在衬底顶表面322上方的迹线304。可移除焊料掩模306以形成掩模开口区域308,由此暴露迹线***表面324、迹线顶表面326、衬底顶表面322、其部分或其组合。
如图5中所说明,所述方法可包含用于在衬底302上方形成图3的预填充材料332的阶段。例如,所述方法可包含在迹线304之间喷射预填充材料332(例如,非导电液体囊封剂502(例如,环氧树脂、粘合剂等))。所述方法可包含直接在图4的衬底顶表面322、残留在图3的掩模开口区域308中的图3的焊料掩模306或其组合上施加非导电液体囊封剂502。所述方法可包含直接接触图3的迹线***表面324或其部分而施加非导电液体囊封剂502。
所述方法可包含控制非导电液体囊封剂502的施加位置、非导电液体囊封剂502在施加位置处的体积或其组合的高精度喷射工艺(例如,使用具有满足阈值的一定水平的流量测量/控制、一定水平或粒度的施加器位置控制或其组合的施加器)。高精度喷射工艺可经配置以使非导电液体囊封剂502远离迹线顶表面326,使得迹线顶表面326不受非导电液体囊封剂502污染。例如,高精度喷射工艺可在迹线304之间的施加位置处喷射非导电液体囊封剂502,其中预填充物顶表面336与迹线顶表面326共面或在其下方。
在一些实施例中,用于形成预填充材料332的阶段可包含在下一制造阶段之前(例如,附接包含图3的裸片310、图3的晶片级底部填充物330或其组合的结构)至少部分地固化(例如,基于曝光、化学试剂、温度变化、工艺延迟或其组合)非导电液体囊封剂502。在一些实施例中,用于形成预填充材料332的阶段可没有固化工艺。在用于形成预填充材料332的阶段与下一制造阶段之间,非导电液体囊封剂502的粘度水平可保持相同。
如图6中所说明,所述方法可包含用于对准临时结构602与衬底302的阶段。临时结构602可包含裸片310、支柱312、焊料316、晶片级底部填充物330或其组合。例如,临时结构602可包含远离裸片310的底表面延伸(例如,在图6中所展示那样向下)的支柱312。焊料316可在与裸片310相对的部分或表面处附接到支柱312或镀覆在支柱312上。晶片级底部填充物330可直接接触裸片310的底表面且囊封支柱312、焊料316、其部分或其组合。
临时结构602可包含在制造工艺(例如,晶片级制造)中的单独步骤或阶段组装的结构。例如,单独步骤或阶段可包含在晶片上形成集成电路(IC),在电连接到IC的晶片表面上形成支柱312,在支柱312上形成焊料凸块,施加晶片级底部填充物330,切割晶片以形成裸片或其组合以组装临时结构602。
对准阶段可包含在衬底302上方对准临时结构602。例如,所述方法可包含对准迹线304及支柱的特定部分的参考部分(例如,中心部分或***边缘或表面)以沿着垂直平面共面或沿着垂直线入射。而且例如,所述方法可包含对准临时结构602及衬底302使得焊料316直接接触迹线304。
如图7中所说明,所述方法可包含用于囊封图3的半导体装置300的支柱312及/或迹线304的阶段。例如,所述方法可包含使晶片级底部填充物330及/或焊料316回流。晶片级底部填充物330及/或焊料316可基于控制其粘度水平(例如通过控制温度(例如,升高温度),施加化学试剂、控制处理持续时间(例如,时间阈值之前的处理)或其组合)而回流或重整。晶片级底部填充物330可经回流以直接接触非导电液体囊封剂502(例如,其中图3的底部填充物底表面334直接接触图3的预填充物顶表面336),使得晶片级底部填充物330及非导电液体囊封剂502的组合填充裸片310的底表面与图4的衬底顶表面322之间的空间或间隔。焊料316可经回流以直接接触支柱312及迹线304,由此在裸片310与迹线304之间形成电连接件。
而且例如,所述方法可包含固化晶片级底部填充物330及/或非导电液体囊封剂502,使焊料316凝固或其组合。固化晶片级底部填充物330及/或非导电液体囊封剂502,使焊料316凝固或其组合可包含控制温度(例如,升高温度),施加光,施加化学试剂,控制处理持续时间(例如,等到时间阈值之后)或其组合。
在制造图3的半导体装置300时,在一或多个制造条件下(例如,在特定温度下,在施加固化剂之前或其组合,例如对于图5中所说明的形成阶段或图7中所说明的回流阶段),非导电液体囊封剂502可对应于小于100Pa-s(例如,在0.01Pa-S与50.0Pa-S之间)的粘度水平。对于所述方法,在一或多个制造条件下(举例来说,例如对于图6中所说明的对准阶段或图7中所说明的回流阶段)非导电液体囊封剂502的粘度水平可低于晶片级底部填充物330的粘度水平。因此,在附接图6的临时结构602之前在迹线304之间施加的非导电液体囊封剂502为半导体装置300提供增加的可靠性。与用晶片级底部填充物330填充迹线304之间的空间相比,非导电液体囊封剂502的较低粘度水平减少在迹线304之间形成陷留空隙。可基于减少陷留空隙来降低半导体装置300的故障率。
图8到11是说明根据本技术的实施例的在进一步制造方法中的一系列选定阶段的半导体装置的横截面图。如图8中所说明,所述方法可包含提供衬底,这与图4中所说明的方法的对应阶段类似。
如图9中所说明,所述方法可包含用于在衬底302上方形成图3的预填充材料332的阶段。例如,所述方法可包含在迹线304之间喷射或施配预填充材料332(例如,在一或多个制造条件下具有助熔功能及粘度水平的NCP 902)。所述方法可包含直接在图4的衬底顶表面322、残留在图3的掩模开口区域308中的图3的焊料掩模306或其组合上施加NCP 902。所述方法可包含直接接触图3的迹线***表面324或其部分而施加NCP 902。
所述方法可包含控制NCP 902的施加位置、NCP 902在施加位置处的体积或其组合的施加工艺(例如,使用具有满足阈值的一定水平的流量测量/控制、一定水平或粒度的施加器位置控制或其组合的施加器)。与高精度喷射工艺相比,所述方法的施加工艺可粒度较小或不太受控。例如,施加工艺可在迹线304之间的施加位置处施加NCP 902,其中预填充物顶表面336与迹线顶表面326共面,在其上方或下方。作为更特定实例,施加工艺可施加NCP902使得迹线顶表面326或其部分被NCP 902覆盖。
在一些实施例中,用于形成预填充材料332的阶段可包含在下一制造阶段之前(例如,附接包含图3的裸片310、图3的晶片级底部填充物330或其组合的结构)部分地固化(例如,基于曝光、化学试剂、温度变化、工艺延迟或其组合)NCP 902。在一些实施例中,用于形成预填充材料332的阶段可没有固化工艺。在用于形成预填充材料332的阶段与下一制造阶段之间,NCP 902的粘度水平可保持相同。在一些实施例中,用于形成预填充材料332的阶段可包含施加NCP 902使得预填充物顶表面336在迹线顶表面326下方且在下一制造阶段之前进一步完全固化NCP 902。
如图10中所说明,所述方法可包含用于对准临时结构602与衬底302的阶段。对准阶段可与图6中所说明的方法的对准阶段类似(例如,沿着垂直线或平面对准支柱312、焊料316及迹线304的部分)。
所述方法可进一步包含对准中间结构602使得焊料316直接接触迹线顶表面326。例如,可移动中间结构602、衬底302或其组合使得裸片310的底表面与衬底顶表面322之间的距离减小,直到焊料316直接接触迹线顶表面326为止。可通过焊料316从迹线顶表面326移除或推出在对准之前迹线顶表面326上(例如,在迹线顶表面326与焊料316之间)的任何NCP(例如,在没有完全固化的情况下形成的NCP)。随着焊料316移动得更靠近迹线顶表面326,NCP 902可基于NCP 902的助焊功能从迹线顶表面326移位。
如图11中所说明,所述方法可包含用于囊封图3的半导体装置300的迹线304及/或支柱312的阶段。例如,所述方法可包含使焊料316及/或晶片级底部填充物330回流,这与图7中所说明的阶段类似。晶片级底部填充物330可经回流以直接接触NCP 902(例如,其中图3的底部填充物底表面334直接接触图3的预填充物顶表面336),使得晶片级底部填充物330及NCP 902的组合填充裸片310的底表面与图4的衬底顶表面322之间的空间或间隔。而且例如,所述方法可包含使晶片级底部填充物330、焊料316、NCP 902或其组合凝固,这与图7中所说明的阶段类似。
在制造图3的半导体装置300时,在一或多个制造条件下(例如,在特定温度下,在施加固化剂之前或其组合,例如对于图9中所说明的形成阶段或图11中所说明的回流阶段),NCP 902可对应于小于100Pa-s(例如,在0.01Pa-S与50.0Pa-S之间)的粘度水平。对于所述方法,在一或多个制造条件下(举例来说,例如对于图10中所说明的对准阶段或图11中所说明的回流阶段),NCP 902的粘度水平可低于晶片级底部填充物330的粘度水平。因此,在附接图6的临时结构602之前在迹线304之间施加的NCP 902为半导体装置300提供增加的可靠性。与用晶片级底部填充物330填充迹线304之间的空间相比,NCP 902的较低粘度水平减少在迹线304之间形成陷留空隙。可基于减少陷留空隙来降低半导体装置300的故障率。
图12到14是说明根据本技术的实施例的在进一步制造方法中的一系列选定阶段的半导体装置的横截面图。如图12中所说明,所述方法可包含提供衬底302,这与如图4中所说明的方法中的对应阶段或如图8中所说明的方法类似。对于所述方法,可部分地移除(例如,基于反应性离子蚀刻或其它各向异性移除、湿法蚀刻或其它各向同性移除等)焊料掩模306以形成图3的掩模开口区域308,由此暴露迹线***表面324的部分、迹线顶表面326或其组合。例如,图3的预填充材料332可包含迹线304之间的焊料掩模306,其中迹线304之间的预填充物顶表面336与迹线顶表面326共面或在其下方。
如图13中所说明,所述方法可包含用于对准临时结构602与衬底302的阶段。对准阶段可与如图6中所说明的方法的对应阶段或如图10中所说明的方法的对应阶段类似。
如图14中所说明,所述方法可包含用于囊封图3的半导体装置300的图3的支柱312及/或图3的迹线304的阶段。例如,所述方法可包含使焊料316及晶片级底部填充物330回流,这与图7或图11中所说明的阶段类似。晶片级底部填充物330可直接接触焊料掩模306。
在一些实施例中,所述方法可包含用于使用图5的焊料掩模306及非导电液体囊封剂502或图9的NCP 902来形成图3的预填充材料332的阶段。例如,所述方法可包含部分地移除焊料掩模306使得迹线304之间的焊料掩模306的顶表面在图3的迹线顶表面326下方。所述方法可进一步包含直接在焊料掩模306的顶表面上且在迹线之间形成非导电液体囊封剂502或NCP 902。形成阶段可与图5或图9中所说明的对应阶段类似。
图15是说明根据本技术的实施例的制造半导体装置的实例方法1500(“方法1500”)的流程图。例如,方法1500可用于制造图3的半导体装置300。同样例如,方法1500可包含图4到14中所说明的阶段。
方法1500可包含提供衬底(例如,图3的衬底302),如框1502处所说明。所提供衬底302可包含从图3的衬底顶表面322突出的图3的迹线304。例如,提供步骤可对应于图4、8或12中所说明的阶段。
提供衬底可包含基于至少部分地移除图3的焊料掩模306来形成开口区域(例如,掩模开口区域308),如框1504中所说明。例如,可在被指定为掩模开口区域308的位置中移除(例如,基于反应性离子蚀刻或其它各向异性移除、湿法蚀刻或其它各向同性移除等)焊料掩模306,使得剩余焊料掩模306具有与图3的迹线顶表面326共面或在其下方的顶表面(例如,迹线304之间的焊料掩模306的顶表面)。在一些实施例中,可完全移除焊料掩模306,由此在掩模开口区域308中暴露衬底顶表面322。
方法1500可进一步包含形成预填充材料(例如,预填充材料332,例如图5的非导电液体囊封剂502、图9的NCP 902、剩余焊料掩模306或组合),如框1506中所说明。可在衬底302上方且在迹线304之间形成预填充材料332。预填充材料332可直接接触图3的迹线***表面324。形成预填充材料可对应于图5、9、12中所说明的阶段或其组合。
在一些实施例中,形成预填充材料332可包含施加非导电液体囊封剂502,如框1510中所说明。对应于图5,可在掩模开口区域308中直接接触焊料掩模306、衬底顶表面322、迹线***表面324或其组合而施加非导电液体囊封剂502。可使用喷射工艺(例如高精度喷射工艺)来施加非导电液体囊封剂502,所述喷射工艺控制喷射非导电液体囊封剂502的位置、非导电液体囊封剂502在所述位置处的体积或其组合。高精度喷射工艺可具有一定水平的控制或粒度,使得在施加工艺期间(例如,基于控制位置及体积)使非导电液体囊封剂502远离迹线顶表面326。此外,对应于非导电液体囊封剂502的图3的预填充物顶表面336可与迹线顶表面326共面或在其下方。
在一些实施例中,形成预填充材料332可包含施加NCP 902,如框1510中所说明。对应于图5,可在掩模开口区域308中施加(例如,使用喷射工艺或施配工艺)直接接触焊料掩模306、衬底顶表面322、迹线***表面324或其组合的NCP 902。可基于其助焊功能来施加NCP 902,而无需考虑使迹线顶表面326远离NCP 902。例如,可施加NCP 902使得一些材料最终直接接触迹线顶表面326中的一或多者的至少部分。同样例如,可施加NCP 902使得对应于NCP 902的预填充物顶表面336与迹线顶表面326共面或在其上方。
在一些实施例中,形成预填充材料332可包含部分地或完全固化(例如,基于化学试剂、暴露于光、时间延迟或其组合)预填充材料332(例如,非导电液体囊封剂502及/或NCP902),如框1512中所说明。在一些实施例中,可在没有固化工艺的情况下形成预填充材料332。
方法1500可进一步包含将临时结构(例如,图6的临时结构602)附接到衬底302及迹线304,如框1514中所说明。可在单独或先前阶段组装临时结构602,如框1550中所说明。例如,如框1552中所说明,组装临时结构602可包含提供图3的裸片310,其中图3的支柱312从裸片310的底表面延伸或突出。如框1554中所说明,组装阶段可进一步包含在支柱312上与裸片310相对的部分处形成焊料凸块(例如,图3的焊料316)。如框1556中所说明,组装阶段可包含将图3的晶片级底部填充物330层压在裸片310的底表面上,使得晶片级底部填充物330直接接触且囊封所述底表面及支柱312。组装临时结构602可进一步包含从晶片结构切割或单片化(未展示)裸片310。
附接临时结构602(例如,起因于组装阶段1550的结构)可包含对准所述结构,如框1516中所说明。对准工艺可对应于图6、10或13中所说明的阶段。例如,对应工艺可对准使得支柱312及迹线304的对应部分沿着对应垂直线重合。而且例如,对准工艺可对准使得焊料316直接接触迹线顶表面326。在一些实施例中,随着焊料316更靠近迹线顶表面326或随着焊料316在后续回流阶段期间水平地扩散,可基于NCP 902的助熔功能从迹线顶表面326移除或推出迹线顶表面326上的NCP 902。
附接临时结构602可进一步包含使晶片级底部填充物330及/或焊料316回流,如框1518中所说明。回流工艺可对应于图7、11或14中所说明的阶段。回流工艺可包含控制温度,施加或移除化学试剂或暴露于光,相对于阈值持续时间控制处理时间等。在晶片级底部填充物330位于预填充材料332上方且焊料316位于迹线顶表面326上方的情况下,回流工艺可使晶片级底部填充物330直接接触预填充材料332(例如,使得底部填充物底表面334与预填充物顶表面336共面)且使焊料316直接接触并覆盖迹线顶表面326的对应部分。
附接工艺可在固化预填充材料332之后进行。在一些实施例中(举例来说,例如在形成预填材料332排除固化工艺的情况下),附接工艺可在不固化预填充材料332的情况下发生。
方法1500可进一步包含固化囊封剂,如框1520中所说明。固化工艺可基于施加化学试剂,将结构暴露于特定光,控制温度,等待阈值时间量或其组合。固化工艺可固化晶片级底部填充物330、预填充材料332或其组合。
图16是说明根据本技术的实施例的并入半导体装置的***的框图。具有上文参考图1到15所描述的特征的半导体装置中的任一者可经并入到无数的更大及/或更复杂***中的任一者中,所述***的代表性实例是图16中示意性展示的***1690。***1690可包含处理器1692、存储器1694(例如,SRAM、DRAM、快闪存储器及/或其它存储器装置)、输入/输出装置1696及/或其它子***或组件1698。上文参考图1到15所描述的半导体组合件、装置及装置封装可包含在图16中所展示的元件中的任一者中。所得***1690可经配置以执行各种各样的合适计算、处理、存储、感测、成像及/或其它功能中的任一者。因此,***1690的代表性实例包含但不限于计算机及/或其它数据处理器,例如台式计算机、膝上型计算机、因特网器具、手持装置(例如,掌上计算机、可穿戴计算机、蜂窝或移动电话、个人数字助理、音乐播放器等)、平板计算机、多处理器***、基于处理器的或可编程的消费类电子产品、网络计算机及迷你计算机。***1690的额外代表性实例包含灯、相机、车辆等。关于这些及其它实例,***1690可例如通过通信网络容纳在单个单元中或分布在多个互连单元上。***1690的组件可对应地包含本地及/或远程存储器存储装置及各种各样的合适计算机可读媒体中的任一者。
根据前述内容,将明白,出于说明目的已在本文中描述本技术的特定实施例,但是可在不脱离本发明的情况下进行各种修改。另外,可在其它实施例中组合或消除特定实施例的上下文中所描述的本发明的某些方面。此外,虽然已在那些实施例的上下文中描述与某些实施例相关联的优点,但是其它实施例也可展现此类优点。并非所有实施例必定展现此类优点落入本发明的范围内。因此,本发明及相关联技术可涵盖本文中未明确展示或描述的其它实施例。
Claims (27)
1.一种半导体装置,其包括:
衬底,其包含迹线,其中所述迹线突出在所述衬底的顶表面上方;
预填充材料,其在所述衬底上方且在所述迹线之间,其中所述预填充材料直接接触所述迹线的***表面;
裸片,其经附接在所述衬底上方;及
晶片级底部填充物,其在所述预填充材料与所述裸片之间。
2.根据权利要求1所述的半导体装置,其中在一定制造条件下所述预填充材料对应于第一粘度水平,其中在所述制造条件下所述第一粘度水平低于所述晶片级底部填充物的第二粘度水平。
3.根据权利要求2所述的半导体装置,其中所述预填充材料包含非导电膏NCP。
4.根据权利要求3所述的半导体装置,其中所述NCP包含助熔功能或特性。
5.根据权利要求3所述的半导体装置,其中所述NCP具有与所述迹线的一或多个顶表面共面或在其上方的顶表面。
6.根据权利要求2所述的半导体装置,其中所述预填充材料包含非导电液体囊封剂。
7.根据权利要求6所述的半导体装置,其中所述非导电液体囊封剂具有与所述迹线的一或多个顶表面共面或在其下方的顶表面。
8.根据权利要求2所述的半导体装置,其中所述预填充材料包含焊料掩模,所述焊料掩模的顶表面与所述迹线的一或多个顶表面共面或在其下方。
9.根据权利要求1所述的半导体装置,其中所述预填充材料直接接触所述晶片级底部填充物。
10.根据权利要求1所述的半导体装置,其中:
所述预填充材料直接接触所述衬底的所述顶表面;
所述裸片包含底表面及从所述裸片突出的支柱,其中所述支柱电耦合到所述迹线;且
所述晶片级底部填充物直接接触所述裸片的所述底表面及所述支柱。
11.一种制造半导体装置的方法,其包括:
提供包含迹线的衬底,其中所述迹线突出在所述衬底的顶表面上方;
在所述衬底上方且在所述迹线之间形成预填充材料,其中所述预填充材料直接接触所述迹线的***表面;及
在所述预填充材料上方将临时结构附接到所述衬底,其中所述临时结构包含裸片及在所述裸片与所述预填充材料之间的晶片级底部填充物。
12.根据权利要求11所述的方法,其中形成所述预填充材料包含在所述迹线之间施加非导电膏NCP。
13.根据权利要求12所述的方法,其中施加所述NCP包含施加包含助熔功能或特性的所述NCP。
14.根据权利要求12所述的方法,其中施加所述NCP包含施加所述NCP使得所述NCP的顶表面与所述迹线的顶表面共面或在其上方。
15.根据权利要求12所述的方法,其中:
施加所述NCP包含直接接触所述迹线的一或多个顶表面的至少部分而施加所述NCP;
附接所述临时结构包含基于与所述NCP相关联的助熔功能来从所述迹线的一或多个顶表面的至少部分移除所述NCP。
16.根据权利要求12所述的方法,其中附接所述临时结构包含在不固化所述NCP的情况下附接所述临时结构。
17.根据权利要求12所述的方法,其进一步包括在附接所述临时结构之前至少部分地固化所述NCP。
18.根据权利要求11所述的方法,其中形成所述预填充材料包含在所述迹线之间喷射非导电液体囊封剂。
19.根据权利要求18所述的方法,其中喷射所述非导电液体囊封剂包含使用高精度喷射工艺来控制喷射所述非导电液体囊封剂的位置、所述非导电液体囊封剂在所述位置处的体积或其组合。
20.根据权利要求19所述的方法,其中喷射所述非导电液体囊封剂包含使所述非导电液体囊封剂远离所述迹线的顶表面。
21.根据权利要求18所述的方法,其中喷射所述非导电液体囊封剂包含喷射所述非导电液体囊封剂使得所述非导电液体囊封剂的顶表面与所述迹线中的一或多者的顶表面共面或在其下方。
22.根据权利要求18所述的方法,其进一步包括在附接所述临时结构之前至少部分地固化所述非导电液体囊封剂。
23.根据权利要求18所述的方法,其中附接所述临时结构包含在不固化所述非导电液体囊封剂的情况下附接所述临时结构。
24.根据权利要求18所述的方法,其进一步包括从所述迹线之间至少部分地移除焊料掩模。
25.根据权利要求24所述的方法,其中所述迹线之间的所述焊料掩模与所述迹线中的一或多者的顶表面共面或在其下方。
26.根据权利要求11所述的方法,其进一步包括组装所述临时结构,包含:
提供包含支柱的所述裸片,所述支柱从所述裸片的底表面延伸;
在与所述裸片相对的所述支柱上形成焊料凸块;及
层压直接接触所述底表面及所述支柱的所述晶片级底部填充物。
27.根据权利要求26所述的方法,其中附接所述临时结构包含使所述焊料凸块及所述晶片级底部填充物回流,其中所述焊料凸块直接接触所述迹线及所述支柱,且所述晶片级底部填充物直接接触所述预填充材料。
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WO2019099070A1 (en) | 2019-05-23 |
US20190311918A1 (en) | 2019-10-10 |
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US20210257226A1 (en) | 2021-08-19 |
US10763131B2 (en) | 2020-09-01 |
CN111433907B (zh) | 2024-01-09 |
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US20190157111A1 (en) | 2019-05-23 |
TW201923985A (zh) | 2019-06-16 |
US11955346B2 (en) | 2024-04-09 |
US20190157112A1 (en) | 2019-05-23 |
US11004697B2 (en) | 2021-05-11 |
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