WO2023173595A1 - 稳压器及其控制方法 - Google Patents
稳压器及其控制方法 Download PDFInfo
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- WO2023173595A1 WO2023173595A1 PCT/CN2022/096425 CN2022096425W WO2023173595A1 WO 2023173595 A1 WO2023173595 A1 WO 2023173595A1 CN 2022096425 W CN2022096425 W CN 2022096425W WO 2023173595 A1 WO2023173595 A1 WO 2023173595A1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a voltage regulator and a control method thereof.
- the voltage stabilizer is a power supply circuit or power supply equipment that can automatically adjust the output voltage. Its function is to stabilize the power supply voltage that fluctuates greatly and does not meet the requirements of electrical equipment within its set value range, so that various circuits can Or the electrical equipment can work normally under the rated working voltage.
- the voltage regulator needs to have a faster response speed.
- Embodiments of the present disclosure provide a voltage regulator and a control method thereof, which are at least conducive to accelerating the startup of the voltage regulator.
- an embodiment of the present disclosure provides a voltage regulator, including: a comparison module configured to compare a reference voltage and a feedback voltage and generate an error voltage based on the comparison; an output voltage adjustment module, and the The output terminal of the comparison module is coupled to the first node and is configured to adjust the input voltage received by the output voltage adjustment module based on the error voltage to provide an output voltage to the output node; a feedback circuit is coupled to the between the output node and the ground voltage, the feedback circuit is configured to divide the output voltage to provide the feedback voltage; a driving voltage adjustment module coupled to the first node for stabilizing The potential at the first node is adjusted during the startup phase of the voltage regulator operation.
- the driving voltage adjustment module is configured to reduce time-consuming adjustment of the input voltage received by the output voltage adjustment module.
- the driving voltage adjustment module includes: a start unit coupled to a control terminal of the output voltage adjustment module, the start unit stops adjusting the potential of the first node to start based on a start signal.
- the voltage regulator an adjustment unit, coupled with the control end of the output voltage adjustment module, the adjustment unit adjusts the potential of the first node based on the adjustment signal to accelerate the startup of the voltage regulator.
- the output voltage adjustment module includes a first PMOS transistor, a control end of the first PMOS transistor is coupled to the first node, and a first end of the first PMOS transistor is coupled to the working power supply. The second end of the first PMOS transistor is coupled to the output node.
- the startup unit includes a second PMOS transistor
- the adjustment unit includes a second NMOS transistor
- the control end of the second PMOS transistor receives the startup signal
- the third PMOS transistor of the second PMOS transistor receives the startup signal.
- One end is coupled to the working power supply
- the second end of the second PMOS tube is coupled to the first node
- the control end of the second NMOS tube receives the adjustment signal
- the second NMOS tube The first end of the second NMOS transistor is coupled to the ground end
- the second end of the second NMOS transistor is coupled to the first node.
- the startup unit includes a second NMOS transistor
- the adjustment unit includes a second PMOS transistor
- the control end of the second NMOS transistor receives the startup signal
- the third NMOS transistor of the second NMOS transistor receives the startup signal.
- One end is coupled to the working power supply
- the second end of the second NMOS tube is coupled to the first node
- the control end of the second PMOS tube receives the adjustment signal
- the second PMOS tube The first end of the second PMOS transistor is coupled to the ground end
- the second end of the second PMOS transistor is coupled to the first node.
- the output voltage adjustment module includes a first NMOS transistor, a control end of the first NMOS transistor is coupled to the first node, and a first end of the first NMOS transistor is coupled to the working power supply. The second end of the first NMOS transistor is coupled to the output node.
- the startup unit includes a second PMOS transistor
- the adjustment unit includes a second NMOS transistor
- the control end of the second PMOS transistor receives the startup signal
- the third PMOS transistor of the second PMOS transistor receives the startup signal.
- One end is coupled to the ground end
- the second end of the second PMOS tube is coupled to the first node
- the control end of the second NMOS tube receives the adjustment signal
- the third end of the second NMOS tube One end is coupled to the working power supply, and a second end of the second NMOS transistor is coupled to the first node.
- the startup unit includes a second NMOS transistor
- the adjustment unit includes a second PMOS transistor
- the control end of the second NMOS transistor receives the startup signal
- the third NMOS transistor of the second NMOS transistor receives the startup signal.
- One end is coupled to the ground end
- the second end of the second NMOS tube is coupled to the first node
- the control end of the second PMOS tube receives the adjustment signal
- the third end of the second PMOS tube One end is coupled to the working power supply, and a second end of the second PMOS tube is coupled to the first node.
- the voltage regulator further includes: a signal generation module, configured to generate the adjustment signal based on the startup signal; wherein generating the adjustment signal based on the startup signal includes: The start signal is sequentially inverted and delayed, and a logical AND operation is performed with the start signal to generate the adjustment signal.
- the signal generation module includes: an inversion unit, the input end of the inversion unit receives the start signal; a delay unit, the input end of the delay unit is connected to the input end of the inversion unit.
- the output terminal is coupled; an AND gate circuit, the first input terminal of the AND gate circuit is coupled with the output terminal of the delay unit, the second input terminal of the AND gate circuit receives the start signal, and the AND gate circuit
- the output terminal of the gate circuit outputs the adjustment signal.
- the voltage regulator further includes: a signal generation module, configured to generate the adjustment signal based on the startup signal; wherein generating the adjustment signal based on the startup signal includes: The start signal is sequentially inverted and delayed, and the signal obtained by performing logical OR operation with the start signal is used to generate the adjustment signal.
- the signal generation module includes: an inversion unit, the input end of the inversion unit receives the start signal; a delay unit, the input end of the delay unit is connected to the input end of the inversion unit.
- the output terminal is coupled; an OR gate circuit, the first input terminal of the OR gate circuit is coupled with the output terminal of the delay unit, the second input terminal of the OR gate circuit receives the start signal, and the OR gate circuit The output terminal of the gate circuit outputs the adjustment signal.
- the feedback circuit includes: a first voltage dividing module coupled between the output node and the comparison module; a second voltage dividing module coupled between the first voltage dividing module and Between the ground terminals, the feedback voltage is the potential at the coupling point between the first voltage dividing module and the second voltage dividing module.
- the comparison module includes: a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein the control end of the third PMOS transistor and the fourth PMOS transistor The control terminal is coupled, and there is a third node between the control terminal of the third PMOS tube and the control terminal of the fourth PMOS tube; the first terminal of the third PMOS tube and the control terminal of the fourth PMOS tube The third end is coupled to the operating power supply, the second end of the third PMOS transistor is coupled to the fifth end of the third NMOS transistor, and the fourth end of the fourth PMOS transistor is coupled to the fourth end of the fourth NMOS transistor.
- the seventh end has a fourth node between the second end and the fifth end, the fourth node is coupled to the first node, and there is a between the fourth end and the seventh end.
- the fifth node, the fifth node is coupled to the third node; the sixth terminal of the third NMOS tube is coupled to the eighth terminal of the fourth NMOS tube, and the control of the third NMOS tube
- the terminal is the first input terminal of the comparison module, the control terminal of the fourth NMOS tube is the second input terminal of the comparison module, and the fourth node is the output terminal of the comparison module.
- the voltage regulator further includes: a fifth NMOS transistor, the control terminal of the fifth NMOS transistor receives a bias voltage. , the first end of the fifth NMOS transistor is coupled to the sixth node, and the second end of the fifth NMOS transistor is coupled to the ground end.
- the embodiments of the present disclosure also provide a control method for a voltage regulator, including: providing a voltage regulator as described in any one of the foregoing; providing a reference voltage and a driving voltage, where In the startup phase of the voltage regulator operation, the driving voltage adjustment module adjusts the potential at the first node based on the driving voltage, so that the feedback circuit generates a feedback voltage, and the comparison module adjusts the potential at the first node based on the reference voltage. and the feedback voltage to generate an error voltage, and causing the output voltage adjustment module to generate an output voltage based on the error voltage.
- the output voltage adjustment module includes a first PMOS transistor or a first NMOS transistor; the driving voltage includes a start signal and an adjustment signal.
- providing the driving voltage includes: providing a startup signal; and generating the adjustment signal based on the startup signal.
- control method of the voltage regulator further includes: providing a bias voltage, and the comparison module receives the bias voltage.
- a driving voltage adjustment module is provided in the voltage regulator, so that during the startup phase of the voltage regulator operation, the potential at the first node can be quickly adjusted to the potential required to start the output voltage adjustment module through the driving voltage adjustment module, thereby accelerating
- the startup of the output voltage adjustment module is to increase the speed at which the output voltage adjustment module provides the output voltage to the output node, thereby facilitating the startup of the voltage regulator.
- 1 to 4 are schematic diagrams of four circuit structures of a voltage regulator provided by an embodiment of the present disclosure
- Figure 5 is a waveform diagram of a start signal and an adjustment signal provided by an embodiment of the present disclosure
- Figure 6 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 5;
- Figure 7 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 6;
- Figures 8 and 9 are schematic diagrams of two other circuit structures of a voltage regulator provided by an embodiment of the present disclosure.
- Figure 10 is another waveform diagram of a start signal and an adjustment signal provided by an embodiment of the present disclosure.
- Figure 11 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 10;
- Figure 12 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 11;
- FIG. 13 is a schematic diagram of another circuit structure of a voltage regulator provided by an embodiment of the present disclosure.
- the implementation of the present disclosure provides a voltage stabilizer and a control method thereof.
- a driving voltage adjustment module is provided in the voltage stabilizer, so that during the startup phase of the voltage stabilizer operation, the potential at the first node can be quickly adjusted through the driving voltage adjustment module. Adjust to the potential required to start the output voltage adjustment module, thereby accelerating the start-up of the output voltage adjustment module, so as to increase the speed at which the output voltage adjustment module provides the output voltage to the output node, thus facilitating the acceleration of the start-up of the voltage regulator.
- FIGS. 1 to 4 are schematic diagrams of four circuit structures of a voltage regulator provided by an embodiment of the present disclosure
- Figure 5 is a waveform diagram of a starting signal and an adjustment signal provided by an embodiment of the present disclosure
- Figure 6 is the same as Figure 5
- Figure 7 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 6
- Figures 8 and 9 are two other circuit structures of the voltage regulator provided by an embodiment of the present disclosure.
- FIG. 10 is another waveform diagram of the startup signal and the adjustment signal provided by an embodiment of the present disclosure
- Figure 11 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 10
- Figure 12 is the signal generation corresponding to Figure 11
- FIG. 13 is another schematic circuit structure diagram of the voltage regulator provided by an embodiment of the present disclosure.
- the voltage regulator includes: a comparison module 100 configured to compare a reference voltage 10a and a feedback voltage 10b and generate an error voltage 10c based on the comparison; an output voltage adjustment module 101 coupled to the first output terminal of the comparison module 100 Node 102 is configured to adjust the input voltage received by the output voltage adjustment module 101 based on the error voltage 10c to provide the output voltage 10d to the output node 103; the feedback circuit 104 is coupled between the output node 103 and the ground voltage, the feedback circuit 104 is configured to divide the output voltage 10d to provide the feedback voltage 10b; the driving voltage adjustment module 105 is coupled to the first node 102 and is used to adjust the potential at the first node 102 during the startup phase of the voltage regulator operation.
- the potential at the first node 102 is first adjusted by driving the voltage adjustment module 105, so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly
- the output voltage adjustment module 101 is started, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, which is beneficial to accelerating the start-up of the voltage regulator.
- the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100, and the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
- the output voltage adjustment module 101 adjusts the input voltage received by the output voltage adjustment module 101 based on the error voltage 10c to provide an output voltage 10d to the output node 103.
- the drive voltage adjustment module 105 is configured to reduce the time required to adjust the input voltage received by the output voltage adjustment module 101 .
- the input voltage received by the output voltage adjustment module 101 is the potential at the first node 102.
- the output voltage adjustment module 101 starts or shuts down based on the potential at the first node 102.
- the driving voltage adjustment module 105 is conducive to reducing the adjustment of the output voltage adjustment.
- the input voltage received by the module 101 takes time, that is, during the startup phase of the voltage regulator operation, the driving voltage adjustment module 105 can quickly adjust the potential at the first node 102 to the potential required to start the output voltage adjustment module 101, so as to The startup of the output voltage regulation module 101 is accelerated, thereby further accelerating the startup of the voltage regulator.
- the driving voltage adjustment module 105 includes: a start unit 115 coupled to the control terminal of the output voltage adjustment module 101.
- the start unit 115 stops adjusting the potential of the first node 102 based on the start signal 11a to start voltage regulation. regulator;
- the adjustment unit 125 is coupled to the control end of the output voltage adjustment module 101.
- the adjustment unit 125 adjusts the potential of the first node 102 based on the adjustment signal 11b to accelerate the startup of the voltage regulator.
- the startup unit 115 can adjust the potential at the first node 102 based on the startup signal 11a, so that the output voltage adjustment module 101 is based on the potential at the first node 102 at this time.
- the output voltage adjustment module 101 is controlled by the startup unit 115 not to provide the output voltage 10d to the output node 103, and the comparison module 100 is also in a non-working state, so that the entire voltage regulator is in a non-working state.
- the output voltage adjustment module 101 includes a first PMOS transistor 111 , the control end of the first PMOS transistor 111 is coupled to the first node 102 , and the first end of the first PMOS transistor 111 is coupled to the working power supply. VDD is coupled, and the second terminal of the first PMOS transistor 111 is coupled to the output node 103 .
- the startup unit 115 includes a second PMOS transistor 135, and the adjustment unit 125 includes a second NMOS transistor 145.
- the control end of the second PMOS transistor 135 receives the startup signal 11a, and the first end of the second PMOS transistor 135 is coupled to the operating power supply VDD. connected, the second end of the second PMOS transistor 135 is coupled to the first node 102, the control end of the second NMOS transistor 145 receives the adjustment signal 11b, the first end of the second NMOS transistor 145 is coupled to the ground end, and the second NMOS The second end of tube 145 is coupled to first node 102 .
- the second PMOS transistor 135 can be in the on state based on the start signal 11a, and the second NMOS transistor 145 can be in the off state based on the adjustment signal 11b, then the first node 102 is equivalent to the working power supply.
- VDD coupling that is, the second PMOS transistor 135 that is in the conductive state at this time can pull up the potential at the first node 102 to a higher value, so that the first PMOS transistor 111 receives the voltage at the first node 102 In the off state, that is, the output voltage adjustment module 101 is in a closed state and does not provide the output voltage 10d to the output node 103.
- the second PMOS transistor 135 can be in the off state based on the startup signal 11a, and the second NMOS transistor 145 can be in the on state based on the adjustment signal 11b, so that the first node 102 with a higher potential is connected to the first node 102 with a higher potential.
- the ground terminal is coupled, that is, the second NMOS transistor 145 that is in the conductive state at this time can quickly pull down the potential at the first node 102 to the potential required to start the first PMOS transistor 111, thereby realizing the driving voltage adjustment module. 105.
- the voltage regulation module 101 provides the speed of the output voltage 10d to the output node 103, thereby facilitating the startup of the voltage regulator.
- the second PMOS transistor 135 may be in the off state based on the start signal 11a, and the second NMOS transistor 145 may also be in the off state based on the adjustment signal 11b,
- the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100.
- the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
- the output voltage adjustment module 101 adjusts based on the error voltage 10c.
- the input voltage received by the output voltage adjustment module 101 is to use the comparison module 100 to adjust the potential at the first node 102 so that the potential at the first node 102 is within a stable value range, so that the first PMOS transistor 111 is in a conductive state. , providing a stable output voltage 10d to the output node 103.
- the output voltage adjustment module 101 includes a first NMOS transistor 121.
- the control end of the first NMOS transistor 121 is coupled to the first node 102.
- the first end of the first NMOS transistor 121 is coupled to the operating power supply VDD.
- the second end of the first NMOS transistor 121 is coupled to the output node 103 .
- the startup unit 115 includes a second PMOS transistor 135, and the adjustment unit 125 includes a second NMOS transistor 145.
- the control end of the second PMOS transistor receives the startup signal 11a, and the first end of the second PMOS transistor 135 is coupled to the ground end.
- the second end of the second PMOS transistor 135 is coupled to the first node 102.
- the control end of the second NMOS transistor 145 receives the adjustment signal 11b.
- the first end of the second NMOS transistor 145 is coupled to the operating power supply VDD.
- the second end of 145 is coupled to first node 102 .
- the second PMOS transistor 135 can be in the on state based on the start signal 11a, and the second NMOS transistor 145 can be in the off state based on the adjustment signal 11b, then the first node 102 is equivalent to the ground terminal. Coupling, that is, the potential at the first node 102 can be pulled down to a lower value through the second PMOS transistor 135 that is in a conductive state at this time, so that the first NMOS transistor 121 that receives the voltage at the first node 102 is turned off. state, that is, the output voltage adjustment module 101 is in a closed state and does not provide the output voltage 10d to the output node 103.
- the second PMOS transistor 135 can be in the off state based on the startup signal 11a, and the second NMOS transistor 145 can be in the on state based on the adjustment signal 11b, so that the first node 102 with a lower potential is connected to the
- the working power supply VDD is coupled, that is, the potential at the first node 102 can be quickly pulled up to the potential required to start the first NMOS transistor 121 through the second NMOS transistor 145 that is in the conductive state at this time, thereby realizing the driving voltage through
- the adjustment module 105 adjusts the potential at the first node 102 so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly turn on the first NMOS transistor 121, thereby Increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103 is beneficial to speeding up the startup of the voltage regulator.
- the second PMOS transistor 135 may be in the off state based on the start signal 11a, and the second NMOS transistor 145 may also be in the off state based on the adjustment signal 11b,
- the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100.
- the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
- the output voltage adjustment module 101 adjusts based on the error voltage 10c.
- the input voltage received by the output voltage adjustment module 101 is to use the comparison module 100 to adjust the potential at the first node 102 so that the potential at the first node 102 is within a stable value range, so that the first NMOS transistor 121 is in a conductive state. , providing a stable output voltage 10d to the output node 103.
- the waveform diagrams of the start signal 11a and the adjustment signal 11b can be shown in Figure 5.
- the potentials represented by the startup signal 11a and the adjustment signal 11b are both at low values, then the second PMOS transistor 135 can be in a conductive state based on the startup signal 11a, and the second NMOS transistor 145 can be in a conducting state based on the adjustment signal.
- the signal 11b is in the cut-off state; in the second phase II, the potentials represented by the start-up signal 11a and the adjustment signal 11b are both at higher values, then the second PMOS transistor 135 can be in the cut-off state based on the start-up signal 11a, and the second NMOS transistor 145 It can be based on the fact that the adjustment signal 11b is in a conductive state; in the third stage III, the potential represented by the startup signal 11a is at a higher value and the potential represented by the adjustment signal 11b is at a lower value, then the second PMOS transistor 135 can be based on The start signal 11a is in a cut-off state, and the second NMOS transistor 145 may also be in a cut-off state based on the adjustment signal 11b.
- the lower value of the potential and the higher value of the potential are relative to the magnitudes of the start signal 11a and the adjustment signal 11b in the first phase I, the second phase II and the third phase III.
- the value of the potential represented by the startup signal 11a in the first phase I is smaller than the value of the potential represented by the second phase II, then it can be considered that the potential represented by the startup signal 11a in the first phase I is at a lower level. value, the potential represented by the activation signal 11a in the second phase II is at a higher value.
- the voltage regulator may also include: a signal generation module 106 for generating an adjustment signal 11b based on the startup signal 11a; wherein generating the adjustment signal 11b based on the startup signal 11a includes: The signal 11a is sequentially inverted and delayed, and the signal obtained is logically ANDed with the start signal 11a to generate the adjustment signal 11b.
- the signal generation module 106 may include: an inverter unit 116 whose input terminal receives the start signal 11a; a delay unit 126 whose input terminal is connected to the inverter unit 116 .
- the output terminal of the unit 116 is coupled; the AND gate circuit 136, the first input terminal of the AND gate circuit 136 is coupled with the output terminal of the delay unit 126, the second input terminal of the AND gate circuit 136 receives the start signal 11a, and the AND gate circuit 136
- the output terminal of 136 outputs the adjustment signal 11b.
- the AND gate circuit 136 may include NAND gates 146 and 156 connected in series with each other. It should be noted that in FIG. 7 , only the AND gate circuit 136 includes NAND gates 146 and 156 connected in series with each other.
- the NOT gate 156 is used as an example. In practical applications, the AND gate circuit 136 can be composed of a single AND gate or a combination of other logic gate circuits, as long as the AND gate circuit 136 can perform a logical AND operation on the two received signals. That’s it.
- the potential values represented by the start signal 11a or the adjustment signal 11b are both low, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 0; the start signal When the potential values represented by 11a or the adjustment signal 11b are both high, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 1.
- the start signal 11 a appears to be 0, the signal received by the first input terminal of the AND gate circuit 136 appears to be 1, and the start signal received by the second input terminal of the AND gate circuit 136 11a behaves as 0, then the adjustment signal 11b output by the output terminal of the AND gate circuit 136 behaves as 0; in the second stage II, the start signal 11a behaves as 1, because the delay unit 126 responds to the received signal output by the inverting unit 116 The delay effect of The adjustment signal 11b output by the output terminal of 136 appears to be 1; in the third stage III, the start signal 11a appears to be 1, and the first input terminal of the AND gate circuit 136 has received the change of the start signal 11a in the second stage II.
- the signal received by the first input terminal of the AND gate circuit 136 changes, the signal received by the first input terminal of the AND gate circuit 136 will appear as 0, and the start signal 11a received by the second input terminal of the AND gate circuit 136 will appear as 1. , then the adjustment signal 11b output by the output terminal of the AND gate circuit 136 appears to be 0.
- the output voltage adjustment module 101 includes a first PMOS transistor 111 .
- the control end of the first PMOS transistor 111 is coupled to the first node 102 .
- the first end of the first PMOS transistor 111 is connected to the working end of the first PMOS transistor 111 .
- the power supply VDD is coupled, and the second terminal of the first PMOS transistor 111 is coupled to the output node 103 .
- the startup unit 115 includes a second NMOS transistor 145
- the adjustment unit 125 includes a second PMOS transistor 135.
- the control end of the second NMOS transistor 145 receives the startup signal 11a, and the first end of the second NMOS transistor 145 is coupled to the operating power supply VDD.
- the second end of the second NMOS transistor 145 is coupled to the first node 102
- the control end of the second PMOS transistor 135 receives the adjustment signal 11b
- the first end of the second PMOS transistor 135 is coupled to the ground end
- the second PMOS transistor 135 is coupled to the ground end.
- the second end of tube 135 is coupled to first node 102 .
- the second NMOS transistor 145 can be in the on state based on the start signal 11a, and the second PMOS transistor 135 can be in the off state based on the adjustment signal 11b, then the first node 102 is equivalent to the working power supply.
- VDD coupling that is, the second NMOS transistor 145 in the on state at this time can pull up the potential at the first node 102 to a higher value, so that the first PMOS transistor 111 receives the voltage at the first node 102 In the off state, that is, the output voltage adjustment module 101 is in a closed state and does not provide the output voltage 10d to the output node 103.
- the second NMOS transistor 145 can be in the off state based on the startup signal 11a, and the second PMOS transistor 135 can be in the on state based on the adjustment signal 11b, so that the first node 102 with a higher potential is connected to the first node 102 with a higher potential.
- the ground terminal is coupled, that is, the second PMOS transistor 135 that is in the conductive state at this time can quickly pull down the potential at the first node 102 to the potential required to start the first PMOS transistor 111, thereby realizing the driving voltage adjustment module. 105.
- the voltage regulation module 101 provides the speed of the output voltage 10d to the output node 103, thereby facilitating the startup of the voltage regulator.
- the second NMOS transistor 145 may be in the off state based on the start signal 11a, and the second PMOS transistor 135 may also be in the off state based on the adjustment signal 11b,
- the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100.
- the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
- the output voltage adjustment module 101 adjusts based on the error voltage 10c.
- the input voltage received by the output voltage adjustment module 101 is to use the comparison module 100 to adjust the potential at the first node 102 so that the potential at the first node 102 is within a stable value range, so that the first PMOS transistor 111 is in a conductive state. , providing a stable output voltage 10d to the output node 103.
- the output voltage adjustment module 101 includes a first NMOS transistor 121 .
- the control end of the first NMOS transistor 121 is coupled to the first node 102 .
- the first end of the first NMOS transistor 121 is connected to the working end of the first NMOS transistor 121 .
- the power supply VDD is coupled, and the second terminal of the first NMOS transistor 121 is coupled to the output node 103 .
- the startup unit 115 includes a second NMOS transistor 145
- the adjustment unit 125 includes a second PMOS transistor 135.
- the control end of the second NMOS transistor 145 receives the startup signal 11a, and the first end of the second NMOS transistor 145 is coupled to the ground end.
- the second end of the second NMOS transistor 145 is coupled to the first node 102
- the control end of the second PMOS transistor 135 receives the adjustment signal 11b
- the first end of the second PMOS transistor 135 is coupled to the operating power supply VDD
- the second PMOS transistor 135 The second end of tube 135 is coupled to first node 102 .
- the second NMOS transistor 145 can be in the on state based on the start signal 11a, and the second PMOS transistor 135 can be in the off state based on the adjustment signal 11b, then the first node 102 is equivalent to the ground terminal. Coupling, that is, the potential at the first node 102 can be pulled down to a lower value through the second NMOS transistor 145 that is in the on state at this time, so that the first NMOS transistor 121 that receives the voltage at the first node 102 is turned off. state, that is, the output voltage adjustment module 101 is in a closed state and does not provide the output voltage 10d to the output node 103.
- the second NMOS transistor 145 can be in the off state based on the startup signal 11a, and the second PMOS transistor 135 can be in the on state based on the adjustment signal 11b, so that the first node 102 with a lower potential is connected to the The working power supply VDD is coupled, that is, the potential at the first node 102 can be quickly pulled up to the potential required to start the first NMOS transistor 121 through the second PMOS transistor 135 that is in the conductive state at this time, thereby realizing the driving voltage.
- the adjustment module 105 adjusts the potential at the first node 102 so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly turn on the first NMOS transistor 121, thereby Increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103 is beneficial to speeding up the startup of the voltage regulator.
- the second NMOS transistor 145 may be in the off state based on the start signal 11a, and the second PMOS transistor 135 may also be in the off state based on the adjustment signal 11b,
- the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100.
- the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
- the output voltage adjustment module 101 adjusts based on the error voltage 10c.
- the input voltage received by the output voltage adjustment module 101 is to use the comparison module 100 to adjust the potential at the first node 102 so that the potential at the first node 102 is within a stable value range, so that the first NMOS transistor 121 is in a conductive state. , providing a stable output voltage 10d to the output node 103.
- the waveform diagrams of the start signal 11a and the adjustment signal 11b can be shown in Figure 10.
- the potentials represented by the startup signal 11a and the adjustment signal 11b are both at relatively high values, then the second NMOS transistor 145 can be in a conductive state based on the startup signal 11a, and the second PMOS transistor 135 can be in a conducting state based on the adjustment signal.
- the signal 11b is in the cut-off state; in the second phase II, the potentials represented by the start-up signal 11a and the adjustment signal 11b are both at low values, then the second NMOS transistor 145 can be in the cut-off state based on the start-up signal 11a, and the second PMOS transistor 135 It can be based on the fact that the adjustment signal 11b is in a conductive state; in the third stage III, the potential represented by the start signal 11a is at a lower value, and the potential represented by the adjustment signal 11b is at a higher value, then the second NMOS transistor 145 can be based on The start signal 11a is in a cut-off state, and the second PMOS transistor 135 may also be in a cut-off state based on the adjustment signal 11b.
- the lower value of the potential and the higher value of the potential are relative to the magnitudes of the start signal 11a and the adjustment signal 11b in the first phase I, the second phase II and the third phase III.
- the value of the potential represented by the startup signal 11a in the first phase I is greater than the value of the potential represented by the second phase II, then it can be considered that the potential represented by the startup signal 11a in the first phase I is at a higher level. value, the potential represented by the activation signal 11a in the second phase II is at a lower value.
- the voltage regulator may also include: a signal generation module 106 for generating an adjustment signal 11b based on the startup signal 11a; wherein generating the adjustment signal 11b based on the startup signal 11a includes: The signal 11a is sequentially inverted and delayed, and the resulting signal is logically ORed with the start signal 11a to generate the adjustment signal 11b.
- the signal generation module 106 may include: an inverting unit 116 whose input terminal receives the start signal 11a; a delay unit 126 whose input terminal is connected to the inverting unit 116 .
- the output terminal of the unit 116 is coupled; the OR gate circuit 166, the first input terminal of the OR gate circuit 166 is coupled with the output terminal of the delay unit 126, the second input terminal of the OR gate circuit 166 receives the start signal 11a, the OR gate circuit
- the output terminal of 166 outputs the adjustment signal 11b.
- the OR circuit 166 may include a NOR gate 176 and a NOT gate 156 connected in series. It should be noted that in FIG. 12 , only the OR circuit 166 includes a NOR gate 176 and a NOR gate 156 connected in series.
- the NOT gate 156 is an example. In practical applications, the OR circuit 166 can be composed of a single OR gate or a combination of other logic gate circuits, as long as the OR circuit 166 can perform a logical OR operation on the two received signals. That’s it.
- the potential values represented by the start signal 11a or the adjustment signal 11b are both low, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 0; the start signal When the potential values represented by 11a or the adjustment signal 11b are both high, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 1.
- the start signal 11a is 1, the signal received by the first input terminal of the AND gate circuit 136 is 0, and the start signal received by the second input terminal of the AND gate circuit 136 is 11a behaves as 1, then the adjustment signal 11b output by the output terminal of the AND gate circuit 136 behaves as 1; in the second stage II, the start signal 11a behaves as 0, because the delay unit 126 responds to the received signal output by the inverting unit 116 The delay effect of The adjustment signal 11b output by the output terminal of 136 appears to be 0; in the third stage III, the start signal 11a appears to be 0, and the first input terminal of the AND gate circuit 136 has received the change of the start signal 11a in the second stage II.
- the signal received by the first input terminal of the AND gate circuit 136 changes, the signal received by the first input terminal of the AND gate circuit 136 will appear as 1, and the start signal 11a received by the second input terminal of the AND gate circuit 136 will appear as 0. , then the adjustment signal 11b output by the output terminal of the AND gate circuit 136 appears to be 1.
- the inverter unit 116 may include: a first switch unit 186 coupled between the operating power supply VDD and the input end of the delay unit 126 . There is a second node 107 between a switch unit 186 and the input terminal of the delay unit 126; the second switch unit 196 is coupled between the ground terminal and the second node 107; wherein, the control terminal of the first switch unit 186, The control terminals of the second switch unit 196 both receive the start signal 11a.
- the first switching unit 186 may be one of a PMOS transistor and an NMOS transistor
- the second switching unit 196 may be the other of a PMOS transistor and an NMOS transistor.
- the first switch unit 186 may be a PMOS transistor, and the second switch unit 196 may be an NMOS transistor.
- the first switching unit may be an NMOS transistor
- the second switching unit may be a PMOS transistor.
- the first switch unit 186 and the second switch unit 196 can also be other switching devices that can be turned on or off based on the start signal 11a, as long as the first switch satisfies the start signal 11a at the same time.
- One of the unit 186 and the second switch unit 196 is turned on based on the start signal 11a at this time, and the other one of the first switch unit 186 and the second switch unit 196 is turned off based on the start signal 11a at this time.
- the delay unit 126 may include: an even number of series-connected inverters 118 .
- the delay unit 126 including two series-connected inverters 118 is used as an example. In actual applications, it only needs to be an even number of inverters 118 . 5 and 10 , an even number of series-connected inverters 118 are used to delay the signal received by the delay unit 126 from the output end of the inverter unit 116 .
- the value of the potential represented by the start signal 11a has changed, and the value of the potential represented by the signal received by the delay unit 126 from the output end of the inverting unit 116 has not yet arrived.
- the value of the potential represented by the signal received by the delay unit 126 from the output end of the inverting unit 116 also changes, so that the adjustment signal 11b and the start signal 11a in the third stage II represent
- the values of the potentials are at different levels, that is, the potential represented by one of the adjustment signal 11b and the startup signal 11a in the circuit is 1, and the potential of the other one of the adjustment signal 11b and the startup signal 11a is represented in the circuit. The potential appears to be 0.
- the delay unit 126 in addition to including an even number of series-connected inverters 118, may also include: a charge and discharge unit 108 coupled between the second node 107 and ground. between ends. Among them, the charging and discharging unit 108 is beneficial to enhancing the delay effect of the delay unit 126 on the signal received from the output end of the inverting unit 116 .
- the feedback circuit 104 may include: a first voltage dividing module 114 coupled between the output node 103 and the comparison module 100; a second voltage dividing module 124, coupled between the first voltage dividing module 114 and the ground terminal, the feedback voltage 10b is the potential at the coupling point of the first voltage dividing module 114 and the second voltage dividing module 124.
- the comparison module 100 it is beneficial to control the size of the feedback voltage 10b provided to the comparison module 100 through the first voltage dividing module 114 and the second voltage dividing module 124 when the output voltage 10d meeting the numerical requirements is output through the output voltage adjustment module 101, so that the feedback
- the magnitude of the voltage 10b is consistent with the magnitude of the reference voltage 10a, that is, the difference between the feedback voltage 10b and the reference voltage 10a is very small or 0, so that the comparison module 100 can output a numerically stable error voltage 10c based on the reference voltage 10a and the feedback voltage 10b.
- the comparison module 100 includes: a third PMOS transistor 110 , a fourth PMOS transistor 120 , a third NMOS transistor 130 and a fourth NMOS transistor 140 ; wherein, the control end of the third PMOS transistor 110 and The control terminal of the fourth PMOS tube 120 is coupled, and there is a third node 109 between the control terminal of the third PMOS tube 110 and the control terminal of the fourth PMOS tube 120; the first terminal of the third PMOS tube 110 and the fourth PMOS tube
- the third end of 120 is coupled to the working power supply VDD
- the second end of the third PMOS transistor 110 is coupled to the fifth end of the third NMOS transistor 130
- the fourth end of the fourth PMOS transistor 120 is coupled to the third end of the fourth NMOS transistor 140.
- a fourth node 119 is between the second terminal and the fifth terminal, the fourth node 119 is coupled to the first node 102, a fifth node 129 is between the fourth terminal and the seventh terminal, the fifth node 129 is connected to The third node 109 is coupled; the sixth terminal of the third NMOS tube 130 is coupled to the eighth terminal of the fourth NMOS tube 140.
- the control terminal of the third NMOS tube 130 is the first input terminal of the comparison module 100.
- the fourth NMOS The control end of the tube 140 is the second input end of the comparison module 100, and the fourth node 119 is the output end of the comparison module.
- control terminal of the third NMOS transistor 130 receives the reference voltage 10a
- control terminal of the fourth NMOS transistor 140 receives the feedback voltage 10b.
- the third PMOS transistor 110, the fourth PMOS transistor 120, the third NMOS transistor 130 and the fourth NMOS transistor 140 are all in a conductive state.
- the conduction degree of the third NMOS transistor 130 is greater than the conduction degree of the fourth NMOS transistor 140, that is, the voltage drop generated by the third NMOS transistor 130 is smaller than the voltage drop generated by the fourth NMOS transistor 140.
- the potential at the fourth node 119 is caused to be lower than the potential at the fifth node 129 .
- the potential at the fifth node 129 is the potential at the control terminals of the third PMOS transistor 110 and the fourth PMOS transistor 120
- the third PMOS transistor 110 and the fourth PMOS transistor 120 The conduction degree of 120 decreases, that is, the voltage drop generated by the third PMOS transistor 110 increases, causing the potential at the fourth node 119 to decrease, that is, the error voltage 10c output by the comparison module 100 decreases, causing the potential at the first node 102 to decrease.
- the conduction degree of the first PMOS tube 111 increases, that is, the voltage drop generated by the first PMOS tube 111 decreases, which is beneficial to increasing the output voltage 10d provided by the output voltage adjustment module 101 to the output node 103, thereby increasing the feedback circuit 104 divides the feedback voltage 10b provided based on the output voltage 10d to reduce the difference between the reference voltage 10a and the feedback voltage 10b.
- the conduction degree of the third NMOS transistor 130 is less than the conduction degree of the fourth NMOS transistor 140, that is, the voltage drop generated by the third NMOS transistor 130 is greater than the voltage drop generated by the fourth NMOS transistor 140.
- the potential at the fourth node 119 is caused to be higher than the potential at the fifth node 129 .
- the potential at the fifth node 129 is the potential at the control terminals of the third PMOS transistor 110 and the fourth PMOS transistor 120, if the potential at the fifth node 129 decreases, the third PMOS transistor 110 and the fourth PMOS transistor 120
- the conduction degree of The potential increases, causing the conduction degree of the first PMOS transistor 111 to decrease, that is, the voltage drop generated by the first PMOS transistor 111 increases, which is beneficial to reducing the output voltage 10d provided by the output voltage adjustment module 101 to the output node 103, thereby reducing the
- the small feedback circuit 104 divides the feedback voltage 10b provided by the output voltage 10d to reduce the difference between the reference voltage 10a and the feedback voltage 10b.
- the voltage regulator may also include: a bias voltage module 150, one end of the bias voltage module 150 is connected to the sixth node 139 is coupled, and the other end of the bias voltage module 150 is coupled to the ground.
- the bias voltage module 150 can be used as a power supply module of the voltage regulator, which is beneficial to the voltage regulator working based on the larger reference voltage 10a.
- the bias voltage module 150 may include a fifth NMOS transistor. The control terminal of the fifth NMOS transistor receives the bias voltage 10e. The first end of the fifth NMOS transistor is coupled to the sixth node 139. The fifth NMOS transistor The second end is coupled to the ground end.
- the potential at the first node 102 is first adjusted by driving the voltage adjustment module 105 so that the potential at the first node 102 quickly reaches the level required to start the output voltage adjustment module 101 potential to quickly start the output voltage adjustment module 101, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, thereby conducive to accelerating the start-up of the voltage regulator.
- the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100, and the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
- the output voltage adjustment module 101 adjusts the input voltage received by the output voltage adjustment module 101 based on the error voltage 10c to provide an output voltage 10d to the output node 103.
- Another embodiment of the present disclosure also provides a control method for a voltage regulator, which is used to control the voltage regulator provided in the previous embodiment.
- a control method for a voltage regulator provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to the previous embodiments will not be described again here.
- the control method of the voltage regulator includes: providing a voltage stabilizer as described in any of the preceding items; providing a reference voltage 10a and a driving voltage.
- the driving voltage adjustment module 105 is based on the driving voltage.
- the potential at the first node 102 is adjusted so that the feedback circuit 104 generates the feedback voltage 10b, the comparison module 100 generates the error voltage 10c based on the reference voltage 10a and the feedback voltage 10b, and the output voltage adjustment module 101 generates an output based on the error voltage 10c. Voltage 10d.
- the potential at the first node 102 is first adjusted based on the driving voltage, so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly
- the output voltage adjustment module 101 is started, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, which is beneficial to accelerating the start-up of the voltage regulator.
- the output voltage adjustment module 101 includes a first PMOS transistor or a first NMOS transistor; the driving voltage includes a start signal 11a and an adjustment signal 11b.
- the driving voltage adjustment module 105 adjusts the potential at the first node 102 based on the driving voltage, refer to the relevant descriptions of the foregoing embodiments and will not be described again.
- the step of providing the driving voltage includes: providing the activation signal 11a; and generating the adjustment signal 11b based on the activation signal 11a.
- the adjustment signal 11b based on the start signal 11a refer to the relevant descriptions of the foregoing embodiments and will not be described again.
- control method of the voltage regulator further includes: providing a bias voltage 10e, and the comparison module 100 receiving the bias voltage 10e.
- the bias voltage 10e can be used as a power supply for the voltage regulator, which is beneficial to the voltage regulator updating based on numerical values. Large reference voltage 10a operates.
- control method of the voltage regulator provided by another embodiment of the present disclosure is conducive to making the potential at the first node 102 quickly reach the potential required to start the output voltage adjustment module 101 during the startup phase of the voltage regulator operation. , to quickly start the output voltage adjustment module 101, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, which is beneficial to accelerating the start-up of the voltage regulator.
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Abstract
一种稳压器及控制方法,稳压器包括比较模块(100),被配置为比较基准电压(10a)和反馈电压(10b)并基于比较生成误差电压(10c);输出电压调节模块(101),与比较模块(100)的输出端耦接于第一节点(102),被配置为基于误差电压(10c)来调整输出电压调节模块(101)接收的输入电压,以向输出节点(103)提供输出电压(10d);反馈电路(104),耦接于输出节点(103)和接地电压之间,反馈电路(104)被配置为对输出电压(10d)进行分压以提供反馈电压(10b);驱动电压调节模块(105),与第一节点(102)耦接,用于在稳压器工作的启动阶段调节第一节点(102)处的电位。稳压器及控制方法有利于加速稳压器的启动。
Description
交叉引用
本公开要求于2022年03月14日递交的名称为“稳压器及其控制方法”、申请号为202210246743.1的中国专利申请的优先权,其通过引用被全部并入本公开。
本公开实施例涉及半导体技术领域,特别涉及一种稳压器及其控制方法。
随着电子技术的广泛应用,对电子***也提出了更高的性能要求。其中,稳压器是一种能自动调整输出电压的供电电路或供电设备,其作用是将波动较大和达不到电器设备要求的电源电压稳定在它的设定值范围内,使各种电路或电器设备能在额定工作电压下正常工作。
然而,为了更快的获取数值范围稳定的输出电压以降低瞬态的压降,需要稳压器具备更快的响应速度。
发明内容
本公开实施例提供一种一种稳压器及其控制方法,至少有利于加速稳压器的启动。
根据本公开一些实施例,本公开实施例一方面提供一种稳压器,包括:比较模块,被配置为比较基准电压和反馈电压并基于所述比较生成误差电压;输出电压调节模块,与所述比较模块的输出端耦接于第一节点,被配置为基于所述误差电压来调整所述输出电压调节模块接收的输入电压,以向输出节点提供输出电压;反馈电路,耦接于所述输出节点和接地电压之间,所述反馈电路被配置为对所述输出电压进行分压以提供所述反馈电压;驱动电压调节模块,与所述第一节点耦接,用于在所述稳压器工作的启动阶段调节所述第一节点处的电位。
在一些实施例中,所述驱动电压调节模块被配置为:降低调整所述输出电压调节模块接收的所述输入电压的耗时。
在一些实施例中,所述驱动电压调节模块包括:启动单元,与所述输出电压调节模块的控制端耦接,所述启动单元基于启动信号停止对所述第一节点的电位的调节以启动所述稳压器;调节单元,与所述输出电压调节模块的控制端耦接,所述调节单元基于调节信号调节所述第一节点的电位以加速所述稳压器的启动。
在一些实施例中,所述输出电压调节模块包括第一PMOS管,所述第一PMOS管的控制端与所述第一节点耦接,所述第一PMOS管的第一端与工作电源耦接,所述第一PMOS管的第二端与所述输出节点耦接。
在一些实施例中,所述启动单元包括第二PMOS管,则所述调节单元包括第二NMOS管,所述第二PMOS管的控制端接收所述启动信号,所述第二PMOS管的第一端与所述工作电源耦接,所述第二PMOS管的第二端与所述第一节点耦接,所述第二NMOS管的控制端接收所述调节信号,所述第二NMOS管的第一端与地端耦接,所述第二NMOS管的第二端与所述第一节点耦接。
在一些实施例中,所述启动单元包括第二NMOS管,则所述调节单元包括第二PMOS管,所述第二NMOS管的控制端接收所述启动信号,所述第二NMOS管的第一端与所述工作电源耦接,所述第二NMOS管的第二端与所述第一节点耦接,所述第二PMOS管的控制端接收所述调节信号,所述第二PMOS管的第一端与地端耦接,所述第二PMOS管的第二端与所述第一节点耦接。
在一些实施例中,所述输出电压调节模块包括第一NMOS管,所述第一NMOS管的控制端与所述第一节点耦接,所述第一NMOS管的第一端与工作电源耦接,所述第一NMOS管的第二端与所述输出节点耦接。
在一些实施例中,所述启动单元包括第二PMOS管,则所述调节单元包括第二NMOS管,所述第二PMOS管的控制端接收所述启动信号,所述第二PMOS管的第一端与地端耦接,所述第二PMOS管的第二端与所述第一节点耦接,所述第二NMOS管的控制端接收所述调节信号,所述第二NMOS管的第一端与所述工作电源耦接,所述第二NMOS管的第二端与所述第一节点耦接。
在一些实施例中,所述启动单元包括第二NMOS管,则所述调节单元包括第二PMOS管,所述第二NMOS管的控制端接收所述启动信号,所述第二NMOS管的第一端与地端耦接,所述第二NMOS管的第二端与所述第一节点耦接,所述第二PMOS管的控制端接收所述调节信号,所述第二PMOS管的第一端与所述工作电源耦接,所述第二PMOS管的第二端与所述第一节点耦接。
在一些实施例中,所述稳压器还包括:信号生成模块,用于基于所述启动信号生成所述调节信号;其中,基于所述启动信号生成所述调节信号,包括,将对所述启动信号依次进行反相、延时处理后得到的信号与所述启动信号进行逻辑与运算,以生成所述调节信号。
在一些实施例中,所述信号生成模块包括:反相单元,所述反相单元的输入端接收所述启动信号;延时单元,所述延时单元的输入端与所述反相单元的输出端耦接;与门电路,所述与门电路的第一输入端与所述延时单元的输出端耦接,所述与门电路的第二输入端接收所述启动信号,所述与门电路的输出端输出所述调节信号。
在一些实施例中,所述稳压器还包括:信号生成模块,用于基于所述启动信号生成所述调节信号;其中,基于所述启动信号生成所述调节信号,包括,将对所述启动信号依次进行反相、延时处理后得到的信号与所述启动信号进行逻辑或运算,以生成所述调节信号。
在一些实施例中,所述信号生成模块包括:反相单元,所述反相单元的输入端接收所述启动信号;延时单元,所述延时单元的输入端与所述反相单元的输出端耦接;或门电路,所述或门电路的第一输入端与所述延时单元的输出端耦接,所述或门电路的第二输入端接收所述启动信号,所述或门电路的输出端输出所述调节信号。
在一些实施例中,所述反馈电路包括:第一分压模块,耦接于所述输出节点与所述比较模块之间;第二分压模块,耦接于所述第一分压模块和地端之间,所述反馈电压为所述第一分压模块与所述第二分压模块耦接处的电位。
在一些实施例中,所述比较模块包括:第三PMOS管、第四PMOS管、第三NMOS管以及第四NMOS管;其中,所述第三PMOS管的控制端和所述第四PMOS管的控制端耦接,所述第三PMOS管的控制端和所述第四PMOS管的控制端之间具有第三节点;所述第三PMOS管的第一端和所述第四PMOS管的第三端耦接工作电源,所述第三PMOS管的第二端耦接所述第三NMOS管的第五端,所述第四PMOS管的第四端耦接所述第四NMOS管的第七端,所述第二端与所述第五端之间具有第四节点,所述第四节点与所述第一节点耦接,所述第四端与所述第七端之间具有第五节点,所述第五节点与所述第三节点耦接;所述第三NMOS管的第六端与所述第四NMOS管的第八端耦接,所述第三NMOS管的控制端为所述比较模块的第一输入端,所述第四NMOS管的控制端为所述比较模块的第二输入端,所述第四节点为所述比较模块的输出端。
在一些实施例中,所述第六端和所述第八端之间具有第六节点,所述稳压器还包括:第五NMOS管,所述第五NMOS管的控制端接收偏置电压,所述第五NMOS管的第一端与所述第六节点耦接,所述第五NMOS管的第二端耦接至所述地端。
根据本公开一些实施例,本公开实施例另一方面还提供一种稳压器的控制方法,包括:提供如前述任一项所述的稳压器;提供基准电压以及驱动电压,在所述稳压器工作的启动阶段,所述驱动电压调节模块基于所述驱动电压调节所述第一节点处的电位,以使所述反馈电路生成反馈电压,以及使所述比较模块基于所述基准电压和所述反馈电压生成误差电压,以及使所述输出电压调节模块基于所述误差电压生成输出电压。
在一些实施例中,所述输出电压调节模块包括第一PMOS管或第一NMOS管;所述驱动电压包括启动信号和调节信号。
在一些实施例中,提供所述驱动电压的步骤包括:提供启动信号;基于所述启动信号生成所述调节信号。
在一些实施例中,所述稳压器的控制方法还包括:提供偏置电压,所述比较模块接收所述偏置电压。
本公开实施例提供的技术方案至少具有以下优点:
在稳压器中设置驱动电压调节模块,使得在稳压器工作的启动阶段,可以通过驱动电 压调节模块快速地将第一节点处的电位调节至启动输出电压调节模块所需要的电位,从而加速输出电压调节模块的启动,以提高输出电压调节模块向输出节点提供输出电压的速度,从而有利于加速稳压器的启动。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明,这些示例性说明并不构成对实施例的限定,除非有特别申明,附图中的图不构成比例限制。一个或多个实施例通过与之对应的附图中的图片进行示例性说明,这些示例性说明并不构成对实施例的限定,除非有特别申明,附图中的图不构成比例限制;为了更清楚地说明本公开实施例或传统技术中的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本公开的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1至图4为本公开一实施例提供的稳压器的四种电路结构示意图;
图5为本公开一实施例提供的启动信号和调节信号的一种波形图;
图6为与图5对应的信号生成模块的电路结构示意图;
图7为与图6对应的信号生成模块的一种电路结构示意图;
图8和图9为本公开一实施例提供的稳压器的另外两种电路结构示意图;
图10为本公开一实施例提供的启动信号和调节信号的另一种波形图;
图11为与图10对应的信号生成模块的电路结构示意图;
图12为与图11对应的信号生成模块的一种电路结构示意图;
图13为本公开一实施例提供的稳压器的又一种电路结构示意图。
本公开实施提供一种稳压器及其控制方法,在稳压器中设置驱动电压调节模块,使得在稳压器工作的启动阶段,可以通过驱动电压调节模块快速地将第一节点处的电位调节至启动输出电压调节模块所需要的电位,从而加速输出电压调节模块的启动,以提高输出电压调节模块向输出节点提供输出电压的速度,从而有利于加速稳压器的启动。
下面将结合附图对本公开的各实施例进行详细的阐述。然而,本领域的普通技术人员可以理解,在本公开各实施例中,为了使读者更好地理解本公开实施例而提出了许多技术细节。但是,即使没有这些技术细节和基于以下各实施例的种种变化和修改,也可以实现本公开实施例所要求保护的技术方案。
本公开一实施例提供一种稳压器,以下将结合附图对本公开一实施例提供的稳压器进行详细说明。图1至图4为本公开一实施例提供的稳压器的四种电路结构示意图;图5为本 公开一实施例提供的启动信号和调节信号的一种波形图;图6为与图5对应的信号生成模块的电路结构示意图;图7为与图6对应的信号生成模块的一种电路结构示意图;图8和图9为本公开一实施例提供的稳压器的另外两种电路结构示意图;图10为本公开一实施例提供的启动信号和调节信号的另一种波形图;图11为与图10对应的信号生成模块的电路结构示意图;图12为与图11对应的信号生成模块的一种电路结构示意图;图13为本公开一实施例提供的稳压器的又一种电路结构示意图。
参考图1,稳压器包括:比较模块100,被配置为比较基准电压10a和反馈电压10b并基于比较生成误差电压10c;输出电压调节模块101,与比较模块100的输出端耦接于第一节点102,被配置为基于误差电压10c来调整输出电压调节模块101接收的输入电压,以向输出节点103提供输出电压10d;反馈电路104,耦接于输出节点103和接地电压之间,反馈电路104被配置为对输出电压10d进行分压以提供反馈电压10b;驱动电压调节模块105,与第一节点102耦接,用于在稳压器工作的启动阶段调节第一节点102处的电位。
在稳压器工作的启动阶段,先通过驱动电压调节模块105对第一节点102处的电位进行调节,使得第一节点102处的电位快速达到启动输出电压调节模块101所需要的电位,以快速的启动输出电压调节模块101,从而提高输出电压调节模块101向输出节点103提供输出电压10d的速度,从而有利于加速稳压器的启动。此外,在输出电压调节模块101第一次向输出节点103提供输出电压10d之后,反馈电路104对输出电压10d进行分压以向比较模块100提供反馈电压10b,比较模块100比较基准电压10a和反馈电压10b并生成误差电压10c,输出电压调节模块101基于误差电压10c来调整输出电压调节模块101接收的输入电压,以向输出节点103提供输出电压10d。
在一些实施例中,驱动电压调节模块105被配置为:降低调整输出电压调节模块101接收的输入电压的耗时。其中,输出电压调节模块101接收的输入电压即为第一节点102处的电位,输出电压调节模块101基于第一节点102处的电位启动或关闭,驱动电压调节模块105有利于降低调整输出电压调节模块101接收的输入电压的耗时,即在稳压器工作的启动阶段,驱动电压调节模块105能够快速的将第一节点102处的电位调节到启动输出电压调节模块101所需要的电位,以加速输出电压调节模块101的启动,从而进一步加速稳压器的启动。
以下将结合图2至图13对本公开实施例进行更为详细的说明。
在一些实施例中,驱动电压调节模块105包括:启动单元115,与输出电压调节模块101的控制端耦接,启动单元115基于启动信号11a停止对第一节点102的电位的调节以启动稳压器;调节单元125,与输出电压调节模块101的控制端耦接,调节单元125基于调节信号11b调节第一节点102的电位以加速稳压器的启动。
需要说明的是,在稳压器处于非工作阶段时,启动单元115可以基于启动信号11a对 第一节点102处的电位进行调节,使得输出电压调节模块101基于此时第一节点102处的电位处于关闭状态,即通过启动单元115控制输出电压调节模块101不会向输出节点103提供输出电压10d,比较模块100也处于非工作状态,使得稳压器整体处于非工作状态。
关于输出电压调节模块101、启动单元115以及调节单元125的具体构造,以下通过四种实施例对其进行详细说明。
在一些实施例中,参考图3,输出电压调节模块101包括第一PMOS管111,第一PMOS管111的控制端与第一节点102耦接,第一PMOS管111的第一端与工作电源VDD耦接,第一PMOS管111的第二端与输出节点103耦接。
其中,启动单元115包括第二PMOS管135,则调节单元125包括第二NMOS管145,第二PMOS管135的控制端接收启动信号11a,第二PMOS管135的第一端与工作电源VDD耦接,第二PMOS管135的第二端与第一节点102耦接,第二NMOS管145的控制端接收调节信号11b,第二NMOS管145的第一端与地端耦接,第二NMOS管145的第二端与第一节点102耦接。
如此,在稳压器的非工作阶段,第二PMOS管135可以基于启动信号11a处于导通状态,第二NMOS管145可以基于调节信号11b处于截止状态,则第一节点102相当于与工作电源VDD耦接,即通过此时处于导通状态的第二PMOS管135可以将第一节点102处的电位上拉至一个较高的数值,使得接收第一节点102处电压的第一PMOS管111处于截止状态,即输出电压调节模块101处于关闭状态,不会向输出节点103提供输出电压10d。
然后,在稳压器工作的启动阶段,第二PMOS管135可以基于启动信号11a处于截止状态,第二NMOS管145可以基于调节信号11b处于导通状态,使得电位较高的第一节点102与地端耦接,即可以通过此时处于导通状态的第二NMOS管145快速将第一节点102处的电位下拉至可以启动第一PMOS管111所需要的电位,从而实现通过驱动电压调节模块105对第一节点102处的电位进行调节,使得第一节点102处的电位快速达到启动输出电压调节模块101所需要的电位的目的,以快速的使得第一PMOS管111导通,从而提高输出电压调节模块101向输出节点103提供输出电压10d的速度,从而有利于加速稳压器的启动。
然后,在输出电压调节模块101第一次向输出节点103提供输出电压10d之后,第二PMOS管135可以基于启动信号11a处于截止状态,第二NMOS管145可以基于调节信号11b也处于截止状态,此时反馈电路104对输出电压10d进行分压以向比较模块100提供反馈电压10b,比较模块100比较基准电压10a和反馈电压10b并生成误差电压10c,输出电压调节模块101基于误差电压10c来调整输出电压调节模块101接收的输入电压,即利用比较模块100调节第一节点102处的电位,使得第一节点102处的电位处于稳定的数值范围内,以使得第一PMOS管111处于导通状态,向输出节点103提供稳定的输出电压10d。
在又一些实施例中,输出电压调节模块101包括第一NMOS管121,第一NMOS管 121的控制端与第一节点102耦接,第一NMOS管121的第一端与工作电源VDD耦接,第一NMOS管121的第二端与输出节点103耦接。
其中,启动单元115包括第二PMOS管135,则调节单元125包括第二NMOS管145,第二PMOS管的控制端接收启动信号11a,第二PMOS管135的第一端与地端耦接,第二PMOS管135的第二端与第一节点102耦接,第二NMOS管145的控制端接收调节信号11b,第二NMOS管145的第一端与工作电源VDD耦接,第二NMOS管145的第二端与第一节点102耦接。
如此,在稳压器的非工作阶段,第二PMOS管135可以基于启动信号11a处于导通状态,第二NMOS管145可以基于调节信号11b处于截止状态,则第一节点102相当于与地端耦接,即通过此时处于导通状态的第二PMOS管135可以将第一节点102处的电位下拉至一个较低的数值,使得接收第一节点102处电压的第一NMOS管121处于截止状态,即输出电压调节模块101处于关闭状态,不会向输出节点103提供输出电压10d。
然后,在稳压器工作的启动阶段,第二PMOS管135可以基于启动信号11a处于截止状态,第二NMOS管145可以基于调节信号11b处于导通状态,使得电位较低的第一节点102与工作电源VDD耦接,即可以通过此时处于导通状态的第二NMOS管145快速将第一节点102处的电位上拉至可以启动第一NMOS管121所需要的电位,从而实现通过驱动电压调节模块105对第一节点102处的电位进行调节,使得第一节点102处的电位快速达到启动输出电压调节模块101所需要的电位的目的,以快速的使得第一NMOS管121导通,从而提高输出电压调节模块101向输出节点103提供输出电压10d的速度,从而有利于加速稳压器的启动。
然后,在输出电压调节模块101第一次向输出节点103提供输出电压10d之后,第二PMOS管135可以基于启动信号11a处于截止状态,第二NMOS管145可以基于调节信号11b也处于截止状态,此时反馈电路104对输出电压10d进行分压以向比较模块100提供反馈电压10b,比较模块100比较基准电压10a和反馈电压10b并生成误差电压10c,输出电压调节模块101基于误差电压10c来调整输出电压调节模块101接收的输入电压,即利用比较模块100调节第一节点102处的电位,使得第一节点102处的电位处于稳定的数值范围内,以使得第一NMOS管121处于导通状态,向输出节点103提供稳定的输出电压10d。
上述两种实施例中,启动信号11a和调节信号11b的波形图可以如图5所示。其中,在第一阶段I,启动信号11a和调节信号11b所表征的电位均处于较低的数值,则第二PMOS管135可以基于启动信号11a处于导通状态,第二NMOS管145可以基于调节信号11b处于截止状态;在第二阶段II,启动信号11a和调节信号11b所表征的电位均处于较高的数值,则第二PMOS管135可以基于启动信号11a处于截止状态,第二NMOS管145可以基于调节信号11b处于导通状态;在第三阶段III,启动信号11a所表征的电位处于较高的数值,调节信号11b所表征的电位处于较低的数值,则第二PMOS管135可以基于启动信号11a处于截 止状态,第二NMOS管145可以基于调节信号11b也处于截止状态。
需要说明的是,电位处于较低的数值和电位处于较高的数值是相对于启动信号11a和调节信号11b在第一阶段I、第二阶段II以及在第三阶段III中所呈现的大小进行区分的,例如,启动信号11a在第一阶段I所表征的电位的数值小于在第二阶段II所表征的电位的数值,则可以认为启动信号11a在第一阶段I所表征的电位处于较低的数值,启动信号11a在第二阶段II所表征的电位处于较高的数值。
上述两种实施例中,参考图6,稳压器还可以包括:信号生成模块106,用于基于启动信号11a生成调节信号11b;其中,基于启动信号11a生成调节信号11b,包括,将对启动信号11a依次进行反相、延时处理后得到的信号与启动信号11a进行逻辑与运算,以生成调节信号11b。
在一些实施例中,继续参考图6,信号生成模块106可以包括:反相单元116,反相单元116的输入端接收启动信号11a;延时单元126,延时单元126的输入端与反相单元116的输出端耦接;与门电路136,与门电路136的第一输入端与延时单元126的输出端耦接,与门电路136的第二输入端接收启动信号11a,与门电路136的输出端输出调节信号11b。
在一些例子中,参考图7,与门电路136可以包括相互串联的与非门146和非门156,需要说明的是,图7中仅以与门电路136包括相互串联的与非门146和非门156为示例,实际应用中,与门电路136可以又单一的与门构成,也可以其他逻辑门电路的组合构成,只需满足与门电路136对接收的两个信号能进行逻辑与运算即可。
需要说明的是,为了便于表述,启动信号11a或调节信号11b所表征的电位的数值均较低时,即意味着启动信号11a或调节信号11b在电路中所表征的电位表现为0;启动信号11a或调节信号11b所表征的电位的数值均较高时,即意味着启动信号11a或调节信号11b在电路中所表征的电位表现为1。
结合参考图5至图7,在第一阶段I,启动信号11a表现为0,与门电路136的第一输入端接收的信号表现为1,与门电路136的第二输入端接收的启动信号11a表现为0,则与门电路136的输出端输出的调节信号11b表现为0;在第二阶段II,启动信号11a表现为1,由于延时单元126对接收的反相单元116输出的信号的延时作用,第二阶段II中,与门电路136的第一输入端接收的信号仍表现为1,与门电路136的第二输入端接收的启动信号11a表现为1,则与门电路136的输出端输出的调节信号11b表现为1;在第三阶段III,启动信号11a表现为1,与门电路136的第一输入端已经接收到由于第二阶段II中启动信号11a的改变导致的与门电路136的第一输入端接收的信号的改变,则与门电路136的第一输入端接收的信号表现为0,与门电路136的第二输入端接收的启动信号11a表现为1,则与门电路136的输出端输出的调节信号11b表现为0。
在又一些实施例中,参考图8,输出电压调节模块101包括第一PMOS管111,第一 PMOS管111的控制端与第一节点102耦接,第一PMOS管111的第一端与工作电源VDD耦接,第一PMOS管111的第二端与输出节点103耦接。
其中,启动单元115包括第二NMOS管145,则调节单元125包括第二PMOS管135,第二NMOS管145的控制端接收启动信号11a,第二NMOS管145的第一端与工作电源VDD耦接,第二NMOS管145的第二端与第一节点102耦接,第二PMOS管135的控制端接收调节信号11b,第二PMOS管135的第一端与地端耦接,第二PMOS管135的第二端与第一节点102耦接。
如此,在稳压器的非工作阶段,第二NMOS管145可以基于启动信号11a处于导通状态,第二PMOS管135可以基于调节信号11b处于截止状态,则第一节点102相当于与工作电源VDD耦接,即通过此时处于导通状态的第二NMOS管145可以将第一节点102处的电位上拉至一个较高的数值,使得接收第一节点102处电压的第一PMOS管111处于截止状态,即输出电压调节模块101处于关闭状态,不会向输出节点103提供输出电压10d。
然后,在稳压器工作的启动阶段,第二NMOS管145可以基于启动信号11a处于截止状态,第二PMOS管135可以基于调节信号11b处于导通状态,使得电位较高的第一节点102与地端耦接,即可以通过此时处于导通状态的第二PMOS管135快速将第一节点102处的电位下拉至可以启动第一PMOS管111所需要的电位,从而实现通过驱动电压调节模块105对第一节点102处的电位进行调节,使得第一节点102处的电位快速达到启动输出电压调节模块101所需要的电位的目的,以快速的使得第一PMOS管111导通,从而提高输出电压调节模块101向输出节点103提供输出电压10d的速度,从而有利于加速稳压器的启动。
然后,在输出电压调节模块101第一次向输出节点103提供输出电压10d之后,第二NMOS管145可以基于启动信号11a处于截止状态,第二PMOS管135可以基于调节信号11b也处于截止状态,此时反馈电路104对输出电压10d进行分压以向比较模块100提供反馈电压10b,比较模块100比较基准电压10a和反馈电压10b并生成误差电压10c,输出电压调节模块101基于误差电压10c来调整输出电压调节模块101接收的输入电压,即利用比较模块100调节第一节点102处的电位,使得第一节点102处的电位处于稳定的数值范围内,以使得第一PMOS管111处于导通状态,向输出节点103提供稳定的输出电压10d。
在再一些实施例中,参考图9,输出电压调节模块101包括第一NMOS管121,第一NMOS管121的控制端与第一节点102耦接,第一NMOS管121的第一端与工作电源VDD耦接,第一NMOS管121的第二端与输出节点103耦接。
其中,启动单元115包括第二NMOS管145,则调节单元125包括第二PMOS管135,第二NMOS管145的控制端接收启动信号11a,第二NMOS管145的第一端与地端耦接,第二NMOS管145的第二端与第一节点102耦接,第二PMOS管135的控制端接收调节信号11b,第二PMOS管135的第一端与工作电源VDD耦接,第二PMOS管135的第二端与第一 节点102耦接。
如此,在稳压器的非工作阶段,第二NMOS管145可以基于启动信号11a处于导通状态,第二PMOS管135可以基于调节信号11b处于截止状态,则第一节点102相当于与地端耦接,即通过此时处于导通状态的第二NMOS管145可以将第一节点102处的电位下拉至一个较低的数值,使得接收第一节点102处电压的第一NMOS管121处于截止状态,即输出电压调节模块101处于关闭状态,不会向输出节点103提供输出电压10d。
然后,在稳压器工作的启动阶段,第二NMOS管145可以基于启动信号11a处于截止状态,第二PMOS管135可以基于调节信号11b处于导通状态,使得电位较低的第一节点102与工作电源VDD耦接,即可以通过此时处于导通状态的第二PMOS管135快速将第一节点102处的电位上拉至可以启动第一NMOS管121所需要的电位,从而实现通过驱动电压调节模块105对第一节点102处的电位进行调节,使得第一节点102处的电位快速达到启动输出电压调节模块101所需要的电位的目的,以快速的使得第一NMOS管121导通,从而提高输出电压调节模块101向输出节点103提供输出电压10d的速度,从而有利于加速稳压器的启动。
然后,在输出电压调节模块101第一次向输出节点103提供输出电压10d之后,第二NMOS管145可以基于启动信号11a处于截止状态,第二PMOS管135可以基于调节信号11b也处于截止状态,此时反馈电路104对输出电压10d进行分压以向比较模块100提供反馈电压10b,比较模块100比较基准电压10a和反馈电压10b并生成误差电压10c,输出电压调节模块101基于误差电压10c来调整输出电压调节模块101接收的输入电压,即利用比较模块100调节第一节点102处的电位,使得第一节点102处的电位处于稳定的数值范围内,以使得第一NMOS管121处于导通状态,向输出节点103提供稳定的输出电压10d。
上述两种实施例中,启动信号11a和调节信号11b的波形图可以如图10所示。其中,在第一阶段I,启动信号11a和调节信号11b所表征的电位均处于较高的数值,则第二NMOS管145可以基于启动信号11a处于导通状态,第二PMOS管135可以基于调节信号11b处于截止状态;在第二阶段II,启动信号11a和调节信号11b所表征的电位均处于较低的数值,则第二NMOS管145可以基于启动信号11a处于截止状态,第二PMOS管135可以基于调节信号11b处于导通状态;在第三阶段III,启动信号11a所表征的电位处于较低的数值,调节信号11b所表征的电位处于较高的数值,则第二NMOS管145可以基于启动信号11a处于截止状态,第二PMOS管135可以基于调节信号11b也处于截止状态。
需要说明的是,电位处于较低的数值和电位处于较高的数值是相对于启动信号11a和调节信号11b在第一阶段I、第二阶段II以及在第三阶段III中所呈现的大小进行区分的,例如,启动信号11a在第一阶段I所表征的电位的数值大于在第二阶段II所表征的电位的数值,则可以认为启动信号11a在第一阶段I所表征的电位处于较高的数值,启动信号11a在第二阶段II所表征的电位处于较低的数值。
上述两种实施例中,参考图11,稳压器还可以包括:信号生成模块106,用于基于启动信号11a生成调节信号11b;其中,基于启动信号11a生成调节信号11b,包括,将对启动信号11a依次进行反相、延时处理后得到的信号与启动信号11a进行逻辑或运算,以生成调节信号11b。
在一些实施例中,继续参考图11,信号生成模块106可以包括:反相单元116,反相单元116的输入端接收启动信号11a;延时单元126,延时单元126的输入端与反相单元116的输出端耦接;或门电路166,或门电路166的第一输入端与延时单元126的输出端耦接,或门电路166的第二输入端接收启动信号11a,或门电路166的输出端输出调节信号11b。
在一些例子中,参考图12,或门电路166可以包括相互串联的或非门176和非门156,需要说明的是,图12中仅以或门电路166包括相互串联的或非门176和非门156为示例,实际应用中,或门电路166可以又单一的或门构成,也可以其他逻辑门电路的组合构成,只需满足或门电路166对接收的两个信号能进行逻辑或运算即可。
需要说明的是,为了便于表述,启动信号11a或调节信号11b所表征的电位的数值均较低时,即意味着启动信号11a或调节信号11b在电路中所表征的电位表现为0;启动信号11a或调节信号11b所表征的电位的数值均较高时,即意味着启动信号11a或调节信号11b在电路中所表征的电位表现为1。
结合参考图10至图12,在第一阶段I,启动信号11a表现为1,与门电路136的第一输入端接收的信号表现为0,与门电路136的第二输入端接收的启动信号11a表现为1,则与门电路136的输出端输出的调节信号11b表现为1;在第二阶段II,启动信号11a表现为0,由于延时单元126对接收的反相单元116输出的信号的延时作用,第二阶段II中,与门电路136的第一输入端接收的信号仍表现为0,与门电路136的第二输入端接收的启动信号11a表现为0,则与门电路136的输出端输出的调节信号11b表现为0;在第三阶段III,启动信号11a表现为0,与门电路136的第一输入端已经接收到由于第二阶段II中启动信号11a的改变导致的与门电路136的第一输入端接收的信号的改变,则与门电路136的第一输入端接收的信号表现为1,与门电路136的第二输入端接收的启动信号11a表现为0,则与门电路136的输出端输出的调节信号11b表现为1。
上述四种实施例中,参考图7和图12,反相单元116可以包括:第一开关单元186,第一开关单元186耦接在工作电源VDD与延时单元126的输入端之间,第一开关单元186与延时单元126的输入端之间具有第二节点107;第二开关单元196,耦接在地端与第二节点107之间;其中,第一开关单元186的控制端、第二开关单元196的控制端均接收启动信号11a。在一些例子中,第一开关单元186可以为PMOS管和NMOS管中的一者,第二开关单元196可以为PMOS管和NMOS管中的另一者,例如,参考图7和图12,第一开关单元186可以为PMOS管,第二开关单元196可以为NMOS管。在其他例子中,第一开关单元可以为NMOS管,第二开关单元可以为PMOS管。此外,实际应用中,第一开关单元186和第二开 关单元196也可以为其他可以实现基于启动信号11a可以导通或关闭的开关器件,只需满足对于同一时刻的启动信号11a,第一开关单元186和第二开关单元196中的一者基于该时刻的启动信号11a导通,第一开关单元186和第二开关单元196中的另一者基于该时刻的启动信号11a关闭即可。
上述四种实施例中,参考图7和图12,延时单元126可以包括:偶数个串联的反相器118。图7和图12中仅以延时单元126包括两个串联的反相器118为示例,实际应用中,只需满足反相器118的数量为偶数即可。其中,参考图5和图10,偶数个串联的反相器118用于对延时单元126从反相单元116的输出端接收到的信号进行延时处理。如此,有利于使得在第二阶段II中,启动信号11a所表征的电位的数值已经改变,而延时单元126从反相单元116的输出端接收到的信号所表征的电位的数值还未来得及改变,使得第二阶段II中的调节信号11b和启动信号11a所表征的电位的数值处于相同的水平,即调节信号11b和启动信号11a在电路中所表征的电位均表现为1或0;然后,在第三阶段II中,延时单元126从反相单元116的输出端接收到的信号所表征的电位的数值也发生改变,使得第三阶段II中的调节信号11b和启动信号11a所表征的电位的数值处于不同的水平,即调节信号11b和启动信号11a中的一者在电路中所表征的电位表现为1,调节信号11b和启动信号11a中的另一者在电路中所表征的电位表现为0。
在一些实施例中,继续参考图7和图12,延时单元126在包括偶数个串联的反相器118的基础上,还可以包括:充放电单元108,耦接在第二节点107与地端之间。其中,充放电单元108有利于增强延时单元126对从反相单元116的输出端接收到的信号的延时效果。
在一些实施例中,参考图3、图4、图8和图9,反馈电路104可以包括:第一分压模块114,耦接于输出节点103与比较模块100之间;第二分压模块124,耦接于第一分压模块114和地端之间,反馈电压10b为第一分压模块114与第二分压模块124耦接处的电位。如此,有利于在通过输出电压调节模块101输出符合数值要求的输出电压10d时,通过第一分压模块114和第二分压模块124控制提供给比较模块100的反馈电压10b的大小,使得反馈电压10b的大小和基准电压10a的大小一致,即反馈电压10b和基准电压10a的差值很小或者为0,使得比较模块100基于基准电压10a和反馈电压10b可以输出数值稳定的误差电压10c,进一步使得输出电压调节模块101基于误差电压10c输出数值稳定的输出电压10d。
在一些实施例中,参考图13,比较模块100包括:第三PMOS管110、第四PMOS管120、第三NMOS管130以及第四NMOS管140;其中,第三PMOS管110的控制端和第四PMOS管120的控制端耦接,第三PMOS管110的控制端和第四PMOS管120的控制端之间具有第三节点109;第三PMOS管110的第一端和第四PMOS管120的第三端耦接工作电源VDD,第三PMOS管110的第二端耦接第三NMOS管130的第五端,第四PMOS管120的第四端耦接第四NMOS管140的第七端,第二端与第五端之间具有第四节点119,第四节点119与第一节点102耦接,第四端与第七端之间具有第五节点129,第五节点129与第三 节点109耦接;第三NMOS管130的第六端与第四NMOS管140的第八端耦接,第三NMOS管130的控制端为比较模块100的第一输入端,第四NMOS管140的控制端为比较模块100的第二输入端,第四节点119为比较模块的输出端。
在一些实施例中,第三NMOS管130的控制端接收基准电压10a,第四NMOS管140的控制端接收反馈电压10b。以下对比较模块100基于基准电压10a和反馈电压10b生成误差电压10c的进行详细说明。
在比较模块100处于工作状态时,第三PMOS管110、第四PMOS管120、第三NMOS管130以及第四NMOS管140均处于导通状态。
若基准电压10a大于反馈电压10b,第三NMOS管130的导通程度大于第四NMOS管140的导通程度,即第三NMOS管130产生的压降小于第四NMOS管140产生的压降,使得第四节点119处的电位低于第五节点129处的电位。由于第五节点129处的电位即为第三PMOS管110和第四PMOS管120的控制端处的电位,若第五节点129处的电位升高,则第三PMOS管110和第四PMOS管120的导通程度降低,即第三PMOS管110产生的压降增大,使得第四节点119处的电位降低,即比较模块100输出的误差电压10c降低,使得第一节点102处的电位降低,使得第一PMOS管111的导通程度增大,即第一PMOS管111产生的压降减小,有利于增大输出电压调节模块101向输出节点103提供输出电压10d,从而增大反馈电路104基于输出电压10d进行分压提供的反馈电压10b,以降低基准电压10a与反馈电压10b之间的差值。
若基准电压10a小于反馈电压10b,第三NMOS管130的导通程度小于第四NMOS管140的导通程度,即第三NMOS管130产生的压降大于第四NMOS管140产生的压降,使得第四节点119处的电位高于第五节点129处的电位。由于第五节点129处的电位即为第三PMOS管110和第四PMOS管120的控制端处的电位,若第五节点129处的电位降低,则第三PMOS管110和第四PMOS管120的导通程度增大,即第三PMOS管110产生的压降减小,使得第四节点119处的电位升高,即比较模块100输出的误差电压10c升高,使得第一节点102处的电位升高,使得第一PMOS管111的导通程度减小,即第一PMOS管111产生的压降增大,有利于减小输出电压调节模块101向输出节点103提供输出电压10d,从而减小反馈电路104基于输出电压10d进行分压提供的反馈电压10b,以降低基准电压10a与反馈电压10b之间的差值。
在一些实施例中,继续参考图13,第六端和第八端之间具有第六节点139,稳压器还可以包括:偏置电压模块150,偏置电压模块150的一端与第六节点139耦接,偏置电压模块150的另一端耦接至地端。其中,偏置电压模块150可以作为稳压器的电源模块,有利于稳压器基于数值更大的基准电压10a进行工作。在一个例子中,偏置电压模块150可以包括第五NMOS管,第五NMOS管的控制端接收偏置电压10e,第五NMOS管的第一端与第六节点139耦接,第五NMOS管的第二端耦接地端。
综上所述,在稳压器工作的启动阶段,先通过驱动电压调节模块105对第一节点102处的电位进行调节,使得第一节点102处的电位快速达到启动输出电压调节模块101所需要的电位,以快速的启动输出电压调节模块101,从而提高输出电压调节模块101向输出节点103提供输出电压10d的速度,从而有利于加速稳压器的启动。此外,在输出电压调节模块101第一次向输出节点103提供输出电压10d之后,反馈电路104对输出电压10d进行分压以向比较模块100提供反馈电压10b,比较模块100比较基准电压10a和反馈电压10b并生成误差电压10c,输出电压调节模块101基于误差电压10c来调整输出电压调节模块101接收的输入电压,以向输出节点103提供输出电压10d。
本公开另一实施例还提供一种稳压器的控制方法,用于控制前述实施例提供的稳压器。以下将结合附图对本公开另一实施例提供的稳压器的控制方法进行详细说明。需要说明的是,与前述实施例相同或相应的部分,在此不作赘述。
参考图13,稳压器的控制方法包括:提供如前述任一项所述的稳压器;提供基准电压10a以及驱动电压,在稳压器工作的启动阶段,驱动电压调节模块105基于驱动电压调节第一节点102处的电位,以使反馈电路104生成反馈电压10b,以及使比较模块100基于基准电压10a和反馈电压10b生成误差电压10c,以及使输出电压调节模块101基于误差电压10c生成输出电压10d。
如此,在稳压器工作的启动阶段,先基于驱动电压对第一节点102处的电位进行调节,使得第一节点102处的电位快速达到启动输出电压调节模块101所需要的电位,以快速的启动输出电压调节模块101,从而提高输出电压调节模块101向输出节点103提供输出电压10d的速度,从而有利于加速稳压器的启动。
在一些实施例中,输出电压调节模块101包括第一PMOS管或第一NMOS管;驱动电压包括启动信号11a和调节信号11b。关于驱动电压调节模块105如何基于驱动电压调节第一节点102处的电位,参照前述实施例的相关描述,在次不做赘述。
在一些实施例中,提供驱动电压的步骤包括:提供启动信号11a;基于启动信号11a生成调节信号11b。关如何基于启动信号11a生成调节信号11b,参照前述实施例的相关描述,在次不做赘述。
在一些实施例中,稳压器的控制方法还包括:提供偏置电压10e,比较模块100接收偏置电压10e,偏置电压10e可以作为稳压器的电源,有利于稳压器基于数值更大的基准电压10a进行工作。
综上所述,本公开另一实施例提供的稳压器的控制方法有利于在稳压器工作的启动阶段,使得第一节点102处的电位快速达到启动输出电压调节模块101所需要的电位,以快速的启动输出电压调节模块101,从而提高输出电压调节模块101向输出节点103提供输出电压10d的速度,从而有利于加速稳压器的启动。
本领域的普通技术人员可以理解,上述各实施方式是实现本公开的具体实施例,而在实际应用中,可以在形式上和细节上对其作各种改变,而不偏离本公开实施例的精神和范围。任何本领域技术人员,在不脱离本公开实施例的精神和范围内,均可作各自更动与修改,因此本公开实施例的保护范围应当以权利要求限定的范围为准。
Claims (20)
- 一种稳压器,包括:比较模块,被配置为比较基准电压和反馈电压并基于所述比较生成误差电压;输出电压调节模块,与所述比较模块的输出端耦接于第一节点,被配置为基于所述误差电压来调整所述输出电压调节模块接收的输入电压,以向输出节点提供输出电压;反馈电路,耦接于所述输出节点和接地电压之间,所述反馈电路被配置为对所述输出电压进行分压以提供所述反馈电压;驱动电压调节模块,与所述第一节点耦接,用于在所述稳压器工作的启动阶段调节所述第一节点处的电位。
- 如权利要求1所述的稳压器,其中,所述驱动电压调节模块被配置为:降低调整所述输出电压调节模块接收的所述输入电压的耗时。
- 如权利要求1所述的稳压器,其中,所述驱动电压调节模块包括:启动单元,与所述输出电压调节模块的控制端耦接,所述启动单元基于启动信号停止对所述第一节点的电位的调节以启动所述稳压器;调节单元,与所述输出电压调节模块的控制端耦接,所述调节单元基于调节信号调节所述第一节点的电位以加速所述稳压器的启动。
- 如权利要求3所述的稳压器,其中,所述输出电压调节模块包括第一PMOS管,所述第一PMOS管的控制端与所述第一节点耦接,所述第一PMOS管的第一端与工作电源耦接,所述第一PMOS管的第二端与所述输出节点耦接。
- 如权利要求4所述的稳压器,其中,所述启动单元包括第二PMOS管,则所述调节单元包括第二NMOS管,所述第二PMOS管的控制端接收所述启动信号,所述第二PMOS管的第一端与所述工作电源耦接,所述第二PMOS管的第二端与所述第一节点耦接,所述第二NMOS管的控制端接收所述调节信号,所述第二NMOS管的第一端与地端耦接,所述第二NMOS管的第二端与所述第一节点耦接。
- 如权利要求4所述的稳压器,其中,所述启动单元包括第二NMOS管,则所述调节单元包括第二PMOS管,所述第二NMOS管的控制端接收所述启动信号,所述第二NMOS管的第一端与所述工作电源耦接,所述第二NMOS管的第二端与所述第一节点耦接,所述第二PMOS管的控制端接收所述调节信号,所述第二PMOS管的第一端与地端耦接,所述第二PMOS管的第二端与所述第一节点耦接。
- 如权利要求3所述的稳压器,其中,所述输出电压调节模块包括第一NMOS管,所述第一NMOS管的控制端与所述第一节点耦接,所述第一NMOS管的第一端与工作电源耦接, 所述第一NMOS管的第二端与所述输出节点耦接。
- 如权利要求7所述的稳压器,其中,所述启动单元包括第二PMOS管,则所述调节单元包括第二NMOS管,所述第二PMOS管的控制端接收所述启动信号,所述第二PMOS管的第一端与地端耦接,所述第二PMOS管的第二端与所述第一节点耦接,所述第二NMOS管的控制端接收所述调节信号,所述第二NMOS管的第一端与所述工作电源耦接,所述第二NMOS管的第二端与所述第一节点耦接。
- 如权利要求7所述的稳压器,其中,所述启动单元包括第二NMOS管,则所述调节单元包括第二PMOS管,所述第二NMOS管的控制端接收所述启动信号,所述第二NMOS管的第一端与地端耦接,所述第二NMOS管的第二端与所述第一节点耦接,所述第二PMOS管的控制端接收所述调节信号,所述第二PMOS管的第一端与所述工作电源耦接,所述第二PMOS管的第二端与所述第一节点耦接。
- 如权利要求5或8所述的稳压器,其中,还包括:信号生成模块,用于基于所述启动信号生成所述调节信号;其中,基于所述启动信号生成所述调节信号,包括,将对所述启动信号依次进行反相、延时处理后得到的信号与所述启动信号进行逻辑与运算,以生成所述调节信号。
- 如权利要求10所述的稳压器,其中,所述信号生成模块包括:反相单元,所述反相单元的输入端接收所述启动信号;延时单元,所述延时单元的输入端与所述反相单元的输出端耦接;与门电路,所述与门电路的第一输入端与所述延时单元的输出端耦接,所述与门电路的第二输入端接收所述启动信号,所述与门电路的输出端输出所述调节信号。
- 如权利要求6或9所述的稳压器,其中,还包括:信号生成模块,用于基于所述启动信号生成所述调节信号;其中,基于所述启动信号生成所述调节信号,包括,将对所述启动信号依次进行反相、延时处理后得到的信号与所述启动信号进行逻辑或运算,以生成所述调节信号。
- 如权利要求12所述的稳压器,其中,所述信号生成模块包括:反相单元,所述反相单元的输入端接收所述启动信号;延时单元,所述延时单元的输入端与所述反相单元的输出端耦接;或门电路,所述或门电路的第一输入端与所述延时单元的输出端耦接,所述或门电路的第二输入端接收所述启动信号,所述或门电路的输出端输出所述调节信号。
- 如权利要求1所述的稳压器,其中,所述反馈电路包括:第一分压模块,耦接于所述输出节点与所述比较模块之间;第二分压模块,耦接于所述第一分压模块和地端之间,所述反馈电压为所述第一分压模块与所述第二分压模块耦接处的电位。
- 如权利要求1所述的稳压器,其中,所述比较模块包括:第三PMOS管、第四PMOS管、第三NMOS管以及第四NMOS管;其中,所述第三PMOS管的控制端和所述第四PMOS管的控制端耦接,所述第三PMOS管的控制端和所述第四PMOS管的控制端之间具有第三节点;所述第三PMOS管的第一端和所述第四PMOS管的第三端耦接工作电源,所述第三PMOS管的第二端耦接所述第三NMOS管的第五端,所述第四PMOS管的第四端耦接所述第四NMOS管的第七端,所述第二端与所述第五端之间具有第四节点,所述第四节点与所述第一节点耦接,所述第四端与所述第七端之间具有第五节点,所述第五节点与所述第三节点耦接;所述第三NMOS管的第六端与所述第四NMOS管的第八端耦接地端,所述第三NMOS管的控制端为所述比较模块的第一输入端,所述第四NMOS管的控制端为所述比较模块的第二输入端,所述第四节点为所述比较模块的输出端。
- 如权利要求15所述的稳压器,其中,所述第六端和所述第八端之间具有第六节点,所述稳压器还包括:第五NMOS管,所述第五NMOS管的控制端接收偏置电压,所述第五NMOS管的第一端与所述第六节点耦接,所述第五NMOS管的第二端耦接至所述地端。
- 一种稳压器的控制方法,包括:提供如权利要求1至16中任一项所述的稳压器;提供基准电压以及驱动电压,在所述稳压器工作的启动阶段,所述驱动电压调节模块基于所述驱动电压调节所述第一节点处的电位,以使所述反馈电路生成反馈电压,以及使所述比较模块基于所述基准电压和所述反馈电压生成误差电压,以及使所述输出电压调节模块基于所述误差电压生成输出电压。
- 如权利要求17所述的控制方法,其中,所述输出电压调节模块包括第一PMOS管或第一NMOS管;所述驱动电压包括启动信号和调节信号。
- 如权利要求18所述的控制方法,其中,提供所述驱动电压的步骤包括:提供启动信号;基于所述启动信号生成所述调节信号。
- 如权利要求17所述的控制方法,其中,还包括:提供偏置电压,所述比较模块接收所述偏置电压。
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CN114665706A (zh) * | 2021-05-03 | 2022-06-24 | 绍兴圆方半导体有限公司 | 电压稳压器及*** |
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