WO2022057366A1 - 一种负压电平转换控制电路和方法 - Google Patents

一种负压电平转换控制电路和方法 Download PDF

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Publication number
WO2022057366A1
WO2022057366A1 PCT/CN2021/102924 CN2021102924W WO2022057366A1 WO 2022057366 A1 WO2022057366 A1 WO 2022057366A1 CN 2021102924 W CN2021102924 W CN 2021102924W WO 2022057366 A1 WO2022057366 A1 WO 2022057366A1
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Prior art keywords
circuit
bias
level shift
voltage
negative voltage
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PCT/CN2021/102924
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English (en)
French (fr)
Inventor
刘炽锋
张鑫
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广州慧智微电子有限公司
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Publication of WO2022057366A1 publication Critical patent/WO2022057366A1/zh
Priority to US18/064,250 priority Critical patent/US20230108055A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only

Definitions

  • the present application relates to integrated circuit technology, and in particular, to a negative voltage level shift control circuit and method.
  • the negative voltage level conversion control circuit is a very common circuit module in the integrated circuit system. Its main function is to realize the conversion between different levels, including the conversion from positive voltage to positive voltage or positive voltage to negative voltage, such as from 1.8V to 3.3V or 2.5V to -2.5V conversion etc.
  • the negative voltage level conversion control circuit includes a negative voltage generation circuit and a level shift unit circuit, wherein the input terminal of the level shift unit circuit can be zero level or positive level, taking the input positive level as an example, The output is then switched to another positive and negative level.
  • each channel is instantaneously turned on during the switching process, that is, there is a leakage path from positive pressure to negative pressure;
  • the number of charges consumed during the pass-through process is large, and there is a risk of pulling up the voltage of the output terminal of the negative voltage generating circuit, thereby affecting the performance of the subsequent circuit.
  • the present application provides a negative voltage level shift control circuit and method.
  • the present application provides a negative voltage level shift control circuit
  • the negative pressure level shift control circuit includes: a negative voltage generating circuit, a bias circuit and a level shift unit circuit; wherein the output end of the bias circuit is connected to the level shift unit circuit is connected, and the other end is connected with the negative pressure generating circuit; the output end of the negative pressure generating circuit is connected with the level shift unit circuit;
  • the bias circuit is configured to receive an enable signal and output a bias voltage; the bias voltage is used to control the switching process of the level shift unit circuit; the enable signal is used to control the bias circuit and the The negative pressure generating circuit is enabled.
  • the negative voltage level shift control circuit further includes: a first delay unit;
  • the input end of the first delay unit is configured to receive the enable signal, and the output end of the first delay unit is connected to the negative pressure generating circuit.
  • the negative voltage level shift control circuit further includes: a second delay unit, wherein the delay time of the first delay unit is greater than that of the second delay unit;
  • the input end of the second delay unit is configured to receive the enable signal, and the output end of the second delay unit is connected to the bias circuit.
  • one end of the bias circuit is connected to a DC power supply, and the DC power supply is used to pull up the bias voltage before the bias circuit is enabled.
  • one end of the level shift unit circuit is connected to the DC power supply.
  • the bias circuit is configured to divide the voltage between the DC power supply and the output terminal of the negative voltage generating circuit to obtain a bias voltage.
  • the present application also provides a negative voltage level shift control method, which is characterized in that it is applied to a negative voltage level shift control circuit, and the negative voltage level shift control circuit includes: a negative voltage generation circuit, a bias circuit, and a power supply circuit. a level shift unit circuit; wherein the output end of the bias circuit is connected to the level shift unit circuit, and the other end is connected to the negative voltage generating circuit; the output end of the negative pressure generating circuit is connected to the level shift unit circuit Bit cell circuit connection;
  • the method includes:
  • the bias circuit receives an enable signal and outputs a bias voltage; the bias voltage is used to control the switching process of the level shift unit circuit; the enable signal is used to control the bias circuit and the The negative pressure generation circuit is enabled.
  • one end of the bias circuit is connected to a DC power supply, and the method further includes:
  • the DC power source pulls up the bias voltage before the bias circuit is enabled.
  • the method further includes:
  • the bias circuit divides the voltage between the DC power supply and the output terminal of the negative voltage generating circuit to obtain a bias voltage.
  • the negative voltage level shift control circuit includes: a negative voltage generating circuit, a bias circuit and a level shift unit circuit; wherein, the bias circuit has a The output end is connected with the level shift unit circuit, and the other end is connected with the negative pressure generating circuit; the output end of the negative pressure generating circuit is connected with the level shift unit circuit; the bias circuit is configured to receive an enable signal to output a bias voltage; the bias voltage is used to control the switching process of the level shift unit circuit; the enable signal is used to enable the bias circuit and the negative voltage generating circuit .
  • the speed of the level shift unit circuit discharging to the ground is accelerated, the instantaneous conduction time during the level conversion process is shortened, and further, the level shift unit is accelerated.
  • Switching speed; the timing control of the enable signal reduces the charge consumption of the negative voltage generating circuit and reduces the risk of the voltage at the output terminal of the negative voltage generating circuit being pulled up; at the same time, the control of the bias voltage at the output terminal of the bias circuit This effectively reduces the risk of overvoltage in the level shift unit circuit when the negative voltage generating circuit operates.
  • 1a is a schematic structural diagram of a negative voltage level shift control circuit in the related art
  • 1b is a schematic diagram of a level shift unit circuit in the related art
  • 1c is a schematic diagram of the voltage change of the output terminal of the negative voltage generating circuit during level switching in the related art
  • FIG. 2 is a schematic diagram of a negative voltage level shift control circuit according to an embodiment of the application.
  • 3a is a schematic diagram of another negative voltage level shift control circuit according to an embodiment of the application.
  • 3b is a schematic diagram of a level shift unit circuit according to an embodiment of the application.
  • 3c is a schematic diagram of a bias circuit according to an embodiment of the present application.
  • FIG. 3d is a schematic diagram of timing waveforms of the negative voltage level shift control circuit in the level shift process provided by the embodiment of the present application.
  • FIG. 1a is a schematic structural diagram of a negative voltage level shift control circuit in the related art.
  • the negative pressure level shift control circuit includes: a negative pressure generation circuit NVG and M level shift units LevelShift_1 to LevelShift_M, where M is Integer greater than or equal to 1.
  • the negative voltage generating circuit NVG is connected between the DC power supply NVDD and the ground node, and its output signal NVG_OUT is sent to M level shift units LevelShift_1 ⁇ LevelShift_M, and the M level shift units have M input terminals In_1 ⁇ In_M and 2M
  • the output terminals are respectively the output terminals Outp_1 ⁇ Outp_M and the output terminals Outn_1 ⁇ Outn_M; each level shift unit is connected between the DC power supply SVDD and the output terminal of the NVG.
  • the input terminals In_1 to In_M of the M level shifting units may be at the ground level or the positive level.
  • the output terminals Outp_1 to Outp_M are converted to another positive level, and the output terminals Outn_1 to Outn_M is converted to negative level.
  • FIG. 1b is a schematic diagram of a level shift unit circuit in the related art.
  • a level shift unit in the level shift unit circuit is used as an example for illustration.
  • the level shift unit includes: a first inverter P1 and 8 metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor, MOS transistors); wherein, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the sixth MOS transistor M6 are PMOS transistors.
  • the MOS transistor M1, the second MOS transistor M2, the seventh MOS transistor M7 and the eighth MOS transistor M8 are NMOS transistors; In is the input end of the level shift unit, and Outn and Outp are the output ends of the level shift unit.
  • the first inverter P1 is used to receive the input signal In and output an inverted signal; the gate of the third MOS transistor M3 is connected to the input end of the first inverter P1, and the fourth MOS transistor M4 The gate is connected to the output end of the first inverter P1, the source of the third MOS transistor M3 and the source of the fourth MOS transistor M4 are connected to the DC power supply SVDD; the drain of the fourth MOS transistor M4 is connected to the sixth MOS transistor The source of M6 is connected, the drain of the third MOS transistor M3 is connected to the source of the fifth MOS transistor M5, the drain of the fifth MOS transistor M5, the drain of the seventh MOS transistor M7 and the output terminal Outn are connected; The drain of the MOS transistor M6, the drain of the eighth MOS transistor M8 and the output terminal Outp are connected; the gate of the fifth MOS transistor M5, the gate of the sixth MOS transistor M6, the gate of the seventh MOS transistor M7 and the eighth The gate of
  • the VNEG terminal is generally connected to the output terminal of the negative voltage generating circuit NVG.
  • the gate of the fourth MOS transistor M4 is at a low level after passing through the first inverter P1.
  • the voltage between the source and the gate of the transistor M4 is greater than the threshold voltage Vthp of the PMOS transistor, so that the fourth MOS transistor M4 is turned on;
  • the conduction of the fourth MOS transistor M4 will raise the source voltage of the sixth MOS transistor M6, because The gate of the sixth MOS transistor M6 is grounded, so the voltage between the source and the gate of the sixth MOS transistor M6 is greater than the PMOS transistor threshold voltage Vthp, so that the sixth MOS transistor M6 is turned on;
  • the fourth MOS transistor M4 and the sixth The conduction of the MOS transistor M6 raises the drain voltage of the eighth MOS transistor M8 again, and when the VNEG terminal is at a negative level, due to the gap between the gate of the eighth MOS transistor M8 and the source of the second MO
  • the resistance or turn off the capacitor in this way, a certain voltage is shared between the gate and the source of the eighth MOS transistor M8, and this voltage is higher than the NMOS threshold voltage Vthn and is sufficient to turn on the eighth MOS transistor M8. Further, the first MOS transistor M1 and the second MOS transistor M2 are initially in an off state, and the current path formed by the conduction of the fourth MOS transistor M4, the sixth MOS transistor M6 and the eighth MOS transistor M8 is effective for the first MOS transistor M1.
  • the gate is charged, so that the first MOS transistor M1 is turned on, and the conduction of the first MOS transistor M1 pulls down the gate voltage of the second MOS transistor M2 and the source voltage of the seventh MOS transistor M7 to the negative level VNEG, so that the first MOS transistor M1 is turned on.
  • the second MOS transistor M2 is turned off, and because the gate of the seventh MOS transistor M7 is at the ground level, the voltage between the source and the gate of the seventh MOS transistor M7 is greater than the NMOS transistor threshold voltage Vthn, thereby turning on the seventh MOS transistor tube M7, so the output signal Outn is pulled down to the negative level VNEG, and the output signal Outp is the positive level SVDD; similarly, when the input signal In is the ground level, the output voltage signal Outp is the negative level VNEG, and the output voltage signal Outn It is a positive level SVDD; from the working principle of the above circuit analysis, it can be seen that the negative voltage level conversion control circuit realizes the logic level from the ground level GND to the positive level SVDD, and converts it to the negative level VNEG to the positive level SVDD. the logic level.
  • each path is instantaneously turned on during the level switching process, that is, there is a leakage path from the positive level SVDD to the negative level VNEG; in addition, this conversion method is between SVDD and VNEG.
  • conversion that is, the conversion between positive voltage and negative voltage; due to the large span from positive voltage to negative voltage, more charges are consumed in the process of instantaneous conduction, and there will be a voltage at the output terminal of the negative voltage generating circuit. The risk of being pulled high, which in turn affects the performance of subsequent circuits.
  • Figure 1c is a schematic diagram of the voltage change at the output terminal of the negative voltage generation circuit during level switching in the related art.
  • the horizontal axis represents the time t, and the unit is us;
  • the vertical axis represents the output terminal voltage of the negative voltage generation circuit, VNEG, in the unit is V; it can be seen that during the conduction process of the negative voltage generating circuit, that is, when the output voltage VNEG of the negative voltage generating circuit is from zero level to -2.5V, the voltage is pulled up from -2V to -0.8V That is, there is a risk of pulling up the output terminal voltage of the negative voltage generating circuit during level switching, however, the pulling up of the output terminal voltage of the negative voltage generating circuit will affect the performance of the subsequent circuits.
  • the VNEG terminal of the level shift unit circuit is the ground level GND.
  • VNEG changes from the ground level to the negative level, which will also shift the level.
  • the MOS tube in the unit circuit has the risk of overvoltage.
  • FIG. 2 is a schematic diagram of a negative voltage level shift control circuit according to an embodiment of the present application.
  • the negative voltage level shift control circuit includes: a negative voltage generation circuit 200 , a bias circuit 201 and a level shifter Unit circuit 202; wherein, the output end of the bias circuit 201 is connected to the level shift unit circuit 202, and the other end of the bias circuit 201 is connected to the output end of the negative pressure generating circuit 200; the output end of the negative pressure generating circuit 200 is connected to the electrical
  • the level shift unit circuit 202 is connected; the bias circuit 201 is configured to receive an enable signal and output a bias voltage; the bias voltage is used to control the switching process of the level shift unit circuit 202;
  • the negative pressure generating circuit 200 is enabled.
  • the negative voltage generating circuit provides the level shift unit circuit with a negative level for level switching, wherein the magnitude of the negative level can be set according to the actual application, for example, -2.5V, -3V, etc.; limit.
  • the level shift unit circuit is composed of at least one level shift unit; wherein, one end of each level shift unit is connected to the DC power supply for power supply, and the other end is connected to the output end of the negative voltage generating circuit;
  • the level shift unit circuit is composed of a plurality of level shift units
  • the level shift unit circuit includes a branch circuit that is connected in parallel by the plurality of level shift units.
  • the enable signal is similar to a trigger signal, and when the enable signal enables the related circuit, it will control the related circuit to enable certain functions, thereby ensuring the normal operation of the related circuit.
  • the enable signal when the enable signal enables the bias circuit, the voltage dividing function of the bias circuit is turned on; when the enable signal enables the negative voltage generating circuit, the negative voltage of the negative voltage generating circuit is turned on produce function.
  • one end of the bias circuit is connected to a DC power supply, and the DC power supply is used to pull up the bias voltage before the bias circuit is enabled.
  • the DC power supply before the bias circuit is enabled, that is, when the enable signal has not entered the bias circuit, the DC power supply can not only supply power to the bias circuit, but also can pull up the bias voltage at the output end of the bias circuit . Since the output end of the bias circuit is connected to the level shift unit circuit, before the bias circuit is enabled, if the bias voltage at the output end of the bias circuit is pulled up, the gate of the NMOS transistor in the level shift unit circuit can be increased. The voltage difference with the source stage accelerates the discharge speed to the ground, thereby shortening the instantaneous turn-on time during the level conversion process, that is, speeding up the switching speed of the level shift unit circuit.
  • one end of the level shift unit circuit is connected to a DC power supply; here, the bias circuit and the level shift unit circuit may be connected to the same DC power supply for power supply, or may be connected to different DC power supplies for power supply; Set according to the actual application scenario, which is not limited in this embodiment of the present application.
  • the supply voltages of the two may be the same or different.
  • a 3V DC power supply A and a 3V DC power supply B can be used to supply power to the bias circuit and the level shift unit circuit, respectively; or a 3V DC power supply A and a 5V DC power supply C can be used to power the bias circuit and the level shifter circuit, respectively.
  • Bit cell circuits are powered.
  • the bias voltage at the output end of the bias circuit can be pulled up to 3V to speed up the discharge speed of the level shift unit circuit to ground.
  • the bias circuit is configured to divide the voltage between the DC power supply and the output terminal of the negative voltage generating circuit to obtain the bias voltage.
  • the bias voltage output by the bias circuit realizes adaptive follow-up according to the voltage between the DC power supply and the output terminal of the negative voltage generating circuit; when the voltage division ratio of the bias circuit is known In the case of , the bias voltage can be obtained according to the voltage between the DC power supply and the output terminal of the negative voltage generating circuit.
  • the voltage dividing ratio may be determined according to the actual circuit structure of the bias circuit; in the case of different circuit structures, the voltage dividing ratio may be 1/2, 1/3, 3/4, etc.; the embodiment of the present application does not limit it.
  • the voltage difference between the DC power supply and the output terminal of the negative voltage generating circuit is 5.5V, when When the voltage division ratio of the bias circuit is 1/2, the voltage division of the bias circuit is 2.75V, and the corresponding bias voltage obtained is 0.25V.
  • the negative voltage level shift control circuit further includes: a first delay unit; an input end of the first delay unit is configured to receive an enable signal, and an output end of the first delay unit is connected to the negative voltage generating circuit connect.
  • the enable signal enables the negative pressure generating circuit after being delayed by the first delay unit; that is, the first delay unit can delay the time when the enable signal enables the negative pressure generating circuit; for example , when the delay time of the first delay unit is 10us, the enable signal enables the negative pressure generating circuit after a delay of 10us.
  • the negative voltage level shift control circuit further includes: a second delay unit, wherein the delay time of the first delay unit is greater than that of the second delay unit; the input end of the second delay unit is configured as After receiving the enable signal, the output end of the second delay unit is connected to the bias circuit.
  • the enable signal enables the bias circuit after being delayed by the second delay unit; that is, the second delay unit may delay the time when the enable signal enables the bias circuit;
  • the enable signal enables the negative pressure generating circuit after a delay of 5us.
  • the enable signal since the delay time of the first delay unit is greater than that of the second delay unit, that is, the enable signal first enables the bias circuit, and then enables the negative voltage generating circuit.
  • the enable signal may directly enable the bias circuit without passing through the second delay unit, or enable the bias circuit after being delayed by the second delay unit.
  • the delay time of the first delay unit may be twice that of the second delay unit.
  • the enable signal enables the bias circuit after a delay of 5us, and after a delay of 10us After the delay, the negative pressure generating circuit is enabled.
  • the corresponding relationship between the delay time of the first delay unit and the second delay unit can be adjusted according to the actual circuit structure, as long as the delay time of the first delay unit is greater than that of the second delay unit. The embodiment is not limited.
  • the first delay unit and the second delay unit may be composed of one or more delay units; the circuit structure of the delay unit may be composed of resistors and capacitors, or may be other components; the embodiments of the present application are not limited.
  • the output of the negative voltage generating circuit is the ground level; since the bias circuit can The voltage between the connected DC power supply and the ground level of the output terminal of the negative voltage generating circuit is divided, thereby effectively reducing the overvoltage risk that may exist in the level shift unit circuit after the negative voltage generating circuit is enabled.
  • the present application provides a negative voltage level shift control circuit and method.
  • the negative voltage level shift control circuit includes: a negative voltage generating circuit, a bias circuit and a level shift unit circuit; wherein the output end of the bias circuit is connected to the The level shift unit circuit is connected, and the other end is connected with the negative pressure generating circuit; the output end of the negative pressure generating circuit is connected with the level shifting unit circuit; the bias circuit is configured to receive the enable signal and output the bias voltage; the bias voltage Used to control the switching process of the level shift unit circuit; the enable signal is used to enable the bias circuit and the negative voltage generating circuit.
  • the speed of the level shift unit circuit discharging to the ground is accelerated, the instantaneous conduction time during the level conversion process is shortened, and further, the level shift unit is accelerated.
  • Switching speed; the timing control of the enable signal reduces the charge consumption of the negative voltage generating circuit and reduces the risk of the voltage at the output terminal of the negative voltage generating circuit being pulled up; at the same time, the control of the bias voltage at the output terminal of the bias circuit This effectively reduces the risk of overvoltage in the level shift unit circuit when the negative voltage generating circuit operates.
  • FIG. 3a is a schematic diagram of another negative voltage level conversion control circuit according to an embodiment of the application.
  • the circuit includes: a first delay unit Delay1, a second delay unit Delay2, and a negative voltage generating circuit NVG , the bias circuit Block_Vbias and the level shift unit circuit LevelShift.
  • the DC power supply NVDD and the DC power supply SVDD supply power to the negative voltage generation circuit NVG and the level shift unit circuit LevelShift respectively; En is the enable signal, Vbias is the output end of the bias circuit, In is the input end of the level shift unit circuit LevelShift, Outn And Outp is the output terminal of the level shift unit circuit LevelShift.
  • the input end of the first delay unit Delay1 is configured to receive the enable signal En, and the output end of the first delay unit Delay1 is connected to the negative pressure generating circuit NVG.
  • the input end of the second delay unit Delay2 is configured to receive the enable signal En, and the output end of the second delay unit Delay2 is connected to the bias circuit Block_Vbias.
  • the output end of the bias circuit Block_Vbias is connected to the level shift unit circuit LevelShift, and the other end is connected to the negative voltage generating circuit NVG.
  • the output terminal of the negative voltage generating circuit NVG is connected to the level shift unit circuit LevelShift.
  • the bias circuit Block_Vbias is configured to receive the enable signal En and output the bias voltage; the bias voltage can be used to control the switching process of the level shift unit circuit LevelShift, and at the same time realize adaptive following during the switching process; the enable signal En is used for Enable the bias circuit Block_Vbias and the negative voltage generating circuit NVG.
  • the negative voltage generating circuit NVG represents the negative voltage generating circuit 200
  • the bias circuit Block_Vbias represents the bias circuit 201
  • the level shift unit circuit LevelShift represents the level shift unit circuit 202 .
  • FIG. 3b is a schematic diagram of a level shift unit circuit according to an embodiment of the present application.
  • a level shift unit in the level shift unit circuit is used as an example for description.
  • FIG. 1b it can be seen that in FIG. The gate of the seventh MOS transistor M7 and the gate of the eighth MOS transistor M8 are connected to the ground in common; while the gate of the seventh MOS transistor M7 and the gate of the eighth MOS transistor M8 in FIG. 3b in the embodiment of the present application are biased The output terminals of the circuit are connected in common.
  • FIG. 3c is a schematic diagram of a bias circuit according to an embodiment of the application.
  • the bias circuit includes: a second inverter P2, a first resistor R1, a second resistor R2, and a ninth MOS transistor M9 ⁇ The seventeenth MOS transistor; wherein, the eleventh MOS transistor M11, the twelfth MOS transistor M12, the fourteenth MOS transistor M14, the fifteenth MOS transistor M15, the sixteenth MOS transistor M16 and the seventeenth MOS transistor M17 are PMOS transistors, the ninth MOS transistor M9, the tenth MOS transistor M10 and the thirteenth MOS transistor M13 are NMOS transistors; In is the input end of the level shift unit, and Outn and Outp are the output ends of the level shift unit.
  • the DC power supply SVDD and the negative level VNEG provide the level shift unit with a positive level and a negative level, respectively.
  • the second inverter P2 is used to receive the enable signal En and output an inverted signal; the gates of the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16 are connected to the gate of the second inverter P2 The output end, the gate of the seventeenth MOS transistor M17 is connected to the input end of the second inverter P2, the source of the fifteenth MOS transistor M15, the source of the sixteenth MOS transistor M16 and the seventeenth MOS transistor M17
  • the source of the MOS transistor M16 is connected to the DC power supply SVDD; the drain of the sixteenth MOS transistor M16, the drain of the thirteenth MOS transistor M13 and the gate of the thirteenth MOS transistor M13 are connected in common; the source of the thirteenth MOS transistor M13 is connected to the drain of the tenth MOS transistor M10; the drain of the fifteenth MOS transistor M15 is connected to the drain of the ninth MOS transistor M9, the gate of the ninth MOS transistor M9, and the drain of the
  • the gates are connected in common; the source of the tenth MOS transistor M10, the source of the twelfth MOS transistor M12 and the output terminal Vbias of the bias circuit are connected; the source of the ninth MOS transistor M9 and the source of the eleventh MOS transistor M11 Connection; the gate of the eleventh MOS transistor M11, the drain of the eleventh MOS transistor M11 and the gate of the twelfth MOS transistor M12 are connected; the drain of the eleventh MOS transistor M11 is connected to VNEG through the second resistor R2 terminal; the drain of the twelfth MOS transistor M12 is connected to the source of the fourteenth MOS transistor M14; the drain and gate of the fourteenth MOS transistor M14 are connected to the VNEG terminal.
  • the enable signal En enables the bias circuit Block_Vbias after the delay of the second delay unit Delay2, and adjusting the voltage divider ratio in the bias circuit Block_Vbias can make the potential of the output terminal Vbias of the bias circuit Block_Vbias according to the The voltage difference between SVDD and VNEG realizes adaptive follow-up; here, the voltage division ratio is taken as an example of 1/2.
  • the VNEG terminal is the ground level GND, so the bias circuit Block_Vbias outputs
  • the terminal Vbias is switched to SVDD/2, which avoids the risk of overvoltage in the level shift unit circuit caused by the drop of the VNEG terminal from the ground level to the negative level after the negative voltage generating circuit NVG is enabled; After the delay, the negative voltage generating circuit NVG is enabled, the VNEG terminal is switched to the negative level, and the output terminal Vbias of the bias circuit Block_Vbias also drops with the negative level VNEG.
  • FIG. 3d is a schematic diagram of the timing waveform of the negative voltage level shift control circuit in the level shift process provided by the embodiment of the application.
  • the enable signal En the input terminal En_Vbias of the bias circuit, and the input terminal En_NVG of the negative voltage generating circuit are low level;
  • the output terminal Vbias of the bias circuit Block_Vbias is high level, and the negative voltage generating circuit NVG makes the output terminal VNEG ground level;
  • the delay unit Delay2 only the enable signal En is at a high level, and the levels of other ports remain unchanged; in the second delay unit Delay2, the delay D2 ends, and the first delay unit Delay1 is delayed.
  • the input terminal En_Vbias of the bias circuit Block_Vbias is high level; the output terminal Vbias of the bias circuit Block_Vbias is half of the high level, and the voltage divider ratio of the bias circuit is taken as an example;
  • the output terminal VNEG of the negative pressure generating circuit NVG is at a negative level; the level of the output terminal Vbias of the bias circuit Block_Vbias decreases together with the output terminal VNEG of the negative pressure generating circuit NVG.
  • the bias voltage output by the bias circuit realizes adaptive follow-up according to the voltage difference between the positive voltage and the negative voltage.
  • the level shift unit circuit first performs the positive level to the ground level domain The conversion between the positive level and the negative level domain is completed, which reduces the charge consumption of the negative voltage generating circuit, reduces the risk of the voltage at the output terminal of the negative voltage generating circuit being pulled up, and can ensure the performance of the subsequent circuit.
  • An embodiment of the present application also provides a negative voltage level shift control method, which is characterized in that, when applied to a negative voltage level shift control circuit, the negative voltage level shift control circuit includes: a negative voltage generation circuit, a bias circuit, and a power supply circuit.
  • a level shift unit circuit wherein the output end of the bias circuit is connected with the level shift unit circuit, and the other end is connected with the negative pressure generating circuit; the output end of the negative pressure generating circuit is connected with the level shift unit circuit; the method includes:
  • the bias circuit receives an enable signal and outputs a bias voltage; the bias voltage is used to control the switching process of the level shift unit circuit; the enable signal is used to enable the bias circuit and the negative voltage generating circuit.
  • circuit structure diagram of the level shift unit circuit proposed in the embodiment of the present application is not limited to the circuit structure shown in FIG. 3b above, but also applicable to the circuit structures of other level shift unit circuits; in the embodiment of the present application
  • the circuit structure diagram of the proposed bias circuit is not limited to the circuit structure shown in FIG. 3c above, but is also applicable to circuit structures of other bias circuits; the embodiments of the present application are not limited.

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Abstract

本申请提供了一种负压电平转换控制电路和方法，所述负压电平转换控制电路包括：负压产生电路、偏置电路和电平移位单元电路；其中，所述偏置电路的输出端与所述电平移位单元电路连接，另一端与所述负压产生电路连接；所述负压产生电路的输出端与所述电平移位单元电路连接；所述偏置电路配置为接收使能信号，输出偏置电压；所述偏置电压用于控制所述电平移位单元电路的切换过程；所述使能信号用于对所述偏置电路和所述负压产生电路使能。

Description

一种负压电平转换控制电路和方法
相关申请的交叉引用
本申请基于申请号为202010970861.8、申请日为2020年09月15日的中国专利申请提出，申请人为广州慧智微电子有限公司，申请名称为“一种负压电平转换控制电路和方法”的技术方案，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及集成电路技术，尤其涉及一种负压电平转换控制电路和方法。
背景技术
负压电平转换控制电路是集成电路***中非常常见的电路模块，其主要功能是实现不同电平间的转换，包括正压到正压或正压到负压的转换，如从1.8V到3.3V或2.5V到-2.5V的转换等。
相关技术中，负压电平转换控制电路包括负压产生电路和电平移位单元电路，其中电平移位单元电路的输入端可以为零电平或正电平，以输入正电平为例，则输出端被转换为另一正电平和负电平。然而，该电平转换方式在切换过程中每条通路都存在瞬时导通的情况，即存在正压到负压的漏电通路；此外，由于正压到负压的跨度较大，所以在瞬时导通的过程中消耗的电荷数较多，会存在将负压产生电路输出端电压拉高的风险，进而影响后续电路的性能。
发明内容
本申请提供一种负压电平转换控制电路和方法。
本申请的技术方案是这样实现的：
本申请提供一种负压电平转换控制电路，所述负压电平转换控制电路 包括：负压产生电路、偏置电路和电平移位单元电路；其中，所述偏置电路的输出端与所述电平移位单元电路连接，另一端与所述负压产生电路连接；所述负压产生电路的输出端与所述电平移位单元电路连接；
所述偏置电路配置为接收使能信号，输出偏置电压；所述偏置电压用于控制所述电平移位单元电路的切换过程；所述使能信号用于对所述偏置电路和所述负压产生电路使能。
在一些实施例中，所述负压电平转换控制电路还包括：第一延时单元；
所述第一延时单元的输入端配置为接收所述使能信号，所述第一延时单元的输出端与所述负压产生电路连接。
在一些实施例中，所述负压电平转换控制电路还包括：第二延时单元，其中，所述第一延时单元的延时时间大于所述第二延时单元；
所述第二延时单元的输入端配置为接收所述使能信号，所述第二延时单元的输出端与所述偏置电路连接。
在一些实施例中，所述偏置电路的一端连接直流电源，所述直流电源用于在所述偏置电路使能前，拉高所述偏置电压。
在一些实施例中，所述电平移位单元电路的一端连接所述直流电源。
在一些实施例中，在所述偏置电路使能后，所述偏置电路配置为对所述直流电源与所述负压产生电路输出端之间的电压进行分压，得到偏置电压。
本申请还提供一种负压电平转换控制方法，其特征在于，应用于负压电平转换控制电路中，所述负压电平转换控制电路包括：负压产生电路、偏置电路和电平移位单元电路；其中，所述偏置电路的输出端与所述电平移位单元电路连接，另一端与所述负压产生电路连接；所述负压产生电路的输出端与所述电平移位单元电路连接；
所述方法包括：
所述偏置电路接收使能信号，输出偏置电压；所述偏置电压用于控制 所述电平移位单元电路的切换过程；所述使能信号用于对所述偏置电路和所述负压产生电路使能。
在一些实施例中，所述偏置电路的一端连接直流电源，所述方法还包括：
所述直流电源在所述偏置电路使能前，拉高所述偏置电压。
在一些实施例中，所述方法还包括：
在所述偏置电路使能后，所述偏置电路对所述直流电源与所述负压产生电路输出端之间的电压进行分压，得到偏置电压。
本申请提供了一种负压电平转换控制电路和方法，所述负压电平转换控制电路包括：负压产生电路、偏置电路和电平移位单元电路；其中，所述偏置电路的输出端与所述电平移位单元电路连接，另一端与所述负压产生电路连接；所述负压产生电路的输出端与所述电平移位单元电路连接；所述偏置电路配置为接收使能信号，输出偏置电压；所述偏置电压用于控制所述电平移位单元电路的切换过程；所述使能信号用于对所述偏置电路和所述负压产生电路使能。如此，通过加入控制电平移位单元电路的偏置电路，使电平移位单元电路对地放电的速度加快，缩短了电平转换过程中瞬时导通的时间，进而，加快了电平移位单元的切换速度；对使能信号的时序控制，减小了对负压产生电路电荷的消耗，降低负压产生电路输出端电压被拉高的风险；同时，对偏置电路输出端偏置电压的控制有效地将降低了负压产生电路工作时导致电平移位单元电路存在的过压风险。
附图说明
图1a为相关技术中负压电平转换控制电路的结构示意图；
图1b为相关技术中电平移位单元电路的示意图；
图1c为相关技术中电平切换时负压产生电路输出端电压变化的示意图；
图2为本申请实施例的一种负压电平转换控制电路的示意图；
图3a为本申请实施例的另一种负压电平转换控制电路的示意图；
图3b为本申请实施例的一种电平移位单元电路的示意图；
图3c为本申请实施例的一种偏置电路的示意图；
图3d为本申请实施例提供的负压电平转换控制电路在电平转换过程的时序波形示意图。
具体实施方式
以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
集成电路在运行过程中，对于不同的应用场景一般需要不同的电压。例如在高速芯片接口电路中，不同电平域间是不能直接互联的，需要相应的电平转换电路进行连接。
图1a为相关技术中负压电平转换控制电路的结构示意图，如图1a所示，负压电平转换控制电路包括：负压产生电路NVG和M个电平移位单元LevelShift_1～LevelShift_M，M为大于或等于1的整数。其中，负压产生电路NVG连接在直流电源NVDD与地节点之间，其输出信号NVG_OUT发送至M个电平移位单元LevelShift_1～LevelShift_M，M个电平移位单元具有M个输入端In_1～In_M和2M个输出端，分别为输出端Outp_1～Outp_M和输出端Outn_1～Outn_M；每个电平移位单元接在直流电源SVDD与NVG的输出端之间。
这里，M个电平移位单元输入端In_1～In_M可以为地电平或正电平，以输入正电平为例，则输出端Outp_1～Outp_M被转换为另一正电平，输出端Outn_1～Outn_M被转换为负电平。
图1b为相关技术中电平移位单元电路的示意图，如图1b所示，以电平移位单元电路中的一个电平移位单元为例进行说明，电平移位单元包括：第一反相器P1和8个金属氧化物半导体场效应晶体管(Metal Oxide  Semiconductor，MOS管)；其中，第三MOS管M3、第四MOS管M4、第五MOS管M5和第六MOS管M6为PMOS管，第一MOS管M1、第二MOS管M2、第七MOS管M7和第八MOS管M8为NMOS管；In为电平移位单元的输入端，Outn和Outp为电平移位单元的输出端。
图1b可以看出，第一反相器P1用于接收输入信号In并输出反相信号；第三MOS管M3的栅极连接在第一反相器P1的输入端，第四MOS管M4的栅极连接在第一反相器P1的输出端，第三MOS管M3的源极和第四MOS管M4的源极连接至直流电源SVDD；第四MOS管M4的漏极与第六MOS管M6的源极连接，第三MOS管M3的漏极与第五MOS管M5的源极连接，第五MOS管M5的漏极、第七MOS管M7的漏极和输出端Outn连接；第六MOS管M6的漏极、第八MOS管M8的漏极和输出端Outp连接；第五MOS管M5的栅极、第六MOS管M6的栅极、第七MOS管M7的栅极和第八MOS管M8的栅极与地共接；第七MOS管M7的源极、第二MOS管M2的栅极和第一MOS管M1的漏极共接；第八MOS管M8的源极、第一MOS管M1的栅极和第二MOS管M2的漏极共接；第一MOS管M1和第二MOS管M2的源极与VNEG端连接。
这里，VNEG端一般接到负压产生电路NVG的输出端，当输入信号In为正电平时，经过第一反相器P1后使第四MOS管M4的栅极为低电平，由于第四MOS管M4的源极和栅极之间的电压大于PMOS管阈值电压Vthp，使得第四MOS管M4导通；第四MOS管M4的导通会抬高第六MOS管M6的源极电压，由于第六MOS管M6的栅极接地，所以第六MOS管M6的源极和栅极之间的电压大于PMOS管阈值电压Vthp，使得第六MOS管M6导通；第四MOS管M4和第六MOS管M6的导通又抬高了第八MOS管M8的漏极电压，并且，在VNEG端为负电平时，由于第八MOS管M8的栅极和第二MOS管M2的源极之间的电压为地电平GND与负电平VNEG之差，从而使第八MOS管M8的栅极和源极之间等效为电容，第二MOS 管M2的漏极和源极之间等效为导通电阻或者关断电容；这样，第八MOS管M8的栅极和源极之间会分担一定电压，且这个电压高于NMOS阈值电压Vthn，并足以使第八MOS管M8导通。进一步地，第一MOS管M1和第二MOS管M2初始处于关断状态，第四MOS管M4、第六MOS管M6和第八MOS管M8导通形成的电流通路对第一MOS管M1的栅极充电，使得第一MOS管M1导通，第一MOS管M1的导通将第二MOS管M2的栅极电压和第七MOS管M7的源级电压拉低到负电平VNEG，使第二MOS管M2关断，同时由于第七MOS管M7的栅极为地电平，所以第七MOS管M7的源极和栅极之间的电压大于NMOS管阈值电压Vthn，从而导通第七MOS管M7，所以输出信号Outn被拉低为负电平VNEG，而输出信号Outp为正电平SVDD；同理，当输入信号In为地电平时，输出电压信号Outp为负电平VNEG，输出电压信号Outn为正电平SVDD；从上述电路分析的工作原理可知，该负压电平转换控制电路实现了将地电平GND到正电平SVDD的逻辑电平，转换为负电平VNEG到正电平SVDD的逻辑电平。
相关技术中，这种转换方式在电平切换过程中每条通路都存在瞬时导通的情况，即，存在正电平SVDD到负电平VNEG的漏电通路；另外，该转换方式是SVDD和VNEG间的转换，即，正压到负压间的转换；由于正压到负压的跨度较大，所以在瞬时导通的过程中消耗的电荷数较多，会存在将负压产生电路输出端电压拉高的风险，进而影响后续电路的性能。
图1c为相关技术中电平切换时负压产生电路输出端电压变化的示意图，如图1c所示，横轴代表时间t，单位为us；纵轴代表负压产生电路输出端电压VNEG，单位为V；可以看出，负压产生电路在导通过程中，即，负压产生电路输出端电压VNEG从零电平到-2.5V的过程中，电压从-2V被拉高到-0.8V；即，电平切换时存在将负压产生电路输出端电压拉高的风险，然而，负压产生电路输出端电压被拉高会影响后续电路的性能。
同时，在负压产生电路使能前，电平移位单元电路的VNEG端为地电 平GND，当负压产生电路使能后，VNEG由地电平变为负电平，也会使电平移位单元电路中的MOS管存在过压风险。
针对以上技术的缺陷以及应用场景，提出以下实施例。
图2为本申请实施例的一种负压电平转换控制电路的示意图，如图2所示，该负压电平转换控制电路包括：负压产生电路200、偏置电路201和电平移位单元电路202；其中，偏置电路201的输出端与电平移位单元电路202连接，偏置电路201的另一端与负压产生电路200的输出端连接；负压产生电路200的输出端与电平移位单元电路202连接；偏置电路201配置为接收使能信号，输出偏置电压；偏置电压用于控制电平移位单元电路202的切换过程；使能信号用于对偏置电路201和负压产生电路200使能。
这里，负压产生电路为电平移位单元电路提供进行电平切换的负电平，其中，负电平的大小可以根据实际应用情况进行设置，例如，-2.5V、-3V等；本申请实施例不作限制。
本申请实施例中，电平移位单元电路由至少一个电平移位单元组成；其中，每个电平移位单元的一端连接直流电源进行供电，另一端与负压产生电路的输出端连接；在电平移位单元电路由多个电平移位单元组成的情况下，电平移位单元电路包括一条由多个电平移位单元并联的支路。
在一些实施例中，使能信号类似于一个触发信号，当使能信号对相关电路使能时，会控制相关电路开启某些功能，进而，能够确保相关电路的正常运行。
本申请实施例中，当使能信号对偏置电路使能时，会开启偏置电路的分压功能；当使能信号对负压产生电路使能时，会开启负压产生电路的负压产生功能。
在一些实施例中，偏置电路的一端连接直流电源，直流电源用于在偏置电路使能前，拉高偏置电压。
本申请实施例中，在偏置电路使能前，即，使能信号还未进入偏置电 路时，直流电源除了对偏置电路进行供电外，还可以拉高偏置电路输出端的偏置电压。由于偏置电路输出端与电平移位单元电路连接，因而，在偏置电路使能前，如果偏置电路输出端的偏置电压被拉高，可以增大电平移位单元电路中NMOS管栅极和源级的电压差，使对地放电的速度加快，从而缩短电平转换过程中瞬时导通的时间，即加快了电平移位单元电路的切换速度。
在一些实施例中，电平移位单元电路的一端连接直流电源；这里，偏置电路与电平移位单元电路可以连接至同一个直流电源进行供电，也可以连接至不同的直流电源进行供电；可以根据实际应用场景进行设置，本申请实施例不作限制。
进一步地，在偏置电路与电平移位单元电路连接至不同直流电源的情况下，两者的供电电压可以相同，也可以不同。例如，可以通过3V的直流电源A和3V的直流电源B分别为偏置电路与电平移位单元电路供电；也可以通过3V的直流电源A和5V的直流电源C分别为偏置电路与电平移位单元电路供电。
在一些实施例中，在偏置电路使能前，若连接3V的直流电源A，则偏置电路输出端的偏置电压可以被拉高至3V以加快电平移位单元电路的对地放电速度。
在一些实施例中，在偏置电路使能后，偏置电路配置为对直流电源与负压产生电路输出端之间的电压进行分压，得到偏置电压。
本申请实施例中，在偏置电路使能后，偏置电路输出的偏置电压根据直流电源与负压产生电路输出端之间的电压实现自适应跟随；在偏置电路分压比已知的情况下，可以根据直流电源与负压产生电路输出端之间的电压，得到偏置电压。
这里，分压比可以根据偏置电路的实际电路结构进行确定；在电路结构不同的情况下，分压比可以为1/2、1/3、3/4等；本申请实施例不作限制。
在一些实施例中，假设偏置电路连接的直流电源为3V，负压产生电路输出端的负压为-2.5V，则直流电源与负压产生电路输出端之间的电压差为5.5V，当偏置电路分压比为1/2时，偏置电路的分压为2.75V，对应得到的偏置电压为0.25V。
在一些实施例中，负压电平转换控制电路还包括：第一延时单元；第一延时单元的输入端配置为接收使能信号，第一延时单元的输出端与负压产生电路连接。
本申请实施例中，使能信号经过第一延时单元的延时后对负压产生电路使能；即，第一延时单元可以延迟使能信号对负压产生电路使能的时间；例如，在第一延时单元的延时时间为10us的情况下，使能信号经过10us的延时后对负压产生电路使能。
在一些实施例中，负压电平转换控制电路还包括：第二延时单元，其中，第一延时单元的延时时间大于第二延时单元；第二延时单元的输入端配置为接收使能信号，第二延时单元的输出端与偏置电路连接。
本申请实施例中，使能信号经过第二延时单元的延时后对偏置电路使能；即，第二延时单元可以延迟使能信号对偏置电路使能的时间；例如，在第二延时单元的延时时间为5us的情况下，使能信号经过5us的延时后对负压产生电路使能。
本申请实施例中，由于第一延时单元的延时时间大于第二延时单元，即，使能信号先对偏置电路使能，再对负压产生电路使能。其中，使能信号可以不经过第二延时单元直接对偏置电路使能，或经过第二延时单元的延时后对偏置电路使能。
在一些实施例中，第一延时单元的延时时间可以为第二延时单元的2倍。例如，在第一延时单元的延时时间为10us、第二延时单元的延时时间为5us的情况下，使能信号经过5us的延时后对偏置电路使能，并经过10us的延时后对负压产生电路使能。这里，对于第一延时单元和第二延时单元 延时时间的对应关系可以根据实际电路结构进行调整，只要满足第一延时单元的延时时间大于第二延时单元即可，本申请实施例不作限制。
在一些实施例中，第一延时单元和第二延时单元可以由一个或多个延时单元组合而成；对于延时单元的电路结构，可以是电阻和电容组成的，也可以是其它器件组成的；本申请实施例不作限制。
在一些实施例中，在使能信号对偏置电路使能，且未对负压产生电路使能的情况下，负压产生电路输出为地电平；由于偏置电路根据分压比可以对其连接的直流电源与负压产生电路输出端地电平之间的电压进行分压，进而，有效降低负压产生电路使能后，电平移位单元电路可能存在的过压风险。
本申请提供了一种负压电平转换控制电路和方法，负压电平转换控制电路包括：负压产生电路、偏置电路和电平移位单元电路；其中，偏置电路的输出端与所述电平移位单元电路连接，另一端与负压产生电路连接；负压产生电路的输出端与电平移位单元电路连接；偏置电路配置为接收使能信号，输出偏置电压；偏置电压用于控制电平移位单元电路的切换过程；使能信号用于对偏置电路和负压产生电路使能。如此，通过加入控制电平移位单元电路的偏置电路，使电平移位单元电路对地放电的速度加快，缩短了电平转换过程中瞬时导通的时间，进而，加快了电平移位单元的切换速度；对使能信号的时序控制，减小了对负压产生电路电荷的消耗，降低负压产生电路输出端电压被拉高的风险；同时，对偏置电路输出端偏置电压的控制有效地将降低了负压产生电路工作时导致电平移位单元电路存在的过压风险。
为了能够更加体现本申请的目的，在本申请上述实施例的基础上，进行进一步的举例说明。
图3a为本申请实施例的另一种负压电平转换控制电路的示意图，如图3a所示，该电路包括：第一延时单元Delay1、第二延时单元Delay2、负压 产生电路NVG、偏置电路Block_Vbias和电平移位单元电路LevelShift。直流电源NVDD和直流电源SVDD分别给负压产生电路NVG和电平移位单元电路LevelShift供电；En为使能信号，Vbias为偏置电路输出端，In为电平移位单元电路LevelShift的输入端，Outn和Outp为电平移位单元电路LevelShift的输出端。
其中，第一延时单元Delay1的输入端配置为接收使能信号En，第一延时单元Delay1的输出端与负压产生电路NVG连接。第二延时单元Delay2的输入端配置为接收使能信号En，第二延时单元Delay2的输出端与偏置电路Block_Vbias连接。偏置电路Block_Vbias的输出端与电平移位单元电路LevelShift连接，另一端与负压产生电路NVG连接。负压产生电路NVG的输出端与电平移位单元电路LevelShift连接。
偏置电路Block_Vbias配置为接收使能信号En，输出偏置电压；偏置电压可以用于控制电平移位单元电路LevelShift的切换过程，同时在切换过程中实现自适应跟随；使能信号En用于对偏置电路Block_Vbias和负压产生电路NVG使能。
这里，负压产生电路NVG表示上述负压产生电路200，偏置电路Block_Vbias表示上述偏置电路201，电平移位单元电路LevelShift表示上述电平移位单元电路202。
图3b为本申请实施例的一种电平移位单元电路的示意图，这里，以电平移位单元电路中的一个电平移位单元为例进行说明，结合图1b，可以看出，图1b中第七MOS管M7的栅极和第八MOS管M8的栅极与地共接；而本申请实施例的图3b中第七MOS管M7的栅极和第八MOS管M8的栅极与偏置电路的输出端共接。
图3c为本申请实施例的一种偏置电路的示意图，如图3c所示，该偏置电路包括：第二反相器P2、第一电阻R1、第二电阻R2、第九MOS管M9～第十七MOS管；其中，第十一MOS管M11、第十二MOS管M12、第十 四MOS管M14、第十五MOS管M15、第十六MOS管M16和第十七MOS管M17为PMOS管，第九MOS管M9、第十MOS管M10和第十三MOS管M13为NMOS管；In为电平移位单元的输入端，Outn和Outp为电平移位单元的输出端。直流电源SVDD和负电平VNEG分别为电平移位单元提供正电平和负电平。
图3c可以看出，第二反相器P2用于接收使能信号En并输出反相信号；第十五MOS管M15和第十六MOS管M16的栅极连接在第二反相器P2的输出端，第十七MOS管M17的栅极连接在第二反相器P2的输入端，第十五MOS管M15的源极、第十六MOS管M16的源极和第十七MOS管M17的源极连接至直流电源SVDD；第十六MOS管M16的漏极、第十三MOS管M13的漏极和第十三MOS管M13的栅极共接；第十三MOS管M13的源极与第十MOS管M10的漏极连接；第十五MOS管M15的漏极经第一电阻R1与第九MOS管M9的漏极、第九MOS管M9的栅极、第十MOS管M10的栅极共接；第十MOS管M10的源极、第十二MOS管M12的源极和偏置电路输出端Vbias连接；第九MOS管M9的源极与第十一MOS管M11的源极连接；第十一MOS管M11的栅极、第十一MOS管M11的漏极和第十二MOS管M12的栅极连接；第十一MOS管M11的漏极经第二电阻R2连接至VNEG端；第十二MOS管M12的漏极与第十四MOS管M14的源极连接；第十四MOS管M14的漏极和栅极连接至VNEG端。
结合图3a-图3c，可以看出，在偏置电路Block_Vbias使能前，偏置电路Block_Vbias中的第十七MOS管M17的栅极为低电平，使第十七MOS管M17导通，偏置电路Block_Vbias输出端Vbias被拉高为SVDD，相比于图1b中电平移位单元中第七MOS管M7和第八MOS管M8的栅极为地电平GND的情况，本申请实施例中的电平移位单元中第七MOS管M7和第八MOS管M8的栅极为高电平SVDD，由于栅极和源级的电压差更大加快了对地放电的速度，从而缩短转换过程中瞬时导通的时间；而后使能信 号En经过第二延时单元Delay2的延时后将偏置电路Block_Vbias使能，调整偏置电路Block_Vbias中的分压比可以使偏置电路Block_Vbias输出端Vbias的电位根据SVDD与VNEG间的电压差实现自适应跟随；这里，分压比以1/2为例，由于此时负压产生电路NVG未使能，VNEG端为地电平GND，所以偏置电路Block_Vbias输出端Vbias切换为SVDD/2，避免了负压产生电路NVG使能后，VNEG端从地电平下降到负电平导致电平移位单元电路存在过压的风险；再经过第一延时单元Delay1的延时后，负压产生电路NVG使能，VNEG端切换为负电平，同时偏置电路Block_Vbias输出端Vbias也随着负电平VNEG一起下降。
图3d为本申请实施例提供的负压电平转换控制电路在电平转换过程的时序波形示意图，如图3d所示，在偏置电路Block_Vbias和负压产生电路NVG使能前，使能信号En、偏置电路输入端En_Vbias、负压产生电路输入端En_NVG为低电平；偏置电路Block_Vbias输出端Vbias为高电平，负压产生电路NVG使输出端VNEG为地电平；当第二延时单元Delay2延时D2的过程中，只有使能信号En为高电平，其余端口的电平保持不变；在第二延时单元Delay2延时D2结束，且第一延时单元Delay1延时D1未结束的时间段内，偏置电路Block_Vbias输入端En_Vbias为高电平；偏置电路Block_Vbias输出端Vbias为高电平的一半，这里偏置电路分压比以1/2为例；在第一延时单元Delay1延时D1结束后，负压产生电路NVG输出端VNEG为负电平；偏置电路Block_Vbias输出端Vbias电平随着负压产生电路NVG输出端VNEG一起降低。
在整个电平切换过程中，偏置电路输出的偏置电压根据正压与负压间的电压差实现自适应跟随，在此过程中电平移位单元电路先进行正电平到地电平域间的转换，再完成正电平到负电平域间的转换，减小了对负压产生电路电荷的消耗，降低负压产生电路输出端电压被拉高的风险，能够确保后续电路的性能。
本申请实施例还提供一种负压电平转换控制方法，其特征在于，应用于负压电平转换控制电路中，负压电平转换控制电路包括：负压产生电路、偏置电路和电平移位单元电路；其中，偏置电路的输出端与所述电平移位单元电路连接，另一端与负压产生电路连接；负压产生电路的输出端与电平移位单元电路连接；方法包括：
偏置电路接收使能信号，输出偏置电压；偏置电压用于控制电平移位单元电路的切换过程；使能信号用于对偏置电路和负压产生电路使能。
需要说明的是，本申请实施例中提出的电平移位单元电路的电路结构图不仅限于上述图3b所记载的电路结构，还适用于其它电平移位单元电路的电路结构；本申请实施例中提出的偏置电路的电路结构图不仅限于上述图3c所记载的电路结构，还适用于其它偏置电路的电路结构；本申请实施例不作限制。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (9)

  1. 一种负压电平转换控制电路，所述负压电平转换控制电路包括：负压产生电路、偏置电路和电平移位单元电路；其中，所述偏置电路的输出端与所述电平移位单元电路连接，另一端与所述负压产生电路连接；所述负压产生电路的输出端与所述电平移位单元电路连接；
    所述偏置电路配置为接收使能信号，输出偏置电压；所述偏置电压用于控制所述电平移位单元电路的切换过程；所述使能信号用于对所述偏置电路和所述负压产生电路使能。
  2. 根据权利要求1所述的电路，所述负压电平转换控制电路还包括：第一延时单元；
    所述第一延时单元的输入端用于接收所述使能信号，所述第一延时单元的输出端与所述负压产生电路连接。
  3. 根据权利要求2所述的电路，所述负压电平转换控制电路还包括：第二延时单元，其中，所述第一延时单元的延时时间大于所述第二延时单元；
    所述第二延时单元的输入端用于接收所述使能信号，所述第二延时单元的输出端与所述偏置电路连接。
  4. 根据权利要求1所述的电路，所述偏置电路的一端连接直流电源，所述直流电源用于在所述偏置电路使能前，拉高所述偏置电压。
  5. 根据权利要求4所述的电路，所述电平移位单元电路的一端连接所述直流电源。
  6. 根据权利要求5所述的电路，在所述偏置电路使能后，所述偏置电路配置为对所述直流电源与所述负压产生电路输出端之间的电压进行分压，得到偏置电压。
  7. 一种负压电平转换控制方法，应用于负压电平转换控制电路中，所 述负压电平转换控制电路包括：负压产生电路、偏置电路和电平移位单元电路；其中，所述偏置电路的输出端与所述电平移位单元电路连接，另一端与所述负压产生电路连接；所述负压产生电路的输出端与所述电平移位单元电路连接；
    所述方法包括：
    所述偏置电路接收使能信号，输出偏置电压；所述偏置电压用于控制所述电平移位单元电路的切换过程；所述使能信号用于对所述偏置电路和所述负压产生电路使能。
  8. 根据权利要求7所述的方法，所述偏置电路的一端连接直流电源，所述方法还包括：
    所述直流电源在所述偏置电路使能前，拉高所述偏置电压。
  9. 根据权利要求8所述的方法，所述方法还包括：
    在所述偏置电路使能后，所述偏置电路对所述直流电源与所述负压产生电路输出端之间的电压进行分压，得到偏置电压。
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CN110868201A (zh) * 2019-12-05 2020-03-06 深圳能芯半导体有限公司 低功耗快响应电平变换电路
CN112202440A (zh) * 2020-09-15 2021-01-08 广州慧智微电子有限公司 一种负压电平转换控制电路和方法

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