WO2023143568A1 - 显示面板、显示模组及显示装置 - Google Patents

显示面板、显示模组及显示装置 Download PDF

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Publication number
WO2023143568A1
WO2023143568A1 PCT/CN2023/073704 CN2023073704W WO2023143568A1 WO 2023143568 A1 WO2023143568 A1 WO 2023143568A1 CN 2023073704 W CN2023073704 W CN 2023073704W WO 2023143568 A1 WO2023143568 A1 WO 2023143568A1
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Prior art keywords
display area
sub
pixel
display panel
layer
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PCT/CN2023/073704
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English (en)
French (fr)
Inventor
肖邦清
王本莲
李正坤
郑海
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/554,961 priority Critical patent/US20240196689A1/en
Publication of WO2023143568A1 publication Critical patent/WO2023143568A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/82—Interconnections, e.g. terminals

Definitions

  • the present application relates to the field of display technology, in particular to a display panel, a display module and a display device.
  • OLED display panels have been widely used due to their advantages of self-illumination, low driving voltage, and fast response speed.
  • An OLED display panel generally includes: a plurality of pixel units, each pixel unit includes a light emitting device and a pixel circuit connected to the light emitting device.
  • the application provides a display panel, a display module, and a display device, and the technical solutions are as follows:
  • a display panel is provided, and the display panel includes:
  • a base substrate having a first display area, and a second display area at least partially surrounding the first display area
  • the driving circuit layer located on one side of the base substrate, the driving circuit layer including a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area;
  • the first electrode layer at least includes a plurality of first-type electrode patterns, the plurality of first-type electrode patterns include a plurality of first electrode patterns located in the first display area, and located in the first display area a plurality of second electrode patterns in the second display area;
  • At least two of the first electrode patterns are connected to one of the plurality of first pixel circuits, and at least two of the second electrode patterns are connected to one of the plurality of second pixel circuits.
  • the second pixel circuit is connected.
  • the display panel also includes:
  • a plurality of first connecting wires, the plurality of first connecting wires are located in the first display area;
  • the plurality of second connection wirings extend from the second display area to the first display area along the pixel row direction, and are located between the first display area and the second display area display area;
  • a plurality of third connecting wires, the plurality of third connecting wires are located in the second display area;
  • At least two of the first electrode patterns are connected by one of the first connecting lines, and one of the first electrode patterns in at least two of the first electrode patterns is connected by one of the second connecting lines connected to one of the first pixel circuits, at least two of the second electrode patterns are connected through one of the third connecting wires, and one of the at least two second electrode patterns is connected to the second electrode pattern One of the second pixel circuits is connected.
  • the display panel further includes a plurality of fourth connection lines and a plurality of fifth connection lines, and the plurality of fourth connection lines and the plurality of fifth connection lines are all along the pixel
  • the row direction extends from the second display area to the first display area
  • the first electrode layer further includes a plurality of second-type electrode patterns and a plurality of third-type electrode patterns
  • the plurality of second-type electrode patterns include a plurality of third electrode patterns located in the first display area, and a plurality of fourth electrode patterns located in the second display area, and the third electrode patterns pass through a
  • the fourth connection wiring is connected to one of the first pixel circuits, and the fourth electrode pattern is connected to one of the second pixel circuits;
  • the plurality of third-type electrode patterns include a plurality of fifth electrode patterns located in the first display area, and a plurality of sixth electrode patterns located in the second display area; the fifth electrode patterns pass through the The fifth connecting wire is connected to one of the first pixel circuits.
  • two adjacent first pixel circuits and three second pixel circuits form a circuit group; at least two second electrode patterns form an electrode pattern group, and one adjacent electrode pattern A group, one of the fourth electrode patterns and one of the sixth electrode patterns constitutes a pattern group;
  • each of the pattern groups corresponds to one of the circuit groups, and for the corresponding pattern group and the circuit group, the area where the orthographic projection of the pattern group on the base substrate is located, There is an overlap with the area where the orthographic projection of the circuit group on the base substrate is located.
  • the first second pixel circuit is the same as the pattern group.
  • the second second pixel circuit is connected with the fourth electrode pattern in the pattern group
  • the third second pixel circuit is connected with the sixth electrode pattern in the pattern group connect.
  • the two first pixel circuits included in a part of the circuit groups in the display panel are connected to the electrode patterns located in the first display area, and the two first pixel circuits included in another part of the circuit groups in the display panel
  • the first pixel circuit is connected to a fixed voltage terminal.
  • the circuit group to which the first pixel circuit connected to the electrode pattern of the first display area belongs is closer to the first display than the circuit group to which the first pixel circuit connected to the fixed voltage terminal belongs. district.
  • the display panel includes red sub-pixels, green sub-pixels and blue sub-pixels, the sub-pixels to which the first type of electrode pattern belongs are green sub-pixels, and the sub-pixels to which the second type of electrode pattern belongs are For red sub-pixels, the sub-pixels to which the third type of electrode pattern belongs are blue sub-pixels.
  • the length of any of the second connecting lines along the direction of the pixel row is less than the length of the fourth connecting line along the direction of the pixel row, and is shorter than the length of the fifth connecting line along the direction of the pixel row.
  • the length of the pixel row direction is less than the length of the fourth connecting line along the direction of the pixel row, and is shorter than the length of the fifth connecting line along the direction of the pixel row.
  • the connecting wires are along The length in the row direction of the pixel is positively related to the distance between the electrode pattern in the first display region connected to the connection line and the second display region along the row direction of the pixel.
  • the second display area includes a first sub-display area, a second sub-display area and a third sub-display area, and the first sub-display area and the first display area are arranged along the pixel column direction, The second sub-display area and the first display area are arranged along the pixel row direction, the third sub-display area and the first sub-display area are arranged along the pixel row direction, and the The second sub-display area is arranged along the direction of the pixel column;
  • the display panel further includes: a plurality of first data lines located in the first sub-display area, a plurality of second data lines located in the second sub-display area and the third sub-display area, and a plurality of second data lines located in the second sub-display area and the third sub-display area, and A plurality of first transfer lines for the first sub-display area and the third sub-display area;
  • the plurality of first data lines are arranged along the pixel row direction and extend along the pixel column direction
  • the plurality of A second data line is arranged along the direction of the pixel row and extends along the direction of the pixel column
  • the plurality of first transfer lines are arranged along the direction of the pixel column and extend along the direction of the pixel row;
  • each of the first data lines is used to connect with the data driving circuit, and each of the first data lines
  • the second end of the data line is connected to the first end of one of the first transfer lines, and the second end of each of the first transfer lines is connected to the first end of one of the second data lines; wherein, each The first data line is also connected to a column of second pixel circuits located in the first sub-display area for connecting to the first target electrode pattern, and each of the second data lines is also connected to a row of second pixel circuits located in the second sub-display area.
  • a column of first pixel circuits in the region is connected to a second target electrode pattern; the first target electrode pattern is at least one of a fourth electrode pattern and a sixth electrode pattern, and the second target electrode pattern is at least One of the third electrode pattern and the fifth electrode pattern.
  • the first target electrode pattern is a fourth electrode pattern or a sixth electrode pattern
  • the second target electrode pattern is a third electrode pattern or a fifth electrode pattern
  • the display panel further includes: A plurality of third data lines in the first sub-display area, and a plurality of fourth data lines located in the second sub-display area and the third sub-display area;
  • the plurality of third data lines are arranged along the pixel row direction and extend along the pixel column direction, the first end of each third data line is used to connect with a data driving circuit, and each of the third data lines
  • the third data line is also connected to a column of second pixel circuits located in the first sub-display area for connecting to the second electrode pattern;
  • the plurality of fourth data lines are arranged along the direction of the pixel row and extend along the direction of the pixel column, the first end of each of the fourth data lines is used to connect with a data driving circuit, and each of the fourth data lines
  • the fourth data line is also connected to a column of first pixel circuits located in the second sub-display area for connecting to the first electrode pattern.
  • the second display area further includes: a fourth sub-display area and a fifth sub-display area, the fourth sub-display area is located on a side of the first display area away from the first sub-display area , the fifth sub-display area and the fourth sub-display area are arranged along the pixel row direction; the plurality of second data lines are also located in the fifth sub-display area; the display panel further includes: A plurality of second transfer lines, and a plurality of fifth data lines located in the fourth sub-display area;
  • the plurality of fifth data lines are arranged along the direction of the pixel row and extend along the direction of the pixel column, and the plurality of second transfer lines are arranged along the direction of the pixel row and extend along the direction of the pixel row;
  • the second end of each second data line is connected to the first end of a second transfer line, and the second end of each second transfer line is connected to the first end of the fifth data line.
  • the fifth data line is also connected to a column of second pixel circuits located in the fourth sub-display area for connecting to the first target electrode pattern.
  • the display panel further includes: a plurality of first dummy numbers located in the third sub-display area According to the line;
  • the plurality of first dummy data lines are arranged along the pixel row direction and extend along the pixel column direction, the first dummy data lines are used to connect to a fixed voltage terminal, and the first dummy data lines also It is connected with a column of first pixel circuits located in the third sub-display area.
  • the second display area further includes: a sixth sub-display area, the sixth sub-display area is located on a side of the third sub-display area away from the first sub-display area; the display panel It also includes: a plurality of seventh data lines located in the sixth sub-display area, and a plurality of second dummy data lines located in the sixth sub-display area;
  • the plurality of seventh data lines are arranged along the pixel row direction and extend along the pixel column direction, each of the seventh data lines is used to connect with a data driving circuit, and each of the seventh data lines is also connected to a column of second pixel circuits located in the sixth sub-display area;
  • the plurality of second dummy data lines are arranged along the pixel row direction and extend along the pixel column direction, each of the second dummy data lines is used to connect to a fixed voltage terminal, and the second dummy data lines
  • the wire is also connected to a column of first pixel circuits located in the sixth display area.
  • the third connecting wiring is located on the same layer as the first electrode layer, and the first connecting wiring and the second connecting wiring are both located on the driving circuit layer and the first electrode layer. between layers.
  • a display module in another aspect, includes a data driving circuit and the display panel as described in the above aspect;
  • the data driving circuit is connected to the first data line, the third data line, the fourth data line and the seventh data line in the display panel.
  • a display device in yet another aspect, includes the display module and the optical sensor described in the above aspects, the orthographic projection of the optical sensor on the display panel and the first display of the display panel The regions at least partially overlap.
  • FIG. 1 is a schematic diagram of a partial structure of a display panel provided by an embodiment of the present application
  • FIG. 2 is a partially enlarged schematic diagram of the display panel shown in FIG. 1;
  • Fig. 3 is a top view of a base substrate provided by an embodiment of the present application.
  • FIG. 4 is a partial cross-sectional view of a display panel provided by an embodiment of the present application.
  • Fig. 5 is a partial schematic diagram of a first electrode layer in a second display area provided by an embodiment of the present application
  • Fig. 6 is a partial schematic diagram of a first electrode layer in a first display area provided by an embodiment of the present application.
  • Fig. 7 is a partial schematic diagram of a first pattern row in a first display area provided by an embodiment of the present application.
  • Fig. 8 is a schematic diagram of a partial structure of another display panel provided by an embodiment of the present application.
  • FIG. 9 is a partially enlarged schematic diagram of the display panel shown in FIG. 8;
  • FIG. 10 is a schematic diagram of a data line, an adapter line and a dummy data line of a display panel provided by an embodiment of the present application;
  • Fig. 11 is a schematic diagram of another display panel data line, transfer line and dummy data line provided by the embodiment of the present application;
  • Fig. 12 is a schematic diagram of a display panel in which no first pixel circuit is designed according to an embodiment of the present application
  • FIG. 13 is a schematic design diagram of a pixel circuit with two voltages and one voltage provided by an embodiment of the present application.
  • Fig. 14 is a schematic diagram of a circuit group provided by an embodiment of the present application.
  • Fig. 15 is a schematic diagram of another circuit group provided by the embodiment of the present application.
  • FIG. 16 is an equivalent circuit diagram of a first pixel circuit or a second pixel circuit provided by an embodiment of the present application.
  • Fig. 17 is a partial schematic diagram of a semiconductor layer in a display panel provided by an embodiment of the present application.
  • FIG. 18 is a partial schematic diagram of a first gate layer in a display panel provided by an embodiment of the present application.
  • FIG. 19 is a partial superimposed schematic diagram of a semiconductor layer and a first gate layer in a display panel provided by an embodiment of the present application;
  • FIG. 20 is a partial schematic diagram of a second gate layer in a display panel provided by an embodiment of the present application.
  • FIG. 21 is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, and a second gate layer in a display panel provided by an embodiment of the present application;
  • Fig. 22 is a partial schematic diagram of an interlayer dielectric layer in a display panel provided by an embodiment of the present application.
  • FIG. 23 is a partially superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer and an interlayer dielectric layer in a display panel provided by an embodiment of the present application;
  • Fig. 24 is a partial schematic diagram of the first source and drain layers in a display panel provided by an embodiment of the present application picture
  • FIG. 25 is a partially superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, and a first source-drain layer in a display panel provided by an embodiment of the present application;
  • Fig. 26 is a partial schematic diagram of a passivation layer in a display panel provided by an embodiment of the present application.
  • Fig. 27 is a partial superposition of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer and a passivation layer in a display panel according to an embodiment of the present application.
  • Fig. 28 is a partial schematic diagram of an intermediate source and drain layer in a display panel provided by an embodiment of the present application.
  • Fig. 29 is a semiconductor layer in a display panel provided by an embodiment of the present application, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source and drain layer, a passivation layer and an intermediate source Schematic diagram of partial overlay of the drain layer;
  • Fig. 30 is a partial schematic diagram of a first flat layer in a display panel provided by an embodiment of the present application.
  • Fig. 31 is a semiconductor layer in a display panel provided by an embodiment of the present application, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source and drain layer, a passivation layer, and an intermediate source Schematic diagram of partial superimposition of the drain layer and the first flat layer;
  • Fig. 32 is a partial schematic diagram of a second source and drain layer in a display panel provided by an embodiment of the present application.
  • Figure 33 is a semiconductor layer in a display panel provided by an embodiment of the present application, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source and drain layer, a passivation layer, and an intermediate source Schematic diagram of local overlay of the drain layer, the first planar layer and the second source-drain layer;
  • Fig. 34 is a partial schematic diagram of a second flat layer in a display panel provided by an embodiment of the present application.
  • Fig. 35 is a semiconductor layer in a display panel provided by an embodiment of the present application, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source and drain layer, a passivation layer, and an intermediate source Schematic diagram of local overlay of the drain layer, the first planar layer, the second source-drain layer and the second planar layer;
  • Fig. 36 is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present application.
  • Fig. 37 is a partial schematic diagram of a first conductive layer in a display panel provided by an embodiment of the present application.
  • Fig. 38 is a partial superimposed schematic diagram after the first conductive layer is formed in the display panel provided by the embodiment of the present application;
  • Fig. 39 is a partial schematic diagram of a first insulating layer in a display panel provided by an embodiment of the present application.
  • Fig. 40 is a partial stack after forming the first insulating layer in the display panel provided by the embodiment of the present application. Add schematic diagram;
  • Fig. 41 is a partial schematic diagram of a second conductive layer in a display panel provided by an embodiment of the present application.
  • Fig. 42 is a partial superimposed schematic diagram after the second conductive layer is formed in the display panel provided by the embodiment of the present application;
  • Fig. 43 is a partial schematic diagram of a second insulating layer in a display panel provided by an embodiment of the present application.
  • Fig. 44 is a partial superimposed schematic diagram after forming a second insulating layer in a display panel according to an embodiment of the present application.
  • Fig. 45 is a partial schematic diagram of a third conductive layer in a display panel provided by an embodiment of the present application.
  • Fig. 46 is a partial superimposed schematic diagram after forming a third conductive layer in a display panel according to an embodiment of the present application.
  • Fig. 47 is a partial schematic diagram of a third insulating layer in a display panel provided by an embodiment of the present application.
  • Fig. 48 is a partial superimposed schematic diagram after forming a third insulating layer in a display panel according to an embodiment of the present application.
  • Fig. 49 is a partial schematic diagram of a first electrode layer in a display panel provided by an embodiment of the present application.
  • Fig. 50 is a partial superimposed schematic diagram after forming a first electrode layer in a display panel according to an embodiment of the present application
  • Fig. 51 is a partial schematic diagram of a pixel defining layer in a display panel provided by an embodiment of the present application.
  • Fig. 52 is a partial superimposed schematic diagram after forming a pixel defining layer in a display panel according to an embodiment of the present application
  • Fig. 53 is a partial schematic diagram of a conductive layer in a display panel provided by an embodiment of the present application.
  • Fig. 54 is a schematic structural diagram of a display module provided by an embodiment of the present application.
  • FIG. 55 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the camera of the display device in order to increase the screen-to-body ratio of the display panel, can be arranged in the display area of the display panel.
  • the pixel circuit of each pixel unit in the area where the camera is located ie, the camera area
  • the pixel circuit located in the non-camera area is connected to the light-emitting element located in the camera area through connecting wires. connected, so as to provide a driving signal for the light-emitting element located in the camera area, so as to drive the light-emitting element to emit light.
  • the pixel circuits connected to the light-emitting elements in the camera area need to be designed in the non-camera area, it may result in more pixel circuits that need to be designed in the non-camera area, which will cause the space occupied by each pixel circuit to be too small. Difficult to prepare.
  • the embodiment of the present application provides a display panel, which can be, for example, an organic light-emitting diode (organic light-emitting diode, OLED) display panel, a micro organic light-emitting diode (micro organic light-emitting diode, Micro OLED) display panel, Quantum dot light emitting diodes (quantum dot light emitting diodes, QLED) display panel, mini light-emitting diode (mini light-emitting diode, Mini LED) display panel or micro light-emitting diode (micro light-emitting diode, Micro LED) display panel etc.
  • OLED organic light-emitting diode
  • Micro OLED micro organic light-emitting diode
  • Quantum dot light emitting diodes quantum dot light emitting diodes
  • mini light-emitting diode mini light-emitting diode, Mini LED
  • micro light-emitting diode micro light-emitting diode, Micro LED
  • FIG. 1 is a schematic diagram of a partial structure of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a partially enlarged schematic view of the display panel shown in FIG. 1 .
  • Fig. 3 is a top view of a base substrate provided by an embodiment of the present application.
  • FIG. 4 is a partial cross-sectional view of a display panel provided by an embodiment of the present application.
  • the display panel 10 may include a base substrate 101 , a driving circuit layer 102 located on one side of the base substrate 101 , and a first electrode layer 103 .
  • the base substrate 101 has a first display area 101a, and a second display area 101b at least partially surrounding the first display area 101a.
  • the first display area 101a may be an under-display camera area (full display with camera, FDC).
  • the first display area 101a is a circular area or a square area.
  • the driving circuit layer 102 includes a plurality of first pixel circuits A1 and a plurality of second pixel circuits A2 located in the second display area 101b. 3 shows a first pixel circuit A1 and a second pixel circuit A2.
  • the first electrode layer 103 includes at least a plurality of first-type electrode patterns 1031, and the plurality of first-type electrode patterns 1031 include a plurality of first electrode patterns 1031a located in the first display area 101a, and a plurality of electrode patterns located in the second display area 101b.
  • the display panel 10 includes a plurality of sub-pixels of different colors, each sub-pixel can be a light-emitting device and a pixel circuit that controls the light-emitting device to emit light, the brightness (gray scale) of the sub-pixels of different colors can be adjusted through the pixel circuit, and multiple colors can be realized through color combination and superposition.
  • the display of different colors can realize the full-color display of the display panel 10 .
  • the light emitting device may include an electrode pattern.
  • the colors of light emitted by the sub-pixels to which the plurality of first-type electrode patterns 1031 belong may be the same.
  • At least two first electrode patterns 1031a are connected to one first pixel circuit A1 among the plurality of first pixel circuits A1.
  • one first pixel circuit A1 can provide data driving signals for two first electrode patterns 1031a.
  • at least two second electrode patterns 1031b are connected to one second pixel circuit A2 among the plurality of second pixel circuits A2.
  • one second pixel circuit A2 can provide data driving signals for two second electrode patterns 1031b.
  • At least two first electrode patterns 1031a in the first display area 101a can be driven by a first pixel circuit A1 located in the second display area 101b, and at least two of the first electrode patterns 1031a in the second display area 101b
  • the second electrode pattern 1031b can be driven by a second pixel circuit A2 located in the second display area 101b. Therefore, when the number of electrode patterns is the same, the scheme of using one pixel circuit to drive two electrode patterns can reduce the required design in the second display area 101b compared to the scheme of using one pixel circuit to drive one electrode pattern.
  • the number of pixel circuits can increase the space that each pixel circuit can occupy, and the manufacturing process is less difficult.
  • the embodiment of the present application provides a display panel, since at least two first electrode patterns in the display panel are connected, and one first electrode pattern of the at least two connected first electrode patterns is connected to one first electrode pattern.
  • the pixel circuits are connected so that one first pixel circuit can drive two first electrode patterns.
  • at least two second electrode patterns are connected, and one second electrode pattern in the connected at least two second electrode patterns is connected to one second pixel circuit, one second pixel circuit can drive two second pixel circuits. electrode pattern. Therefore, when the number of electrode patterns is the same, the scheme of driving two electrode patterns with one pixel circuit can reduce the number of pixel circuits that need to be designed in the second display area, and further increase the number of pixel circuits required for each pixel circuit. It can occupy less space, and the difficulty of process preparation is relatively low.
  • the portion of the base substrate 101 and the driving circuit layer 102 located in the first display region 101 a has higher light transmittance.
  • the base substrate 101 may be a transparent glass substrate, which provides high transparency.
  • the driving circuit layer 102 does not set a circuit structure in the first display area 101a (that is, the first pixel circuit A1 and the second pixel circuit A2 are both arranged in the second display area 101b, but not in the first display area 101a), and keep driving The circuit layer 102 is sufficiently transparent.
  • the side of the base substrate 101 away from the driving circuit layer 102 can be provided with sensors, such as optical sensors such as cameras, proximity light sensors, and 3D sensing modules, and the orthographic projection of the sensor on the base substrate 101 is located at the first Display area 101a.
  • the light-sensing surface of the optical sensor faces the display surface side of the display panel 10 for receiving ambient light on the display surface side of the display panel 10 .
  • the first electrode layer 103 located in the first display area 101a The first electrode pattern 1031a is made of transparent conductive materials, such as indium tin oxide (ITO) and indium zinc oxide (IZO), so that the light transmittance of the first display area 101a is relatively high, which is suitable for placing cameras and other transmittance requirements. high devices.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the display panel 10 can realize full-screen display in the display area.
  • An optical sensor is arranged in the first display area 101a, and the optical sensor can receive external light through the film layer in
  • the display panel 10 may further include: multiple first connecting wires L1 , multiple second connecting wires L2 and multiple third connecting wires L3 .
  • a plurality of first connecting wires L1 are located in the first display area 101a.
  • a plurality of second connection wires L2 extend from the second display area 101b to the first display area 101a along the pixel row direction X, and are located in the first display area 101a and the second display area 101b.
  • a plurality of third connecting wires L3 are located in the second display area 101b.
  • At least two first electrode patterns 1031a are connected by a first connection line L1, and one first electrode pattern 1031a of the at least two first electrode patterns 1031a is connected to a first pixel circuit A1 by a second connection line L2 connect.
  • one first pixel circuit A1 can provide data driving signals for two first electrode patterns 1031a.
  • at least two second electrode patterns 1031b are connected through a third connection line L3, and one second electrode pattern 1031b of the at least two second electrode patterns 1031b is connected to a second pixel circuit A2.
  • one second pixel circuit A2 can provide data driving signals for two second electrode patterns 1031b.
  • the display panel 10 further includes a plurality of fourth connecting wires L4 and a plurality of fifth connecting wires L5 . Both the plurality of fourth connection lines L4 and the plurality of fifth connection lines L5 extend along the pixel row direction X from the second display area 101b to the first display area 101a.
  • the first electrode layer 103 further includes a plurality of second-type electrode patterns 1032 and a plurality of third-type electrode patterns 1033 .
  • the plurality of second-type electrode patterns 1032 includes a plurality of third electrode patterns 1032a located in the first display area 101a, and a plurality of fourth electrode patterns 1032b located in the second display area 101b.
  • the plurality of third-type electrode patterns 1033 includes a plurality of fifth electrode patterns 1033a located in the first display area 101a, and a plurality of sixth electrode patterns 1033b located in the second display area 101b.
  • the third electrode pattern 1032a is connected to a first pixel circuit A1 through a fourth connection line L4, and the fourth electrode pattern 1032b is connected to a second pixel circuit A2.
  • the fifth electrode pattern 1033a is connected to a first pixel circuit A1 through a fifth connection line L5, and the sixth electrode pattern 1033b is connected to a second pixel circuit A2. That is, each of the plurality of third electrode patterns 1032a and the plurality of fifth electrode patterns 1033a is driven by a first pixel circuit A1. multiple fourth electricity Each electrode pattern of the pole pattern 1032b and the plurality of sixth electrode patterns 1033b is driven by a second pixel circuit A2.
  • a plurality of first electrode patterns 1031a, a plurality of third electrode patterns 1032a and a plurality of fifth electrode patterns 1033a can be arranged in multiple rows, arranged in A plurality of electrode patterns in one row is referred to as a first pattern rowM.
  • At least one first pattern row M includes at least two first electrode patterns 1031a, at least one third electrode pattern 1032a, and at least one fifth electrode pattern 1033a arranged in a row.
  • At least two first electrode patterns 1031a in the first pattern row M are connected through a first connecting wire L1.
  • the first pattern row M is circularly arranged in the order of the third electrode pattern 1032a, the first electrode pattern 1031a, the fifth electrode pattern 1033a and the first electrode pattern 1031a.
  • a plurality of first pattern rows M are arranged in multiple rows, and each first pattern row M includes a first sub-pattern row M1 and a second sub-pattern row M2 arranged in parallel.
  • the third electrode patterns 1032a and the fifth electrode patterns 1033a are arranged alternately in the first sub-pattern row M1, and a plurality of first electrode patterns 1031a are arranged in sequence in the second sub-pattern row M2.
  • the number of the first electrode patterns 1031a in the second sub-pattern row M2 is consistent with the total number of the third electrode patterns 1032a and the fifth electrode patterns 1033a in the second sub-pattern row M2, and the first electrode patterns 1031a are arranged on the second sub-pattern row M2. On the central axis of the adjacent third electrode pattern 1032a and fifth electrode pattern 1033a.
  • a plurality of second electrode patterns 1031b, a plurality of fourth electrode patterns 1032b and a plurality of sixth electrode patterns 1033b can be arranged in multiple rows, and electrode patterns arranged in a row are called second patterns. row (not shown in the figure).
  • At least one second pattern row includes at least two second electrode patterns 1031b, at least one fourth electrode pattern 1032b, and at least one sixth electrode pattern 1033b arranged in a row.
  • At least two second electrode patterns 1031b in the second pattern row are connected through a third connecting wire L3.
  • the second pattern row is arranged cyclically in the order of the fourth electrode pattern 1032b, the second electrode pattern 1031b, the sixth electrode pattern 1033b and the second electrode pattern 1031b.
  • a plurality of second pattern rows are arranged in multiple rows, and each second pattern row includes a third sub-pattern row and a fourth sub-pattern row arranged in parallel.
  • the fourth electrode patterns 1032b and the sixth electrode patterns 1033b are arranged alternately in the third sub-pattern row, and a plurality of second electrode patterns 1031b are arranged in sequence in the fourth sub-pattern row.
  • the number of second electrode patterns 1031b in the fourth sub-pattern row is consistent with the total number of fourth electrode patterns 1032b and sixth electrode patterns 1033b in the third sub-pattern row, and the second electrode pattern 1031b is arranged adjacent to it On the central axis of the fourth electrode pattern 1032b and the sixth electrode pattern 1033b.
  • multiple first electrode patterns 1031a, multiple third electrode patterns 1032a and multiple fifth electrode patterns 1033a can also be arranged in multiple columns
  • multiple second electrode patterns 1031b, multiple fourth electrode patterns 1032b and multiple sixth patterns can also be arranged in multiple columns.
  • the manner of arranging multiple columns is similar to the manner of arranging multiple rows, which will not be repeated in this embodiment of the present application.
  • the colors of the light emitted by the sub-pixels belonging to the plurality of second-type electrode patterns 1032 may be the same, and the colors of the light emitted by the sub-pixels belonging to the plurality of third-type electrode patterns 1033 may be the same.
  • the sub-pixels to which the plurality of first-type electrode patterns 1031 belong may be green sub-pixels, and the color of the light emitted by the green sub-pixels is green.
  • the sub-pixels to which the plurality of second-type electrode patterns 1032 belong can be one of red sub-pixels and blue sub-pixels
  • the sub-pixels to which the plurality of third-type electrode patterns 1033 belong can be one of red sub-pixels and blue sub-pixels.
  • the sub-pixels to which the plurality of second-type electrode patterns 1032 belong may be red sub-pixels
  • the sub-pixels to which the plurality of third-type electrode patterns 1032 belong to may be blue sub-pixels.
  • the color of light emitted by the red sub-pixel is red
  • the color of light emitted by the blue sub-pixel is blue. That is, in the embodiment of the present application, one pixel circuit is used to drive two green sub-pixels, and one pixel circuit is used to drive one red sub-pixel or one blue sub-pixel.
  • two adjacent first pixel circuits A1 and three second pixel circuits A2 form a circuit group A.
  • At least two second electrode patterns 1031b constitute an electrode pattern group
  • an adjacent electrode pattern group, a fourth electrode pattern 1032b and a sixth electrode pattern 1033b constitute a pattern group B.
  • Each pattern group B corresponds to a circuit group A, and for the corresponding pattern group B and circuit group A, the area where the orthographic projection of the pattern group B on the base substrate 101 is located is the same as that of the circuit group A on the base substrate The areas where the orthographic projections on 101 are located overlap.
  • the space occupied by the circuit group A (five pixel circuits) is equivalent to the space occupied by the pattern group B (four electrode patterns). That is, five pixel circuits are correspondingly disposed on the lower sides of the four electrode patterns.
  • the first second pixel circuit A2 and the electrode pattern group in the pattern group B are connected to the fourth electrode pattern 1032b in the pattern group B, and the third second pixel circuit A2 is connected to the sixth electrode pattern 1033b in the pattern group B . That is, among the five pixel circuits included in each circuit group A, three of the second pixel circuits A2 can be used as pixel circuits for driving the four electrode patterns in the pattern group B of the second display area 101b.
  • the two first pixel circuits A1 included in a part of the circuit group A in the display panel 10 are connected to the electrode patterns located in the first display area 101a, and the two first pixel circuits A1 included in another part of the circuit group A are connected to the fixed voltage terminal connect. That is, among the circuit groups A of the display panel 10, some circuit groups A The two first pixel circuits A1 in the group A can be used as pixel circuits driving the electrode patterns in the first display area 101a, and the two first pixel circuits A1 in the remaining circuit group A are not connected to the electrode patterns in the first display area 101a, Instead, it is connected to a fixed voltage terminal as a dummy pixel circuit. Since the dummy pixel circuit is connected to the fixed voltage terminal, it can avoid the dummy pixel circuit from affecting the signal transmitted by each signal line in the display panel 10 and ensure the display effect of the display panel 10 .
  • the circuit group A to which the first pixel circuit A1 connected to the electrode pattern of the first display area 101a belongs is closer to the circuit group A to which the first pixel circuit A1 connected to the fixed voltage terminal belongs.
  • a display area 101a A display area 101a.
  • the length of the second connecting wiring L2 used to connect the electrode pattern in the first display area 101a and the first pixel circuit A1 in the second display area 101b can be shortened, and the length of the second connecting wiring L2 can be improved.
  • the reliability of the transmission signal ensures the display effect of the display panel 10 .
  • one first pixel circuit A1 provides data driving signals to two first electrode patterns 1031a, if the second connection line L2 connecting the first pixel circuit A1 and the two first electrode patterns 1031a is longer than It is easy to be affected by resistance-capacitance interference, so that the sub-pixels to which the first electrode pattern 1031a belongs cannot be turned on at low gray levels.
  • the length of any second connecting wire L2 along the pixel row direction X is smaller than the length of the fourth connecting wire L4 along the pixel row direction X, and is shorter than the length of the fifth connecting wire L5 along the pixel row direction X.
  • the length in the row direction X is to say, for the first electrode pattern 1031a relative to the third electrode pattern 1032a and the fifth electrode pattern 1033a, the first electrode pattern 1031a can preferentially pass through the second connection line L2 and the first pixel circuit of the second display area 101b A1 connection.
  • the length of the second connecting wire L2 connected to the first electrode pattern 1031a can be reduced, the resistance-capacitance interference intensity of the second connecting wire L2 can be weakened, and each sub-pixel in the first display area 101a can be ensured It can be displayed normally in low grayscale.
  • each of the multiple second connecting wires L2, the multiple fourth connecting wires L4, and the multiple fifth connecting wires L5 is connected along the direction of the pixel row.
  • the length of X is positively related to the distance between the electrode pattern located in the first display area 101a connected by the connection line along the pixel row direction X and the second display area 101b. That is, the electrode patterns located in the first display area 101a are sequentially connected to the first pixel circuit A1 in the second display area 101b through the second connecting wire L2.
  • the second display area 101b may include a first sub-display area 101b1, a second sub-display area 101b2 and a third sub-display area 101b3.
  • the first sub-display area 101b1 and the first display area 101a are arranged along the pixel column direction Y
  • the second sub-display area 101b2 and the first display area 101a are arranged along the pixel row direction X
  • the third sub-display area 101b3 and the first sub-display area 101b1 are arranged along the pixel row direction X
  • the second display area 101b may include a first sub-display area 101b1, two second sub-display areas 101b2 and two third sub-display areas 101b3.
  • the first sub-display area 101b1 may be located on the lower side of the first display area 101a
  • the two second sub-display areas 101b2 may be respectively located on both sides of the first display area 101a along the pixel row direction X
  • the two third sub-display areas 101b3 It may be located on both sides of the first sub-display region 101b1 along the pixel row direction X.
  • Both the second sub-display area 101b2 and the third sub-display area 101b3 may be transitional display areas of the display panel.
  • the display panel 10 may further include: a plurality of first data lines S1 located in the first sub-display area 101b1, a plurality of second data lines S2 located in the second sub-display area 101b2 and the third sub-display area 101b3, And a plurality of first transfer lines Z1 located in the first sub-display area 101b1 and the third sub-display area 101b3.
  • the multiple first data lines S1 are arranged along the pixel row direction X and extend along the pixel column direction Y
  • the multiple second data lines S2 are arranged along the pixel row direction X and extend along the pixel column direction Y
  • the multiple first data lines S2 are arranged along the pixel row direction X and extend along the pixel column direction Y.
  • the transition line Z1 is arranged along the pixel column direction Y and extends along the pixel row direction X.
  • the first end of each first data line S1 is used to connect to the data driving circuit
  • the second end of each first data line S1 is connected to the first end of a first transfer line Z1, and each first transfer line Z1
  • the second end of is connected to the first end of a second data line S2.
  • the data driving signal provided by the data driving circuit can be transmitted through the first data line S1, the first transfer line Z1 and the second data line S2, and the connected first data line S1, a first transfer line Z1 and the data driving signal transmitted by a second data line S2 are the same.
  • the first end of the second data line S2 is closer to the third sub-display area 101b3 and closer to the boundary of the second sub-display area 101b2.
  • the length of the second data line S2 along the direction Y of the pixel column may be slightly larger than the length of the second sub-display area 101b2 along the direction Y of the pixel column, as long as the first end of the second data line S2 can be located at the third
  • the sub-display area 101b3 can further facilitate the connection between the first end of the second data line S2 located in the third sub-display area 101b3 and the second end of the first transition line Z1 located in the third sub-display area 101b3.
  • Each first data line S1 is also connected to a row of second pixel circuits A2 located in the first sub-display area 101b1 for connecting the first target electrode pattern
  • each second data line S2 is also connected to a row of second pixel circuits A2 located in the second sub-display area 101b2
  • a column of first pixel circuits A1 for connecting to the second target electrode pattern is connected.
  • the first data line S1 is connected to a column of first target electrode patterns through a column of second pixel circuits A2, and A column of second target electrode patterns connected to a column of second data lines S2 through a column of first pixel circuits A1 may be arranged along the pixel column direction Y.
  • the electrode patterns located in the same column in the first display area 101a and the first sub-display area 101b1 can obtain the same data driving signal.
  • the first target electrode pattern is at least one of the fourth electrode pattern 1032b and the sixth electrode pattern 1033b
  • the second target electrode pattern is at least one of the third electrode pattern 1032a and the fifth electrode pattern 1033a. A sort of.
  • the first target electrode pattern is the fourth electrode pattern 1032b or the sixth electrode pattern 1033b
  • the second target electrode pattern is the third electrode pattern 1032a or the fifth electrode pattern 1033a
  • the display panel 10 may further include: a plurality of third data lines S3 located in the first sub-display area 101b1, and a plurality of fourth data lines S4 located in the second display area 101b and the third sub-display area 101b3.
  • the multiple third data lines S3 are arranged along the pixel row direction X and extend along the pixel column direction Y
  • the multiple fourth data lines S4 are arranged along the pixel row direction X and extend along the pixel column direction Y.
  • each third data line S3 and the first end of each fourth data line S4 are used to connect with the data driving circuit.
  • Each third data line S3 is also connected to a column of second pixel circuits A2 located in the first sub-display area 101b1 for connecting to the second electrode pattern 1031b
  • each fourth data line S4 is also connected to a row of second pixel circuits A2 located in the second sub-display area 101b2.
  • a column of first pixel circuits A1 for connecting to the first electrode pattern 1031a is connected.
  • the data driving signal provided by the data driving circuit can be transmitted to a column of second pixel circuits A2 located in the first sub-display area 101b1 through the third data line S3, and then drive a column of second pixel circuits A2 connected to the column of second pixel circuits A2.
  • Two electrode patterns 1031b can be transmitted to a column of first pixel circuits A1 located in the second sub-display area 101b2 through the fourth data line S4, and then drive a column of first electrodes connected to the column of first pixel circuits A1 Pattern 1031a.
  • the data driving signals obtained by the second type of electrode patterns 1032 are transferred and transmitted through the first transfer line Z1.
  • the data driving signals obtained by the third type of electrode patterns 1033 are transferred and transmitted through the first transfer line Z1.
  • the data drive signals obtained by the first type of electrode patterns 1031 are transferred and transmitted through the data lines (the third data line S3 or the fourth data line S4) connected to the data drive circuit. ) transmission without using the first transfer line Z1 to transfer the transmission.
  • the length of the data line connected to the first type of electrode pattern 1031 can be reduced (in the transfer transmission scheme, the length of the data line is the total length of the connected data line and the transfer line), thereby reducing the resistance of the data line and capacitance, increasing the The driving capability of the pixel circuit optimizes the display effect.
  • the second display area 101b may further include: a fourth sub-display area 101b4 and a fifth sub-display area 101b5.
  • the fourth sub-display area 101b4 is located on the side of the first display area 101a away from the first sub-display area 101b1, and the fifth sub-display area 101b5 and the fourth sub-display area 101b4 are arranged along the pixel row direction X.
  • the second display area 101b may include a fourth sub-display area 101b4 and two fifth sub-display areas 101b5, one fourth sub-display area 101b4 may be located on the upper side of the first display area 101a, and two fifth sub-display areas
  • the regions 101b5 are respectively located on both sides of the fourth sub-display region 101b4 along the pixel row direction X.
  • the fifth sub-display area 101b5 may be called a transitional display area.
  • the first display area 101a may be located inside the second display area 101b, and the second display area 101b may completely surround the first display area 101a. Therefore, in order to transmit the data drive signal to the fourth sub-display area 101b4 of the first display area 101a away from the first sub-display area 101b1, the display panel 10 may include: a plurality of second transfer lines Z2, a plurality of third transfer lines Z3, a plurality of fifth data lines S5 and a plurality of sixth data lines S6 located in the fourth sub-display area 101b4.
  • the plurality of fifth data lines S5 are arranged along the pixel row direction X and extend along the pixel column direction Y
  • the plurality of sixth data lines S6 are arranged along the pixel row direction X and extend along the pixel column direction Y.
  • a plurality of second transition lines Z2 are arranged along the pixel column direction Y and extend along the pixel row direction X
  • a plurality of third transition lines Z3 are arranged along the pixel column direction Y and extend along the pixel row direction X.
  • each second data line S2 is connected to the first end of a second transition line Z2, and the second end of each second transition line Z2 is connected to the first end of the fifth data line S5.
  • the fifth data line S5 is also connected to a column of second pixel circuits A2 located in the fourth sub-display area 101b4 for connecting to the first target electrode pattern.
  • the second end of each fourth data line S4 is connected to the first end of a third transition line Z3, and the second end of each third transition line Z3 is connected to the first end of the sixth data line S6.
  • the sixth data line S6 is also connected to a column of second pixel circuits A2 located in the fourth sub-display area 101b4 for connecting to the second electrode pattern 1031b.
  • the data driving circuit can sequentially pass through the first data line S1, the first transition line Z1, the second data line S2, the second transition line Z2 and the fifth data line S5 to the fourth sub-display area 101b4 for connecting A column of second pixel circuits A2 of the first target electrode pattern provides data driving signals.
  • the data drive circuit provides data drive signals to a column of second pixel circuits A2 in the fourth sub-display area 101b4 for connecting to the second electrode pattern 1031b through the fourth data line S4, the third transition line Z3 and the sixth data line S6 in sequence. . That is, in this solution, each of the second pixel circuits A2 in the fourth sub-display area 101b4 needs to obtain the data driving signal by switching the signal.
  • the base substrate 101 also has a peripheral region 101c surrounding the second display region 101b.
  • many lines The second end of the second data line S2, the plurality of second transfer lines Z2, the first end of the plurality of fifth data lines S5, the second end of the plurality of fourth data lines S4, and the plurality of third transfer lines Z3, And the first ends of the plurality of sixth data lines S6 can all be located in the peripheral area 101c, and located in the area of the fourth sub-display area 101b4 away from the first display area 101a.
  • connection between the second data line S2 and the second transfer line Z2, the connection between the second transfer line Z2 and the fifth data line S5, the connection between the fourth data line S4 and the third transfer line Z3, and Connections between the third transition line Z3 and the sixth data line S6 may both be located in the peripheral area 101c.
  • the first target electrode pattern is one of the second electrode pattern 1031b, the fourth electrode pattern 1032b and the sixth electrode pattern 1033b, the second target electrode pattern is the first electrode pattern 1031a, One of the third electrode pattern 1032a and the fifth electrode pattern 1033a.
  • the data driving signals obtained by the second type of electrode patterns 1032 are transferred and transmitted through the first transfer line Z1.
  • the data driving signals obtained by the third type of electrode patterns 1033 are transferred and transmitted through the first transfer line Z1.
  • the data drive signal obtained by the first type of electrode patterns 1031 is transferred and transmitted via the first transfer line Z1 .
  • the fourth sub-display area 101b4 of a sub-display area 101b1 transmits the data driving signal, so that the display panel 10 includes: a plurality of second transition lines Z2, and a plurality of fifth data lines S5 located in the fourth sub-display area 101b4.
  • the plurality of fifth data lines S5 are arranged along the pixel row direction X and extend along the pixel column direction Y.
  • a plurality of second transition lines Z2 are arranged along the pixel column direction Y and extend along the pixel row direction X.
  • the second end of each second data line S2 is connected to the first end of a second transition line Z2, and the second end of each second transition line Z2 is connected to the first end of the fifth data line S5.
  • the fifth data line S5 is also connected to a column of second pixel circuits A2 located in the fourth sub-display area 101b4 for connecting to the first target electrode pattern.
  • the data driving circuit can sequentially pass through the first data line S1, the first transition line Z1, the second data line S2, the second transition line Z2 and the fifth data line S5 to the fourth sub-display area 101b4 for connecting A column of second pixel circuits A2 of the first target electrode pattern provides data driving signals.
  • the base substrate 101 also has a peripheral region 101c surrounding the second display region 101b.
  • the second ends of the plurality of second data lines S2, the plurality of second transfer lines Z2, and the first ends of the plurality of fifth data lines S5 Both ends may be located in the peripheral area 101c, and located in a region of the fourth sub-display area 101b4 away from the first display area 101a. That is, the connection between the second data line S2 and the second transition line Z2, and the connection between the second transition line Z2 and the fifth data line S5 may both be located in the peripheral area 101c.
  • the display panel 10 further includes: a plurality of first dummy data lines D1 located in the third sub-display area 101b3.
  • the plurality of first dummy data lines D1 may be arranged along the pixel row direction X and extend along the pixel column direction Y.
  • One end of the first dummy data line D1 is used to be connected to a fixed voltage end, and the first dummy data line D1 is also connected to a column of first pixel circuits A1 located in the third sub-display area 101b3.
  • the first pixel circuit A1 located in the third sub-display area 101b3 may be a dummy pixel circuit, and the dummy pixel circuit may refer to a pixel circuit not connected to any electrode pattern.
  • the fixed voltage terminal can provide a fixed voltage signal to the dummy pixel circuit through the first dummy data line D1, thereby preventing the dummy pixel circuit from affecting the signal transmitted by each signal line in the display panel 10 and ensuring the display effect of the display panel 10.
  • the first dummy data line D1 can be arranged on the same layer as other data lines (such as the second data line S2 ) mentioned in the above embodiments, and of course also can be arranged on different layers, which is not limited in this embodiment of the present application. If the first dummy data line D1 is set on the same layer as the other data lines mentioned in the above-mentioned embodiments, there may be a space between the first dummy data line D1 and other data lines, thereby avoiding the first dummy data line D1 and other data lines. The data lines influence each other, so that the first dummy data line D1 transmits a fixed voltage signal, while other data lines transmit data driving signals.
  • each first dummy data line D1 arranged on the same layer as other data lines may be co-linear with one second data line S2 with a gap.
  • the layered first dummy data line D1 is connected to a column of first pixel circuits A1 located in the third sub-display area 101b3.
  • the column of first pixel circuits A1 located in the third sub-display area 101b3 is located in the same column as the column of first pixel circuits A1 located in the second sub-display area 101b2 connected to the fourth data line S4.
  • all the first dummy data lines D1 can be on the same layer as other data lines.
  • Settings can also be set in different layers.
  • the second display area 101b further includes a sixth sub-display area 101b6.
  • the sixth sub-display area 101b6 may be called a normal display area.
  • the second display area 101b includes two sixth sub-display areas 101b6, and the two sixth sub-display areas 101b6 may be respectively located in the first third sub-display area 101b3, the first sub-display area 101b1, and the second
  • the third sub-display area 101b3 is located on both sides of the pixel row direction X, and is located in the first second sub-display area 101b2, the first display area 101a, and the second second sub-display area 101b2 along the pixel row direction X. sides.
  • the display panel 10 may further include: a plurality of seventh data lines S7 located in the sixth sub-display area 101b6, and a plurality of second dummy data lines D2 located in the sixth sub-display area 101b6.
  • One end of each seventh data line S7 is used to connect to a data driving circuit, and each seventh data line S7 is also connected to a column of second pixel circuits A2 located in the sixth sub-display area 101b6.
  • the data driving circuit can provide the data driving signal to the second pixel circuit A2 through the seventh data line S7.
  • each second dummy data line D2 is used to connect to a fixed voltage end, and each second dummy data line D2 is also connected to a column of first pixel circuits A1 located in the sixth sub-display area 101b6. Therefore, the fixed voltage terminal can provide a fixed voltage signal to the first pixel circuit A1 through the second dummy data line D2.
  • the first pixel circuit A1 located in the sixth sub-display area 101b6 may be a dummy pixel circuit.
  • the third connecting wire L3 may be arranged in a different layer from the first connecting wire L1 and the second connecting wire L2.
  • the display panel 10 may include a connection layer 104 between the driving circuit layer 102 and the first electrode layer 103 .
  • the first connecting wire L1 and the second connecting wire L2 may be located in the connecting layer 104 , that is, both the first connecting wire L1 and the second connecting wire L2 may be located between the driving circuit layer 102 and the first electrode layer 103 .
  • the third connection wire L3 is located on the first electrode layer 103 .
  • the electrode pattern included in the first electrode layer 103 may be a laminated structure of a first film layer, a second film layer and a third film layer.
  • the material of the first film layer and the third film layer can be indium tin oxide (Indium tin oxide, ITO), the material of the second film layer can be silver (Ag), that is, the electrode pattern can be a stack of ITO/Ag/ITO .
  • the third connection line L3 located on the first electrode layer 103 may mean that: the third connection line L3 is the same as the electrode pattern, and is also a stack of ITO/Ag/ITO; or, the third connection line L3 may be an electrode pattern A layer of ITO (such as the first film layer or the third film layer) is included.
  • connection layer 104 may include at least one conductive layer and at least one insulating layer, and each conductive layer is provided with an insulating layer on a side away from the base substrate 101 .
  • connection layer 104 may include: A first conductive layer 1041 , a first insulating layer 1042 , a second conductive layer 1043 , a second insulating layer 1044 , a third conductive layer 1045 and a third insulating layer 1046 are sequentially stacked on one side.
  • Each conductive layer of the first conductive layer 1041 , the second conductive layer 1043 and the third conductive layer 1045 includes a plurality of first connecting wires L1 and/or a plurality of second connecting wires L2 .
  • the first insulating layer 1042 has a first via hole
  • the second insulating layer 1044 has a second via hole
  • the third insulating layer 1046 has a third via hole.
  • the first conductive layer 1041 is electrically connected to the second conductive layer 1043 through the first via hole
  • the second conductive layer 1043 is electrically connected to the third conductive layer 1045 through the second via hole
  • the third conductive layer 1045 is electrically connected to the second conductive layer 1045 through the third via hole.
  • An electrode layer 103 is electrically connected.
  • the connecting wires (second connecting wire L2, fourth connecting wire L2, L4 and the fifth connecting traces (L5) are evenly distributed on the three conductive layers, and by reasonably arranging the positions of the connecting traces, the distance between adjacent connecting traces is too small to cause short circuit or crosstalk.
  • the area of the first display area 101a is relatively small, or a connection wiring (second connection line) for connecting the first pixel circuit A1 located in the second display area 101b and the electrode pattern of the first display area 101a is prepared.
  • the process precision of the wiring L2, the fourth connecting wiring L4 and the fifth connecting wiring L5) is relatively high, and when the width of the connecting wiring can be reduced, all the connecting wiring can be arranged on two conductive layers or even Arranged on a conductive layer, which can reduce the number of mask plates used in the preparation process, simplify the process, improve the light transmittance of the first display area 101a and reduce the overall thickness of the display panel 10, and realize the light and thin display panel 10 change.
  • each conductive layer is also provided with a connection part, which can be used to connect the connection line to the pixel circuit, or to connect the connection line on different layers, or to connect the connection line to the first electrode layer 103
  • the electrode patterns in the connection may include a plurality of first connection portions 1041a
  • the second conductive layer 1043 may include a plurality of second connection portions 1043a
  • the third conductive layer 1045 may include a plurality of third connection portions 1045a.
  • the first connecting wire L1 is located in the third conductive layer 1045 and the second connecting wire L2 is located in the first conductive layer 1041 as an example.
  • the second pixel circuit A2 is connected to the first connection part 1041a
  • the first connection part 1041a is connected to the second connection part 1043a
  • the second connection part 1043a is connected to the third connection part 1045a
  • the portion 1045a is connected to one electrode pattern (the second electrode pattern 1031b, the fourth electrode pattern 1032b, or the sixth electrode pattern 1033b).
  • the third connection part 1045a is connected to a second electrode pattern 1031b
  • the third connection part 1045a is also connected to the third connection line L3, and the third connection line L3 is connected to another third connection part 1045a, and the other A third connection portion 1045a is connected to another second electrode pattern 1031b.
  • the second connection wiring L2 Connect to the first pixel circuit A1 through a first connection part 1041a, connect the second connection line L2 to the second connection part 1043a through another first connection part 1041a, connect the second connection part 1043a to the third connection part 1045a
  • the third connection part 1045a is connected to one electrode pattern (the first electrode pattern 1031a, the third electrode pattern 1032a or the fifth electrode pattern 1033a).
  • third connecting portion 1045a is connected to one first electrode pattern 1031a, then the third connecting portion 1045a is also connected to the first connecting trace L1, and the first connecting trace L1 is connected to another third connecting portion 1045a.
  • a third connection portion 1045a is connected to another second electrode pattern 1031b.
  • the orthographic projection of the third connecting portion 1045a on the base substrate 101 may at least partially overlap with the orthographic projection of the electrode pattern connected to the third connecting portion 1045a on the base substrate 101, so that the electrode pattern passes through the third connecting portion 1045a.
  • the third via hole of the third insulating layer 1046 is connected to the third connection portion 1045a.
  • Orthographic projections of the connected second connecting portion 1043a and third connecting portion 1045a on the base substrate 101 at least partially overlap, so that the third connecting portion 1045a passes through the second via hole penetrating the second insulating layer 1044 and the second The connecting portion 1043a is connected.
  • the first conductive layer 1041 , the second conductive layer 1043 and the third conductive layer 1045 all include transparent conductive materials.
  • the material of the first conductive layer 1041 , the second conductive layer 1043 and the third conductive layer 1045 can be indium tin oxide or indium zinc oxide.
  • Each insulating layer included in the connection layer 104 includes a transparent insulating material.
  • the material of the first insulating layer 1042 , the second insulating layer 1044 and the third insulating layer 1046 may be polyimide (PI).
  • the display panel 10 further includes a light emitting film layer 105 , a pixel defining layer 106 , a second electrode layer 107 , an encapsulation layer 108 and a buffer layer (buffer) 109 .
  • the encapsulation layer 108 covers the side of the second electrode layer 107 away from the base substrate 101 to realize the encapsulation of the display panel 10 .
  • the buffer layer 109 may be located between the base substrate 101 and the driving circuit layer 102 .
  • the first electrode layer 103 , the pixel defining layer 106 , the light emitting film layer 105 , and the second electrode layer 107 can form a plurality of light emitting devices, for example, form a plurality of OLEDs.
  • the luminescent film layer 105 includes a plurality of luminescent layers 1051
  • the pixel defining layer 106 has a plurality of openings, each opening exposes an electrode pattern in the first electrode layer 103, and each luminescent layer 1051 is located in an opening and is connected to the electrode pattern.
  • the part of the second electrode layer 107 located in the opening serves as the second electrode of the light emitting device.
  • the sequentially stacked electrode patterns (anode pole), the light emitting layer 1051 and the second electrode (cathode) constitute a light emitting device.
  • the pixel circuit in the driving circuit layer 102 can be electrically connected with the light emitting device, for example, the pixel circuit can be electrically connected with the electrode pattern of the first electrode layer 103 in the light emitting device, so as to control the light emitting device to emit light.
  • the driving circuit layer 102 includes a semiconductor layer 10201, a first gate insulating layer (gate insulator, GI) 10202, a first gate layer (gate) 10203, a first Two gate insulating layers 10204, second gate layer 10205, interlevel dielectric layer (inter level dielectric, ILD) 10206, first source and drain layer 10207, passivation layer (passivation layer, PVX) 10208, intermediate source and drain A pole layer 10209, a first planarization layer (planarization layer, PLN) 10210, a second source-drain layer 10211 and a second planarization layer 10212, and a plurality of pixel circuits in the driving circuit layer 102 are arranged in an array, and each pixel circuit includes multiple thin film transistors.
  • GI gate insulator
  • ILD interlevel dielectric layer
  • PVX passivation layer
  • the first conductive layer 1041 in the connection layer 104 is located on the side of the second planar layer 10212 away from the base substrate 101 .
  • the first insulating layer 1042 may be called a third planar layer
  • the second insulating layer 1044 may be called a fourth planar layer
  • the third insulating layer 1046 may be called a fifth planar layer.
  • the pixel circuit in the driving circuit layer 102 can be electrically connected to the light emitting device through the connection layer 104 .
  • the first source-drain layer 10207 may include the source and drain of the thin film transistors in each pixel circuit, and the source and drain may have an interval.
  • the first source-drain layer 10207 may also include the transition lines (the first transition line Z1 , the second transition line Z2 and the third transition line Z3 ) described in the above embodiments.
  • the middle source-drain layer 10209 may include power lines (for example, VDD lines) for providing power signals to the display panel 10 .
  • the intermediate source-drain layer 10209 may further include the transition lines (the first transition line Z1 , the second transition line Z2 and the third transition line Z3 ) described in the above embodiments.
  • the second source-drain layer may include the data lines described in the above embodiments (the first data line S1, the second data line S2, the third data line S3, the fourth data line S4, the fifth data line S5, the sixth data line line S6 and seventh data line S7) and dummy data lines (first dummy data line D1 and second dummy data line D2).
  • the space that each pixel circuit can occupy in the pixel row direction can be Relatively large, 29.8 ⁇ m (micrometer).
  • the pixel circuit for driving the electrode pattern in the first display area needs to be arranged in the second sub-display area (transition display area) of the second display area. .
  • the uniformity of the pixel circuits in the display panel is poor.
  • the sixth sub-display area can Design a dummy pixel circuit, for example, in Figure 13, design a first pixel circuit (dummy pixel circuit) for every two second pixel circuits, that is, the design of pixel circuit two voltage one (pixel circuit two voltage one can refer to the original design For the position of the two second pixel circuits, an additional dummy pixel circuit needs to be designed).
  • design a first pixel circuit (dummy pixel circuit) for every two second pixel circuits that is, the design of pixel circuit two voltage one (pixel circuit two voltage one can refer to the original design
  • pixel circuit two voltage one can refer to the original design
  • an additional dummy pixel circuit needs to be designed.
  • FIG. 12 where originally four pixel circuits need to be designed, six pixel circuits need to be designed.
  • the space that each pixel circuit can occupy in the direction of the pixel row is small, 19.8 ⁇ m, which is difficult to manufacture in terms of technology.
  • the embodiment of the present application since the embodiment of the present application drives two second electrode patterns through one second pixel circuit, the number of pixel circuits to be designed can be reduced. Compared with FIG. 13 , in FIG. 14 , only five pixel circuits need to be designed in positions where six pixel circuits are originally required to be designed. The space that each pixel circuit can occupy in the pixel row direction can be larger, 23.83 ⁇ m, and the manufacturing difficulty is relatively low. Moreover, the arrangement of the pixel circuits in each sub-area in the second display area is different, and the uniformity of the pixel circuits in the display panel is also better.
  • three second pixel circuits and two first pixel circuits in five pixel circuits can be arranged in accordance with the second pixel circuit, the second pixel circuit, the first pixel circuit, the second pixel circuit and The first pixel circuit is arranged in a manner.
  • the three second pixel circuits and the two first pixel circuits among the five pixel circuits can also be arranged according to the second pixel circuit, the second pixel circuit, the second pixel circuit, the first pixel circuit and the first pixel circuit.
  • the arrangement of pixel circuits may also be used, which is not limited in this embodiment of the present application.
  • the pixel circuit may include a plurality of thin film transistors and a storage capacitor.
  • the plurality of thin film transistors include a data first reset control transistor T1 , a threshold compensation transistor T2 , a drive transistor T3 , a write transistor T4 , a first light emission control transistor T5 , a second light emission control transistor T6 and a third reset control transistor T7 .
  • the storage capacitor Cst may include two capacitor plates Cst1 and Cst2.
  • the capacitor plate Cst1 may be referred to as one end, the first end, the first pole or the first storage capacitor electrode of the storage capacitor Cst.
  • the capacitor plate Cst2 may be referred to as another end, a second end, a second pole, or a second storage capacitor electrode of the storage capacitor Cst.
  • the first pole of the first reset control transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit
  • the second pole of the first reset control transistor T1 is electrically connected to the gate of the drive transistor T3, and the first reset control transistor T3
  • the gate of T1 is electrically connected to the reset control signal line to receive the reset control signal Reset.
  • the first pole of the threshold compensation transistor T2 is connected to the first pole of the drive transistor T3, and the threshold compensation
  • the gate of the transistor T2 is electrically connected to the scanning signal line to receive the scanning signal Gate
  • the second electrode of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3.
  • the first pole of the data writing transistor T4 is connected to the second pole of the driving transistor T3, the gate of the data writing transistor T4 is electrically connected to the scanning signal line to receive the scanning signal Gate, and the second pole of the data writing transistor T4 is connected to the data
  • the line is connected to receive the data driving signal Data.
  • the first electrode of the first light emission control transistor T5 is electrically connected to the first power signal line
  • the second electrode of the first light emission control transistor T5 is electrically connected to the second electrode of the driving transistor T3
  • the gate of the first light emission control transistor T5 is electrically connected to the second electrode of the driving transistor T3.
  • the light emission control signal line is electrically connected to receive the light emission control signal EM.
  • the gate of the second light emission control transistor T6 is electrically connected to the light emission control signal line to receive the light emission control signal EM.
  • the first pole of the third reset control transistor T7 is connected to the reset power signal line to receive the reset signal Vinit
  • the second pole of the third reset control transistor T7 is connected to the electrode pattern of the light emitting device
  • the gate of the first reset transistor T7 is connected to the reset signal line.
  • the control signal line is electrically connected to receive the reset control signal Reset.
  • a first pole of the storage capacitor Cst is electrically connected to the first power signal line
  • a second pole of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3.
  • the cathode of the light emitting device may be electrically connected to the second power signal line.
  • the above-mentioned first power signal line refers to the signal line of the output voltage signal VDD
  • the second power signal line refers to the signal line of the output voltage signal VSS.
  • FIG. 17 is a partial schematic diagram of a semiconductor layer in a display panel provided by an embodiment of the present application.
  • the semiconductor layer may have a curved or bent shape, and the semiconductor layer includes a semiconductor pattern (channel region) and a doped region pattern (source-drain doped region) of each transistor, and each transistor in the same pixel circuit
  • the pattern of the active layer and the pattern of the doped region are integrally arranged.
  • the semiconductor layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region may be conductorized by doping or the like to realize electrical connection of various structures. That is, the semiconductor layer of each transistor of each pixel circuit is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (ie, a source region and a drain region) and a semiconductor pattern, different The semiconductor patterns of the transistors are spaced apart.
  • the semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials and the like. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • FIG. 18 is a partially superimposed schematic diagram of the first gate layer in the display panel provided by the embodiment of the present application.
  • the display panel includes a first gate insulating layer located on a side of the semiconductor layer away from the base substrate, for insulating the above-mentioned semiconductor layer from the subsequently formed first gate layer.
  • FIG. 18 shows a first gate layer included in the display panel, and the first gate layer is disposed on the first gate insulating layer so as to be insulated from the semiconductor layer.
  • the first gate layer may include a second storage capacitor electrode Cst2, a plurality of scanning signal lines g1 extending along the pixel row direction X, a plurality of reset control signal lines g2, a plurality of light emission control signal lines g3, and the first gate
  • the layers also include the gates of the individual transistors.
  • the gate of the data writing transistor T4 can be the overlapping part of the scanning signal line g1 and the semiconductor layer;
  • the first overlapping part, the gate of the first light emission control transistor T5 may be the second part where the light emission control signal line g3 overlaps with the semiconductor layer.
  • the gate of the first reset control transistor T1 is the first part where the reset control signal line g2 overlaps the semiconductor layer, and the gate of the third reset control transistor T7 is the second part where the reset control signal line g2 overlaps the semiconductor layer.
  • the gate of the threshold compensation transistor T2 may be a portion where the protruding structure P protruding from the scan signal line g1 overlaps with the semiconductor layer.
  • the gate of the driving transistor T3 may be the second storage capacitor electrode Cst2.
  • each dotted rectangular box in FIG. 19 shows each portion where the first gate layer overlaps with the semiconductor layer.
  • the semiconductor layers on both sides of each channel region are conductorized by processes such as ion doping to serve as the first pole and the second pole of each transistor.
  • the source and drain of the transistor can be symmetrical in structure, so there can be no difference in the physical structure of the source and drain.
  • the transistors except for the gate as the control electrode, it is directly described that one of them is the first pole and the other is the second pole, so the first pole of all or part of the transistors in the embodiment of the present application and second pole are interchangeable as required.
  • the scanning signal line g1 , the reset control signal line g2 and the light emitting control signal line g3 are arranged along the direction Y of the pixel column.
  • the second storage capacitor electrode Cst2 ie, the gate of the driving transistor T3
  • the protruding structure P protruding from the scanning signal line g1 is located on a side of the scanning signal line g1 close to the light emission control signal line g3 .
  • a second gate insulating layer may be formed on the above-mentioned first gate layer for insulating the above-mentioned first gate layer from the second gate layer formed subsequently.
  • Fig. 20 is a partial schematic diagram of a second gate layer in a display panel provided by an embodiment of the present application
  • Fig. 21 is a semiconductor layer, a first gate layer and a second gate layer in a display panel provided by an embodiment of the present application
  • the local overlay schematic diagram As shown in Figure 20 and Figure 21, the second gate layer includes a first storage capacitor electrode Cst1, a plurality of first reset power signal lines g4 extending along the pixel row direction X and a plurality of second reset power supply signal lines g4 extending along the pixel row direction X Reset the power signal line g5.
  • the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 at least partially overlap to form a storage capacitor Cst.
  • an interlayer dielectric layer may be formed on the above-mentioned second gate layer to insulate the above-mentioned second gate layer from the subsequently formed first source-drain layer.
  • the via holes are represented by filling patterns in FIGS. 22 to 23 . Other unpatterned areas are used to represent areas where the ILD layer has solid material. It should be noted that each via hole opened in the interlayer dielectric layer is used to connect the subsequently formed film layer with the film layer on the side of the interlayer dielectric layer close to the base substrate. That is, each via hole is a via hole for connecting the film layers.
  • Fig. 24 is a partial schematic diagram of the first source-drain layer in the display panel provided by the embodiment of the present application
  • Fig. 25 is the semiconductor layer, the first gate layer, and the second gate layer in the display panel provided by the embodiment of the present application , a partial overlay schematic diagram of the interlayer dielectric layer and the first source-drain layer.
  • the first source-drain layer includes a first connection structure h1, a second connection structure h2, a third connection structure h3, a fourth connection structure h4, a fifth connection structure h5 and a sixth connection structure h6.
  • the first connection structure h1 is configured to connect the source (or drain) of the threshold compensation transistor T2 and the gate of the driving transistor T3 .
  • the second connection structure h2 is configured to connect the second light emission control transistor T6.
  • the third connection structure h3 is configured to connect the source (or drain) of the third reset control transistor T7 and the reset power signal line g4.
  • the fourth connection structure h4 is configured to connect the VDD signal line and the source (or drain) of the first light emission control transistor T5.
  • the fifth connection structure h5 is configured to connect the source (or drain) of the data writing transistor T4 and the data line g6.
  • the sixth connection structure h6 is configured to connect to the second reset power signal line g5.
  • a passivation layer may be formed on the above-mentioned first source-drain layer for insulating the above-mentioned first source-drain layer from the subsequently formed intermediate source-drain layer.
  • the via holes are represented by filling patterns in FIGS. 26 to 27 . Other unpatterned areas are used to represent areas where the passivation layer has solid material. It should be noted that each via hole opened in the passivation layer is used to connect the subsequently formed film layer with the film layer on the side of the passivation layer close to the substrate. That is, each via hole is a via hole for connecting the film layers.
  • FIG. 28 is a partial schematic diagram of the intermediate source and drain layers in the display panel provided by the embodiment of the present application
  • FIG. 29 is a semiconductor layer, a first gate layer, and a second gate layer in the display panel provided by the embodiment of the present application. Schematic diagram of local overlay of the interlayer dielectric layer, the first source-drain layer, the passivation layer and the middle source-drain layer.
  • the intermediate source-drain layer includes a first signal line VDD1 , a seventh connection structure h7 and an eighth connection structure h8 .
  • the first signal line VDD1 is configured to be connected to the fourth connection structure h4, the seventh connection structure h7 is configured to be connected to the second connection structure h2, and the eighth connection structure h8 is configured to be connected to the fifth connection structure h5.
  • a first planar layer ( PLN1 ) may be formed on the above intermediate source and drain layer for insulating the above intermediate source and drain layer from the subsequently formed second source and drain layer.
  • filling patterns are used to represent via holes in FIGS. 30 to 31 .
  • Other unpatterned areas are used to represent areas where the first flat layer has solid material.
  • each via hole opened in the first planar layer is used to connect the subsequently formed film layer with the film layer on the side of the first planar layer close to the base substrate. That is, each via hole is a via hole for connecting the film layers.
  • FIG. 32 is a partial schematic diagram of the second source and drain layers in the display panel provided by the embodiment of the present application
  • FIG. 33 is a semiconductor layer, the first gate layer, and the second gate layer in the display panel provided by the embodiment of the present application.
  • the second source-drain layer includes a second signal line VDD2 , a data line g6 and a ninth connection structure h9 .
  • the second signal line VDD2 is configured to be connected to the first signal line VDD1
  • the data line g6 is configured to be connected to the eighth connection structure h8
  • the ninth connection structure h9 is configured to be connected to the seventh connection structure h7.
  • the wiring for transmitting the VDD signal includes a first signal line VDD1 and a second signal line VDD2.
  • a second planar layer may be formed on the above-mentioned second source-drain layer to insulate the above-mentioned intermediate source-drain layer from the first conductive layer in the subsequently formed connection layer.
  • PPN2 a second planar layer
  • filling patterns are used to represent via holes in FIGS. 34 to 35 .
  • Other unpatterned areas are used to represent areas where the second flat layer has solid material.
  • each via hole opened in the second planar layer is used to connect the subsequently formed film layer with the film layer on the side of the second planar layer close to the base substrate. That is, each via hole is a via hole for connecting the film layers.
  • the embodiment of the present application provides a display panel, since at least two first electrode patterns in the display panel are connected, and one first electrode pattern of the at least two connected first electrode patterns is connected to one first electrode pattern.
  • the pixel circuits are connected so that one first pixel circuit can drive two first electrode patterns.
  • at least two second electrode patterns are connected, and one second electrode pattern in the connected at least two second electrode patterns is connected to one second pixel circuit, one second pixel circuit can drive two second pixel circuits. electrode pattern. Therefore, when the number of electrode patterns is the same, the scheme of driving two electrode patterns with one pixel circuit can reduce the number of pixel circuits that need to be designed in the second display area, and further increase the number of pixel circuits required for each pixel circuit. It can occupy less space, and the difficulty of process preparation is relatively low.
  • FIG. 36 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application. This method can be used to prepare the display panels provided in the above embodiments. Referring to Figure 36, the method may include:
  • Step S101 sequentially forming a buffer layer, a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, and an interlayer dielectric layer on one side of the base substrate, A first source and drain layer, a passivation layer, an intermediate source and drain layer, a first flat layer, a second source and drain layer, and a second flat layer.
  • a base substrate when preparing the display panel, a base substrate may be obtained first.
  • the base substrate may be a transparent glass substrate or a flexible substrate.
  • the prepared display panel may be a flexible display panel.
  • a buffer layer and various film layers in the driving circuit layer may be formed on one side of the base substrate.
  • each film layer in the driving circuit layer can refer to FIG. 17 to FIG. 35 . The embodiment of the present application will not be repeated here.
  • Step S102 sequentially forming a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer and a third insulating layer on the side of the second planar layer away from the base substrate.
  • a first conductive layer is formed on a side of the second flat layer away from the base substrate, and the first conductive layer may include a plurality of first connection parts.
  • a first insulating layer (third planar layer PLN3 ) is formed on a side of the first conductive layer away from the base substrate.
  • a filling pattern is used to represent the first via hole in FIG. 39 and FIG. 40 .
  • Other areas where the fill pattern is not drawn are used to represent areas where the first insulating layer has a solid material.
  • each of the first via holes opened in the first insulating layer is used to connect the subsequently formed film layer to the film layer on the side of the first insulating layer close to the base substrate. That is, each of the first via holes is a via hole for connecting the film layers.
  • a second conductive layer is formed on a side of the first insulating layer away from the base substrate, and the second conductive layer may include a plurality of second connection parts.
  • a second insulating layer (fourth planar layer PLN4 ) is formed on a side of the second conductive layer away from the base substrate.
  • filling patterns are used to represent the second via holes in FIGS. 43 and 44 .
  • Other areas where the hatch pattern is not drawn are used to represent areas where the second insulating layer has a solid material.
  • each of the second via holes opened in the second insulating layer is used to connect the subsequently formed film layer with the film layer on the side of the second insulating layer close to the base substrate. That is, each of the second via holes is a via hole for connecting the film layers.
  • a third conductive layer is formed on the side of the second insulating layer away from the base substrate, and the third conductive layer may have multiple third connection portions.
  • a third insulating layer (fifth planar layer PLN5 ) is formed on a side of the third conductive layer away from the base substrate.
  • a filling pattern is used in FIG. 47 and FIG. 48 to represent the third via hole. Other areas where the hatch pattern is not drawn are used to represent areas where the third insulating layer has solid material.
  • each third via hole opened in the third insulating layer is used for the subsequent formation of the film layer and the third insulating layer close to the substrate.
  • the film layers on one side of the board 101 are connected. That is, each of the third via holes is a via hole for connecting the film layers.
  • Step S103 forming a first electrode layer, a pixel defining layer, a light-emitting film layer, a second electrode layer and an encapsulation layer on the side of the third insulating layer away from the base substrate.
  • the first electrode layer is formed on the side of the third insulating layer away from the base substrate.
  • the first electrode layer may include a plurality of electrode patterns, and each electrode pattern may serve as an anode of a pixel device.
  • the second electrode pattern, the fourth electrode pattern and the sixth electrode pattern are shown in FIGS. 49 and 50 .
  • a pixel defining layer is formed on the side of the first electrode layer away from the base substrate.
  • the pixel defining layer may have a plurality of openings, each opening exposing an electrode pattern in a first electrode layer.
  • filling patterns are used to represent the openings in FIG. 51 and FIG. 52
  • other regions without filling patterns are used to represent regions with solid materials in the pixel defining layer.
  • the openings in the pixel defining layer are used to connect the subsequently formed film layer to the film layer on the side of the pixel defining layer close to the base substrate. That is, each opening is an opening for the light emitting layer in the light emitting film layer to contact the electrode pattern in the first electrode layer.
  • the light emitting film layer, the second electrode layer and the encapsulation layer can be continuously formed on the side of the pixel defining layer away from the base substrate, which will not be described in detail in this embodiment of the present application.
  • the manufacturing method of the display panel provided in the embodiment of the present application mainly uses other areas in the second display area that are not the second sub-display area (such as the first sub-display area, the third sub-display area, and the fourth sub-display area) area, the fifth sub-display area and the sixth sub-display area) as an example for illustration.
  • 17 to 51 all take the example of including one circuit group A along the pixel row direction and including two circuit groups A along the pixel column direction.
  • the difference between the film layers in the second sub-display region and other regions in the second display region is mainly the conductive layers.
  • the part of the conductive layer located in the second sub-display region includes not only the connecting portion, but also a second connecting trace, a fourth connecting trace or a fifth connecting trace. That is, the part of the conductive layer located in the second sub-display area may include connecting wires for connecting the pixel circuits located in the second sub-display area and the electrode patterns located in the first display area.
  • the conductive layer in FIG. 53 can be the first conductive layer, the second conductive layer or the third conductive layer.
  • the connection part in FIG. 53 can be the first connection part, the second connection part or the third connection part.
  • the embodiment of the present application provides a method for manufacturing a display panel, since at least two first electrode patterns in the prepared display panel are connected, and one of the connected at least two first electrode patterns is first The electrode pattern is connected to one first pixel circuit, so one first pixel circuit can drive two first electrode patterns.
  • at least two second electrode patterns are connected, and one second electrode pattern of the connected at least two second electrode patterns is connected to a second pixel circuit, therefore It is possible to make one second pixel circuit drive two second electrode patterns. Therefore, when the number of electrode patterns is the same, the scheme of driving two electrode patterns with one pixel circuit can reduce the number of pixel circuits that need to be designed in the second display area, and further increase the number of pixel circuits required for each pixel circuit. It can occupy less space, and the difficulty of process preparation is relatively low.
  • Fig. 54 is a schematic structural diagram of a display module provided by an embodiment of the present application.
  • the display device may include a data driving circuit 20 and the display panel 10 provided in the above-mentioned embodiments.
  • the data driving circuit 20 can be connected with the first data line S1, the third data line S3, the fourth data line S4 and the seventh data line S7 in the display panel 10, which are the first data line S1, the third data line S3, the fourth data line S4 and the seventh data line S7 directly provide data driving signals.
  • FIG. 54 schematically shows a first data line S1 , a third data line S3 , a fourth data line S4 and a seventh data line S7 .
  • the second data line S2 is connected to the first data line S1 through the first transfer line Z1
  • the fifth data line S5 is connected to the second data line S2 through the second transfer line Z2.
  • S1 provides data driving signals for the second data line S2 and the fifth data line S5.
  • the sixth data line S6 is connected to the fourth data line S4 through the third transfer line Z3, so the data driving circuit 20 provides a data driving signal for the sixth data line S6 through the fourth data line S4.
  • the display module can basically have the same technical effect as the display panel described in the previous embodiments, for the sake of brevity, the technical effect of the display device will not be described here again.
  • an embodiment of the present application provides a display device, which may include the display module 01 provided in the above embodiments and electrical components such as a sensor 02 , such as an optical sensor.
  • the display device includes optical sensors such as a front camera, a proximity light sensor, and a 3D sensing module. These optical components need to receive light from the display surface side of the display device to achieve corresponding functions.
  • the optical sensor is usually mounted on the non-display surface side of the display module 01 , and the photosensitive surface side of the optical sensor faces the display module 01 .
  • the orthographic projection of the optical sensor 02 on the display panel 10 at least partially overlaps with the first display area 101 a in the display panel 10 .
  • the display device may be an active-matrix organic light-emitting diode (AMOLED) display device, a passive-matrix organic light-emitting diode (passive-matrix organic light-emitting diode, PMOLED) display device.
  • AMOLED active-matrix organic light-emitting diode
  • PMOLED passive-matrix organic light-emitting diode
  • QLED Quantum dot light emitting diodes
  • electronic paper mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames or navigators and any other products or components with display functions.
  • the display device can basically have the same technical effect as the display panel described in the previous embodiments, for the sake of brevity, the technical effect of the display device will not be described here again.
  • Words such as “comprises” or “comprising” and similar terms mean that the elements or items listed before “comprising” or “comprising” include the elements or items listed after “comprising” or “comprising” and their equivalents, and do not exclude other component or object.
  • Words such as “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “Down”, “Left”, “Right” and so on are only used to indicate relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

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Abstract

本申请公开了一种显示面板、显示模组及显示装置，涉及显示技术领域。由于显示面板中至少两个第一电极图案连接，且连接的至少两个第一电极图案中的一个第一电极图案与一个第一像素电路连接，因此可以使得一个第一像素电路驱动两个第一电极图案。同时，由于至少两个第二电极图案连接，且连接的至少两个第二电极图案中的一个第二电极图案与一个第二像素电路连接，因此可以使得一个第二像素电路驱动两个第二电极图案。由此，在电极图案的数量相同的情况下，采用一个像素电路驱动两个电极图案的方案，能够减少第二显示区中所需设计的像素电路的数量，进而能够增大每个像素电路所能够占用的空间，工艺制备难度较低。

Description

显示面板、显示模组及显示装置
本公开要求于2022年1月30日提交的申请号为PCT/CN2022/075193、发明名称为“显示面板及制备方法、显示装置”的PCT国际专利申请的优先权，本公开还要求于2022年9月28日提交的申请号为202211193942.7，发明名称为“显示面板、显示模组及显示装置”的中国专利申请的优先权，上述两个优先权案件的全部内容通过引用结合在本公开中。
技术领域
本申请涉及显示技术领域，特别涉及一种显示面板、显示模组及显示装置。
背景技术
有机发光二极管(organic light-emitting diode，OLED)显示面板由于具有自发光，驱动电压低，以及响应速度快等优点而得到了广泛的应用。OLED显示面板一般包括：多个像素单元，每个像素单元包括发光器件以及与该发光器件连接的像素电路。
发明内容
本申请提供了一种显示面板、显示模组及显示装置，所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，所述衬底基板具有第一显示区，以及至少部分围绕所述第一显示区的第二显示区；
位于所述衬底基板的一侧的驱动电路层，所述驱动电路层包括位于所述第二显示区的多个第一像素电路和多个第二像素电路；
以及第一电极层，所述第一电极层至少包括多个第一类电极图案，所述多个第一类电极图案包括位于所述第一显示区的多个第一电极图案，以及位于所述第二显示区的多个第二电极图案；
其中，至少两个所述第一电极图案与所述多个第一像素电路中的一个第一像素电路连接，至少两个所述第二电极图案与所述多个第二像素电路中的一个 所述第二像素电路连接。
可选的，所述显示面板还包括：
多条第一连接走线，所述多条第一连接走线位于所述第一显示区；
多条第二连接走线，所述多条第二连接走线沿像素行方向从所述第二显示区延伸至所述第一显示区，且位于所述第一显示区和所述第二显示区；
多条第三连接走线，所述多条第三连接走线位于所述第二显示区；
其中，至少两个所述第一电极图案通过一条所述第一连接走线连接，且至少两个所述第一电极图案中的一个所述第一电极图案通过一条所述第二连接走线与一个所述第一像素电路连接，至少两个所述第二电极图案通过一条所述第三连接走线连接，且至少两个所述第二电极图案中的一个所述第二电极图案与一个所述第二像素电路连接。
可选的，所述显示面板还包括多条第四连接走线和多条第五连接走线，所述多条第四连接走线和所述多条第五连接走线均沿所述像素行方向从所述第二显示区延伸至所述第一显示区；所述第一电极层还包括多个第二类电极图案和多个第三类电极图案；
所述多个第二类电极图案包括位于所述第一显示区的多个第三电极图案，以及位于所述第二显示区的多个第四电极图案，所述第三电极图案通过一条所述第四连接走线与一个所述第一像素电路连接，所述第四电极图案与一个所述第二像素电路连接；
所述多个第三类电极图案包括位于所述第一显示区的多个第五电极图案，以及位于所述第二显示区的多个第六电极图案；所述第五电极图案通过所述第五连接走线与一个所述第一像素电路连接。
可选的，相邻的两个所述第一像素电路和三个所述第二像素电路构成一个电路组；至少两个所述第二电极图案构成一个电极图案组，相邻的一个电极图案组，一个所述第四电极图案以及一个所述第六电极图案构成一个图案组；
其中，每个所述图案组与一个所述电路组对应，且对于相对应的所述图案组和所述电路组，所述图案组在所述衬底基板上的正投影的所处区域，与所述电路组在所述衬底基板上的正投影的所处区域存在交叠。
可选的，对于每个所述电路组以及与所述电路组对应的一个图案组，所述电路组包括的三个所述第二像素电路中，第一个第二像素电路与所述图案组中 的电极图案组的一个第二电极图案连接，第二个第二像素电路与所述图案组中的第四电极图案连接，第三个第二像素电路与所述图案组中的第六电极图案连接。
可选的，所述显示面板中的一部分电路组包括的两个所述第一像素电路与位于所述第一显示区的电极图案连接，所述显示面板中的另一部分电路组包括的两个所述第一像素电路与固定电压端连接。
可选的，与所述第一显示区的电极图案连接的第一像素电路所属的电路组，相对于与所述固定电压端连接的第一像素电路所属的电路组更靠近所述第一显示区。
可选的，所述显示面板包括红色子像素，绿色子像素以及蓝色子像素，所述第一类电极图案所属的子像素为绿色子像素，所述第二类电极图案所属的子像素为红色子像素，所述第三类电极图案所属的子像素为蓝色子像素。
可选的，任一所述第二连接走线沿所述像素行方向的长度，小于所述第四连接走线沿所述像素行方向的长度，且小于所述第五连接走线沿所述像素行方向的长度。
可选的，对于所述多条第二连接走线，所述多条第四连接走线以及所述多条第五连接走线中的每个所述连接走线，所述连接走线沿所述像素行方向的长度，与所述连接走线所连接的位于所述第一显示区的电极图案沿所述像素行方向和所述第二显示区之间的距离正相关。
可选的，所述第二显示区包括第一子显示区，第二子显示区和第三子显示区，所述第一子显示区和所述第一显示区沿像素列方向排布，所述第二子显示区和所述第一显示区沿所述像素行方向排布，所述第三子显示区和所述第一子显示区沿所述像素行方向排布，且和所述第二子显示区沿所述像素列方向排布；
所述显示面板还包括：位于所述第一子显示区的多条第一数据线，位于所述第二子显示区和所述第三子显示区的多条第二数据线，以及位于所述第一子显示区和所述第三子显示区的多条第一转接线；所述多条第一数据线沿所述像素行方向排布且沿所述像素列方向延伸，所述多条第二数据线沿所述像素行方向排布且沿所述像素列方向延伸，所述多条第一转接线沿所述像素列方向排布且沿所述像素行方向延伸；
每条所述第一数据线的第一端用于与数据驱动电路连接，每条所述第一数 据线的第二端与一条所述第一转接线的第一端连接，每条所述第一转接线的第二端与一条所述第二数据线的第一端连接；其中，每条所述第一数据线还与位于所述第一子显示区中用于连接第一目标电极图案的一列第二像素电路连接，每条所述第二数据线还与位于所述第二子显示区中用于连接第二目标电极图案的一列第一像素电路连接；所述第一目标电极图案至少为第四电极图案和第六电极图案中的一种，所述第二目标电极图案至少为第三电极图案和第五电极图案中的一种。
可选的，所述第一目标电极图案为第四电极图案或第六电极图案，所述第二目标电极图案为第三电极图案或第五电极图案；所述显示面板还包括：位于所述第一子显示区的多条第三数据线，以及位于所述第二子显示区和所述第三子显示区的多条第四数据线；
所述多条第三数据线沿所述像素行方向排布且沿所述像素列方向延伸，每条所述第三数据线的第一端用于与数据驱动电路连接，且每条所述第三数据线还与位于所述第一子显示区中用于连接第二电极图案的一列第二像素电路连接；
所述多条第四数据线沿所述像素行方向排布且沿所述像素列方向延伸，每条所述第四数据线的第一端用于与数据驱动电路连接，且每条所述第四数据线还与位于所述第二子显示区中用于连接第一电极图案的一列第一像素电路连接。
可选的，所述第二显示区还包括：第四子显示区和第五子显示区，所述第四子显示区位于所述第一显示区远离所述第一子显示区的一侧，所述第五子显示区和所述第四子显示区沿所述像素行方向排布；所述多条第二数据线还位于所述第五子显示区；所述显示面板还包括：多条第二转接线，以及位于所述第四子显示区的多条第五数据线；
所述多条第五数据线沿所述像素行方向排布且沿所述像素列方向延伸，所述多条第二转接线沿所述像素列方向排布且沿所述像素行方向延伸；每条所述第二数据线的第二端与一条所述第二转接线的第一端连接，每条所述第二转接线的第二端与所述第五数据线的第一端连接；所述第五数据线还与位于所述第四子显示区中用于连接所述第一目标电极图案的一列第二像素电路连接。
可选的，所述显示面板还包括：位于所述第三子显示区的多条第一虚设数 据线；
所述多条第一虚设数据线沿所述像素行方向排布且沿所述像素列方向延伸，所述第一虚设数据线用于与固定电压端连接，且所述第一虚设数据线还与位于所述第三子显示区的一列第一像素电路连接。
可选的，所述第二显示区还包括：第六子显示区，所述第六子显示区位于所述第三子显示区远离所述第一子显示区的一侧；所述显示面板还包括：位于所述第六子显示区的多条第七数据线，以及位于所述第六子显示区的多条第二虚设数据线；
所述多条第七数据线沿所述像素行方向排布且沿所述像素列方向延伸，每条所述第七数据线用于与数据驱动电路连接，每条所述第七数据线还与位于所述第六子显示区中的一列第二像素电路连接；
所述多条第二虚设数据线沿所述像素行方向排布且沿所述像素列方向延伸，每条所述第二虚设数据线用于与固定电压端连接，且所述第二虚设数据线还与位于所述第六显示区的一列第一像素电路连接。
可选的，所述第三连接走线与所述第一电极层位于同层，所述第一连接走线和所述第二连接走线均位于所述驱动电路层和所述第一电极层之间。
另一方面，提供了一种显示模组，所述显示模组包括数据驱动电路以及如上述方面所述的显示面板；
其中，所述数据驱动电路与所述显示面板中的第一数据线，第三数据线，第四数据线和第七数据线连接。
又一方面，提供了一种显示装置，所述显示装置包括上述方面所述的显示模组及光学传感器，所述光学传感器在所述显示面板上的正投影与所述显示面板的第一显示区至少部分交叠。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示面板的局部结构示意图；
图2是图1所示的显示面板的局部放大示意图；
图3是本申请实施例提供的一种衬底基板的俯视图；
图4是本申请实施例提供的一种显示面板的局部截面图；
图5是本申请实施例提供的一种第二显示区中第一电极层的局部示意图；
图6是本申请实施例提供的一种第一显示区中第一电极层的局部示意图；
图7是本申请实施例提供的一种第一显示区的第一图案行的局部示意图；
图8是本申请实施例提供的另一种显示面板的局部结构示意图；
图9是图8所示的显示面板的局部放大示意图；
图10是本申请实施例提供的一种显示面板的数据线，转接线以及虚设数据线的示意图；
图11是本申请实施例提供的另一种显示面板的数据线，转接线以及虚设数据线的示意图；
图12是本申请实施例提供的一种在显示面板中未设计第一像素电路的示意图；
图13是本申请实施例提供的一种像素电路二压一的设计示意图；
图14是本申请实施例提供的一种电路组的示意图；
图15是本申请实施例提供的另一种电路组的示意图；
图16是本申请实施例提供的一种第一像素电路或第二像素电路的等效电路图；
图17是本申请实施例提供的一种显示面板中的半导体层的局部示意图；
图18是本申请实施例提供的一种显示面板中的第一栅极层的局部示意图；
图19是本申请实施例提供的一种在显示面板中半导体层和第一栅极层的局部叠加示意图；
图20是本申请实施例提供的一种显示面板中的第二栅极层的局部示意图；
图21是本申请实施例提供的一种显示面板中的半导体层，第一栅极层以及第二栅极层的局部叠加示意图；
图22是本申请实施例提供的一种显示面板中的层间介电层的局部示意图；
图23是本申请实施例提供的一种显示面板中的半导体层，第一栅极层，第二栅极层以及层间介电层的局部叠加示意图；
图24是本申请实施例提供的一种显示面板中的第一源漏极层的局部示意 图；
图25是本申请实施例提供的一种在显示面板中的半导体层，第一栅极层，第二栅极层，层间介电层以及第一源漏极层的局部叠加示意图；
图26是本申请实施例提供的一种显示面板中的钝化层的局部示意图；
图27是本申请实施例提供的一种在显示面板中的半导体层，第一栅极层，第二栅极层，层间介电层，第一源漏极层以及钝化层的局部叠加示意图；
图28是本申请实施例提供的一种显示面板中的中间源漏极层的局部示意图；
图29是本申请实施例提供的一种在显示面板中的半导体层，第一栅极层，第二栅极层，层间介电层，第一源漏极层，钝化层以及中间源漏极层的局部叠加示意图；
图30是本申请实施例提供的一种显示面板中的第一平坦层的局部示意图；
图31是本申请实施例提供的一种在显示面板中的半导体层，第一栅极层，第二栅极层，层间介电层，第一源漏极层，钝化层，中间源漏极层以及第一平坦层的局部叠加示意图；
图32是本申请实施例提供的一种显示面板中的第二源漏极层的局部示意图；
图33是本申请实施例提供的一种在显示面板中的半导体层，第一栅极层，第二栅极层，层间介电层，第一源漏极层，钝化层，中间源漏极层，第一平坦层以及第二源漏极层的局部叠加示意图；
图34是本申请实施例提供的一种显示面板中的第二平坦层的局部示意图；
图35是本申请实施例提供的一种在显示面板中的半导体层，第一栅极层，第二栅极层，层间介电层，第一源漏极层，钝化层，中间源漏极层，第一平坦层，第二源漏极层以及第二平坦层的局部叠加示意图；
图36是本申请实施例提供的一种显示面板的制备方法的流程图；
图37是本申请实施例提供的一种显示面板中的第一导电层的局部示意图；
图38是本申请实施例提供的一种在显示面板中形成第一导电层后的局部叠加示意图；
图39是本申请实施例提供的一种显示面板中的第一绝缘层的局部示意图；
图40是本申请实施例提供的一种在显示面板中形成第一绝缘层后的局部叠 加示意图；
图41是本申请实施例提供的一种显示面板中的第二导电层的局部示意图；
图42是本申请实施例提供的一种在显示面板中形成第二导电层后的局部叠加示意图；
图43是本申请实施例提供的一种显示面板中的第二绝缘层的局部示意图；
图44是本申请实施例提供的一种在显示面板中形成第二绝缘层后的局部叠加示意图；
图45是本申请实施例提供的一种显示面板中的第三导电层的局部示意图；
图46是本申请实施例提供的一种在显示面板中形成第三导电层后的局部叠加示意图；
图47是本申请实施例提供的一种显示面板中的第三绝缘层的局部示意图；
图48是本申请实施例提供的一种在显示面板中形成第三绝缘层后的局部叠加示意图；
图49是本申请实施例提供的一种显示面板中的第一电极层的局部示意图；
图50是本申请实施例提供的一种在显示面板中形成第一电极层后的局部叠加示意图；
图51是本申请实施例提供的一种显示面板中的像素界定层的局部示意图；
图52是本申请实施例提供的一种在显示面板中形成像素界定层后的局部叠加示意图；
图53是本申请实施例提供的一种显示面板中导电层的局部示意图；
图54是本申请实施例提供的一种显示模组的结构示意图；
图55是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，为了提高显示面板的屏占比，可以将显示装置的摄像头设置在显示面板的显示区域。且为了增大摄像头所在区域的透过率，通常将该摄像头所在区域(即，摄像头区域)中各像素单元的像素电路设置在非摄像头区域。位于非摄像头区域的像素电路通过连接走线与位于摄像头区域的发光元件连 接，从而为位于摄像头区域的发光元件提供驱动信号，以驱动发光元件发光。
但是，由于与摄像头区域的发光元件连接的像素电路需要设计在非摄像头区域，因此可能会导致非摄像头区域需要设计的像素电路较多，进而会导致各个像素电路所能够占用的空间过小，工艺上难以制备。
本申请实施例提供了一种显示面板，该显示面板例如可以为有机发光二极管(organic light-emitting diode，OLED)显示面板，微型有机发光二极管(micro organic light-emitting diode，Micro OLED)显示面板，量子点有机发光二级管(quantum dot light emitting diodes，QLED)显示面板，迷你型发光二极管(mini light-emitting diode，Mini LED)显示面板或微型发光二极管(micro light-emitting diode，Micro LED)显示面板等。以下以显示面板为OLED显示面板为例进行介绍。
图1是本申请实施例提供的一种显示面板的局部结构示意图。图2是图1所示的显示面板的局部放大示意图。图3是本申请实施例提供的一种衬底基板的俯视图。图4是本申请实施例提供的一种显示面板的局部截面图。结合图1至图4，显示面板10可以包括衬底基板101，位于衬底基板101的一侧的驱动电路层102，以及第一电极层103。
其中，衬底基板101具有第一显示区101a，以及至少部分围绕第一显示区101a的第二显示区101b。该第一显示区101a可以为屏下摄像头区(full display with camera，FDC)。该第一显示区101a为圆形区域或者方形区域。
驱动电路层102包括位于第二显示区101b的多个第一像素电路A1和多个第二像素电路A2。其中图3中示出了一个第一像素电路A1和一个第二像素电路A2。
第一电极层103至少包括多个第一类电极图案1031，多个第一类电极图案1031包括位于第一显示区101a的多个第一电极图案1031a，以及位于第二显示区101b的多个第二电极图案1031b。显示面板10包括不同颜色的多个子像素，每个子像素可以发光器件和控制发光器件发光的像素电路，通过像素电路调节不同颜色的子像素的亮度(灰阶)，通过颜色组合和叠加可以实现多种颜色的显示，从而实现显示面板10的全彩化显示。其中，发光器件可以包括一个电极图案。上述多个第一类电极图案1031所属的子像素发出的光线的颜色可以相同。
至少两个第一电极图案1031a与多个第一像素电路A1中的一个第一像素电路A1连接。由此可以使得一个第一像素电路A1为两个第一电极图案1031a提供数据驱动信号。并且，至少两个第二电极图案1031b与多个第二像素电路A2中的一个第二像素电路A2连接。由此可以使得一个第二像素电路A2为两个第二电极图案1031b提供数据驱动信号。
在本申请实施例中，第一显示区101a中的至少两个第一电极图案1031a可以通过位于第二显示区101b的一个第一像素电路A1来驱动，第二显示区101b中的至少两个第二电极图案1031b可以通过位于第二显示区101b的一个第二像素电路A2来驱动。由此，在电极图案的数量相同的情况下，采用一个像素电路驱动两个电极图案的方案相对于采用一个像素电路驱动一个电极图案的方案而言，能够减少第二显示区101b中所需设计的像素电路的数量，进而能够增大每个像素电路所能够占用的空间，工艺制备难度较低。
综上所述，本申请实施例提供了一种显示面板，由于显示面板中至少两个第一电极图案连接，且连接的至少两个第一电极图案中的一个第一电极图案与一个第一像素电路连接，因此可以使得一个第一像素电路驱动两个第一电极图案。同时，由于至少两个第二电极图案连接，且连接的至少两个第二电极图案中的一个第二电极图案与一个第二像素电路连接，因此可以使得一个第二像素电路驱动两个第二电极图案。由此，在电极图案的数量相同的情况下，采用一个像素电路驱动两个电极图案的方案，能够减少第二显示区中所需设计的像素电路的数量，进而能够增大每个像素电路所能够占用的空间，工艺制备难度较低。
在一些实施例中，衬底基板101和驱动电路层102位于第一显示区101a的部分透光度较高。示例的，衬底基板101可以为透明玻璃基板，提供较高的透明度。驱动电路层102在第一显示区101a中不设置电路结构(即第一像素电路A1以及第二像素电路A2均设置在第二显示区101b，而未设置在第一显示区101a)，保持驱动电路层102足够的透明度。在显示装置中，衬底基板101远离驱动电路层102一侧可以设置有传感器，例如摄像头、接近光传感器、3D感测模块等光学传感器，且传感器在衬底基板101上的正投影位于第一显示区101a。光学传感器的感光面朝向显示面板10的显示面一侧，用于接收显示面板10的显示面一侧的环境光。示例的，第一电极层103中的位于第一显示区101a 的第一电极图案1031a采用透明导电材料，例如，氧化铟锡(ITO)、氧化铟锌(IZO)，从而使得第一显示区101a的光线透过率较高，适合放置摄像头等透过率要求高的器件。从而显示面板10能实现在显示区全屏显示。在第一显示区101a设置光学传感器，且光学传感器能够透过第一显示区101a中的膜层接收外部光线，实现相应功能。
参考图1和图2，显示面板10还可以包括：多条第一连接走线L1，多条第二连接走线L2以及多个第三连接走线L3。多条第一连接走线L1位于第一显示区101a。多条第二连接走线L2沿像素行方向X从第二显示区101b延伸至第一显示区101a，且位于第一显示区101a和第二显示区101b。多条第三连接走线L3位于第二显示区101b。
至少两个第一电极图案1031a通过一条第一连接走线L1连接，且至少两个第一电极图案1031a中的一个第一电极图案1031a通过一条第二连接走线L2与一个第一像素电路A1连接。由此可以使得一个第一像素电路A1为两个第一电极图案1031a提供数据驱动信号。并且，至少两个第二电极图案1031b通过一条第三连接走线L3连接，且至少两个第二电极图案1031b中的一个第二电极图案1031b与一个第二像素电路A2连接。由此可以使得一个第二像素电路A2为两个第二电极图案1031b提供数据驱动信号。
在本申请实施例中，参考图1和图2，显示面板10还包括多条第四连接走线L4和多条第五连接走线L5。多条第四连接走线L4和多条第五连接走线L5均沿像素行方向X从第二显示区101b延伸至第一显示区101a。结合图1，图5以及图6，第一电极层103还包括多个第二类电极图案1032和多个第三类电极图案1033。多个第二类电极图案1032包括位于第一显示区101a的多个第三电极图案1032a，以及位于第二显示区101b的多个第四电极图案1032b。多个第三类电极图案1033包括位于第一显示区101a的多个第五电极图案1033a，以及位于第二显示区101b的多个第六电极图案1033b。
其中，第三电极图案1032a通过一条第四连接走线L4与一个第一像素电路A1连接，第四电极图案1032b与一个第二像素电路A2连接。第五电极图案1033a通过第五连接走线L5与一个第一像素电路A1连接，第六电极图案1033b与一个第二像素电路A2连接。也即是，多个第三电极图案1032a以及多个第五电极图案1033a中的每个电极图案均通过一个第一像素电路A1来驱动。多个第四电 极图案1032b以及多个第六电极图案1033b中的每个电极图案均通过一个第二像素电路A2来驱动。
在本申请实施例中，参考图7，在第一显示区101a中，多个第一电极图案1031a，多个第三电极图案1032a以及多个第五电极图案1033a可以排列成多行，排成一行的多个电极图案称为第一图案行M。至少一个第一图案行M包括排成一行的至少两个第一电极图案1031a，至少一个第三电极图案1032a以及至少一个第五电极图案1033a。第一图案行M中的至少两个第一电极图案1031a通过第一连接走线L1连接。
可选的，第一图案行M按照第三电极图案1032a，第一电极图案1031a，第五电极图案1033a以及第一电极图案1031a的次序循环设置。示例的，多个第一图案行M排列为多行，每个第一图案行M包括平行设置的第一子图案行M1和第二子图案行M2。第一子图案行M1中第三电极图案1032a和第五电极图案1033a交替设置，第二子图案行M2中多个第一电极图案1031a依次设置。第二子图案行M2的第一电极图案1031a的个数与第二子图案行M2中第三电极图案1032a和第五电极图案1033a的总个数一致，且第一电极图案1031a设置于与其相邻的第三电极图案1032a和第五电极图案1033a的中轴线上。
另外，在第二显示区101b中，多个第二电极图案1031b，多个第四电极图案1032b以及多个第六电极图案1033b可以排列成多行，排成一行的电极图案称为第二图案行(图中未示出)。至少一个第二图案行包括排成一行的至少两个第二电极图案1031b，至少一个第四电极图案1032b以及至少一个第六电极图案1033b。第二图案行中的至少两个第二电极图案1031b通过第三连接走线L3连接。
可选的，第二图案行按照第四电极图案1032b，第二电极图案1031b，第六电极图案1033b以及第二电极图案1031b的次序循环设置。示例的，多个第二图案行排列为多行，每个第二图案行包括平行设置的第三子图案行和第四子图案行。第三子图案行中第四电极图案1032b和第六电极图案1033b交替设置，第四子图案行中多个第二电极图案1031b依次设置。第四子图案行的第二电极图案1031b的个数与第三子图案行中第四电极图案1032b和第六电极图案1033b的总个数一致，且第二电极图案1031b设置于与其相邻的第四电极图案1032b和第六电极图案1033b的中轴线上。
当然，多个第一电极图案1031a，多个第三电极图案1032a以及多个第五电极图案1033a也可以排列成多列，多个第二电极图案1031b，多个第四电极图案 1032b以及多个第六图案也可以排列成多列。排成多列的方式和排成多行的方式类似，本申请实施例在此不再赘述。
在本申请实施例中，多个第二类电极图案1032所属的子像素发出的光线的颜色可以相同，多个第三类电极图案1033所属的子像素发出的光线的颜色可以相同。示例的，多个第一类电极图案1031所属的子像素可以为绿色子像素，该绿色子像素发出的光线的颜色为绿色。多个第二类电极图案1032所属的子像素可以为红色子像素和蓝色子像素中的一种，多个第三类电极图案1033所属的子像素可以为红色子像素和蓝色子像素中的另一种。例如，多个第二类电极图案1032所属的子像素可以为红色子像素，多个第三类电极图案1032所属的子像素可以为蓝色子像素。红色子像素发出的光线的颜色为红色，蓝色子像素发出的光线的颜色为蓝色。也即是，在本申请实施例中，一个像素电路用于驱动两个绿色子像素，一个像素电路用于驱动一个红色子像素或一个蓝色子像素。
在本申请实施例中，参考图1，相邻的两个第一像素电路A1和三个第二像素电路A2构成一个电路组A。至少两个第二电极图案1031b构成一个电极图案组，相邻的一个电极图案组，一个第四电极图案1032b以及一个第六电极图案1033b构成一个图案组B。每个图案组B与一个电路组A对应，且对于相对应的图案组B和电路组A，图案组B在衬底基板101上的正投影的所处区域，与电路组A在衬底基板101上的正投影的所处区域存在交叠。
可选的，每个电路组A以及与该电路组A对应的图案组B，电路组A(五个像素电路)所占的空间相当于图案组B(四个电极图案)所占的空间。也即是，四个电极图案的下侧对应设置五个像素电路。
对于每个电路组A以及与该电路组A对应的一个图案组B，电路组A包括的三个第二像素电路A2中，第一个第二像素电路A2与图案组B中的电极图案组的一个第二电极图案1031b连接，第二个第二像素电路A2与图案组B中的第四电极图案1032b连接，第三个第二像素电路A2与图案组B中的第六电极图案1033b连接。也即是，每个电路组A包括的五个像素电路中，其中三个第二像素电路A2可以作为驱动位于第二显示区101b的图案组B中的四个电极图案的像素电路。
另外，显示面板10中的一部分电路组A包括的两个第一像素电路A1与位于第一显示区101a的电极图案连接，另一部分电路组A包括的两个第一像素电路A1与固定电压端连接。也即是，显示面板10的电路组A中，某些电路组A 中的两个第一像素电路A1可以作为驱动位于第一显示区101a的电极图案的像素电路，其余电路组A中的两个第一像素电路A1不与第一显示区101a的电极图案连接，而是作为虚设(dummy)像素电路与固定电压端连接。由于虚设像素电路与固定电压端连接，因此可以避免虚设像素电路对显示面板10中各个信号线传输的信号造成影响，保证显示面板10的显示效果。
在本申请实施例中，与第一显示区101a的电极图案连接的第一像素电路A1所属的电路组A，相对于与固定电压端连接的第一像素电路A1所属的电路组A更靠近第一显示区101a。由此，可以使得用于连接位于第一显示区101a的电极图案与位于第二显示区101b的第一像素电路A1的第二连接走线L2的长度较短，能够提高第二连接走线L2传输信号的可靠性，确保显示面板10的显示效果。
在本申请实施例中，一个第一像素电路A1向两个第一电极图案1031a提供数据驱动信号，若连接第一像素电路A1和两个第一电极图案1031a的第二连接走线L2长度过长，容易受到电阻-电容干扰，造成第一电极图案1031a所属的子像素在低灰阶下无法起亮的情况发生。
因此，参考图1和图2，任一第二连接走线L2沿像素行方向X的长度，小于第四连接走线L4沿像素行方向X的长度，且小于第五连接走线L5沿像素行方向X的长度。也即是，第一电极图案1031a相对于第三电极图案1032a以及第五电极图案1033a而言，第一电极图案1031a可以优先通过第二连接走线L2和第二显示区101b的第一像素电路A1连接。由此，可以减小与第一电极图案1031a连接的第二连接走线L2的长度，减弱第二连接走线L2受电阻-电容的干扰强度，确保第一显示区101a中的每个子像素都能够在低灰阶下正常显示。
当然，参考图8和图9，多条第二连接走线L2，多条第四连接走线L4以及多条第五连接走线L5中的每个连接走线，连接走线沿像素行方向X的长度，与连接走线所连接的位于第一显示区101a的电极图案沿像素行方向X和第二显示区101b之间的距离正相关。也即是，位于第一显示区101a的电极图案依次通过第二连接走线L2与第二显示区101b的第一像素电路A1连接。
参考图3，第二显示区101b可以包括第一子显示区101b1，第二子显示区101b2和第三子显示区101b3。其中，第一子显示区101b1和第一显示区101a沿像素列方向Y排布，第二子显示区101b2和第一显示区101a沿像素行方向X 排布，第三子显示区101b3和第一子显示区101b1沿像素行方向X排布，且和第二子显示区101b2沿像素列方向Y排布。
其中，第二显示区101b可以包括一个第一子显示区101b1，两个第二子显示区101b2以及两个第三子显示区101b3。第一子显示区101b1可以位于第一显示区101a的下侧，两个第二子显示区101b2可以分别位于第一显示区101a沿像素行方向X的两侧，两个第三子显示区101b3可以位于第一子显示区101b1沿像素行方向X的两侧。第二子显示区101b2和第三子显示区101b3均可以为显示面板的过渡显示区。
参考图10，显示面板10还可以包括：位于第一子显示区101b1的多条第一数据线S1，位于第二子显示区101b2和第三子显示区101b3的多条第二数据线S2，以及位于第一子显示区101b1和第三子显示区101b3的多条第一转接线Z1。
其中，多条第一数据线S1沿像素行方向X排布且沿像素列方向Y延伸，多条第二数据线S2沿像素行方向X排布且沿像素列方向Y延伸，多条第一转接线Z1沿像素列方向Y排布且沿像素行方向X延伸。每条第一数据线S1的第一端用于与数据驱动电路连接，每条第一数据线S1的第二端与一条第一转接线Z1的第一端连接，每条第一转接线Z1的第二端与一条第二数据线S2的第一端连接。由此可以使得数据驱动电路提供的数据驱动信号能够通过第一数据线S1，第一转接线Z1以及第二数据线S2传输，并且相连接的一条第一数据线S1，一条第一转接线Z1以及一条第二数据线S2传输的数据驱动信号相同。
相对于第三子显示区101b3远离第二子显示区101b2的边界，第二数据线S2的第一端更靠近第三子显示区101b3靠近第二子显示区101b2的边界。也即是，第二数据线S2的沿像素列方向Y的长度可以略大于第二子显示区101b2沿像素列方向Y的长度，只需使得第二数据线S2的第一端能够位于第三子显示区101b3，进而能够便于第二数据线S2位于第三子显示区101b3的第一端与第一转接线Z1位于第三子显示区101b3的第二端连接。
每条第一数据线S1还与位于第一子显示区101b1中用于连接第一目标电极图案的一列第二像素电路A2连接，每条第二数据线S2还与位于第二子显示区101b2中用于连接第二目标电极图案的一列第一像素电路A1连接。
对于通过一条第一转接线Z1相连接的第一数据线S1和第二数据线S2，该第一数据线S1通过一列第二像素电路A2连接的一列第一目标电极图案，以及 第二数据线S2通过一列第一像素电路A1连接的一列第二目标电极图案可以沿像素列方向Y排布。由此可以使得位于第一显示区101a以及第一子显示区101b1中位于同一列的电极图案能够获得相同的数据驱动信号。
在本申请实施例中，第一目标电极图案至少为第四电极图案1032b和第六电极图案1033b中的一种，第二目标电极图案至少为第三电极图案1032a和第五电极图案1033a中的一种。
作为第一种可选的实现方式，第一目标电极图案为第四电极图案1032b或第六电极图案1033b，第二目标电极图案为第三电极图案1032a或第五电极图案1033a。参考图10，显示面板10还可以包括：位于第一子显示区101b1的多条第三数据线S3，以及位于第二显示区101b和第三子显示区101b3的多条第四数据线S4。多条第三数据线S3沿像素行方向X排布且沿像素列方向Y延伸，多条第四数据线S4沿像素行方向X排布且沿像素列方向Y延伸。每条第三数据线S3的第一端以及每条第四数据线S4的第一端均用于与数据驱动电路连接。每条第三数据线S3还与位于第一子显示区101b1中用于连接第二电极图案1031b的一列第二像素电路A2连接，每条第四数据线S4还与位于第二子显示区101b2中用于连接第一电极图案1031a的一列第一像素电路A1连接。
也即是，数据驱动电路提供的数据驱动信号可以通过第三数据线S3传输至位于第一子显示区101b1的一列第二像素电路A2，进而驱动与该列第二像素电路A2连接的一列第二电极图案1031b。并且，数据驱动电路提供的数据驱动信号可以通过第四数据线S4传输至位于第二子显示区101b2的一列第一像素电路A1，进而驱动与该列第一像素电路A1连接的一列第一电极图案1031a。
在该第一种实现方式中，显示面板10中位于同一列的第二类电极图案1032(第三电极图案1032a和第四电极图案1032b)获得的数据驱动信号通过第一转接线Z1转接传输。位于同一列的第三类电极图案1033(第五电极图案1033a和第六电极图案1033b)获得的数据驱动信号通过第一转接线Z1转接传输。位于同一列的第一类电极图案1031(第一电极图案1031a和第二电极图案1031b)获得的数据驱动信号直接通过与数据驱动电路连接的数据线(第三数据线S3或第四数据线S4)传输，无需采用第一转接线Z1转接传输。由此，可以降低与第一类电极图案1031连接的数据线的长度(转接传输的方案中，数据线的长度为相连接的数据线以及转接线的总长度)，进而降低数据线的电阻和电容，提高 像素电路的驱动能力，优化显示效果。
参考图3，第二显示区101b还可以包括：第四子显示区101b4和第五子显示区101b5。第四子显示区101b4位于第一显示区101a远离第一子显示区101b1的一侧，第五子显示区101b5和第四子显示区101b4沿像素行方向X排布。例如，第二显示区101b可以包括一个第四子显示区101b4和两个第五子显示区101b5，一个第四子显示区101b4可以位于第一显示区101a的上侧，两个第五子显示区101b5分别位于第四子显示区101b4沿像素行方向X的两侧。该第五子显示区101b5可以称为过渡显示区。
可选的，第一显示区101a可以位于第二显示区101b的内部，第二显示区101b可以完全包围第一显示区101a。由此，为了向第一显示区101a远离第一子显示区101b1的第四子显示区101b4传输数据驱动信号，可以使得显示面板10包括：多条第二转接线Z2，多条第三转接线Z3，位于第四子显示区101b4的多条第五数据线S5和多条第六数据线S6。其中，多条第五数据线S5沿像素行方向X排布且沿像素列方向Y延伸，多条第六数据线S6沿像素行方向X排布且沿像素列方向Y延伸。多条第二转接线Z2沿像素列方向Y排布且沿像素行方向X延伸，多条第三转接线Z3沿像素列方向Y排布且沿像素行方向X延伸。
每条第二数据线S2的第二端与一条第二转接线Z2的第一端连接，每条第二转接线Z2的第二端与第五数据线S5的第一端连接。第五数据线S5还与位于第四子显示区101b4中用于连接第一目标电极图案的一列第二像素电路A2连接。每条第四数据线S4的第二端与一条第三转接线Z3的第一端连接，每条第三转接线Z3的第二端与第六数据线S6的第一端连接。第六数据线S6还与位于第四子显示区101b4中用于连接第二电极图案1031b的一列第二像素电路A2连接。由此，数据驱动电路可以依次通过第一数据线S1，第一转接线Z1，第二数据线S2，第二转接线Z2以及第五数据线S5向位于第四子显示区101b4中用于连接第一目标电极图案的一列第二像素电路A2提供数据驱动信号。数据驱动电路依次通过第四数据线S4，第三转接线Z3以及第六数据线S6向位于第四子显示区101b4中用于连接第二电极图案1031b的一列第二像素电路A2提供数据驱动信号。也即是，此种方案中，第四子显示区101b4中的各个第二像素电路A2均需通过转接信号的方式获取数据驱动信号。
参考图3，衬底基板101还具有围绕第二显示区101b的周边区101c。多条 第二数据线S2的第二端，多条第二转接线Z2，多条第五数据线S5的第一端，多条第四数据线S4的第二端，多条第三转接线Z3，以及多条第六数据线S6的第一端均可以位于周边区101c，且位于第四子显示区101b4远离所述第一显示区101a的区域。也即是，第二数据线S2和第二转接线Z2的连接处，第二转接线Z2和第五数据线S5的连接处，第四数据线S4和第三转接线Z3的连接处，以及第三转接线Z3和第六数据线S6的连接处均可以位于周边区101c。
作为第二种可选的实现方式，第一目标电极图案为第二电极图案1031b，第四电极图案1032b以及第六电极图案1033b中的一种，第二目标电极图案为第一电极图案1031a，第三电极图案1032a以及第五电极图案1033a中的一种。
在该第二种实现方式中，显示面板10中位于同一列的第二类电极图案1032(第三电极图案1032a和第四电极图案1032b)获得的数据驱动信号通过第一转接线Z1转接传输。位于同一列的第三类电极图案1033(第五电极图案1033a和第六电极图案1033b)获得的数据驱动信号通过第一转接线Z1转接传输。位于同一列的第一类电极图案1031(第一电极图案1031a和第二电极图案1031b)获得的数据驱动信号第一转接线Z1转接传输。
若第二显示区101b完全包围第一显示区101a，参考图11，第二显示区101b还包括：第四子显示区101b4和第五子显示区101b5，则为了向第一显示区101a远离第一子显示区101b1的第四子显示区101b4传输数据驱动信号，可以使得显示面板10包括：多条第二转接线Z2，以及位于第四子显示区101b4的多条第五数据线S5。
其中，多条第五数据线S5沿像素行方向X排布且沿像素列方向Y延伸。多条第二转接线Z2沿像素列方向Y排布且沿像素行方向X延伸。每条第二数据线S2的第二端与一条第二转接线Z2的第一端连接，每条第二转接线Z2的第二端与第五数据线S5的第一端连接。第五数据线S5还与位于第四子显示区101b4中用于连接第一目标电极图案的一列第二像素电路A2连接。由此，数据驱动电路可以依次通过第一数据线S1，第一转接线Z1，第二数据线S2，第二转接线Z2以及第五数据线S5向位于第四子显示区101b4中用于连接第一目标电极图案的一列第二像素电路A2提供数据驱动信号。
参考图11，衬底基板101还具有围绕第二显示区101b的周边区101c。多条第二数据线S2的第二端，多条第二转接线Z2，以及多条第五数据线S5的第一 端均可以位于周边区101c，且位于第四子显示区101b4远离所述第一显示区101a的区域。也即是，第二数据线S2和第二转接线Z2的连接处，以及第二转接线Z2和第五数据线S5的连接处均可以位于周边区101c。
在本申请实施例中，显示面板10还包括：位于第三子显示区101b3的多条第一虚设数据线D1。该多条第一虚设数据线D1可以沿像素行方向X排布且沿像素列方向Y延伸。该第一虚设数据线D1的一端用于与固定电压端连接，且第一虚设数据线D1还与位于第三子显示区101b3的一列第一像素电路A1连接。
其中，位于第三子显示区101b3的第一像素电路A1可以为虚设像素电路，虚设像素电路可以是指不与任何电极图案连接的像素电路。固定电压端可以通过第一虚设数据线D1向虚设像素电路提供固定电压信号，从而可以避免该虚设像素电路对显示面板10中各个信号线传输的信号造成影响，保证显示面板10的显示效果。
可选的，第一虚设数据线D1可以与上述实施例提到的其他数据线(比如第二数据线S2)同层设置，当然也可以异层设置，本申请实施例对此不做限定。若第一虚设数据线D1与上述实施例提到的其他数据线同层设置，则可以使得该第一虚设数据线D1与其他数据线之间具有间隔，进而避免第一虚设数据线D1和其他数据线相互影响，使得第一虚设数据线D1传输固定电压信号，而其他数据线传输数据驱动信号。
对于上述第一种实现方式，显示面板10包括的位于第三子显示区101b3的多条第一虚设数据线D1中，一部分第一虚设数据线D1可以与其他数据线同层设置，另一部分第一虚设数据线D1与其他数据线异层设置。可选的，与其他数据线同层设置的每条第一虚设数据线D1可以与一条第二数据线S2共线且具有间隔。同时，由于第四数据线S4位于第三子显示区101b3，且要穿过第三子显示区101b3与数据驱动电路连接，因此为了避让第四数据线S4，需设计与第四数据线S4异层设置的第一虚设数据线D1与位于第三子显示区101b3的一列第一像素电路A1连接。其中，该位于第三子显示区101b3的一列第一像素电路A1与第四数据线S4连接的位于第二子显示区101b2的第一像素电路A1位于同一列。
对于上述第二种实现方式，显示面板10包括的位于第三子显示区101b3的多条第一虚设数据线D1中，所有第一虚设数据线D1均可以和其他数据线同层 设置，当然也可以异层设置。
在本申请实施例中，第二显示区101b还包括第六子显示区101b6。该第六子显示区101b6可以称为正常显示区。可选的，第二显示区101b包括两个第六子显示区101b6，两个第六子显示区101b6可以分别位于第一个第三子显示区101b3，第一子显示区101b1，以及第二个第三子显示区101b3沿像素行方向X的两侧，且位于第一个第二子显示区101b2，第一显示区101a，以及第二个第二子显示区101b2沿像素行方向X的两侧。
显示面板10还可以包括：位于第六子显示区101b6的多条第七数据线S7，以及位于第六子显示区101b6的多条第二虚设数据线D2。每条第七数据线S7的一端用于连接数据驱动电路，且每条第七数据线S7还与位于第六子显示区101b6中的一列第二像素电路A2连接。由此可以使得数据驱动电路通过第七数据线S7向第二像素电路A2提供数据驱动信号。每条第二虚设数据线D2的一端用于连接固定电压端，且每条第二虚设数据线D2还与位于第六子显示区101b6中的一列第一像素电路A1连接。由此可以使得固定电压端通过第二虚设数据线D2向第一像素电路A1提供固定电压信号。其中，位于第六子显示区101b6中的第一像素电路A1可以为虚设像素电路。
在本申请实施例中，第三连接走线L3可以和第一连接走线L1以及第二连接走线L2均异层设置。例如，参考图4，显示面板10可以包括位于驱动电路层102和第一电极层103之间的连接层104。第一连接走线L1和第二连接走线L2可以位于该连接层104，即第一连接走线L1和第二连接走线L2可以均位于驱动电路层102和第一电极层103之间。第三连接走线L3位于第一电极层103。
可选的，第一电极层103包括的电极图案可以为第一膜层，第二膜层以及第三膜层的层叠结构。第一膜层和第三膜层的材料可以为氧化铟锡(Indium tin oxide，ITO)，第二膜层的材料可以为银(Ag)，即电极图案可以为ITO/Ag/ITO的叠层。第三连接走线L3位于第一电极层103可以是指：第三连接走线L3与电极图案相同，也为ITO/Ag/ITO的叠层；或者，第三连接走线L3可以为电极图案包括的一层ITO(如第一膜层或第三膜层)。
可选的，连接层104可以包括至少一层导电层和至少一层绝缘层，且每层导电层远离衬底基板101一侧均设置有一层绝缘层。
示例的，该连接层104可以包括：位于驱动电路层102远离衬底基板101 的一侧依次层叠的第一导电层1041，第一绝缘层1042，第二导电层1043，第二绝缘层1044，第三导电层1045以及第三绝缘层1046。该第一导电层1041，第二导电层1043以及第三导电层1045中的每个导电层包括多条第一连接走线L1和/或多条第二连接走线L2。第一绝缘层1042中具有第一过孔，第二绝缘层1044中具有第二过孔，第三绝缘层1046中具有第三过孔。第一导电层1041通过第一过孔与第二导电层1043电连接，第二导电层1043通过第二过孔与第三导电层1045电连接，第三导电层1045通过第三过孔与第一电极层103电连接。
在本申请实施例中，可以将用于连接位于第二显示区101b的第一像素电路A1和第一显示区101a的电极图案的连接走线(第二连接走线L2，第四连接走线L4以及第五连接走线L5)均匀分布于三个导电层，通过合理布置连接走线的位置，进而避免相邻的连接走线间距过小，造成短路或串扰问题。
需要说明的是，在第一显示区101a的面积较小，或者制备用于连接位于第二显示区101b的第一像素电路A1和第一显示区101a的电极图案的连接走线(第二连接走线L2，第四连接走线L4以及第五连接走线L5)的工艺精度较高，连接走线的宽度能够减小的情况下，可以将所有的连接走线布置于两层导电层甚至布置于一层导电层，这样可减少制备过程中掩膜板的使用数量，简化工艺，同时提高第一显示区101a的光线透过率以及降低显示面板10的整体厚度，实现显示面板10的轻薄化。
参考图4，各个导电层还设置有连接部，连接部可以用于将连接走线与像素电路连接，或者将位于不同层的连接走线连接，又或者将连接走线与第一电极层103中的电极图案连接。例如，第一导电层1041可以包括多个第一连接部1041a，第二导电层1043可以包括多个第二连接部1043a，第三导电层1045可以包括多个第三连接部1045a。
图4中，以第一连接走线L1位于第三导电层1045，第二连接走线L2位于第一导电层1041为例。在第二显示区101b中，第二像素电路A2与第一连接部1041a连接，第一连接部1041a与第二连接部1043a连接，第二连接部1043a与第三连接部1045a连接，第三连接部1045a与一个电极图案(第二电极图案1031b，第四电极图案1032b或第六电极图案1033b)连接。若第三连接部1045a与一个第二电极图案1031b连接，则该第三连接部1045a还与第三连接走线L3连接，第三连接走线L3与另一第三连接部1045a连接，该另一第三连接部1045a与另一第二电极图案1031b连接。在第一显示区101a中，第二连接走线L2通 过一个第一连接部1041a与第一像素电路A1连接，第二连接走线L2通过另一个第一连接部1041a与第二连接部1043a连接，第二连接部1043a与第三连接部1045a连接，第三连接部1045a与一个电极图案(第一电极图案1031a，第三电极图案1032a或第五电极图案1033a)连接。若第三连接部1045a与一个第一电极图案1031a连接，则该第三连接部1045a还与第一连接走线L1连接，第一连接走线L1与另一第三连接部1045a连接，该另一第三连接部1045a与另一第二电极图案1031b连接。
其中，第三连接部1045a在衬底基板101上的正投影，可以与该第三连接部1045a连接的电极图案在衬底基板101上的正投影至少部分交叠，从而使得电极图案通过贯穿第三绝缘层1046的第三过孔与第三连接部1045a连接。相连接的第二连接部1043a和第三连接部1045a在衬底基板101上的正投影至少部分交叠，从而使得第三连接部1045a通过贯穿第二绝缘层1044的第二过孔与第二连接部1043a连接。相连接的第一连接部1041a和第二连接部1043a在衬底基板101上的正投影至少部分交叠，从而使得第二连接部1043a通过贯穿第一绝缘层1042的第一过孔与第一连接部1041a连接。相连接的第一连接部1041a和像素电路在衬底基板101上的正投影至少部分交叠，从而使得第一连接部1041a能够与像素电路连接。由此，通过在各导电层中设置连接部，可以使得像素电路与电极图案的连接更加稳定。
可选的，第一导电层1041，第二导电层1043以及第三导电层1045均包括透明导电材料。例如第一导电层1041，第二导电层1043以及第三导电层1045的材料可以为氧化铟锡或氧化铟锌。连接层104包括的各个绝缘层包括透明绝缘材料。例如第一绝缘层1042，第二绝缘层1044以及第三绝缘层1046的材料可以为聚酰亚胺(Polyimide，PI)。
在本申请实施例中，参考图4，显示面板10还包括发光膜层105，像素界定层106，第二电极层107，封装层108以及缓冲层(buffer)109。其中，封装层108覆盖在第二电极层107远离衬底基板101的一侧，实现对显示面板10的封装。缓冲层109可以位于衬底基板101和驱动电路层102之间。
第一电极层103，像素界定层106，发光膜层105，以及第二电极层107可以构成多个发光器件，例如构成多个OLED。其中，发光膜层105包括多个发光层1051，像素界定层106具有多个开口，每个开口暴露第一电极层103中的一个电极图案，每个发光层1051位于一个开口内并与电极图案接触，第二电极层107位于开口内的部分作为发光器件的第二电极。从而依次堆叠的电极图案(阳 极)，发光层1051和第二电极(阴极)组成发光器件。
驱动电路层102中的像素电路可以与发光器件电连接，如像素电路可以与发光器件中第一电极层103的电极图案电连接，以控制发光器件发光。
在一些实施例中，驱动电路层102包括依次层叠设置于衬底基板101上的半导体层10201、第一栅极绝缘层(gate insulator，GI)10202、第一栅极层(gate)10203、第二栅极绝缘层10204，第二栅极层10205，层间介电层(inter level dielectric，ILD)10206，第一源漏极层10207，钝化层(passivation layer，PVX)10208，中间源漏极层10209，第一平坦层(planarization layer，PLN)10210，第二源漏极层10211以及第二平坦层10212，驱动电路层102中的多个像素电路呈阵列排布，每个像素电路包括多个薄膜晶体管。上述连接层104中的第一导电层1041位于第二平坦层10212远离衬底基板101的一侧。第一绝缘层1042可以称为第三平坦层，第二绝缘层1044可以称为第四平坦层，第三绝缘层1046可以称为第五平坦层。驱动电路层102中的像素电路可以通过连接层104与发光器件实现电连接。
可选的，第一源漏极层10207可以包括各个像素电路中薄膜晶体管的源极和漏极，该源极和漏极可以具有间隔。当然，第一源漏极层10207还可以包括上述实施例所述的转接线(第一转接线Z1，第二转接线Z2和第三转接线Z3)。中间源漏极层10209可以包括用于为显示面板10提供电源信号的电源走线(例如VDD走线)。或者，中间源漏极层10209还可以包括上述实施例所述的转接线(第一转接线Z1，第二转接线Z2和第三转接线Z3)。第二源漏极层可以包括上述实施例所述的数据线(第一数据线S1，第二数据线S2，第三数据线S3，第四数据线S4，第五数据线S5，第六数据线S6和第七数据线S7)和虚设数据线(第一虚设数据线D1和第二虚设数据线D2)。
需要说明的是，对于较高的像素分辨率(pixels per inch，PPI)的显示面板中像素电路的设计，若第二显示区的第六子显示区(正常显示区)中，仅设置用于驱动位于第二显示区中的电极图案的像素电路，而不设置虚设像素电路，且每个像素电路驱动一个电极图案，则参考图12，每个像素电路在像素行方向上所能够占用的空间可以相对较大，为29.8μm(微米)。而此种方案中，为了提高第一显示区的透过率，需使得用于驱动位于第一显示区的电极图案的像素电路设置在第二显示区的第二子显示区(过渡显示区)。由此可能会导致第二显示区中不同子区的像素电路排布不同，显示面板中像素电路的均一性较差。
由此，为了提高显示面板中像素电路的设计均一性，可以在第六子显示区 中设计虚设像素电路，例如图13中，每两个第二像素电路设计一个第一像素电路(虚设像素电路)，即像素电路二压一的设计(像素电路二压一可以是指原本需要设计两个第二像素电路的位置，需要额外再设计一个虚设像素电路)。相对于图12而言，原本需要设计四个像素电路的位置，需要设计六个像素电路。但是，此种方案中，每个像素电路在像素行方向上所能占用的空间较小，为19.8μm，工艺上难以制备。
在本申请实施例中，由于本申请实施例通过一个第二像素电路驱动两个第二电极图案，因此可以减少所需设计的像素电路的数量。相对于图13而言，在图14中，原本需要设计六个像素电路的位置，仅需设计五个像素电路。每个像素电路在像素行方向所能占用的空间可以较大，为23.83μm，制备难度较低。并且，第二显示区中各个子区中的像素电路排布不同，显示面板中像素电路的均一性也较好。
参考图14，五个像素电路(一个电路组)中的三个第二像素电路和两个第一像素电路可以按照第二像素电路，第二像素电路，第一像素电路，第二像素电路以及第一像素电路的方式排布。当然，参考图15，五个像素电路中的三个第二像素电路和两个第一像素电路也可以按照第二像素电路，第二像素电路，第二像素电路，第一像素电路以及第一像素电路的方式排布。当然，排布方式也可以为其他方式，本申请实施例对此不做限定。
在本申请实施例中，第一像素电路和第二像素电路的等效电路图可以参考图16，该像素电路可以包括多个薄膜晶体管和一个存储电容器。多个薄膜晶体管包括数据第一复位控制晶体管T1，阈值补偿晶体管T2，驱动晶体管T3，写入晶体管T4，第一发光控制晶体管T5，第二发光控制晶体管T6以及第三复位控制晶体管T7。
存储电容器Cst可以包括两个电容极板Cst1和Cst2，在申请实施例中，电容极板Cst1可以称为存储电容器Cst的一端、第一端、第一极或第一存储电容电极，电容极板Cst2可以称为存储电容器Cst的另一端、第二端、第二极或第二存储电容电极。
其中，第一复位控制晶体管T1的第一极与复位电源信号线电连接以接收复位信号Vinit，第一复位控制晶体管T1的第二极与驱动晶体管T3的栅极电连接，第一复位控制晶体管T1的栅极与复位控制信号线电连接以接收复位控制信号Reset。阈值补偿晶体管T2的第一极与驱动晶体管T3的第一极连接，阈值补偿 晶体管T2的栅极与扫描信号线电连接以接收扫描信号Gate，阈值补偿晶体管T2的第二极与驱动晶体管T3的栅极连接。数据写入晶体管T4的第一极与驱动晶体管T3的第二极连接，数据写入晶体管T4的栅极与扫描信号线电连接以接收扫描信号Gate，数据写入晶体管T4的第二极与数据线连接以接收数据驱动信号Data。第一发光控制晶体管T5的第一极与第一电源信号线电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第二极电连接，第一发光控制晶体管T5的栅极与发光控制信号线电连接以接收发光控制信号EM。第二发光控制晶体管T6的栅极与发光控制信号线电连接以接收发光控制信号EM。第三复位控制晶体管T7的第一极与复位电源信号线连接以接收复位信号Vinit，第三复位控制晶体管T7的第二极与发光器件的电极图案连接，第一复位晶体管T7的栅极与复位控制信号线电连接以接收复位控制信号Reset。存储电容器Cst的第一极与第一电源信号线电连接，存储电容器Cst的第二极与驱动晶体管T3的栅极电连接。另外，发光器件的阴极可以与第二电源信号线电连接。上述第一电源信号线指输出电压信号VDD的信号线，第二电源信号线指输出电压信号VSS的信号线。
图17是本申请实施例提供的显示面板中的半导体层的局部示意图。参考图17，该半导体层可具有弯曲或弯折形状，半导体层包括各晶体管的半导体图案(沟道区)和掺杂区图案(源漏掺杂区)，且同一像素电路中的各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，半导体层可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个像素电路的各晶体管的半导体层为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和半导体图案，不同晶体管的半导体图案之间隔开。
半导体层可采用非晶硅，多晶硅，氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
图18是本申请实施例提供的显示面板中的第一栅极层的局部叠加示意图。其中，显示面板包括位于半导体层远离衬底基板一侧的第一栅极绝缘层，用于将上述的半导体层与后续形成的第一栅极层绝缘。图18示出了该显示面板包括的第一栅极层，第一栅极层设置在第一栅极绝缘层上，从而与半导体层绝缘。 第一栅极层可以包括第二存储电容电极Cst2，沿像素行方向X延伸的多条扫描信号线g1，多条复位控制信号线g2，多条发光控制信号线g3，且该第一栅极层还包括各个晶体管的栅极。
例如，结合图17至图19，数据写入晶体管T4的栅极可以为扫描信号线g1与半导体层交叠的部分；第二发光控制晶体管T6的栅极可以为发光控制信号线g3与半导体层交叠的第一部分，第一发光控制晶体管T5的栅极可以为发光控制信号线g3与半导体层交叠的第二部分。第一复位控制晶体管T1的栅极为复位控制信号线g2与半导体层交叠的第一部分，第三复位控制晶体管T7的栅极为复位控制信号线g2与半导体层交叠的第二部分。阈值补偿晶体管T2的栅极可为从扫描信号线g1突出的突出结构P与半导体层交叠的部分。如图18所示，驱动晶体管T3的栅极可为第二存储电容电极Cst2。
需要说明的是，图19中的各虚线矩形框示出了第一栅极层与半导体层交叠的各个部分。作为各个晶体管的沟道区，在每个沟道区两侧的半导体层通过离子掺杂等工艺导体化作为各个晶体管的第一极和第二极。晶体管的源极，漏极在结构上可以是对称的，所以其源极，漏极在物理结构上可以是没有区别的。在本申请实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本申请实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
如图18和图19所示，扫描信号线g1，复位控制信号线g2和发光控制信号线g3沿像素列方向Y排布。在像素列方向Y上，第二存储电容电极Cst2(即驱动晶体管T3的栅极)位于扫描信号线g1和发光控制信号线g3之间。从扫描信号线g1突出的突出结构P位于扫描信号线g1靠近发光控制信号线g3的一侧。
另外，上述的第一栅极层上可以形成有第二栅极绝缘层，用于将上述的第一栅极层与后续形成的第二栅极层绝缘。
图20是本申请实施例提供的一种显示面板中第二栅极层的局部示意图，图21是本申请实施例提供的显示面板中的半导体层，第一栅极层以及第二栅极层的局部叠加示意图。如图20和图21所示，第二栅极层包括第一存储电容电极Cst1，沿像素行方向X延伸的多条第一复位电源信号线g4和沿像素行方向X延伸的多条第二复位电源信号线g5。第一存储电容电极Cst1与第二存储电容电极Cst2至少部分重叠以形成存储电容器Cst。
另外，上述的第二栅极层上可以形成有层间介电层，用于将上述的第二栅极层与后续形成的第一源漏极层绝缘。参考图22和图23，为了便于示出层间介电层(ILD)中的各个过孔，图22至图23中采用填充图案表示过孔。其他未绘制填充图案的区域用于表示层间介电层具有实材的区域。需要说明的是，该层间介电层中开设的各个过孔是用于后续形成的膜层与该层间介电层靠近衬底基板的一侧的膜层连接。也即是，该各个过孔是用于供膜层连接的过孔。
图24是本申请实施例提供的显示面板中的第一源漏极层的局部示意图，图25是本申请实施例提供的显示面板中的半导体层，第一栅极层，第二栅极层，层间介电层以及第一源漏极层的局部叠加示意图。如图24和图25所示，第一源漏极层包括第一连接结构h1，第二连接结构h2，第三连接结构h3，第四连接结构h4，第五连接结构h5以及第六连接结构h6。第一连接结构h1被配置为连接阈值补偿晶体管T2的源极(或漏极)和驱动晶体管T3的栅极。第二连接结构h2被配置为连接第二发光控制晶体管T6。第三连接结构h3被配置为连接第三复位控制晶体管T7的源极(或漏极)和复位电源信号线g4。第四连接结构h4被配置为连接VDD信号线和第一发光控制晶体管T5的源极(或漏极)。第五连接结构h5被配置为连接数据写入晶体管T4的源极(或漏极)和数据线g6。第六连接结构h6被配置为连接第二复位电源信号线g5。
另外，上述的第一源漏极层上可以形成有钝化层，用于将上述的第一源漏极层与后续形成的中间源漏极层绝缘。参考图26和图27，为了便于示出钝化层(PVX)中的各个过孔，图26至图27中采用填充图案表示过孔。其他未绘制填充图案的区域用于表示钝化层具有实材的区域。需要说明的是，该钝化层中开设的各个过孔是用于后续形成的膜层与该钝化层靠近衬底基板的一侧的膜层连接。也即是，该各个过孔是用于供膜层连接的过孔。
图28是本申请实施例提供的显示面板中的中间源漏极层的局部示意图，图29是本申请实施例提供的显示面板中的半导体层，第一栅极层，第二栅极层，层间介电层，第一源漏极层，钝化层以及中间源漏极层的局部叠加示意图。如图28和图29所示，中间源漏极层包括第一信号线VDD1，第七连接结构h7和第八连接结构h8。该第一信号线VDD1被配置为与第四连接结构h4连接，第七连接结构h7被配置为与第二连接结构h2连接，第八连接结构h8被配置为与第五连接结构h5连接。
另外，上述的中间源漏极层上可以形成有第一平坦层(PLN1)，用于将上述的中间源漏极层与后续形成的第二源漏极层绝缘。参考图30和图31，为了便于示出第一平坦层中的各个过孔，图30至图31中采用填充图案表示过孔。其他未绘制填充图案的区域用于表示第一平坦层具有实材的区域。需要说明的是，该第一平坦层中开设的各个过孔是用于后续形成的膜层与该第一平坦层靠近衬底基板的一侧的膜层连接。也即是，该各个过孔是用于供膜层连接的过孔。
图32是本申请实施例提供的显示面板中第二源漏极层的局部示意图，图33是本申请实施例提供的显示面板中的半导体层，第一栅极层，第二栅极层，层间介电层，第一源漏极层，钝化层，中间源漏极层以及第二源漏极层的层叠示意图。如图32和图33所示，第二源漏极层包括第二信号线VDD2，数据线g6以及第九连接结构h9。该第二信号线VDD2被配置为与第一信号线VDD1连接，数据线g6被配置为与第八连接结构h8连接，第九连接结构h9被配置为与第七连接结构h7连接。用于传输VDD信号的走线包括第一信号线VDD1和第二信号线VDD2。
另外，上述的第二源漏极层上可以形成有第二平坦层(PLN2)，用于将上述的中间源漏极层与后续形成的连接层中的第一导电层绝缘。参考图34和图35，为了便于示出第二平坦层中的各个过孔，图34至图35中采用填充图案表示过孔。其他未绘制填充图案的区域用于表示第二平坦层具有实材的区域。需要说明的是，该第二平坦层中开设的各个过孔是用于后续形成的膜层与该第二平坦层靠近衬底基板的一侧的膜层连接。也即是，该各个过孔是用于供膜层连接的过孔。
综上所述，本申请实施例提供了一种显示面板，由于显示面板中至少两个第一电极图案连接，且连接的至少两个第一电极图案中的一个第一电极图案与一个第一像素电路连接，因此可以使得一个第一像素电路驱动两个第一电极图案。同时，由于至少两个第二电极图案连接，且连接的至少两个第二电极图案中的一个第二电极图案与一个第二像素电路连接，因此可以使得一个第二像素电路驱动两个第二电极图案。由此，在电极图案的数量相同的情况下，采用一个像素电路驱动两个电极图案的方案，能够减少第二显示区中所需设计的像素电路的数量，进而能够增大每个像素电路所能够占用的空间，工艺制备难度较低。
图36是本申请实施例提供的一种显示面板的制备方法的流程图。该方法可以用于制备上述实施例所提供的显示面板。参考图36，该方法可以包括：
步骤S101、在衬底基板的一侧依次形成缓冲层，半导体层，第一栅极绝缘层，第一栅极层，第二栅极绝缘层，第二栅极层，层间介电层，第一源漏极层，钝化层，中间源漏极层，第一平坦层，第二源漏极层，第二平坦层。
在本申请实施例中，在制备显示面板时，可以先获取一衬底基板。其中，该衬底基板可以为透明玻璃基板或柔性基板。相应的，制备得到的显示面板可以为柔性显示面板。之后，可以在该衬底基板的一侧形成缓冲层以及驱动电路层中的各个膜层。其中，驱动电路层中的各个膜层可以参考图17至图35。本申请实施例在此不再赘述。
步骤S102、在第二平坦层远离衬底基板的一侧依次形成第一导电层，第一绝缘层，第二导电层，第二绝缘层，第三导电层以及第三绝缘层。
参考图37和图38，在第二平坦层远离衬底基板的一侧形成第一导电层，且该第一导电层可以包括多个第一连接部。参考图39和图40，在第一导电层远离衬底基板的一侧形成第一绝缘层(第三平坦层PLN3)。为了便于示出第一绝缘层中的各个第一过孔，图39和图40中采用填充图案表示第一过孔。其他未绘制填充图案的区域用于表示第一绝缘层具有实材的区域。需要说明的是，该第一绝缘层中开设的各个第一过孔是用于后续形成的膜层与该第一绝缘层靠近衬底基板的一侧的膜层连接。也即是，该各个第一过孔是用于供膜层连接的过孔。
参考图41和图42，在第一绝缘层远离衬底基板的一侧形成第二导电层，且该第二导电层可以包括多个第二连接部。参考图43和图44，在第二导电层远离衬底基板的一侧形成第二绝缘层(第四平坦层PLN4)。为了便于示出第二绝缘层中的各个第二过孔，图43和图44中采用填充图案表示第二过孔。其他未绘制填充图案的区域用于表示第二绝缘层具有实材的区域。需要说明的是，该第二绝缘层中开设的各个第二过孔是用于后续形成的膜层与该第二绝缘层靠近衬底基板的一侧的膜层连接。也即是，该各个第二过孔是用于供膜层连接的过孔。
参考图45和图46，在第二绝缘层远离衬底基板的一侧形成第三导电层，且该第三导电层可以多个第三连接部。参考图47和图48，在第三导电层远离衬底基板的一侧形成第三绝缘层(第五平坦层PLN5)。为了便于示出第三绝缘层中的各个第二过孔，图47和图48中采用填充图案表示第三过孔。其他未绘制填充图案的区域用于表示第三绝缘层具有实材的区域。需要说明的是，该第三绝缘层中开设的各个第三过孔是用于后续形成的膜层与该第三绝缘层靠近衬底基 板101的一侧的膜层连接。也即是，该各个第三过孔是用于供膜层连接的过孔。
步骤S103、在第三绝缘层远离衬底基板的一侧形成第一电极层，像素界定层，发光膜层，第二电极层以及封装层。
参考图49和图50，在第三绝缘层远离衬底基板的一侧形成第一电极层。该第一电极层可以包括多个电极图案，每个电极图案可以作为一个像素器件的阳极。图49和图50中示出了第二电极图案，第四电极图案以及第六电极图案。
参考图51和图52，在第一电极层远离衬底基板的一侧形成像素界定层。该像素界定层可以具有多个开口，每个开口暴露一个第一电极层中的一个电极图案。为了便于示出像素界定层中的各个开口，图51和图52中采用填充图案表示开口，其他未绘制填充图案的区域用于表示像素界定层具有实材的区域。需要说明的是，该像素界定层中开设的各个开口是用于后续形成的膜层与该像素界定层靠近衬底基板的一侧的膜层连接。也即是，该各个开口是用于供发光膜层中的发光层与第一电极层中的电极图案接触的开口。
在形成像素界定层之后，可以继续在像素界定层远离衬底基板的一侧形成发光膜层，第二电极层和封装层，本申请实施例在此不再详述。
需要说明的是，本申请实施例提供的显示面板的制备方法主要以第二显示区中非第二子显示区的其他区域(如第一子显示区，第三子显示区，第四子显示区，第五子显示区以及第六子显示区)为例进行说明。图17至图51均以沿像素行方向包括一个电路组A，沿像素列方向包括两个电路组A为例。
对于第二显示区中的第二子显示区(过渡显示区)，其和第二显示区中的其他区域中膜层的区别主要是各个导电层。参考图53，导电层位于第二子显示区的部分除了包括连接部之外，还包括第二连接走线，第四连接走线或第五连接走线。也即是，导电层位于第二子显示区的部分可以包括用于连接位于第二子显示区的像素电路和位于第一显示区的电极图案的连接走线。图53中的导电层可以为第一导电层，第二导电层或第三导电层。相应的，图53中的连接部可以为第一连接部，第二连接部或第三连接部。
综上所述，本申请实施例提供了一种显示面板的制备方法，由于制备得到的显示面板中至少两个第一电极图案连接，且连接的至少两个第一电极图案中的一个第一电极图案与一个第一像素电路连接，因此可以使得一个第一像素电路驱动两个第一电极图案。同时，由于至少两个第二电极图案连接，且连接的至少两个第二电极图案中的一个第二电极图案与一个第二像素电路连接，因此 可以使得一个第二像素电路驱动两个第二电极图案。由此，在电极图案的数量相同的情况下，采用一个像素电路驱动两个电极图案的方案，能够减少第二显示区中所需设计的像素电路的数量，进而能够增大每个像素电路所能够占用的空间，工艺制备难度较低。
图54是本申请实施例提供的一种显示模组的结构示意图。如图54，显示装置可以包括数据驱动电路20以及上述实施例所提供的显示面板10。其中，该数据驱动电路20可以与显示面板10中的第一数据线S1，第三数据线S3，第四数据线S4和第七数据线S7连接，为第一数据线S1，第三数据线S3，第四数据线S4以及第七数据线S7直接提供数据驱动信号。其中，图54均示意性的示出了一条第一数据线S1，一条第三数据线S3，一条第四数据线S4和一条第七数据线S7。
并且，第二数据线S2通过第一转接线Z1与第一数据线S1连接，第五数据线S5通过第二转接线Z2与第二数据线S2连接，因此数据驱动电路20通过第一数据线S1为第二数据线S2和第五数据线S5提供数据驱动信号。第六数据线S6通过第三转接线Z3与第四数据线S4连接，因此数据驱动电路20通过第四数据线S4为第六数据线S6提供数据驱动信号。
由于显示模组可以与前面实施例描述的显示面板具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述显示装置的技术效果。
参考图55，本申请实施例提供了一种显示装置，该显示装置可以包括上述实施例所提供的显示模组01以及传感器02之类的电气元件，例如：光学传感器。以显示装置为手机为例，显示装置包括诸如前置摄像头、接近光传感器、3D感测模块等光学传感器，这些光学部件需要接收来自显示装置的显示面侧的光线，以实现相应的功能。在显示装置中，光学传感器通常安装在显示模组01的非显示面侧，光学传感器的感光面一侧朝向显示模组01。其中，该光学传感器02在显示面板10上的正投影与显示面板10中的第一显示区101a至少部分交叠。
在本申请实施例中，该显示装置可以为有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED)显示装置、无源矩阵有机发光二极管(passive-matrix organic light-emitting diode，PMOLED)显示装置、 量子点发光二极管(quantum dot light emitting diodes，QLED)显示装置、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
由于显示装置可以与前面实施例描述的显示面板具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述显示装置的技术效果。
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。除非另作定义，本申请的实施方式使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (18)

  1. 一种显示面板，其特征在于，所述显示面板(10)包括：
    衬底基板(101)，所述衬底基板(101)具有第一显示区(101a)，以及至少部分围绕所述第一显示区(101a)的第二显示区(101b)；
    位于所述衬底基板(101)的一侧的驱动电路层(102)，所述驱动电路层(102)包括位于所述第二显示区(101b)的多个第一像素电路(A1)和多个第二像素电路(A2)；
    以及第一电极层(103)，所述第一电极层(103)至少包括多个第一类电极图案(1031)，所述多个第一类电极图案(1031)包括位于所述第一显示区(101a)的多个第一电极图案(1031a)，以及位于所述第二显示区(101b)的多个第二电极图案(1031b)；
    其中，至少两个所述第一电极图案(1031a)与所述多个第一像素电路(A1)中的一个第一像素电路(A1)连接，至少两个所述第二电极图案(1031b)与所述多个第二像素电路(A2)中的一个所述第二像素电路(A2)连接。
  2. 根据权利要求1所述的显示面板，其特征在于，所述显示面板(10)还包括：
    多条第一连接走线(L1)，所述多条第一连接走线(L1)位于所述第一显示区(101a)；
    多条第二连接走线(L2)，所述多条第二连接走线(L2)沿像素行方向(X)从所述第二显示区(101b)延伸至所述第一显示区(101a)；
    多条第三连接走线(L3)，所述多条第三连接走线(L3)位于所述第二显示区(101b)；
    其中，至少两个所述第一电极图案(1031a)通过一条所述第一连接走线(L1)连接，且至少两个所述第一电极图案(1031a)中的一个所述第一电极图案(1031a)通过一条所述第二连接走线(L2)与一个所述第一像素电路(A1)连接，至少两个所述第二电极图案(1031b)通过一条所述第三连接走线(L3)连接，且至少两个所述第二电极图案(1031b)中的一个所述第二电极图案(1031b)与一个所述第二像素电路(A2)连接。
  3. 根据权利要求2所述的显示面板，其特征在于，所述显示面板(10)还包括多条第四连接走线(L4)和多条第五连接走线(L5)，所述多条第四连接走线(L4)和所述多条第五连接走线(L5)均沿所述像素行方向(X)从所述第二显示区(101b)延伸至所述第一显示区(101a)；所述第一电极层(103)还包括多个第二类电极图案(1032)和多个第三类电极图案(1033)；
    所述多个第二类电极图案(1032)包括位于所述第一显示区(101a)的多个第三电极图案(1032a)，以及位于所述第二显示区(101b)的多个第四电极图案(1032b)，所述第三电极图案(1032a)通过一条所述第四连接走线(L4)与一个所述第一像素电路(A1)连接；
    所述多个第三类电极图案(1033)包括位于所述第一显示区(101a)的多个第五电极图案(1033a)，以及位于所述第二显示区(101b)的多个第六电极图案(1033b)，所述第五电极图案(1033a)通过所述第五连接走线(L5)与一个所述第一像素电路(A1)连接。
  4. 根据权利要求3所述的显示面板，其特征在于，相邻的两个所述第一像素电路(A1)和三个所述第二像素电路(A2)构成一个电路组(A)；至少两个所述第二电极图案(1031b)构成一个电极图案组，相邻的一个电极图案组，一个所述第四电极图案(1032b)以及一个所述第六电极图案(1033b)构成一个图案组(B)；
    其中，每个所述图案组(B)与一个所述电路组(A)对应，且对于相对应的所述图案组(B)和所述电路组(A)，所述图案组(B)在所述衬底基板(101)上的正投影的所处区域，与所述电路组(A)在所述衬底基板(101)上的正投影的所处区域存在交叠。
  5. 根据权利要求4所述的显示面板，其特征在于，对于每个所述电路组(A)以及与所述电路组(A)对应的一个图案组(B)，所述电路组(A)包括的三个所述第二像素电路(A2)中，第一个第二像素电路(A2)与所述图案组(B)中的电极图案组的一个第二电极图案(1031b)连接，第二个第二像素电路(A2)与所述图案组(B)中的第四电极图案(1032b)连接，第三个第二像素电路(A2) 与所述图案组(B)中的第六电极图案(1033b)连接。
  6. 根据权利要求4或5所述的显示面板，其特征在于，所述显示面板(10)中的一部分电路组(A)包括的两个所述第一像素电路(A1)与位于所述第一显示区(101a)的电极图案连接，所述显示面板中的另一部分电路组(A)包括的两个所述第一像素电路(A1)与固定电压端连接。
  7. 根据权利要求6所述的显示面板，其特征在于，与所述第一显示区(101a)的电极图案连接的第一像素电路(A1)所属的电路组(A)，相对于与所述固定电压端连接的第一像素电路(A1)所属的电路组(A)更靠近所述第一显示区(101a)。
  8. 根据权利要求3至7任一所述的显示面板，其特征在于，所述显示面板包括红色子像素，绿色子像素以及蓝色子像素，所述第一类电极图案所属的子像素为绿色子像素，所述第二类电极图案所属的子像素为红色子像素，所述第三类电极图案所属的子像素为蓝色子像素。
  9. 根据权利要求3至8任一所述的显示面板，其特征在于，任一所述第二连接走线(L2)沿所述像素行方向(X)的长度，小于所述第四连接走线(L4)沿所述像素行方向(X)的长度，且小于所述第五连接走线(L5)沿所述像素行方向(X)的长度。
  10. 根据权利要求3至8任一所述的显示面板，其特征在于，对于所述多条第二连接走线(L2)，所述多条第四连接走线(L4)以及所述多条第五连接走线(L5)中的每个所述连接走线，所述连接走线沿所述像素行方向(X)的长度，与所述连接走线所连接的位于所述第一显示区(101a)的电极图案沿所述像素行方向(X)和所述第二显示区(101b)之间的距离正相关。
  11. 根据权利要求1至10任一所述的显示面板，其特征在于，所述第二显示区(101b)包括第一子显示区(101b1)，第二子显示区(101b2)和第三子显 示区(101b3)，所述第一子显示区(101b1)和所述第一显示区(101a)沿像素列方向(Y)排布，所述第二子显示区(101b2)和所述第一显示区(101a)沿所述像素行方向(X)排布，所述第三子显示区(101b3)和所述第一子显示区(101b1)沿所述像素行方向(X)排布，且和所述第二子显示区(101b2)沿所述像素列方向(Y)排布；
    所述显示面板还包括：位于所述第一子显示区(101b1)的多条第一数据线(S1)，位于所述第二子显示区(101b2)和所述第三子显示区(101b3)的多条第二数据线(S2)，以及位于所述第一子显示区(101b1)和所述第三子显示区(101b3)的多条第一转接线(Z1)；所述多条第一数据线(S1)沿所述像素行方向(X)排布且沿所述像素列方向(Y)延伸，所述多条第二数据线(S2)沿所述像素行方向(X)排布且沿所述像素列方向(Y)延伸，所述多条第一转接线(Z1)沿所述像素列方向(Y)排布且沿所述像素行方向(X)延伸；
    每条所述第一数据线(S1)的第一端用于与数据驱动电路连接，每条所述第一数据线(S1)的第二端与一条所述第一转接线(Z1)的第一端连接，每条所述第一转接线(Z1)的第二端与一条所述第二数据线(S2)的第一端连接；其中，每条所述第一数据线(S1)还与位于所述第一子显示区(101b1)中用于连接第一目标电极图案的一列第二像素电路(A2)连接，每条所述第二数据线(S2)还与位于所述第二子显示区(101b2)中用于连接第二目标电极图案的一列第一像素电路(A1)连接；所述第一目标电极图案至少为第四电极图案(1032b)和第六电极图案(1033b)中的一种，所述第二目标电极图案至少为第三电极图案(1032a)和第五电极图案(1033a)中的一种。
  12. 根据权利要求11所述的显示面板，其特征在于，所述第一目标电极图案为第四电极图案(1032b)或第六电极图案(1033b)，所述第二目标电极图案为第三电极图案(1032a)或第五电极图案(1033a)；所述显示面板还包括：位于所述第一子显示区(101b1)的多条第三数据线(S3)，以及位于所述第二子显示区(101b2)和所述第三子显示区(101b3)的多条第四数据线(S4)；
    所述多条第三数据线(S3)沿所述像素行方向(X)排布且沿所述像素列方向(Y)延伸，每条所述第三数据线(S3)的第一端用于与数据驱动电路连接，且每条所述第三数据线(S3)还与位于所述第一子显示区(101b1)中用于连接 第二电极图案(1031b)的一列第二像素电路(A2)连接；
    所述多条第四数据线(S4)沿所述像素行方向(X)排布且沿所述像素列方向(Y)延伸，每条所述第四数据线(S4)的第一端用于与数据驱动电路连接，且每条所述第四数据线(S4)还与位于所述第二子显示区(101b2)中用于连接第一电极图案(1031a)的一列第一像素电路(A1)连接。
  13. 根据权利要求11或12所述的显示面板，其特征在于，所述第二显示区(101b)还包括：第四子显示区(101b4)和第五子显示区(101b5)，所述第四子显示区(101b4)位于所述第一显示区(101a)远离所述第一子显示区(101b1)的一侧，所述第五子显示区(101b5)和所述第四子显示区(101b4)沿所述像素行方向(X)排布；所述多条第二数据线(S2)还位于所述第五子显示区(101b5)；所述显示面板还包括：多条第二转接线(Z2)，以及位于所述第四子显示区(101b4)的多条第五数据线(S5)；
    所述多条第五数据线(S5)沿所述像素行方向(X)排布且沿所述像素列方向(Y)延伸，所述多条第二转接线(Z2)沿所述像素列方向(Y)排布且沿所述像素行方向(X)延伸；每条所述第二数据线(S2)的第二端与一条所述第二转接线(Z2)的第一端连接，每条所述第二转接线(Z2)的第二端与所述第五数据线(S5)的第一端连接；所述第五数据线(S5)还与位于所述第四子显示区(101b4)中用于连接所述第一目标电极图案的一列第二像素电路(A2)连接。
  14. 根据权利要求11至13任一所述的显示面板，其特征在于，所述显示面板(10)还包括：位于所述第三子显示区(101b3)的多条第一虚设数据线(D1)；
    所述多条第一虚设数据线(D1)沿所述像素行方向(X)排布且沿所述像素列方向(Y)延伸，所述第一虚设数据线(D1)用于与固定电压端连接，且所述第一虚设数据线(D1)还与位于所述第三子显示区(101b3)的一列第一像素电路(A1)连接。
  15. 根据权利要求1至14任一所述的显示面板，其特征在于，所述第二显示区(101b)还包括：第六子显示区(101b6)，所述第六子显示区(101b6)位于所述第三子显示区(101b3)远离所述第一子显示区(101b1)的一侧；所述 显示面板还包括：位于所述第六子显示区(101b6)的多条第七数据线(S7)，以及位于所述第六子显示区(101b6)的多条第二虚设数据线(D2)；
    所述多条第七数据线(S7)沿所述像素行方向(X)排布且沿所述像素列方向(Y)延伸，每条所述第七数据线(S7)用于与数据驱动电路连接，每条所述第七数据线(S7)还与位于所述第六子显示区(101b6)中的一列第二像素电路(A2)连接；
    所述多条第二虚设数据线(D2)沿所述像素行方向(X)排布且沿所述像素列方向(Y)延伸，每条所述第二虚设数据线(D2)用于与固定电压端连接，且所述第二虚设数据线(D2)还与位于所述第六显示区的一列第一像素电路(A1)连接。
  16. 根据权利要求1至15任一所述的显示面板，其特征在于，所述第三连接走线(L3)与所述第一电极层(103)位于同层，所述第一连接走线(L1)和所述第二连接走线(L2)均位于所述驱动电路层(102)和所述第一电极层(103)之间。
  17. 一种显示模组，其特征在于，所述显示模组包括数据驱动电路(20)以及如权利要求1至16任一所述的显示面板(10)；
    其中，所述数据驱动电路(20)与所述显示面板(10)中的第一数据线(S1)，第三数据线(S3)，第四数据线(S4)和第七数据线(S7)连接。
  18. 一种显示装置，其特征在于，所述显示装置包括权利要求15所述的显示模组(01)及光学传感器(02)，所述光学传感器(02)在所述显示面板(10)上的正投影与所述显示面板(10)中的第一显示区(101a)至少部分交叠。
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