WO2021243875A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2021243875A1
WO2021243875A1 PCT/CN2020/114624 CN2020114624W WO2021243875A1 WO 2021243875 A1 WO2021243875 A1 WO 2021243875A1 CN 2020114624 W CN2020114624 W CN 2020114624W WO 2021243875 A1 WO2021243875 A1 WO 2021243875A1
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WIPO (PCT)
Prior art keywords
opening
area
signal line
compensation capacitor
sub
Prior art date
Application number
PCT/CN2020/114624
Other languages
English (en)
French (fr)
Inventor
张鑫
周洋
代俊秀
廖茂颖
张毅
舒晓青
马宏伟
都蒙蒙
王蓉
董向丹
张振华
杨双宾
程博
李宇婧
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/419,749 priority Critical patent/US20220320231A1/en
Priority to CN202080002551.5A priority patent/CN114730798A/zh
Publication of WO2021243875A1 publication Critical patent/WO2021243875A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • the display screen of the display device is developing in the direction of large-screen and full-screen.
  • a display device such as a mobile phone, a tablet computer, etc.
  • the camera device is usually arranged on a side outside the display area of the display screen.
  • the camera device can be combined and overlapped with the display area of the display screen to reserve a place for the camera device in the display area to maximize the display area of the display screen.
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a first opening area, a second opening area, an area between openings, a display area, and a first signal line.
  • the first opening area includes a first opening and a first opening peripheral area surrounding the first opening;
  • a second opening area is arranged adjacent to the first opening area along the first direction, and includes a second opening and a surrounding area.
  • the second opening peripheral area of the second opening; the inter-opening area is located between the first opening area and the second opening area, the inter-opening area, the first opening peripheral area and the second opening area
  • At least one of the three opening peripheral regions includes a first dummy sub-pixel; a display region at least partially surrounds the first opening region, the second opening region, and the inter-opening region, and includes a plurality of pixels, each The pixel includes a plurality of sub-pixels, each of the sub-pixels includes a pixel circuit, the pixel circuit includes: a transistor, a light-emitting element, and a storage capacitor, including an active layer, a gate, and a source and drain; a light-emitting element and the transistor One of the source and drain of the storage capacitor is connected; the storage capacitor includes a first plate and a second plate, the gate and the first plate of the storage capacitor are arranged in the same layer; the first signal line extends along the first direction, including A first portion passing through the peripheral area of the first opening
  • the first electrode plate is provided on the same layer as the first part of the first signal line and is electrically connected to the first signal line, and is provided on the same layer as the second electrode plate of the storage capacitor; the second electrode plate is the same layer as the first part of the first signal line.
  • the first plate of the compensation capacitor is arranged in different layers and insulated, wherein the orthographic projection of the second plate of the first compensation capacitor on the base substrate and the first plate of the first compensation capacitor are in place. The orthographic projections on the base substrate at least partially overlap.
  • At least one embodiment of the present disclosure further provides a display substrate.
  • the display substrate includes a base substrate.
  • the base substrate includes a first opening area, a display area, a plurality of first signal lines, a plurality of second signal lines, and a first opening area.
  • Floating electrode is a first electrode.
  • the first opening area includes a first opening and a first opening peripheral area surrounding the first opening; a display area at least partially surrounds the first opening area, and includes: a first display area located at the second opening area of the first opening area And a second display area located on the second side of the first opening area, wherein the first side and the second side are opposite to each other in the first direction, and the first display area and the
  • the second display area includes a plurality of pixels; a plurality of first signal lines are configured to provide first display signals to the plurality of pixels, extend along the first direction and pass through the first display area and the first display area.
  • the plurality of second signal lines are configured to provide second display signals to the plurality of pixels, extend in a second direction intersecting the first direction, and a portion of the plurality of second signal lines extends along the The second direction passes through the peripheral area of the first opening, and each second signal line of the portions of the plurality of second signal lines includes a longitudinal winding portion located in the peripheral area of the first opening, wherein The longitudinal winding portion is partially arranged around the first opening; the longitudinal winding portion closest to the first opening among the longitudinal winding portions of the plurality of second signal lines is an edge longitudinal winding portion, The first floating electrode and the edge longitudinal winding portion are arranged in the same layer and located on a side of the edge longitudinal winding portion close to the first opening.
  • At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
  • Figure 1 is a schematic plan view of a display substrate
  • FIG. 2A is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 2B is a partial enlarged schematic diagram of FIG. 2A including a first opening area and a second opening area;
  • FIG. 2C is a partial enlarged schematic diagram of FIG. 2A including the first opening area and the area between the openings;
  • 3A is a schematic cross-sectional view of sub-pixels in the display area of the display substrate
  • 3B is another schematic cross-sectional view of sub-pixels in the display area of the display substrate
  • FIG. 4A is a schematic diagram of a planar layout of a first dummy pixel circuit in a display substrate according to an embodiment of the present disclosure
  • Fig. 4B is a schematic cross-sectional view taken along line A2-B2 in Fig. 4A;
  • 4C-4G are schematic diagrams of various layers of a first dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure
  • 4H is a schematic diagram of another first electrode plate of a first compensation capacitor of a display substrate provided by an embodiment of the present disclosure
  • Fig. 4I is a schematic cross-sectional view taken along line A3-B3 in Fig. 4A;
  • Figure 4J is a partial view showing the substrate
  • FIG. 5A is an enlarged schematic diagram of part C in FIG. 2C;
  • FIG. 5B is an enlarged schematic diagram of part D in FIG. 2C;
  • FIG. 5C is an enlarged schematic diagram of part E in FIG. 2C;
  • FIG. 5D is an enlarged schematic diagram of part F in FIG. 2C;
  • FIG. 5E is an enlarged schematic diagram of the area where the first signal line and the second signal line are changed layers
  • Figures 5F-5H are schematic cross-sectional views taken along lines A4-B4, A5-B5, and A6-B6 in Figure 5E, respectively;
  • FIG. 6 is an equivalent circuit diagram of a pixel circuit in an array substrate provided by an embodiment of the disclosure.
  • FIG. 7A is a schematic diagram of a planar layout of a pixel circuit in an array substrate provided by an embodiment of the present disclosure
  • 7B-7K are schematic diagrams of various layers of a pixel circuit of an array substrate provided by an embodiment of the present disclosure.
  • Fig. 8A is a schematic cross-sectional view taken along the line A-A' in Fig. 7A;
  • Fig. 8B is a schematic cross-sectional view taken along the line B-B' in Fig. 7A;
  • FIG. 9 is a signal timing diagram of the working process of the pixel circuit shown in FIG. 6;
  • FIG. 10A is an enlarged schematic diagram of a first opening area of a display substrate provided by an embodiment of the present disclosure
  • 10B is an enlarged schematic diagram of a first opening area of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 10C is an enlarged schematic diagram of a first opening area of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is an enlarged schematic diagram of part H in FIG. 10A;
  • FIG. 12 is an enlarged schematic diagram of part G in FIG. 11;
  • FIG. 13 is an enlarged schematic diagram of part I in FIG. 16;
  • FIG. 14 is an enlarged schematic diagram of part J in FIG. 13;
  • FIG. 15 is a schematic plan view of yet another display substrate according to an embodiment of the disclosure.
  • 16A is a schematic plan view of a second virtual pixel circuit in a second virtual sub-pixel in a display substrate according to an embodiment of the present disclosure
  • Fig. 16B is a schematic cross-sectional view taken along line A3-B3 in Fig. 16A;
  • 16C-16F are schematic diagrams of various layers of a second dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 17 is a schematic plan view of a second virtual pixel circuit in a second virtual sub-pixel in a display substrate according to an embodiment of the present disclosure.
  • Fig. 1 is a schematic plan view of a display substrate.
  • the display substrate 10 includes a display area 101 and a peripheral area 102 surrounding the display area 101.
  • the display area 101 is designed, for example, in an irregular shape with a notch 103 on at least one side.
  • Devices such as cameras, distance sensors, etc. are arranged in the area of the notch 103, thereby contributing to the realization of the narrow frame design of the display substrate 10.
  • the display area 101 includes a first display area 1011 and a second display area 1012 located on the left and right sides of the notch 103.
  • the first display area 1011 and the second display area 1012 are opposite to the bottom of the display area 101.
  • the sides are at the same horizontal position, and are driven by one or more scanning signal lines (gate lines) that extend horizontally from the left and right in the figure, for example.
  • the first display area and the second display area may also be in different horizontal positions.
  • the first display area and the second display area are arranged along the curved edge of the display screen, and the first display area and the second display area may not be in the same horizontal position.
  • the number of pixels in the same row of pixels in the first display area 1011 and the second display area 1012 is greater than that in the display area 101 except for the first display area 1011 and the second display area 1012.
  • the number of pixels in a row of pixels in a part is small.
  • the number of pixels connected to the horizontally extending signal lines used to provide display signals (such as scanning signals) for pixels in the same row of the first display area 1011 and the second display area 1012 It is different from the number of pixels connected to the signal lines used to provide electrical signals (such as scanning signals) for a row of pixels in other parts of the display area 101 except for the first display area 1011 and the second display area 1012, and the number of pixels connected in the notch
  • the number of pixels in different rows of pixels in the first display area 1011 and the second display area 1012 may also be different.
  • the display substrate 10 because the number of pixels in different rows of pixels is different, the load of the signal lines connecting the pixels of different rows is different, and the signal transmission speeds of these signal lines are different. The difference between the actual display signal and the design value is The deviation is different, which will affect the display effect of the display substrate.
  • load compensation can be performed on these signal lines with different loads, so that the loads of these signal lines are basically the same, thereby reducing the adverse effect of the notch 103 on the display quality.
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a first opening area, a second opening area, an area between openings, a display area, and a first signal line.
  • the first opening area includes a first opening and a first opening peripheral area surrounding the first opening;
  • a second opening area is arranged adjacent to the first opening area along the first direction, and includes a second opening and a surrounding area.
  • the second opening peripheral area of the second opening; the inter-opening area is located between the first opening area and the second opening area, the inter-opening area, the first opening peripheral area and the second opening area
  • At least one of the three opening peripheral regions includes a first dummy sub-pixel; a display region at least partially surrounds the first opening region, the second opening region, and the inter-opening region, and includes a plurality of pixels, each The pixel includes a plurality of sub-pixels, each of the sub-pixels includes a pixel circuit, and the pixel circuit includes: a transistor, a light-emitting element, and a storage capacitor, including an active layer, a gate, and a source and drain; a light-emitting element and the transistor One of the source and drain of the storage capacitor is connected; the storage capacitor includes a first plate and a second plate, the gate and the first plate of the storage capacitor are arranged in the same layer; the first signal line extends along the first direction, including A first portion passing through the peripheral area of the first
  • the first electrode plate is provided on the same layer as the first part of the first signal line and is electrically connected to the first signal line, and is provided on the same layer as the second electrode plate of the storage capacitor; the second electrode plate is the same layer as the first part of the first signal line.
  • the first plate of the compensation capacitor is arranged in different layers and insulated, wherein the orthographic projection of the second plate of the first compensation capacitor on the base substrate and the first plate of the first compensation capacitor are in place. The orthographic projections on the base substrate at least partially overlap.
  • At least one embodiment of the present disclosure further provides a display substrate.
  • the display substrate includes a base substrate.
  • the base substrate includes a first opening area, a display area, a plurality of first signal lines, a plurality of second signal lines, and a first opening area.
  • Floating electrode is a first electrode.
  • the first opening area includes a first opening and a first opening peripheral area surrounding the first opening; a display area at least partially surrounds the first opening area, and includes: a first display area located at the second opening area of the first opening area And a second display area located on the second side of the first opening area, wherein the first side and the second side are opposite to each other in the first direction, and the first display area and the
  • the second display area includes a plurality of pixels; a plurality of first signal lines are configured to provide first display signals to the plurality of pixels, extend along the first direction and pass through the first display area and the first display area.
  • the plurality of second signal lines are configured to provide second display signals to the plurality of pixels, extend in a second direction intersecting the first direction, and a portion of the plurality of second signal lines extends along the The second direction passes through the peripheral area of the first opening, and each second signal line of the portions of the plurality of second signal lines includes a longitudinal winding portion located in the peripheral area of the first opening, wherein The longitudinal winding portion is partially arranged around the first opening; the longitudinal winding portion closest to the first opening among the longitudinal winding portions of the plurality of second signal lines is an edge longitudinal winding portion, The first floating electrode and the edge longitudinal winding portion are arranged in the same layer and located on a side of the edge longitudinal winding portion close to the first opening.
  • FIG. 2A is a schematic plan view of a display substrate according to an embodiment of the disclosure
  • FIG. 2B is a partial enlarged schematic view of FIG. 2A including a first opening area and a second opening area.
  • the display substrate 20 includes a base substrate, and the base substrate includes a first opening area 202A, a second opening area 202B, an inter-opening area 2014, a display area 201, and a first signal line 23.
  • the first opening area 202A includes a first opening 201A and a first opening peripheral area 203A surrounding the first opening 201A; the second opening area 202B and the first opening area 202A are adjacently arranged along the first direction R1 and include a second opening 201B And the second opening peripheral area 203B surrounding the second opening 201B.
  • the inter-opening area 2014 is located between the first opening area 202A and the second opening area 202B.
  • the display area 201 at least partially surrounds the first opening area 202A, the second opening area 202B, and the inter-opening area 2014, and includes a plurality of pixels, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit.
  • the first signal line 23 extends along the first direction R1, and includes a first portion passing through the first opening peripheral region 202A, the inter-opening region 2014, and the second opening peripheral region 203B, and is configured to provide the pixel circuit with a first portion.
  • One display signal is configured to provide the pixel circuit with a first portion.
  • the second opening region 202B and the first opening region 202A are arranged along the first direction R1, and thus, the inter-opening region 2014 is located in the first opening in the first direction R1.
  • the second opening area 202B can also be arranged along the second direction R2 with the first opening area 202A.
  • the inter-opening area 2014 is located between the first opening area 202A and the second opening area 202A in the second direction R2. Between the opening areas 202B.
  • the embodiment of the present disclosure does not limit the arrangement direction of the second opening area 202B and the first opening area 202A.
  • the display area 201 includes pixels arranged in an array, and each pixel includes one or more sub-pixels, and also includes various signal lines for transmitting various electrical signals to the sub-pixels to realize the display function; the frame area 204 includes various sub-pixels.
  • a driving circuit, signal lines that electrically connect the sub-pixels, contact pads, etc., and the signal lines of the frame area 204 are electrically connected (or integrally formed) with the signal lines (such as gate lines, data lines, etc.) in the display area 201 to provide the sub-pixels. Electrical signals (such as scan signals, data signals, etc.).
  • the first opening 201A is set to allow light from the display side of the display substrate to pass through to reach the camera and the distance sensor to realize light sensing, thereby realizing functions such as image shooting and distance sensing; for example, in the area corresponding to the first opening 201A
  • a camera, a distance sensor, and other devices can be arranged on the back side of the display substrate (that is, the side opposite to the display side), and the camera, the distance sensor, etc. are at least partially exposed through the first opening 201A.
  • various signal lines from the frame area 204 extend through the display area 201.
  • these signal lines pass through the first opening peripheral area 203A and bypass the first opening 201A, and then enter the display area.
  • electrical signals such as scanning signals, data signals, etc.
  • these signal lines may not be provided in the first opening 201A to increase the light transmittance of the first opening 201A .
  • the display area 201 includes a first display area 2011 and a second display area 2012.
  • the first display area 2011 is located on the first side of the first opening area 202A
  • the second display area 2012 is located on the second side of the first opening area 202A.
  • the first side and the second side are in the first direction R1 (in the figure) In the horizontal direction) are opposite to each other.
  • the first display area 2011, the first opening peripheral area 203A, and the second display area 2012 are sequentially arranged along the first direction R1.
  • the whole formed by the first display area 2011 and the second display area 2012 includes a first pixel array.
  • the first pixel array includes a plurality of pixels arranged in an array, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit.
  • the display substrate includes a plurality of first signal lines 2301/2302/2303/2304/2305/2306, and the first signal line 2301 is configured to provide a first pixel array with a Display signals, and sequentially pass through the first display area 2011, the first opening peripheral area 203A, and the second display area 2012 along the first direction R1, thereby electrically connecting the first display area 2011 and the first display area 2011 on opposite sides of the first opening 201A.
  • the sub-pixels in the second display area 2012 for example, provide the first display signal for the sub-pixels of the plurality of pixels in the first display area 2011 and the second display area 2012 that are at the same horizontal position as the first opening peripheral area 203A.
  • the first display signal may be, for example, a gate scan signal, a light emission control signal, or a reset voltage signal in any form of electrical signal.
  • a plurality of first signal lines 2301/2302/2303/2304/2305/2306 can provide scan signals, light emission control signals, reset voltage signals, etc. for the pixel circuits in the first display area 2011 and the second display area 2012 of the display area.
  • the display substrate 20 further includes a third display area 2013.
  • the third display area 2013 includes a first portion 2013C located on the first side of the first display area 2011 and the second display area 2012 in the second direction R2, and a first portion 2013C located on the first side of the first display area 2011 and the second display area 2012 in the second direction R2.
  • the second portion 2013D of the second side of the display area 2012, the first side of the first display area 2011 and the second display area 2012 and the second side of the first display area 2011 and the second display area 2012 are in the second direction R2 Opposite each other; the first part 2013C and the second part 2013D are both connected to the first display area 2011 and the second display area 2012.
  • the two edges 2013A and 2013B of the first portion 2013C of the third display area 2013 that are opposite to each other in the second direction R2 are respectively aligned with the edges of the first display area 2011 that extend along the second direction R2 and are away from the first opening 201A.
  • 2011A and the edge 2012A of the second display area 201 extending along the second direction R2 and away from the first opening 201A are aligned.
  • the third display area 2013 includes multiple rows and multiple columns of pixels.
  • the display substrate 20 further includes a plurality of third signal lines 2307, and the plurality of third signal lines 2307 are located in the first portion 2013C and the second portion 2013D of the third display area 2013.
  • the third signal lines 2307 are configured to respectively provide third scanning signals to the rows of pixels in the third display area 2013 and extend along the first direction R1; for example, in this embodiment, the second signal lines 24 are sequentially along the second direction R2. It passes through the second portion 2013D of the third display area 2013, the first opening peripheral area 203A, and the first portion 2013C of the third display area 2013, and is configured to provide a second display signal to a plurality of columns of pixels in the third display area 2013.
  • the third display area 2013 also includes a plurality of pixels, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit.
  • Each pixel of the third display area 2013 may have the same structure as each pixel of the first display area and the second display area.
  • the number of pixels included in each row of pixels in multiple rows and multiple columns of sub-pixels in the third display area 2013 is substantially the same.
  • the number of pixels electrically connected to the plurality of third signal lines 2037 is substantially the same, so the plurality of third signal lines 2037 have substantially the same load.
  • each row of pixels in multiple rows and multiple columns includes more pixels than the first pixel row of the first pixel array and more pixels than the second pixel row of the first pixel array.
  • the load of each first signal line 2301/2302/2303/2304 after load compensation is basically the same as the load of the multiple third signal lines 2037, and each first signal line 2301/2302/2303/2304 is
  • the signal transmission speed of each third signal line 2037 is basically the same, and the deviation between the actual display signal transmitted to the pixel circuit of the sub-pixel and the design value is basically the same, so that the display consistency of the display area 201 can be maintained, and the display substrate can be improved. 20 display effect.
  • the display substrate 20 further includes a first power line VDD
  • the first power line VDD is connected to the first voltage terminal and is configured to provide a first power voltage to the pixel circuits of one or more sub-pixels.
  • the first power supply line VDD includes a plurality of first sub-wiring lines 2421/2422 extending in the first direction R1 and a plurality of second sub-wiring lines 2423/2424 extending in the second direction R2.
  • the first part of the first sub-wiring 2421 among the plurality of first sub-wiring 2421/2422 is disconnected in the first opening area 202A, and the second part of the first sub-wiring 2422 among the plurality of first sub-wiring 2421/2422 Through the third display area.
  • the first sub-wiring 2422 runs through the first portion 2013C of the third display area 2013 along the first direction R1.
  • the first part of the second sub-wiring 2423 of the multiple second sub-wiring 2423/2424 is disconnected in the first opening area 202A, and the second part of the second sub-wiring 2424 of the multiple second sub-wiring 2423/2424
  • the first display area 2011 and the third display area 2013 are sequentially passed through, for example, in this embodiment, the second portion 2013D of the third display area 2013, the first display area 2011, and the first portion 2013C of the third display area 2013 are sequentially passed through.
  • the second sub-wiring 2424 sequentially passes through the second display area 2012 and the third display area 2013, for example, in this embodiment, passes through the second portion 2013D, the second display area 2012, and the third display area of the third display area 2013 in order.
  • the first part of area 2013 is 2013C.
  • At least one of the first sub-wiring 2421 of the first part and the second sub-wiring 2424 of the second part 2424 is electrically connected in the first display area 2011 and the second display area 2012, and the second sub-travel of the first part
  • the line 2423 is electrically connected to at least one of the first sub-wiring 2422 in the second part of the first sub-wiring 2422 in the third display area 2013, so as to provide uniformity for the sub-pixels in each row and column of the first pixel array and the second pixel array.
  • the planar shape of the first opening area of the display substrate is not limited to a circle, for example, it may also be a regular pattern such as a rectangle, an ellipse, or the like, or a racetrack shape (for example, as shown in FIG. 15), a drop shape, etc. irregular shape.
  • the arrangement principles and technical effects of the first signal line and the second signal line are the same as or similar to those of the circular example described above.
  • At least one of the inter-opening area 2014, the first opening peripheral area 203A, and the second opening peripheral area 203B includes a first dummy sub-pixel.
  • the inter-opening area 2014 includes the first dummy sub-pixel.
  • a virtual sub-pixel 11 as an example, that is, the first virtual sub-pixel 11 is located in part A in FIG. 2C. The structure of the first virtual sub-pixel will be described in detail later.
  • the first dummy sub-pixel 11 may also be located in the first opening peripheral area 203A or/and the second opening peripheral area 203B.
  • the structure of the sub-pixels in the display area such as the sub-pixels 12 in the part B and the part C in FIG. 3C, will be introduced below.
  • the pixel circuit of each sub-pixel in the display area 201 of the display substrate 20 includes a transistor, which is described by taking a thin film transistor (TFT) as an example, a light-emitting element 180 and a storage capacitor CST.
  • the thin film transistor includes an active layer 120, a gate 121, and source and drain electrodes 122/123;
  • the storage capacitor CST includes a first plate CE1 and a second capacitor plate CE2.
  • the light emitting element 180 includes a cathode 183, an anode 181, and a light emitting layer 182 between the cathode 183 and the anode 181.
  • the anode 181 is electrically connected to one of the source and drain electrodes 122/123 of the thin film transistor TFT, such as the drain electrode 123.
  • the light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and correspondingly, the light-emitting layer 182 is an organic light-emitting layer or a quantum dot light-emitting layer.
  • the display area 201 further includes a first gate insulating layer 151 located between the active layer 120 and the gate electrode 121, a second gate insulating layer 152 located above the gate electrode 121, and an interlayer insulating layer 160.
  • the second gate insulating layer 152 is located between the first electrode plate CE1 and the second capacitor electrode plate CE2, so that the first electrode plate CE1, the second gate insulating layer 152 and the second capacitor electrode plate CE2 constitute a storage capacitor CST.
  • the interlayer insulating layer 160 covers the second capacitor plate CE2.
  • the display area 201 further includes an insulating layer 113 (for example, a passivation layer) covering the pixel circuit and a first planarization layer 112.
  • the display area 201 further includes a pixel defining layer 170 for defining a plurality of sub-pixels, and spacers (not shown) on the pixel defining layer 170 and other structures. As shown in FIG. 3A, the display area 201 further includes an insulating layer 113 (for example, a passivation layer) covering the pixel circuit and a first planarization layer 112.
  • the display area 201 further includes a pixel defining layer 170 for defining a plurality of sub-pixels, and spacers (not shown) on the pixel defining layer 170 and other structures. As shown in FIG.
  • the insulating layer 113 is located above the source and drain electrodes 122/123 (for example, the passivation layer is formed of silicon oxide, silicon nitride, or silicon oxynitride), and the insulating layer 113 is located above There is a first planarization layer 112, and the anode 181 is electrically connected to the drain 123 through a via hole penetrating the first planarization layer 112 and the insulating layer 113.
  • the first opening peripheral area 203A of the display substrate 20 further includes encapsulation layers 291, 292, and 293.
  • the display area 201 further includes an encapsulation layer 190, and the encapsulation layer 190 includes a plurality of encapsulation sublayers 191/192/193.
  • the encapsulation layer 190 is not limited to three layers, and may also be two layers, or four, five or more layers.
  • the first encapsulation layer 291 and the first encapsulation sublayer 191 in the encapsulation layer 190 are provided on the same layer
  • the second encapsulation layer 292 is provided on the same layer as the second encapsulation sublayer 192 in the encapsulation layer 190
  • the third encapsulation layer 293 is provided on the same layer as the first encapsulation sublayer 191 in the encapsulation layer 190.
  • the third encapsulation sublayer 193 in the encapsulation layer 190 is arranged in the same layer.
  • both the first encapsulation layer 291 and the third encapsulation layer 293 may include inorganic encapsulation materials, such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the second encapsulation layer 292 may include organic materials, such as resin materials.
  • the multi-layer packaging structure of the display area 201 and the first opening peripheral area 203A can achieve a better packaging effect to prevent impurities such as water vapor or oxygen from penetrating into the display substrate 20.
  • the display substrate further includes a buffer layer 111 on the base substrate 210.
  • the buffer layer 111 serves as a transition layer to prevent harmful substances in the base substrate 210 from intruding into the interior of the display substrate 20.
  • the adhesion of the film layer in the display substrate 20 on the base substrate 210 can be increased.
  • the material of the buffer layer 111 may include a single-layer or multi-layer structure formed of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • 3B is another schematic cross-sectional view of the sub-pixels in the display area of the display substrate.
  • the difference from the display area shown in FIG. 3A is that in the display area shown in FIG.
  • the transfer electrode 171 is covered with the second planarization layer 114, for example, the second planarization layer 114 is covered on the first planarization layer 112.
  • the display area of the display substrate may not have the insulating layer 113 and the second planarization layer 114.
  • the base substrate 210 may be a glass substrate, a quartz substrate, a metal substrate, a resin substrate, or the like.
  • the material of the base substrate 210 may include an organic material.
  • the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and polyethylene terephthalate. Resin materials such as esters and polyethylene naphthalate.
  • the base substrate 210 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiment of the present disclosure.
  • the material of any one of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarization layer 112, the pixel defining layer 170, and the spacers may include silicon oxide, silicon nitride , Inorganic insulating materials such as silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin.
  • the embodiments of the present disclosure do not specifically limit the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarization layer 112, the pixel defining layer 170, and the spacers.
  • the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarization layer 112, the second planarization layer 114, the pixel defining layer 170, and the spacers may be the same or the same as each other.
  • the parts are the same, and may also be different from each other, which is not limited in the embodiments of the present disclosure.
  • the display substrate 20 may further include a barrier wall 28 located in the peripheral area 203A of the first opening and at least partially surrounding the first opening 201A.
  • the barrier wall 28 at least partially overlaps the first signal line and the second signal line.
  • the barrier wall 28 can provide barrier and support in the peripheral area 203A of the first opening, maintain the stability of the first opening 201A, protect the photoelectric sensor components such as the camera in the first opening 201A, and block harmful impurities such as water vapor and oxygen from passing through the first opening.
  • 201A diffuses into the display area, thereby preventing harmful impurities from deteriorating the pixel circuit in the display area.
  • FIG. 4A is a schematic diagram of a plan layout of a first dummy pixel circuit in a display substrate provided by an embodiment of the present disclosure.
  • the first dummy pixel circuit is part A in FIG. 2C; -B2 line cross-sectional schematic diagram, FIGS. 4C-4G are schematic diagrams of each layer of a first dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure.
  • the first portion 2301A of the first signal line 2301 passes through the first dummy sub-pixel 11, the first dummy sub-pixel 11 includes a dummy pixel circuit, and the dummy pixel circuit includes a first compensation capacitor COM1,
  • the first compensation capacitor COM1 includes: a first electrode plate CE11 and a second electrode plate CE12.
  • the first electrode plate CE11 of the first compensation capacitor COM1 is provided on the same layer as the first portion 2301A of the first signal line 2301 and is electrically connected to the first signal line 2301, and is provided on the same layer as the second electrode plate CE2 of the storage capacitor CST;
  • the second electrode plate CE12 of a compensation capacitor COM1 and the first electrode plate CE11 of the first compensation capacitor COM1 are arranged in different layers and insulated from each other.
  • the orthographic projection of the second electrode plate CE12 of the first compensation capacitor COM1 on the base substrate 210 and the orthographic projection of the first electrode plate CE11 of the first compensation capacitor COM1 on the base substrate 210 at least partially overlap.
  • the first compensation capacitor COM1 compensates the load on the first signal line 2301, thereby reducing the display difference caused by the different loads on the first signal line connected to the pixels of different rows due to the different numbers of pixels in different rows, so that the first The display effect of the display area 2011 and the second display area 2012 is consistent with the display effect of the pixel rows in the display area 201 where the first opening area 202A is not provided, and the display quality is improved.
  • the first electrode plate CE11 and the second electrode plate CE2 of the storage capacitor CST are arranged in the same layer, the first electrode plate CE11 can not only form a compensation capacitor with the metal layer above it (in the direction away from the base substrate) , And can also form a compensation capacitor with the semiconductor layer below it (in the direction close to the base substrate). If the first electrode plate CE11 and the gate electrode 121 are arranged in the same layer, it will form a TFT with the semiconductor layer.
  • the first electrode plate CE11 of the first compensation capacitor COM1 and the first signal line 2301 are integrally formed.
  • the material of the second electrode plate CE12 of the first compensation capacitor COM1 includes a semiconductor material and is a conductor, and is provided in the same layer as the above-mentioned active layer 120.
  • the material of the second electrode plate CE12 of the first compensation capacitor COM1 includes the same material as the active layer 120, such as a-Si, polysilicon, and the like.
  • the second plate CE12 of the first compensation capacitor COM1 is heavily doped to enhance its conductivity and make it a conductor.
  • the active layer 120 can be doped at the same time, since the second electrode plate CE12 of the first compensation capacitor COM1 will not be blocked, and heavy doping can be realized.
  • the doping material is boron (B).
  • a voltage signal is applied to the second electrode plate CE12.
  • the semiconductor material is equivalent to a conductor, so it can be used as a capacitor electrode plate, and the existing layers are fully utilized. It can be formed simultaneously with the active layer 120 through the same patterning process.
  • the same patterning process refers to using the same mask to pass the same exposure for patterning.
  • the virtual pixel circuit further includes a second compensation capacitor COM2, and the second compensation capacitor COM2 includes a first electrode plate CE21 and a second electrode plate CE22.
  • the first electrode plate CE21 of the first compensation capacitor COM1 is reused as the first electrode plate CE21 of the second compensation capacitor COM2; the second electrode plate CE22 and the first electrode plate CE21 of the second compensation capacitor COM2 are arranged in different layers and insulated, and It is arranged on the same layer as the above-mentioned source and drain electrodes 122/123.
  • the orthographic projection of the second electrode plate CE22 of the second compensation capacitor COM2 on the base substrate 210 and the orthographic projection of the first electrode plate CE21 of the second compensation capacitor CE22 on the base substrate 210 at least partially overlap.
  • the second compensation capacitor further compensates the load on the first signal line 2301, thereby reducing the display difference caused by the different loads on the first signal line connecting the pixels of different rows due to the different numbers of pixels in different rows.
  • the display effect of the display area 2011 and the second display area 2012 is consistent with the display effect of the pixel rows in the display area 201 where the first opening area 202A is not provided, and the display quality is improved.
  • the existing layer that is, the conductive layer where the source and drain electrodes 122/123 are located
  • it can be formed with the source and drain electrodes 122/123 by performing a patterning process on the same film layer, simplifying the manufacturing process of the display plate and saving costs.
  • the second plate CE22 of the second compensation capacitor COM2 is electrically connected to the second plate CE12 of the first compensation capacitor COM1, so that the first compensation capacitor and the second compensation capacitor are connected in parallel to provide more effective compensation and greater compensation Scope.
  • FIG. 4H is a schematic diagram of another first electrode plate of the first compensation capacitor of the display substrate provided by an embodiment of the present disclosure.
  • the first plate CE11 of the first compensation capacitor COM1 includes a first extension 21 and a second extension 22.
  • the first extension 21 is connected to the first portion 2301A of the first signal line 2303, extends from the first portion 2301A of the first signal line 2303 and is located on the first side of the first portion 2301A of the first signal line 2303 in the second direction R2,
  • the second direction R2 intersects the first direction R1, such as perpendicular but not limited to this;
  • the second extension 22 is connected to the first portion 2301A of the first signal line 2303, extends from the first portion 2301A of the first signal line 2303 and is located at the first portion 2301A of the first signal line 2303.
  • the first portion 2301A of the signal line 2303 is a second side opposite to the first side in the second direction R2.
  • first extension 21, the second extension 22 and the first portion 2301A of the first signal line 2303 are integrally formed.
  • the display substrate further includes a first power line.
  • the first power line is connected to the first voltage terminal and is configured to provide a first power voltage to the pixel circuit and is connected to the second plate CE2 of the storage capacitor CST.
  • the first power line includes: a plurality of first power lines extending in a first direction.
  • a sub-wiring line and a plurality of second sub-wiring lines extending along the second direction, and the plurality of second sub-wiring lines are electrically connected with the plurality of first sub-wiring lines.
  • the first part of the second sub-wiring 2424 among the plurality of second sub-wiring passes through the inter-opening area 2014 and passes through the first dummy sub-pixel 11.
  • the second plate CE22 of the second compensation capacitor COM2 includes a first part CE221 and a second part CE222.
  • the first part of the second sub-wiring 2424 is the same as the first part CE221 of the second plate of the second compensation capacitor.
  • Layer is arranged and electrically connected to serve as the second part CE222 of the second plate of the second compensation capacitor, and the first part of the second sub-wiring 2424 is electrically connected to the second plate CE12 of the first compensation capacitor COM1, thereby realizing the first
  • the second plate CE22 of the two compensation capacitor COM2 is electrically connected to the second plate CE12 of the first compensation capacitor COM1.
  • the first part of the second sub-wiring 2424 and the second plate CE22 of the second compensation capacitor COM2 are integrally formed.
  • Fig. 4I is a schematic cross-sectional view taken along the line A3-B3 in Fig. 4A.
  • the display substrate 20 further includes: a first insulating layer 151 (for example, the aforementioned first gate insulating layer) between the second electrode plate CE12 of the first compensation capacitor COM1 and the aforementioned gate 121, The second insulating layer 152 (for example, the above-mentioned second gate insulating layer) between the gate 121 and the first electrode plate CE11 of the first compensation capacitor COM1, and the first electrode plate CE11 and the first electrode plate CE11 of the first compensation capacitor COM1
  • the third insulating layer 160 (for example, the aforementioned interlayer insulating layer) between the second plate CE22 of the two compensation capacitors COM2.
  • the first part of the second sub-wiring 2424 passes through the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160 and exposes the first via hole VH10 of the second electrode plate CE12 of the first compensation capacitor COM1 and the first compensation
  • the second plate CE12 of the capacitor COM1 is electrically connected.
  • the display substrate 20 further includes a plurality of second signal lines 24.
  • the plurality of second signal lines 24 are configured to provide second display signals to the plurality of sub-pixels.
  • the first part of the second signal line 2411 of the plurality of second signal lines 24 passes through the inter-opening area 2014 and passes through the first dummy sub-pixel 11 along the second direction R2.
  • the first part of the second signal line 2411 is located on the side of the second electrode plate CE22 of the second compensation capacitor COM2 away from the base substrate 210.
  • the first part 21 of the second electrode plate CE22 of the second compensation capacitor COM2 has a hollow area H1, passing through the first virtual sub-pixel 11 where the second electrode plate CE22 of the second compensation capacitor COM2 is located.
  • the orthographic projection of the first part of the second signal line 2411 on the base substrate 210 and the hollow area H1 at least partially overlap, so as to reduce the overlapping area of the first part of the second signal line 2411 and the second electrode plate CE22 of the second compensation capacitor COM2 , Reduce the capacitance formed by the overlap of the two, thereby reducing the load of the first part of the second signal line 2411.
  • the second electrode plate CE22 of the second compensation capacitor COM2 has a plurality of hollow areas H1/H2.
  • two hollow areas H1 are taken as an example.
  • the two directions R2 are spaced apart from each other. In this way, the load of the first part of the second signal line 2411 can be adjusted in steps according to different needs.
  • the plurality of hollow areas include adjacent first hollow areas H1 and second hollow areas H2, the length of the first hollow area H1 in the second direction R2 and the length of the second hollow area H2
  • the length in the second direction R2 is different, and the load of the first part of the second signal line 2411 can be adjusted differently according to the different parts of the load of the first part of the second signal line 2411.
  • the portion P of the second electrode plate CE22 of the second compensation capacitor COM2 located between the first hollow area H1 and the second hollow area H2 is continuous along the first direction R1; the second compensation The second plate CE22 of the capacitor COM2 includes a first edge and a second edge opposite to each other in the second direction R2, and at least one of the first edge and the second edge is cut off by a hollow area.
  • the first signal line includes a gate scan signal line and a reset signal line.
  • the first signal line 2303 is a gate scan signal line and is configured to provide a gate scan signal to the sub-pixel.
  • the first display signal is a gate scan signal;
  • the first signal line 2301 is a reset signal line and is configured to provide a gate scan signal to the sub-pixel.
  • a reset voltage signal is provided, and correspondingly, the first display signal is a reset voltage signal.
  • the second signal line 24 is a data line and is configured to provide the sub-pixel with a data signal for controlling the light-emitting gray level of the sub-pixel.
  • the second plate CE12 of the first compensation capacitor COM1 covers the entire first virtual sub-pixel 11, and the first plate CE11 of the first compensation capacitor COM1
  • the orthographic projection on the base substrate 210 is located within the orthographic projection of the second electrode plate CE12 of the first compensation capacitor COM1 on the base substrate 210.
  • the size of the first compensation capacitor COM1 is smaller than the size of the second compensation capacitor COM2.
  • the effective size of each plate of the first compensation capacitor COM1 and the second compensation capacitor COM2 can be adjusted as needed to adjust the sizes of the first compensation capacitor COM1 and the second compensation capacitor COM2.
  • the display area 201 includes a first display area 2011 and a second display area 2012.
  • the first display area 2011 is located on the side of the first opening area 202A away from the inter-opening area 2014; the second display area 2012 is located on the side of the second opening area 202B away from the inter-opening area 2014.
  • Both the first display area 2011 and the second display area 2012 include a plurality of pixels.
  • the whole formed by the first display area 2011 and the second display area 2012 includes a plurality of pixel rows extending along the first direction R1, such as the first row, the second row, the third row...
  • the plurality of pixel rows are cut off by the whole constituted by the first opening area 202A, the inter-opening area 2014, and the second opening area 202B.
  • the number of pixels in the first row of pixels is different from the number of pixels in the second row
  • the number of first compensation capacitors in the first virtual pixel row corresponding to the pixels in the first row is different from the number of pixels corresponding to the second row of pixels in the second row.
  • the number of the first compensation capacitors in the virtual pixel rows is different, so as to make the load of the first signal lines of the pixels of different rows uniform.
  • the first signal line 2303 sequentially passes through the first display area 2011, the first opening peripheral area 203A, the inter-opening area 2014, the second opening peripheral area 203B, and the second display area 2012 along the first direction R1.
  • the first signal line 2303 also includes a second portion 2303B passing through the first display area 2011 and a third portion 2303C passing through the second display area 2012, and the second portion 2303B and the third portion 2303C are arranged in the same layer as the gate electrode 121. Therefore, the second part 2303B and the first part 2303A need to be changed layers, and the first part 2303A and the third part 2303C need to be changed layers.
  • Fig. 5A is an enlarged schematic diagram of part C in Fig. 2C
  • Figs. 5B-5D are enlarged schematic diagrams of part D, part E, and part F in Fig. 2C, respectively
  • Fig. 5E is a layer change of the first signal line and the second signal line
  • Figures 5F-5H are schematic cross-sectional views taken along lines A4-B4, A5-B5, and A6-B6 in Figure 5E, respectively.
  • the display substrate 20 further includes a first connection structure, for example, the first connection structure includes a first sub-connection structure 311 and a second sub-connection structure 312.
  • the first connection structure 311/312 is located in the first opening peripheral area 203A, such as at the junction of the first opening peripheral area 203A and the first display area 2011, and is connected to the second portion 2303B/2301B and the first signal line of the first signal line.
  • the first part 2303A/2301A of a signal line are arranged in different layers
  • the second part 2303B/2301B of the first signal line is electrically connected to the first connection structure 311/312, and the first part 2303A/2301A of the first signal line is connected to the first connection.
  • the structure 311/312 is electrically connected to realize the layer change when the first signal line 2303/2301 enters the first opening peripheral area 203A from the first display area 2011.
  • the first signal line 2303 is a gate scan signal line
  • the first signal line 2301 is a reset signal line.
  • 5E and 5F the second part 2301B of the reset signal line and the first part 2301A of the reset signal line are arranged in different layers, and the second part 2301B of the reset signal line is electrically connected to the second sub-connection structure 312 through the via hole VH11 to reset
  • the first part 2301A of the signal line is electrically connected to the second sub-connection structure 312 through the via VH12, so that the second part 2301B of the reset signal line is electrically connected to the first part 2301A of the reset signal line, so that the reset signal line 2301 undergoes a layer change
  • the wiring is routed around the first opening.
  • the second part 2303B of the gate scan signal line and the first part 2303A of the gate scan signal line are arranged in different layers, and the second part 2303B of the gate scan signal line is connected to the first sub through the via hole VH13.
  • the structure 311 is electrically connected, and the first part 2303A of the gate scan signal line is electrically connected to the first sub-connection structure 311 through the via hole VH14, so that the second part 2303B of the gate scan signal line is electrically connected to the first part 2303A of the gate scan signal line.
  • the gate scan signal line 2303 is routed around the first opening after changing the layer.
  • first connection structure and the second connection structure are arranged on the same layer as the source and drain electrodes 122/123.
  • the display substrate 20 also includes a second connection structure.
  • the second connection structure is located in the second opening peripheral area 203B, for example, at the junction of the second opening peripheral area 203B and the first display area.
  • the first part 2303A/2301A of the first signal line and the third part 2303C/2301C of the first signal line are arranged in different layers; the first part 2303A/2301A of the first signal line and the second connection structure (not shown) Electrically connected, the third portion 2303C/2301C of the first signal line is electrically connected to the second connection structure to realize another layer change of the first signal line 2303, that is, the first signal line 2303 enters the second signal line from the peripheral area 203B of the second opening.
  • the second connection structure includes a third sub-connection structure and a fourth sub-connection structure, which are respectively provided corresponding to the gate scan signal line 2303 and the reset signal line 2301, so as to realize the gate scan signal line 2303 and the reset signal line 2301, respectively.
  • the arrangement of the third sub-connection structure and the fourth sub-connection structure can refer to the arrangement of the above-mentioned first sub-connection structure and the second sub-connection structure.
  • the third sub-connection structure and the fourth sub-connection structure are substantially symmetrical to the first sub-connection structure and the second sub-connection structure.
  • the first gate line GLn and the second gate line GLn-1 that provide gate scan signals to the sub-pixels 12 in the same row are exchanged through the same first sub-connection structure 311 to save space.
  • the reset signal lines that provide reset voltage signals to multiple rows of sub-pixels can be layered through the same second connection structure 312 to save space.
  • the same second connecting structure 312 is routed along the boundary area between the first display area and the peripheral area of the first opening in a zigzag line, so as to make reasonable use of space and leave enough space for other structures such as the first connecting structure and the second connecting structure. Space.
  • a plurality of second connection structures 312 separated from each other can also be used for layer change.
  • a part of the second signal line 2410 enters the peripheral area of the first opening from the display area (the same is true for the second opening, taking the first opening as an example), always located at the source and drain 122/123 The side away from the base substrate 210 does not change the layer.
  • a part of the second signal line 2412 enters the peripheral area of the first opening from the display area (the same is true for the second opening, taking the first opening as an example).
  • the second signal line 2412 includes a first portion 2412A passing through the display area and a first portion 2412A passing through the first opening.
  • the second portion 2412B of the opening peripheral region 203A, the first portion 2412A of the second signal line 2412 is located on the side of the source and drain 122/123 away from the base substrate 210, and the second portion 2412B of the second signal line 2412 is connected to the source and drain
  • the pole 122/123 is set on the same floor. Therefore, the second signal line 2412 needs to be layer changed.
  • the first part 2412A of the second signal line 2412 is directly connected to the second part 2412B of the second signal line 2412 through the via hole VH15 passing through the insulating layer 113, and no additional connection electrodes are required to simplify the production. Craft.
  • the data line 2410 without layer change is adjacent to the data line 2412 with layer change in the first direction.
  • FIG. 6 is an equivalent circuit diagram of a pixel circuit in an array substrate provided by an embodiment of the present disclosure
  • FIG. 7A is a schematic diagram of a planar layout of a pixel circuit in an array substrate provided by an embodiment of the present disclosure.
  • FIG. 7A takes the layer structure of pixel circuits in two adjacent sub-pixels as an example.
  • the data line 1 below is an example of the second signal line 24 described above.
  • Each of the plurality of sub-pixels 1030 includes a pixel circuit, and the pixel circuit includes a light-emitting device, a storage capacitor CST, a driving transistor T1 (hereinafter also referred to as a first transistor), a data writing transistor T2 (hereinafter also referred to as a second transistor), and a data line 1 and the first connection structure CP1.
  • Each of the driving transistor T1 and the data writing transistor includes an active layer, a gate, a first electrode, and a second electrode.
  • the driving transistor T1 is configured to control the light emitting device to emit light, for example, to control a driving current for driving the light emitting device to emit light.
  • the data line 1 is connected to the first pole of the data writing transistor T2 and is configured to provide the data writing transistor T2 with a data signal for controlling the display gray scale of the sub-pixel 1030.
  • the data writing transistor T2 is configured to write a data signal to the gate of the driving transistor T1 in response to a first scan signal applied to the gate of the data writing transistor T2.
  • the first connection structure CP1 is connected to the gate of the driving transistor T1 and the first plate of the storage capacitor CST.
  • the first connection structure CP1 and the data line 1 are arranged in different layers, that is, the first connection structure CP1 and the data line 1 are arranged in different layers.
  • first connection structure CP1 There is an insulating layer between the first connection structure CP1 and the data line 1 in a direction perpendicular to the base substrate 210.
  • the distance between the two is small, which will cause the first connection structure CP1 to be horizontally
  • a large parasitic capacitance is formed between the data line 1 and the data line 1, especially in a high-resolution display panel, this phenomenon is particularly serious. This parasitic capacitance will directly lead to unsatisfactory display effects.
  • the parasitic capacitance formed between the first connection structure CP1 and the data line 1 is unstable, because during the display process, the data signal on the data line 1 is constantly changing, and as the data signal is written into the gate of the driving transistor T1 It means that the data signal is written into the N1 node in FIG. 6, which causes the N1 node signal to jump, thereby affecting the fluctuation of the current flowing through the N1 node and affecting the display effect.
  • the first connection structure CP1 is the actual structure corresponding to the N1 node in FIG.
  • disposing the first connection structure CP1 and the data line 1 in different layers can reduce or avoid The parasitic capacitance is formed between the two, which can improve or avoid the adverse effects on the display effect and achieve a more ideal display effect.
  • the above-mentioned parasitic capacitances are formed between the data line 1 corresponding to the same sub-pixel 1030 and the first connection structure CP1, which correspond to two adjacent ones respectively.
  • the above-mentioned parasitic capacitance (represented by parasitic capacitance 2 below) is also formed between the data line 1 in each sub-pixel and the first connection structure CP1.
  • the degree of crosstalk between the two on node N1 It is 0.678%. The greater the value of the crosstalk degree, the greater the interference formed, and the greater the adverse effect on the display.
  • the value of the parasitic capacitance 1 is about 0.0321fF, and the value of the parasitic capacitance 2 can reach 0.0242fF, and the degree of crosstalk between the two on the N1 node is 0.218%. It can be seen that the values of the parasitic capacitance 1 and the parasitic capacitance 2 in the array substrate provided by the embodiment of the present disclosure are significantly reduced compared to the situation where the two are arranged in the same layer, and the degree of crosstalk generated to the N1 node is significantly reduced, thereby affecting the display The adverse effects caused have a significant improvement effect.
  • the pixel circuit includes a plurality of thin film transistors: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and The seventh transistor T7, the multiple signal lines connected to the multiple thin film transistors T1, T2, T3, T4, T5, T6, and T7, and the storage capacitor CST, that is, the pixel circuit in this embodiment has a 7T1C structure.
  • the plurality of signal lines include gate lines GLn/GLn-1 (ie, scan signal lines), light emission control lines EM, reset signal lines RL, data lines DAT, and first power supply lines VDD.
  • the gate line GLn/GLn-1 may include a first gate line GLn and a second gate line GLn-1.
  • the first gate line GLn is used to transmit the gate scan signal
  • the second gate line GLn-1 is used to transmit the reset voltage signal.
  • the emission control line EM is used to transmit the emission control signal, for example, is connected to the first emission control terminal EM1 and the Two light-emitting control terminal EM2.
  • the gate of the fifth transistor T5 is connected to the first light emission control terminal EM1, or used as the first light emission control terminal EM1 to receive the first light emission control signal;
  • the gate of the sixth transistor T6 is connected to the second light emission control terminal EM2, or As the second light emission control terminal EM2, to receive the second light emission control signal.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned 7T1C structure pixel circuit.
  • the pixel circuit may also adopt other types of circuit structures, such as 7T2C structure or 9T2C structure, which is not limited by the embodiment of the present disclosure.
  • the first gate of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4.
  • the first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5.
  • the first drain electrode D1 of the first thin film transistor T1 is electrically connected to the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6.
  • the second gate of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive the gate scan signal;
  • the second source S2 of the second thin film transistor T2 is configured To be electrically connected to the data line DAT to receive data signals;
  • the second drain electrode D2 of the second thin film transistor T2 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the third gate of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, and the third source S3 of the third thin film transistor T3 is connected to the first gate line GLn of the first thin film transistor T1.
  • the drain electrode D1 is electrically connected, and the third drain electrode D3 of the third thin film transistor T3 is electrically connected to the first gate electrode of the first thin film transistor T1.
  • the fourth gate of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal
  • the fourth source S4 of the fourth thin film transistor T4 is configured
  • the fourth drain electrode D4 of the fourth thin film transistor T4 is electrically connected to the first gate electrode of the first thin film transistor T1.
  • the fifth gate of the fifth thin film transistor T5 is configured to be electrically connected to the light emission control line EM to receive the light emission control signal
  • the fifth source S5 of the fifth thin film transistor T5 is configured to be connected to the light emission control line EM.
  • a power line VDD is electrically connected to receive the first power signal
  • the fifth drain electrode D5 of the fifth thin film transistor T5 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the sixth gate of the sixth thin film transistor T6 is configured to be electrically connected to the emission control line EM to receive the emission control signal, and the sixth source S6 of the sixth thin film transistor T6 is connected to the first thin film transistor.
  • the first drain D1 of T1 is electrically connected, and the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first display electrode (for example, the anode 181 shown in FIG. 6) of the light emitting device (for example, the light emitting device 180 shown in FIG. 6). connect.
  • the thin film transistor TFT in FIGS. 7A-7C is the sixth thin film transistor T6.
  • the seventh gate of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal
  • the seventh source S7 of the seventh thin film transistor T7 is The first display electrode (for example, the anode 181 shown in FIG. 6) of the device is electrically connected
  • the seventh drain electrode D7 of the seventh thin film transistor T7 is configured to be electrically connected to the reset signal line RL to receive the reset voltage signal.
  • the seventh drain electrode D7 of the seventh thin film transistor T7 may be electrically connected to the reset signal line RL by being connected to the fourth source electrode S4 of the fourth thin film transistor T4.
  • the fourth transistor T4 and the seventh transistor T7 are reset transistors, which are configured to provide a reset signal to the sub-pixel.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the first electrode of any transistor has a source electrode
  • the second electrode has a drain electrode; or, if any transistor has a first electrode electrode that has a drain electrode, the second electrode has a source electrode.
  • the source and drain of each transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure.
  • the source and drain of all or part of the transistors are based on Needs are interchangeable.
  • FIG. 7B-7F are schematic diagrams of various layers of a pixel circuit of an array substrate provided by an embodiment of the present disclosure
  • FIG. 8A is a schematic cross-sectional view taken along the line A-A' in FIG. 7A.
  • the pixel circuit includes the aforementioned thin film transistors T3, T4, T5, T6, and T7, a storage capacitor CST, and a plurality of thin film transistors T1, T2, T3, T4, T5, T6. And T7 of the first gate line GLn, the second gate line GLn-1, the light emission control line EM, the reset signal line RL, the data line DAT, and the first power supply line VDD.
  • FIGS. 7A-7F and FIG. 8A the specific features of the structure of the pixel circuit of the embodiment of the present disclosure will be described with reference to FIGS. 7A-7F and FIG. 8A.
  • the data line 1 and the first connection structure CP1 both extend along the first direction, and the orthographic projection of the first connection structure CP1 on the base substrate 210 is the same as that of the data line 1 on the base substrate 210.
  • the orthographic projections are at least partially opposite to each other in the lateral direction R2. This structure is conducive to the compactness of the pixel circuit structure.
  • the lateral direction R2 is parallel to the base substrate 210 and perpendicular to the first direction R1.
  • the distance between the orthographic projection of the first connection structure CP1 on the base substrate 210 and the orthographic projection of the data line 1 on the base substrate 210 (the proximity of the orthographic projection of the first connection structure CP1 on the base substrate 210)
  • the maximum distance from the side of the orthographic projection of the data line 1 on the base substrate 210 to the side of the orthographic projection of the data line 1 on the base substrate 210 that is close to the orthographic projection of the first connection structure CP1 on the base substrate 210) is less than
  • the size of one sub-pixel 1030 in the lateral direction is more conducive to the compactness of the pixel circuit structure.
  • the distance between the first connection structure CP1 and the data line 1 in the lateral direction R2 is small, the above-mentioned Parasitic capacitance phenomenon.
  • the distance between the data line 1 corresponding to the same sub-pixel 1030 and the first connection structure CP1 is smaller than the size of one sub-pixel 1030 in the lateral direction R2, and respectively corresponds to the data line 1 in two adjacent sub-pixels.
  • the distance from the first connection structure CP1 is smaller than the size of one sub-pixel 1030 in the lateral direction R2.
  • the size of one sub-pixel 1030 in the lateral direction R2 is 30 ⁇ m to 90 ⁇ m.
  • the array substrate provided by the embodiment of the present disclosure can simultaneously prevent the above-mentioned parasitic capacitance phenomenon.
  • the pixel circuit includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer.
  • FIG. 7A shows a schematic layout diagram of the stacked position relationship of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer of the pixel circuit.
  • FIG. 7B shows the semiconductor layer of the pixel circuit.
  • the semiconductor layer shown in FIG. 7B includes the active layer A1 of the first thin film transistor T1, the active layer A2 of the second thin film transistor T2, the active layer A3 of the third thin film transistor T3, and the active layer A3 of the fourth thin film transistor T4.
  • the semiconductor layer can be formed by a patterning process using a semiconductor material layer.
  • the semiconductor layer can be used to make the above, and the active layer of each transistor can include a source region, a drain region, and a channel region between the source region and the drain region.
  • the semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials (for example, indium gallium tin oxide (IGZO)), or the like.
  • IGZO indium gallium tin oxide
  • the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • a first insulating layer is formed on the above-mentioned semiconductor layer.
  • various insulating layers are not shown in FIGS. 7A and 7B-7K.
  • the first insulating layer 151 of the pixel circuit is disposed on the side of the first conductive layer away from the base substrate 210.
  • FIG. 7C shows the first conductive layer of the pixel circuit
  • FIG. 7G shows a schematic diagram after the first conductive layer and the semiconductor layer are laminated.
  • the first conductive layer is located on the side of the semiconductor layer away from the base substrate 210.
  • the first insulating layer 151 is located between the active layer and the first conductive layer of each transistor.
  • the first conductive layer includes the first plate CE1 of the storage capacitor CST, the first gate line GLn, the second gate line GLn-1, the light emission control line EM, and the gate of the first thin film transistor T1, the second thin film transistor The gate of T2, the gate of the third thin film transistor T3, the gate of the fourth thin film transistor T4, the gate of the fifth thin film transistor T5, the gate of the sixth thin film transistor T6, and the gate of the seventh thin film transistor T7.
  • the active layers of the above-mentioned transistors are arranged in the same layer, and the gates of the above-mentioned transistors and the first plate CE1 of the storage capacitor CST are arranged in the same layer, so that the first insulating layer 151 is located on the active layer of each transistor and each transistor. Between the gate and the first plate CE1 of the storage capacitor CST. It can be seen that the driving transistor, that is, the gate of the first transistor T1 (or the gate of each transistor) and the first plate CE1 of the storage capacitor CST are located far away from the active layer of the driving transistor (or the active layer of each transistor). One side of the base substrate 210.
  • the gate of the thin film transistor T7 is the overlapped portion of the first gate line GLn, the second gate line GLn-1 and the semiconductor layer, respectively.
  • the third thin film transistor T3 may be a thin film transistor with a double gate structure, and a gate of the third thin film transistor T3 may be a portion where the first gate line GLn overlaps the semiconductor layer, and the third thin film transistor
  • the other gate electrode of T3 may be a protrusion protruding from the first gate line GLn;
  • the gate electrode of the first thin film transistor T1 may be integrally formed with the first electrode plate CE1, that is, the first electrode plate CE1 is reused as the first thin film transistor The gate of T1.
  • the fourth thin film transistor T4 may be a thin film transistor with a double-gate structure, and the two gates are respectively the overlapping parts of the second gate line GLn-1 and the semiconductor layer.
  • the gates of the above-mentioned thin film transistors are respectively integrally formed with the corresponding first gate line GLn or the second gate line GLn-1.
  • the first gate line GLn, the second gate line GLn-1, and the gate of each thin film transistor are arranged in the same layer as the first electrode plate CE1 of the storage capacitor CST, and can be formed simultaneously by the same patterning process.
  • the array substrate 100 further includes a first power line VDD, the first power line is connected to the first voltage terminal VDD and the second plate CE2 of the storage capacitor CST, and is configured to provide the light-emitting control transistor, that is, the second plate CE2 of the storage capacitor CST.
  • a transistor T1 provides the first voltage.
  • the first power line VDD includes a first sub-wiring 21 extending in a first direction R1 and a second sub-wiring 22 extending in a second direction, the first direction R1 intersects the second direction, for example, the second direction is Lateral R2.
  • the first sub-wire 21 is electrically connected to the second sub-wire 22.
  • FIG. 7D shows the second conductive layer of the pixel circuit
  • FIG. 7H shows a schematic diagram after the second conductive layer and the semiconductor layer are laminated.
  • the second conductive layer is located on the side of the first conductive layer away from the base substrate 210.
  • the second conductive layer of the pixel circuit includes the second plate CE2 of the storage capacitor CST, the reset signal line RL, and the second sub-wiring 22, which shows that the second sub-wiring 22 is arranged on the same layer as the second plate CE2 of the storage capacitor CST, and the second plate CE2 of the storage capacitor CST is located at the gate of the driving transistor, that is, the gate of the first transistor T1 (or the gate of each transistor) and the first of the storage capacitor CST.
  • the second sub-wiring 22 and the second plate CE2 of the storage capacitor CST are integrally formed, so that they can be formed by the same patterning process.
  • the second electrode plate CE2 and the first electrode plate CE1 at least partially overlap to form a storage capacitor CST.
  • the second conductive layer may further include a light shielding portion 791.
  • the orthographic projection of the light shielding portion 791 on the base substrate 210 covers at least part of the active layer of the second thin film transistor T2, the active layer between the drain of the third thin film transistor T3 and the drain of the fourth thin film transistor T4, thereby Prevent external light from affecting the active layers of the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4.
  • the light-shielding portion 791 may be electrically connected to the first power line VDD through the via hole VH9 in the insulating layer, as shown in FIGS. 7A and 8C.
  • the first connection structure CP1 is located between the first sub-wiring 21 and the data line 1 (and the first sub-wiring 21 and the data line 1).
  • a connecting structure CP1 and the first sub-wiring 21 belong to the pixel circuit of the same sub-pixel.
  • the second conductive layer may also include the aforementioned light-shielding portion 791 to To shield the active layer of the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4, the second conductive layer can be used to achieve this purpose, thereby simplifying the manufacturing process of the array substrate.
  • the array substrate 100 further includes a second insulating layer 152.
  • the second insulating layer 152 is located between the first plate CE1 of the storage capacitor CST and the second plate CE2 of the storage capacitor CST. Between a conductive layer and a second conductive layer. For clarity, the second insulating layer 152 is also not shown in FIGS. 7B-7F.
  • the array substrate 100 further includes a second power supply line VSS.
  • the first power line VDD is a power line that provides a high voltage to the pixel circuit
  • the second power line VSS is connected to the second voltage terminal and the second power line VSS provides a low voltage (lower than the aforementioned high voltage) power line to the pixel circuit.
  • the first power supply line VDD provides a constant first power supply voltage
  • the first power supply voltage is a positive voltage
  • the second power supply line VSS provides a constant second power supply voltage
  • the second power supply voltage can be It is negative voltage and so on.
  • the second power supply voltage may be a ground voltage.
  • the data line 1 is located on the side of the first connection structure CP1 away from the base substrate 210.
  • FIG. 7E shows the third conductive layer of the pixel circuit
  • FIG. 7I shows a schematic diagram after the third conductive layer and the semiconductor layer are laminated.
  • the third conductive layer is located on the side of the second conductive layer away from the base substrate 1.
  • the third conductive layer of the pixel circuit includes the first connection structure CP1 and the first sub-wiring 21 of the first power line VDD, that is, the first connection structure CP1 and the first sub-wiring 21 21 Same layer settings. As shown in FIG.
  • the array substrate 100 further includes a third insulating layer 160.
  • the third insulating layer 160 is located between the second plate CE2 of the storage capacitor CST and the first connection structure CP1, that is, between the second conductive layer and the third conductive layer. Between conductive layers.
  • the first sub-wiring 21 is electrically connected to the second sub-wiring 22 through a via hole (for example, via VH3) penetrating the third insulating layer 160.
  • a via hole for example, via VH3
  • the third conductive layer further includes a second connection structure CP2, a third connection structure CP3, and a fourth connection structure CP4.
  • One end of the first connection structure CP1 passes through the via hole (for example via hole VH5) of the first electrode plate CE1 of the storage capacitor CST and the first electrode plate of the storage capacitor CST which penetrates through the second insulating layer 152 and the third insulating layer 160 and exposes part of the storage capacitor CST.
  • CE1 connection for example via hole VH5
  • the other end of the first connection structure CP1 is connected to the semiconductor layer through at least one via hole (for example, via hole VH4) penetrating through the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160, for example, with the corresponding first insulating layer in the semiconductor layer.
  • the drain regions of the three thin film transistors T3 are connected.
  • One end of the second connection structure CP2 is connected to the reset signal line RL through a via hole (for example, via hole VH6) penetrating the third insulating layer 160, and the other end of the second connection structure CP2 is connected to the reset signal line RL by penetrating the first insulating layer 151 and the second insulating layer.
  • At least one via (for example, via VH7) of 152 and third insulating layer 160 is connected to the semiconductor layer, for example, connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer.
  • the third connection structure CP3 is connected to the drain region of the sixth thin film transistor T6 in the semiconductor layer through at least one via hole (for example, via hole VH8) penetrating through the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160 .
  • the fourth connection structure CP4 is connected to the drain region of the fifth thin film transistor T5 in the semiconductor layer through at least one via hole (for example, via hole VH2) penetrating through the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160 .
  • the fifth connection structure CP5 passes through the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160 and exposes part of the semiconductor layer through at least one via hole (for example, via hole VH1) and the third thin film transistor T3 in the semiconductor layer.
  • the drain area is connected.
  • FIG. 7F shows the fourth conductive layer of the pixel circuit
  • FIG. 7J shows a schematic diagram after the fourth conductive layer and the semiconductor layer are laminated
  • FIG. 7K shows the fourth conductive layer, the third conductive layer and the semiconductor layer are laminated Schematic diagram after.
  • the fourth conductive layer is located on the side of the third conductive layer away from the base substrate 210.
  • the fourth conductive layer includes a data line 1 (DATA), a sixth connection structure CP6, and a seventh connection structure CP7.
  • DATA data line 1
  • CP6 sixth connection structure
  • CP7 seventh connection structure
  • the array substrate 100 further includes a fourth insulating layer 113, which is located between the third conductive layer and the fourth conductive layer, that is, between the first connection structure CP1 and the data line 1 (DATA).
  • the fourth insulating layer 113 is a flat layer.
  • the via hole VH1 also penetrates the fourth insulating layer 113 to expose at least part of the fifth connection structure CP5, and the data line 1 (DATA) is electrically connected to the fifth connection structure CP5 through the via hole VH1, thereby realizing the data line 1 (DATA) and the semiconductor layer
  • the drain region of the third thin film transistor T3 in is electrically connected.
  • the seventh connection structure CP7 directly contacts the data line 1 to realize electrical connection between the two.
  • the seventh connection structure CP7 can widen the part of the data line 1 that needs to be connected to the semiconductor layer, such as the data line 1 and the seventh connection.
  • the entire structure of the structure CP7 is electrically connected to the fifth connection structure CP5 through the via hole VH1, so that the data line 1 (DATA) is electrically connected to the drain region of the third thin film transistor T3 in the semiconductor layer.
  • the seventh connection structure CP7 and the data line 1 are integrally formed.
  • the via hole VH2 also penetrates the fourth insulating layer 113 to expose at least part of the fourth connection structure CP4, and the sixth connection structure CP6 is electrically connected to the fourth connection structure CP4 through the via hole VH2, thereby realizing the sixth connection structure CP6 and the active
  • the drain region corresponding to the fifth thin film transistor T5 in the layer is connected to serve as the drain of the fifth thin film transistor T5.
  • the sixth connection structure CP6 is used to connect to the anode of the light emitting device (for example, the anode 181 shown in FIG. 6).
  • the anode of the light emitting device for example, the anode 181 shown in FIG. 6
  • the sixth connection structure CP6 is used to connect to the anode of the light emitting device (for example, the anode 181 shown in FIG. 6).
  • the anode of the light emitting device for example, the anode 181 shown in FIG. 6
  • the sixth connection structure CP6 is used to connect to the anode
  • the shape, size, and position of the sixth connection structure CP6 in the left sub-pixel 1030 shown in FIG. 7A are different from the shape, size, and position of the sixth connection structure CP6 in the right sub-pixel 1030, respectively. .
  • the shape, size, and position of the sixth connection structure CP6 extends in the direction intersecting the first direction R1 and the lateral direction R2, and its upper end (not the same as the fourth connection structure CP4 The position of the connected end) is such that it is connected to the anode located at the upper end.
  • the thickness of the fourth insulating layer 113 in the direction perpendicular to the base substrate 210 is greater than the thickness of the first insulating layer 151 in the direction perpendicular to the base substrate 210, and the thickness of the second insulating layer 152 in the direction perpendicular to the base substrate 210.
  • the thickness in the direction of the base substrate 210, the thickness of the third insulating layer 160 in the direction perpendicular to the base substrate 210, and the thickness of the fourth insulating layer 113 in the direction perpendicular to the base substrate 210. At least one. In order to enhance the insulating effect of the fourth insulating layer 113, the parasitic capacitance between the data line 1 and the first connection structure CP1 can be better reduced or avoided.
  • the thickness of the fourth insulating layer 113 in the direction perpendicular to the base substrate 210 is a few microns, for example, less than 5 ⁇ m to 10 ⁇ m. This thickness range can achieve a better reduction or avoid the data line 1 and the first connection structure CP1 The effect of the parasitic capacitance between them does not increase the size of the array substrate 100 excessively.
  • the first sub-wiring 21 and the data line 1 are arranged in different layers. Since the adjacent distance between the first sub-wiring 21 and the data line 1 is relatively small, this design can avoid the first sub-wiring. A parasitic capacitance is generated between the line 21 and the data line, so as to prevent the parasitic capacitance from affecting the display effect.
  • the adjacent first sub-wiring 21 and the data line 1 respectively correspond to two adjacent sub-pixels.
  • the orthographic projection of the first connection structure CP1 on the base substrate 210 and the orthographic projection of the data line 1 on the base substrate 210 do not overlap, and the first trace 21 is on the base substrate 210
  • the orthographic projection of and the orthographic projection of the data line 1 on the base substrate 210 do not overlap.
  • the solution of the embodiment of the present disclosure can better prevent the crosstalk between the signals on these signal lines.
  • the materials of the data line 1 and the first connection structure CP1 are both metallic materials.
  • the fourth conductive layer forming the data line 1 adopts a stacked structure Ti/Al/Ti including three layers of metal.
  • Fig. 8C is a schematic cross-sectional view taken along the line B-B' in Fig. 7A.
  • the plurality of sub-pixels includes a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel.
  • FIG. 7A shows two adjacent sub-pixels, the first sub-pixel is the sub-pixel on the left in FIG. 7A, and the second sub-pixel is the sub-pixel on the right in FIG. 7A, that is, the first sub-pixel and the second sub-pixel.
  • the pixels are adjacent in the horizontal direction; of course, in other embodiments, the first sub-pixel and the second sub-pixel may also be adjacent in the vertical direction, and the directions and positions of other structures can be adjusted adaptively.
  • the first reset transistor T4 includes an active layer A4, a gate (the part of GLn-1 that overlaps the active layer A4), a first electrode (for example, a source), and a second Electrode (for example, a drain);
  • the second reset transistor T7 includes an active layer A7, a gate (a portion of the gate line GLn-1 that overlaps the active layer A7), a first electrode (for example, a source), and a second Electrode (e.g. drain).
  • the active layer of the reset transistor of the first reset transistor T4 includes a channel region (a portion of the active layer A4 overlapping the gate line GLn-1) and an electrode region E1.
  • the active layer A7 of the second reset transistor T7 includes a channel region (a portion of the active layer A7 overlapping the gate line GLn-1) and an electrode region E1.
  • the first reset transistor T4 and the second reset transistor T7 share the same electrode region E1.
  • the second connection structure CP2 extends along the first direction R1 and includes a first end and a second end opposite to each other in the first direction R1; the second connection structure CP2 of the pixel circuit of the second sub-pixel is located in the lateral direction R2.
  • One of the channel region of the active layer of the first reset transistor T4 of the pixel circuit of the first sub-pixel and the channel region of the active layer of the second reset transistor T7 is close to one of the data lines 1 of the pixel circuit of the first sub-pixel side.
  • the first end of the second connection structure CP2 is electrically connected to the reset signal line RL through the via hole VH6, and the second end of the second connection structure CP2 is connected to the reset transistor (T4 and T7) of the pixel circuit of the second sub-pixel through the via hole VH7.
  • the electrode area E1 of the active layer is electrically connected.
  • the second connection structure CP2 constitutes the first electrode and the second electrode of the first reset transistor T4 and the second reset transistor T7.
  • the first reset transistor T4 and the second reset transistor T7 of the second sub-pixel of the pixel circuit of the active layer electrode area E1 extends from the first sub-pixel to adjacent to it in the lateral direction
  • the orthographic projection of the first reset transistor T4 and the electrode area E1 of the active layer of the second reset transistor T7 of the pixel circuit of the second sub-pixel on the base substrate and the pixel belonging to the first sub-pixel The orthographic projection of the data line 1 of the circuit on the base substrate at least partially overlaps.
  • the electrode area E1 of the active layer of the first reset transistor T4 and the second reset transistor T7 intersects the data line 1, so as to more fully and flexibly use the limited pixel area, and form the required easy implementation and other structures Connected semiconductor layer pattern. Since the electrode area E1 of the active layer that overlaps the projection of the data line 1 is far from the second conductive layer where the data line 1 is located in the direction perpendicular to the base substrate, the intersection of the two will not interfere with each other. Interference occurs between the signals.
  • FIGS. 7A, 7F, 7J, and 7K three data lines 1 are shown respectively, and the three data lines 1 belong to the pixel circuits of three adjacent sub-pixels; the data line 1 in the middle is The pixel circuit belonging to the first sub-pixel, and the data line 1 on the right side belongs to the pixel circuit of the second sub-pixel.
  • FIG. 9 is a signal timing diagram of the pixel circuit shown in FIG. 6.
  • the working principle of the pixel circuit shown in FIG. 6 will be described below in conjunction with the signal timing diagram shown in FIG. 9.
  • the first emission control line EM1 and the second emission control line EM2 in FIG. 6 are the same common emission control line as an example.
  • the first light-emitting control line EM1 and the second light-emitting control line EM2 may also be different signal lines, respectively, which provide different first light-emitting control signals and second light-emitting control signals.
  • the transistors shown in FIG. 9 are all P-type transistors.
  • the gate of each P-type transistor is turned on when it is connected to a low level, and is turned off when it is connected to a high level.
  • the following embodiments are the same as this, and will not be repeated here.
  • the working process of the pixel circuit includes three stages, namely the reset stage P1, the data writing and compensation stage P2, and the light-emitting stage P3.
  • the figure shows the timing waveform of each signal in each stage.
  • the second gate line Gn-1 provides a reset signal Rst
  • the fourth transistor T4 and the seventh transistor T7 are turned on by the low level of the reset signal
  • the reset signal low level signal, for example, can be grounded or Other low-level signals
  • the reset signal is applied to the N4 node, that is, the light-emitting element 180 is reset, so that the light-emitting element 180 can be displayed in a black state and does not emit light before the light-emitting stage P3 , Improve the display effect such as the contrast of the display device using the pixel circuit.
  • the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off by the high-level signals respectively connected to them.
  • the first gate line GLn provides the scan signal Gn-1
  • the data line DAT provides the data signal Data
  • the second transistor T2 and the third transistor T3 are turned on.
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off by the high-level signals respectively connected to them.
  • the first transistor T1, and the third transistor T3 the first node N1 is charged (that is, the storage capacitor CST is charged), that is, the potential of the first node N1 gradually increases. It is easy to understand that since the second transistor T2 is turned on, the potential of the second node N2 remains at Vdata.
  • Vdata represents the voltage value of the data signal Data
  • Vth represents the threshold voltage of the first transistor T1.
  • the first transistor T1 is described as a P-type transistor, so the threshold here The voltage Vth may be a negative value.
  • the potentials of the first node N1 and the third node N3 are both Vdata+Vth, that is to say, the voltage information with the data signal Data and the threshold voltage Vth is stored in the storage capacitor CST , To provide gray scale display data and compensate the threshold voltage of the first transistor T1 during the subsequent light-emitting stage.
  • the light emitting control line provides the light emitting control signal EM, and the fifth transistor T5 and the sixth transistor T6 are turned on by the low level of the light emitting control signal EM.
  • the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned off when the high level is connected to each of them.
  • the potential of the first node N1 is Vdata+Vth, and the potential of the second node N2 is VDD, so the first transistor T1 is also kept on at this stage.
  • the anode and cathode of the light-emitting element 180 are respectively connected to the first power supply voltage (high voltage) and the second voltage VSS (low voltage) provided by the first power line VDD, so that the light-emitting element 180 is driven by the first transistor T1. Glows under the action of electric current.
  • the display substrate further includes: a third signal line extending along the first direction, including a first portion passing through the peripheral area of the first opening, the area between the openings, and the peripheral area of the second opening, configured to A third display signal is provided to the pixel circuit.
  • the first part of the third signal line is arranged in the same layer as the gate; for example, the third display signal is a light-emitting drive scan signal (EM line).
  • EM line light-emitting drive scan signal
  • the display substrate further includes a second dummy sub-pixel, and the second dummy sub-pixel includes a second dummy pixel circuit as shown in FIG. 16A.
  • the second dummy pixel circuit includes a dummy semiconductor layer, which is provided in the same layer as the active layer, and is electrically connected to the first part of the second sub-wiring, wherein the first part of the third signal line is on the substrate.
  • FIGS. 16A-16F are schematic diagrams of various layers of a second dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure.
  • the inter-opening area 2014 further includes a second dummy sub-pixel, and the second dummy sub-pixel includes a second dummy pixel circuit, as shown in FIG. 16A.
  • the second virtual pixel circuit includes a second compensation capacitor COM10, and the second compensation capacitor COM10 includes a first electrode plate CE10 and a second electrode plate CE20.
  • FIG. 16D shows a structure of the second dummy pixel circuit in the first conductive layer
  • FIG. 16E shows a structure of the second dummy pixel circuit in the second conductive layer.
  • the first electrode plate CE10 of the fourth compensation capacitor COM10 and the first signal line 2301 are arranged on the same layer, for example, are located on the first conductive layer, and the fourth compensation capacitor COM10
  • the first electrode plate CE10 is electrically connected to the first signal line 2301.
  • the orthographic projection of the first signal line 2301 on the base substrate 210 and the orthographic projection of the second electrode plate CE20 of the fourth compensation capacitor COM10 on the base substrate 210 at least partially overlap.
  • the first pole CE10 board of the fourth compensation capacitor COM10 includes: a second body portion CE100 and a third extension portion CE101.
  • the second body portion CE100 is located on the first side of the first signal line 2301 in the second direction R2; the third extension portion CE101 extends from the second body portion CE100 in the second direction R2 toward the first signal line 2301, and is located in the second direction R2.
  • a signal line 2301 is on the first side in the second direction and is located between the second body part CE100 and the first signal line 2301, and the second body part CE100 is electrically connected to the first signal line 2301 through the third extension part CE101 .
  • the first pole CE20 board of the fourth compensation capacitor COM10 includes a fourth extension portion CE102, which extends from the first signal line 2301 toward a direction away from the second body portion CE100, and is located at the end of the first signal line 2301.
  • the second side in the second direction R2 is electrically connected to the first signal line 2301, and the second side of the first signal line 2301 is opposite to the first side of the first signal line 2301, thereby further increasing the fourth compensation capacitor COM10 If the area of the first electrode plate CE10 is increased at the same time as the area of the second electrode plate of the fourth compensation capacitor COM10, the fourth compensation capacitor COM10 can be further increased to meet the requirements for different compensation levels of the first signal line.
  • the second body portion CE100, the third extension portion CE101, the first signal line 2301, and the fourth extension portion CE102 are integrally formed, so that these structures can be formed by the same patterning process, simplifying the manufacturing process of the display substrate.
  • the second electrode plate CE20 of the fourth compensation capacitor COM10 includes a third body portion CE200 and a fifth extension portion CE201.
  • the third body portion CE200 is located on the first side of the first signal line 2301 in the second direction R2; the fifth extension portion CE201 extends from the third body portion CE200 in the second direction R2 toward the first signal line 2301, the first The orthographic projection of the signal line 2301 on the base substrate 210 and the orthographic projection of the fifth extension portion CE201 on the base substrate 210 at least partially overlap.
  • the orthographic projection of the first plate CE10 of the fourth compensation capacitor COM10 on the base substrate 210 is located on the front of the second plate CE20 of the fourth compensation capacitor COM10 on the base substrate 210.
  • a limited space is used to form the required size of the fourth compensation capacitor.
  • a part 7921 of the second electrode plate CE20 of the fourth compensation capacitor COM10 may be the same as the position and pattern of the light shielding part in the pixel circuit of the display area to maintain uniformity of etching.
  • the second dummy sub-pixel includes a second dummy semiconductor layer, and the second dummy semiconductor layer is located on a side of the first plate of the fourth compensation capacitor close to the base substrate.
  • FIG. 16C shows the pattern of the second virtual sub-pixel, and the second virtual sub-pixel is the virtual sub-pixel A02 on the right side in FIG. 16C. As shown in conjunction with FIGS.
  • the second virtual semiconductor layer includes a first portion AP21 and a second portion AP22 spaced apart so as not to be connected to each other; the first portion AP21 is located on the first side of the first signal line 2301, and the second portion AP22 is located The second side of the first signal line 2301; the orthographic projection of the first signal line 2301 on the base substrate 210 and the orthographic projection of the first dummy semiconductor layer on the base substrate 210 do not overlap, so that the second dummy pixel circuit is not There are real thin film transistors that do not realize the display function. For example, the orthographic projection of the fourth compensation capacitor COM10 on the base substrate 210 and the orthographic projection of the first virtual semiconductor layer on the base substrate do not overlap.
  • FIG. 16F shows the structure of the second dummy pixel circuit on the third conductive layer.
  • the second dummy pixel circuit includes a second transfer electrode CP10, the second transfer electrode CP10 and the first transfer electrode of the first dummy pixel circuit, and pixels in the display area
  • the first connection portion CP1 of the circuit is arranged in the same layer, for example, they are all located on the third conductive layer, and are electrically connected to the second electrode plate CE20 of the fourth compensation capacitor COM10, for example, the second transfer electrode CP10 passes through the via hole VH40 and the via hole
  • the VH50 is electrically connected to the second plate CE20 of the fourth compensation capacitor COM10 to maintain the etching uniformity between this and other positions such as the display area of the display substrate.
  • the second plate CE20 of the fourth compensation capacitor COM10 is connected to the first power supply line VDD through the via hole VH40 and the via hole VH50, for example, with the first line of the first power supply line VDD.
  • the line 2424 is connected to provide the first power voltage to the second plate CE20 of the fourth compensation capacitor COM10 to form the fourth compensation capacitor COM10.
  • the second part AP22 of the second dummy semiconductor layer is configured to be sent an electrical signal through the second dummy pixel circuit;
  • the first part AP21 of the first dummy semiconductor layer has a first end P21 and a
  • the second terminal P22 and the second terminal P22 are configured to be sent the electrical signal through the second dummy pixel circuit.
  • the first terminal P21 is connected to the second terminal P22, so that the electrical signal from the second terminal P2 can be transmitted to the first terminal P2.
  • the terminal P21 prevents signal drift caused by no signal input at the first terminal P21. For example, as shown in FIG.
  • the second terminal P22 is electrically connected to the second sub-wiring 2424 of the first power line VDD, for example, through the via hole VH20, thereby connecting the second sub-wiring from the first power line VDD.
  • the first power supply voltage of 2424 is transmitted to the second terminal P22 and the first terminal P21.
  • the structure of the first power supply line VDD is not limited to those shown in FIGS. 16A-16F, as long as the first power supply line VDD is connected to the second terminal P22.
  • the orthographic projection of the first portion of the third signal line, such as the light-emitting scan signal line EM, on the base substrate 210 and the orthographic projection of the dummy semiconductor layer on the base substrate 210 at least partially overlap to form
  • the third compensation capacitor is used to compensate the load of the third signal line to obtain a more uniform display effect.
  • the second virtual pixel structure is not limited to the situation shown in FIGS. 16A-16F.
  • the data lines are in the same layer as the source and drain 122/123.
  • the dummy semiconductor layer can also be arranged to overlap the third signal line, such as the light-emitting scanning signal line EM, to form a third compensation capacitor.
  • the embodiment of the present disclosure does not limit this.
  • the second opening area 202B and the first opening area 202A are arranged along the first direction R1, so that the inter-opening area 2014 is located in the first opening area in the first direction R1 Between 202A and the second opening area 202B.
  • the first display area 2011 is located on the side of the first opening area 202A away from the inter-opening area 2014
  • the second display area 2012 is located on the side of the second opening area 202B away from the inter-opening area 2014.
  • the first display area 2011 is located on the first side of the first opening area 202A
  • the second display area 2012 is located on the second side of the second opening area 201B.
  • the first display area, the first opening area, the inter-opening area, the second opening area, and the second display area are sequentially arranged along the first direction.
  • the first opening area 202A and the second opening area 201B respectively, it is still satisfied that the first display area 2011 is located on the first side of the first opening area 202A, and the second display area 2012 is located on the second side of the first opening area 202A, The first side and the second side are opposite to each other in the first direction R1.
  • the first signal line 23 sequentially passes through the first display area 2011, the first opening peripheral area 203A, the inter-opening area 2014, the second opening peripheral area 203B, and the second display area 2012 along the first direction R1.
  • the first signal line 2301 includes a first lead portion E1A1/E2A2 located in the peripheral area 203A of the first opening (ie, taking a first signal line as an example, for example, the first lead portion is the straight line in FIG. 2B
  • the section E1A1 and the straight section E2A2 and the lateral winding portion A1A2 located in the first opening peripheral area 203A that is, the lateral winding portion is the curved section A1A2 in FIG. 2B
  • the lateral winding portion A1A2 is partially arranged around the first opening 201A.
  • the second signal line 24 is configured to provide a second display signal to the first pixel array, and passes through the first opening peripheral area 203A in a second direction R2 that intersects the first direction R1, and includes a longitudinal winding located in the first opening peripheral area 203A.
  • the line part C1C2, that is, the longitudinal winding part is the curved section C1C2 in FIG. 2B; the longitudinal winding part C1C2 is partially arranged around the first opening 201A.
  • the orthographic projection of the first lead portion E1A1/E2A2 on the base substrate and the orthographic projection of the second signal line 24 on the base substrate respectively have a first overlap area S1/S2, that is, an area where the two intersect.
  • the orthographic projection of the horizontal winding portion A1A2 on the base substrate and the orthographic projection of the longitudinal winding portion C1C2 on the base substrate have a second overlap area.
  • the two overlap in the A1C1 section and the D1A2 section, and the second overlap area is The area represented by A1C1 and D1A2.
  • a compensation capacitor is formed between the first signal line 2301 and the second signal line 24 that overlap each other in a direction perpendicular to the base substrate, thereby compensating for the first signal line Therefore, the display difference caused by the different loads of the first signal lines connecting the pixels of different rows due to the different numbers of pixels in different rows of the pixels in the first pixel array is reduced, so that the first display area 2011 and the second display
  • the display effect of the area 2012 is consistent with the display effect of the pixel rows in the display area 201 where the first opening area 202A is not provided, and the display quality is improved.
  • the above wiring method can also reduce the arrangement space of the first signal line and the second signal line, and reduce the area occupied by the peripheral area 203A of the first opening as much as possible. Therefore, for example, when the under-screen camera function is implemented through the first opening area 202A, the influence of the first opening area 202A on the display effect of the area is reduced, or, in other embodiments, when the first opening peripheral area 203A is located in the frame area 204 In the middle, the width of the frame area 204 can also be reduced, thereby helping to achieve a narrow frame and large-screen design of the display substrate 20. For example, as shown in FIG.
  • the orthographic projection of the lead portion E1A1 of the first signal line 2301 on the base substrate and the orthographic projection of the longitudinal winding portion of the second signal line 24 on the base substrate have a first overlap area. That is, each of the plurality of first signal lines sequentially passes through the first display area, the first opening peripheral area, and the second display area along the first direction, and includes A first lead part and a lateral winding part in the peripheral area of the first opening, the lateral winding part is partially arranged around the first opening, and the first lead part is connected to the lateral winding part; the plurality of The orthographic projection of the lateral winding portion of the first signal line on the base substrate overlaps with the orthographic projection of the longitudinal winding portion of the plurality of second signal lines on the base substrate, respectively Area.
  • FIG. 17 is a schematic plan view of a second virtual pixel circuit in a second virtual sub-pixel in a display substrate according to an embodiment of the present disclosure.
  • the main difference between FIG. 17 and FIG. 16A is that the data line DATA is located on the side of the source and drain electrodes 122/123 away from the base substrate, and the relative position of the data line DATA and the first power line VDD in the first direction is different. Refer to Figure 16A for other structures.
  • FIG. 10A is an enlarged schematic diagram of a first opening area of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate further includes first floating electrodes 41/42.
  • the longitudinal winding part closest to the first opening 201A is the edge longitudinal winding part 2401/2402
  • the first floating electrodes 41/42 are arranged in the same layer as the edge longitudinal winding part And it is located on the side of the edge longitudinal winding portion 2401/2402 close to the first opening 201A.
  • the first floating electrodes 41/42 are arranged in the same layer as the edge longitudinal winding part and are located on the side of the edge longitudinal winding part 2401/2402 close to the first opening 201A, thereby avoiding the edge longitudinal winding part
  • the difference in etchability increases the uniformity of etching.
  • the first floating electrode is not loaded with any electrical signal and will not cause interference to other signal lines around it.
  • the plurality of pixels includes a first pixel column and a second pixel column respectively extending in a second direction R2;
  • the first opening 201A has a first side and a second pixel column opposite to each other in the first direction R2.
  • the display substrate includes two edge longitudinal winding portions corresponding to the first opening 201A, and the two edge longitudinal winding portions include: an edge longitudinal winding portion configured to provide a second display signal to the first pixel column, and The edge longitudinal winding portion of the pixel column providing the second display signal partially surrounds the first opening on the first side of the first opening; an edge configured to provide the second display signal to the second pixel column
  • the longitudinal winding part, the edge longitudinal winding part that provides the second display signal to the second pixel column partially surrounds the first opening on the second side of the first opening;
  • the first floating electrode includes: a first part 41 and a first part 41 Two part 42.
  • the first part 41 is located at the side of the edge longitudinal winding part that provides the second display signal to the first pixel column near the first opening 201A; the second part 42 is located at the edge longitudinal winding that provides the second display signal to the second pixel column The side of the part close to the first opening 201A.
  • the line width and extension direction of the first floating electrode and the longitudinal winding portion of the edge are substantially the same, so as to further increase the etching uniformity of the longitudinal winding portion of the engraved edge.
  • first interval between two adjacent second signal lines in the plurality of second signal lines for example, there is a first interval between the longitudinal winding portions of two adjacent second signal lines, and the first floating
  • the interval between the electrode and the edge longitudinal winding part is substantially equal to the first interval, so as to further increase the etching uniformity of the edge longitudinal winding part.
  • the first portion 41 of the first floating electrode and the second portion 42 of the first floating electrode are spaced apart from each other.
  • the first part 41 of the first floating electrode and the second part of the first floating electrode are integrally formed.
  • the overall planar shape formed by the first part 41 of the first floating electrode and the second part 42 of the first floating electrode is an unclosed ring surrounding the first opening 201A.
  • the opening in the ring can better release the accumulated charges and avoid signal interference to the surrounding signal lines.
  • the overall planar shape formed by the first part 41 of the first floating electrode and the second part 42 of the first floating electrode may also be a closed ring.
  • the display substrate further includes a second floating electrode.
  • the lateral winding portion closest to the first opening 201A is the edge lateral winding portion, and the second floating electrode is transverse to the edge.
  • the winding part is arranged in the same layer and is arranged in a different layer from the first floating electrode.
  • the second floating electrode is located on the side of the edge transverse winding part close to the first opening.
  • the second floating electrode is located on the base substrate 210.
  • the projection and the orthographic projection of the first floating electrode on the base substrate 210 have an overlapping area, thereby avoiding the difference in the etching properties of the lateral winding portion of the edge and increasing the etching uniformity.
  • the line width and extension direction of the second floating electrode and the edge lateral winding part are basically the same, so as to further increase the etching uniformity of the edge lateral winding part.
  • the interval between the electrode and the edge lateral winding part is substantially equal to the second interval, so as to further increase the etching uniformity of the edge lateral winding part.
  • the first signal line includes a plurality of gate scan signal lines and a plurality of reset signal lines.
  • the gate scan signal line 2303A (in this case, the part is the first part 2303A of the gate scan signal line) and the reset signal line 2301A (in this case, the part is the first part 2301A of the gate scan signal line)
  • the lateral winding portions 2303A-1 of the gate scanning signal line 2303A and the lateral winding portions 2301A-1 of the reset signal line 2301A are alternately arranged in the second direction.
  • the gate scan signal line 2303A of the plurality of gate scan signal lines 2303A closest to the first opening 201A is the edge gate scan signal line 2303A-0
  • the reset signal line of the plurality of reset signal lines 2301A closest to the first opening 201A is the edge reset Signal line 2301A-0.
  • the second floating electrode includes: a first sub floating electrode 511 and a second sub floating electrode 512.
  • the first sub-floating electrode 511 is arranged in the same layer as the gate scanning signal line and is located on the side of the edge gate scanning signal line 2303A close to the first opening 201A; the second sub-floating electrode 512 is arranged in the same layer as the reset signal line 2301A-0 And located on the side of the edge reset signal line 2301A-0 close to the first opening 201A; the edge gate scanning signal line 2303A-0 is farther from the first opening 201A than the edge reset signal line 2301A-0, and the first sub floating electrode 511 is larger than the first opening 201A.
  • the two sub-floating electrodes 512 are far away from the first opening 201A, and the orthographic projection of the first floating electrode on the base substrate at least overlaps with the first sub-floating electrode, which can solve the problem of the edge reset signal line 2301A-0 and the edge
  • the etching uniformity of the reset signal line 2301A-0 is problematic.
  • the edge reset signal line 2301A-0 is farther from the first opening 201A than the edge gate scan signal line 2303A-0
  • the second sub floating electrode 512 is farther from the first opening 201A than the first sub floating electrode 511
  • the first floating electrode The orthographic projection on the base substrate at least has an overlap area with the second sub-floating electrode, which can also solve the problem of the etching uniformity of the edge reset signal line 2301A-0 and the edge reset signal line 2301A-0.
  • the part of the plurality of second signal lines includes a first part of the second signal line 2410 and a second part of the second signal line 2412, and the first part of the second signal line 2410 is connected to the
  • the second part of the second signal lines 2412 are arranged in different layers and alternately arranged in the first direction. Please refer to the previous description for the layer on which they are located.
  • the second signal line closest to the first opening in the first part of the second signal line 2410 is the edge first sub-data signal line
  • the second signal line closest to the first opening in the second part of the second signal line 2412 is the edge
  • the orthographic projection on the substrate has an overlapping area, and the orthographic projection of the longitudinal winding portion of each second signal line in the second part of the second signal line on the base substrate is the same as the lateral winding of each reset signal line.
  • the orthographic projection of the line portion on the base substrate has an overlapping area;
  • the first floating electrode includes: a third sub-floating electrode 411 and a fourth sub-floating electrode 412.
  • the third sub-floating electrode 411 is arranged in the same layer as the first part of the second signal line 2410 and is located on the edge of the first sub-data signal line on the side close to the first opening;
  • the fourth sub-floating electrode 412 is the same as the second part of the second signal line
  • the line 2412 is arranged in the same layer and is located on the side of the second sub-data signal line of the edge close to the first opening 201A;
  • the orthographic projection of the third sub-floating electrode 411 on the base substrate has an overlapping area with the first sub-floating electrode 511 ,
  • the orthographic projection of the fourth sub-floating electrode 412 on the base substrate and the second sub-floating electrode 512 have an overlapping area.
  • the first part of the second signal line 2410 (here, the longitudinal winding part) is arranged on the same layer as the source and drain 122/123, and the second part of the second signal line 2412 (here, the longitudinal winding part) is located at
  • the first part of the second signal line 2410 is on the side away from the base substrate; multiple gate scan signal lines are arranged on the same layer as the second plate of the storage capacitor, and multiple reset signal lines are connected to the first electrode of the storage capacitor CST.
  • the plate CE1 is arranged in the same layer; or, the multiple gate scan signal lines are arranged in the same layer as the first plate CE1 of the storage capacitor CST, and the multiple reset signal lines are arranged on the same layer as the second plate CE1 of the storage capacitor CST.
  • CE2 is set at the same layer.
  • the gate scan signal line and the reset signal line are both wound at the first opening, instead of being disconnected at the first opening.
  • the plurality of first signal lines include a plurality of gate scan signal lines and a plurality of reset signal lines, and the gate scan signal lines and the reset signal lines are arranged in different layers; each The gate scan signal line sequentially passes through the first display area, the first opening peripheral area, and the second display area along the first direction, and includes a first lead portion located in the first opening peripheral area And a lateral winding part, wherein the lateral winding part is partially arranged around the first opening, and the first lead part is connected to the lateral winding part; each of the reset signal lines includes: a first part And the second part.
  • the first part passes through the first display area in the first direction; the second part passes through the second display area in the first direction, and is separated from the first part by the first opening area. That is, the gate scan signal line is wound at the first opening, and the reset signal line is disconnected at the first opening.
  • the plurality of first signal lines include a plurality of gate scan signal lines and a plurality of reset signal lines, and the gate scan signal lines and the reset signal lines are arranged in different layers; each The reset signal line sequentially passes through the first display area, the first opening peripheral area, and the second display area along the first direction, and includes a first lead part and a first lead located in the first opening peripheral area.
  • the lateral winding part wherein the lateral winding part is partially arranged around the first opening, and the first lead part is connected to the lateral winding part; each of the gate scan signal lines includes: a first part And the second part.
  • the first portion passes through the first display area along the first direction; the second portion passes through the second display area along the first direction, and is separated from the first portion by the first opening area . That is, the reset signal line is wound at the first opening, and the gate scan signal line is disconnected at the first opening.
  • the plurality of first signal lines include a plurality of gate scan signal lines and a plurality of reset signal lines, and the gate scan signal lines and the reset signal lines are arranged in different layers; each The gate scan signal line includes: a first part and a second part. The first portion passes through the first display area along the first direction; the second portion passes through the second display area along the first direction, and is separated from the first portion by the first opening area And, each of the reset signal lines includes: a first part and a second part, the first part passes through the first display area in the first direction; the second part passes through the first display area in the first direction The second display area is separated from the first portion by the first opening area. That is, the gate scan signal line and the reset signal line are both disconnected at the first opening.
  • a bilateral drive method can be adopted to load the disconnected signal lines with drive signals from both sides of the substrate in the first direction.
  • a bilateral drive method can be adopted to load the disconnected signal lines with drive signals from both sides of the substrate in the first direction.
  • the display substrate may further include outer floating electrodes.
  • the longitudinal winding part farthest from the first opening among the longitudinal winding parts of the portion of the plurality of second signal lines is an outer edge longitudinal winding part, and the outer floating electrode is longitudinally connected to the outer edge.
  • the winding part is arranged in the same layer and is located on a side of the outer edge longitudinal winding part away from the first opening, so as to increase the etching uniformity of the outer longitudinal winding part.
  • each of the portions of the plurality of second signal lines further includes a second lead part.
  • the second lead part extends along the second direction and is connected to the longitudinal winding part.
  • the arrangement density of the second lead part is greater than the arrangement density of the longitudinal winding part.
  • the line width of the second lead part is substantially equal to the line width of the longitudinal winding part. Due to the difference in arrangement density and the limitation of the etching process, the design line width of the second lead part is made smaller than the longitudinal direction in the manufacturing process.
  • the design line width of the winding part can make the final line width of the two formed basically equal. Or, if the difference in the design line width is not made, the line width of the second lead part is smaller than the line width of the longitudinal winding part.
  • At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
  • the display device may be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other devices with display functions or other types of devices, which are not limited in the embodiments of the present disclosure.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display function such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

一种显示基板以及显示装置。该显示基板中，第一开口区域包括第一开口和围绕第一开口的第一开口周边区域；第二开口区域与第一开口区域相邻，且包括第二开口和围绕第二开口的第二开口周边区域；开口间区域位于第一开口区域和第二开口区域之间，开口间区域、第一开口周边区域和第二开口周边区域中至少一者包括第一虚拟子像素；显示区域至少部分围绕第一开口区域、第二开口区域和开口间区域且包括子像素。第一信号线沿第一方向延伸，包括穿过第一开口周边区域、开口间区域和第二开口周边区域的第一部分；第一部分穿过第一虚拟子像素，第一虚拟子像素包括第一补偿电容，其第一极板与第一信号线的第一部分同层且电连接，且与存储电容的第二极板同层；第二极板与第一补偿电容的第一极板异层且绝缘，第一补偿电容的第二极板与第一补偿电容的第一极板至少部分重叠。

Description

显示基板以及显示装置
本申请要求于2020年06月05日递交的中国专利申请第202010507064.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板以及显示装置。
背景技术
目前，显示器件的显示屏正往大屏化、全屏化方向发展。通常，显示器件(例如手机、平板电脑等)具有摄像装置(或成像装置)，该摄像装置通常设置在显示屏的显示区域外的一侧。但是，由于摄像装置的安装需要占据一定的边框位置，因此不利于显示屏的全屏化、窄边框设计。例如，可以将摄像装置与显示屏的显示区域结合、重叠在一起，在显示区域中为摄像装置预留位置，以获得显示屏显示区域的最大化。
发明内容
本公开至少一实施例提供了一种显示基板，该显示基板包括衬底基板、第一开口区域、第二开口区域、开口间区域、显示区域和第一信号线。第一开口区域包括第一开口和围绕所述第一开口的第一开口周边区域；第二开口区域与所述第一开口区域沿所述第一方向相邻设置，且包括第二开口和围绕所述第二开口的第二开口周边区域；开口间区域位于所述第一开口区域和所述第二开口区域之间，所述开口间区域、所述第一开口周边区域和所述第二开口周边区域三者中的至少一者包括第一虚拟子像素；显示区域至少部分围绕所述第一开口区域、所述第二开口区域和所述开口间区域，且包括多个像素，每个所述像素包括多个子像素，每个所述子像素包括像素电路，所述像素电路包括：晶体管、发光元件和存储电容，包括有源层、栅极和源漏极； 发光元件与所述晶体管的源漏极之一连接；存储电容包括第一极板和第二极板，所述栅极、所述存储电容的第一极板同层设置；第一信号线沿第一方向延伸，包括穿过所述第一开口周边区域、所述开口间区域和所述第二开口周边区域的第一部分，配置为给所述像素电路提供第一显示信号；所述第一信号线的第一部分穿过所述第一虚拟子像素，所述第一虚拟子像素包括虚拟像素电路，所述虚拟像素电路包括第一补偿电容，所述第一补偿电容包括：第一极板和第二极板。第一极板与所述第一信号线的第一部分同层设置且与第一信号线电连接，且与所述存储电容的第二极板同层设置；第二极板与所述第一补偿电容的第一极板异层设置且绝缘，其中，所述第一补偿电容的第二极板在所述衬底基板上的正投影与所述第一补偿电容的第一极板在所述衬底基板上的正投影至少部分重叠。
本公开至少一实施例还提供一种显示基板，该显示基板包括衬底基板，衬底基板包括：第一开口区域、显示区域、多条第一信号线、多条第二信号线和第一浮置电极。第一开口区域包括第一开口和围绕所述第一开口的第一开口周边区域；显示区域至少部分围绕所述第一开口区域，包括：第一显示区域，位于所述第一开口区域的第一侧；以及第二显示区域，位于所述第一开口区域的第二侧，其中，所述第一侧与所述第二侧在第一方向上彼此相对，所述第一显示区域和所述第二显示区域包括多个像素；多条第一信号线配置为给所述多个像素提供第一显示信号，沿所述第一方向延伸且穿过所述第一显示区域和所述第二显示区域；多条第二信号线配置为给所述多个像素提供第二显示信号，沿与所述第一方向相交的第二方向延伸，所述多条第二信号线的部分沿所述第二方向穿过所述第一开口周边区域，所述多条第二信号线的所述部分中的每条第二信号线包括位于所述第一开口周边区域的纵向绕线部，其中，所述纵向绕线部部分地围绕所述第一开口设置；所述多条第二信号线的纵向绕线部中最靠近所述第一开口的纵向绕线部为边缘纵向绕线部，所述第一浮置电极与所述边缘纵向绕线部同层设置且位于所述边缘纵向绕线部的靠近所述第一开口的一侧。
本公开至少一实施例提供一种显示装置，包括上述任一的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板的平面示意图；
图2A为本公开一实施例提供的一种显示基板的平面示意图；
图2B为图2A中包括第一开口区域和第二开口区域的局部放大示意图；
图2C为图2A中包括第一开口区域和开口间区域的局部放大示意图；
图3A为显示基板的显示区域中的子像素的一种截面示意图；
图3B为显示基板的显示区域中的子像素的另一种截面示意图；
图4A为本公开一实施例提供的一种显示基板中的第一虚拟像素电路的平面布局示意图；
图4B为沿图4A中的A2-B2线的截面示意图；
图4C-4G为本公开一实施例提供的一种显示基板的第一虚拟像素电路的各层的示意图；
图4H为本公开一实施例提供的另一种显示基板的第一补偿电容的第一极板的示意图；
图4I为沿图4A中的A3-B3线的截面示意图；
图4J是显示基板的局部图；
图5A为图2C中的局部C的放大示意图；
图5B为图2C中的局部D的放大示意图；
图5C为图2C中的局部E的放大示意图；
图5D为图2C中的局部F的放大示意图；
图5E为第一信号线和第二信号线进行换层的区域的放大示意图；
图5F-5H分别为沿图5E中的A4-B4线、A5-B5线和A6-B6线的截面示意图；
图6为本公开一实施例提供的一种阵列基板中的像素电路的等效电路图；
图7A为本公开一实施例提供的一种阵列基板中的像素电路的平面布局 示意图；
图7B-图7K为本公开一实施例提供的一种阵列基板的像素电路的各层的示意图；
图8A为沿图7A中的A-A’线的一种截面示意图；
图8B为沿图7A中的B-B’线的一种截面示意图；
图9是图6所示的像素电路的工作过程的信号时序图；
图10A是本公开一实施例提供的一种显示基板的第一开口区域的放大示意图；
图10B是本公开一实施例提供的另一种显示基板的第一开口区域的放大示意图；
图10C是本公开一实施例提供的另一种显示基板的第一开口区域的放大示意图；
图11是图10A中的局部H的放大示意图；
图12是图11中的局部G的放大示意图；
图13是图16中的局部I的放大示意图；
图14是图13中的局部J的放大示意图；
图15为本公开实施例的又一种显示基板的平面示意图；
图16A为本公开一实施例提供的一种显示基板中的一个第二虚拟子像素中的第二虚拟像素电路的平面布局示意图；
图16B为沿图16A中的A3-B3线的截面示意图；
图16C-图16F为本公开一实施例提供的一种显示基板的第二虚拟像素电路的各层的示意图；
图17为本公开一实施例提供的一种显示基板中的一个第二虚拟子像素中的第二虚拟像素电路的平面布局示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描 述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在下面的描述中，当提及两个或更多部件“一体成型”时，表示这些部件通过至少同一原料层形成，例如通过对同一膜层进行同一次构图工艺形成，由此彼此之间不存在界面而是连续的。
图1为一种显示基板的平面示意图。如图1所示，该显示基板10包括显示区域101和围绕显示区域101的周边区域102，显示区域101被设计为例如在至少一侧具有凹口103的不规则形状，该显示基板10可以在凹口103的区域中布置例如摄像头、距离传感器等器件，由此有助于实现显示基板10的窄边框设计。
如图1所示，显示区域101包括位于凹口103的左右两侧的第一显示区域1011和第二显示区域1012，第一显示区域1011与和第二显示区域1012相对于显示区域101的底边(图中下侧边缘)处于相同的水平位置，例如由图中相同的左右水平延伸的一条或多条扫描信号线(栅线)驱动。当然，在其他一些实施例中，第一显示区域与第二显示区域也可以处于不同的水平位置，例如当采用该显示基板的显示屏为异形(非矩形或非类似矩形)显示屏时，在异形屏中，例如第一显示区域与第二显示区域沿显示屏地弯曲的边缘排布，则第一显示区域与第二显示区域未必在同一水平位置。由于凹口103的存在，位于第一显示区域1011与和第二显示区域1012中的同一行像素的 像素数量，比除了第一显示区域1011与和第二显示区域1012外的显示区域101中其他部分(例如图1中的中部)的一行像素的像素数量少。因此，在该显示基板10中，对于水平延伸的用于为第一显示区域1011与和第二显示区域1012中的同一行像素提供显示信号(例如扫描信号)的信号线所连接的像素数量，与用于为除了第一显示区域1011与和第二显示区域1012外的显示区域101中其他部分的一行像素提供电信号(例如扫描信号)的信号线所连接的像素数量不同，并且在凹口103为不规则形状(例如梯形、水滴形等)时，第一显示区域1011和第二显示区域1012中不同行像素的像素数量也可能不同。因此，在该显示基板10中，由于不同行像素的像素数量不同，导致连接不同行像素的信号线的负载不同，进而这些信号线传输信号的速度不同，实际的显示信号与设计值之间的偏差不同，这会影响显示基板的显示效果。
例如，可以对这些负载不同的信号线进行负载补偿，以使这些信号线的负载基本相同，从而减小由于设置凹口103对显示质量的不利影响。
本公开至少一实施例提供了一种显示基板，该显示基板包括衬底基板、第一开口区域、第二开口区域、开口间区域、显示区域和第一信号线。第一开口区域包括第一开口和围绕所述第一开口的第一开口周边区域；第二开口区域与所述第一开口区域沿所述第一方向相邻设置，且包括第二开口和围绕所述第二开口的第二开口周边区域；开口间区域位于所述第一开口区域和所述第二开口区域之间，所述开口间区域、所述第一开口周边区域和所述第二开口周边区域三者中的至少一者包括第一虚拟子像素；显示区域至少部分围绕所述第一开口区域、所述第二开口区域和所述开口间区域，且包括多个像素，每个所述像素包括多个子像素，每个所述子像素包括像素电路，所述像素电路包括：晶体管、发光元件和存储电容，包括有源层、栅极和源漏极；发光元件与所述晶体管的源漏极之一连接；存储电容包括第一极板和第二极板，所述栅极、所述存储电容的第一极板同层设置；第一信号线沿第一方向延伸，包括穿过所述第一开口周边区域、所述开口间区域和所述第二开口周边区域的第一部分，配置为给所述像素电路提供第一显示信号；所述第一信号线的第一部分穿过所述第一虚拟子像素，所述第一虚拟子像素包括虚拟像素电路，所述虚拟像素电路包括第一补偿电容，所述第一补偿电容包括：第 一极板和第二极板。第一极板与所述第一信号线的第一部分同层设置且与第一信号线电连接，且与所述存储电容的第二极板同层设置；第二极板与所述第一补偿电容的第一极板异层设置且绝缘，其中，所述第一补偿电容的第二极板在所述衬底基板上的正投影与所述第一补偿电容的第一极板在所述衬底基板上的正投影至少部分重叠。
本公开至少一实施例还提供一种显示基板，该显示基板包括衬底基板，衬底基板包括：第一开口区域、显示区域、多条第一信号线、多条第二信号线和第一浮置电极。第一开口区域包括第一开口和围绕所述第一开口的第一开口周边区域；显示区域至少部分围绕所述第一开口区域，包括：第一显示区域，位于所述第一开口区域的第一侧；以及第二显示区域，位于所述第一开口区域的第二侧，其中，所述第一侧与所述第二侧在第一方向上彼此相对，所述第一显示区域和所述第二显示区域包括多个像素；多条第一信号线配置为给所述多个像素提供第一显示信号，沿所述第一方向延伸且穿过所述第一显示区域和所述第二显示区域；多条第二信号线配置为给所述多个像素提供第二显示信号，沿与所述第一方向相交的第二方向延伸，所述多条第二信号线的部分沿所述第二方向穿过所述第一开口周边区域，所述多条第二信号线的所述部分中的每条第二信号线包括位于所述第一开口周边区域的纵向绕线部，其中，所述纵向绕线部部分地围绕所述第一开口设置；所述多条第二信号线的纵向绕线部中最靠近所述第一开口的纵向绕线部为边缘纵向绕线部，所述第一浮置电极与所述边缘纵向绕线部同层设置且位于所述边缘纵向绕线部的靠近所述第一开口的一侧。
下面通过几个具体的实施例对本公开进行说明。为了保持本发明实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本发明实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同的参考标号表示。
图2A为本公开实施例的一种显示基板的平面示意图，图2B为图2A中包括第一开口区域和第二开口区域的局部放大示意图。
如图2A和图2B所示，显示基板20包括衬底基板，衬底基板包括第一开口区域202A、第二开口区域202B、开口间区域2014、显示区域201和第一信号线23。第一开口区域202A包括第一开口201A和围绕第一开口201A 的第一开口周边区域203A；第二开口区域202B与第一开口区域202A沿第一方向R1相邻设置，且包括第二开口201B和围绕第二开口201B的第二开口周边区域203B。开口间区域2014位于第一开口区域202A和第二开口区域202B之间。显示区域201至少部分围绕第一开口区域202A、第二开口区域202B和开口间区域2014，且包括多个像素，每个像素包括多个子像素，每个所述子像素包括像素电路。如图2B所示，第一信号线23沿第一方向R1延伸，包括穿过第一开口周边区域202A、开口间区域2014和第二开口周边区域203B的第一部分，配置为给像素电路提供第一显示信号。
例如，在图2A和图2B所示的实施例中，第二开口区域202B与第一开口区域202A沿第一方向R1排列，由此，开口间区域2014在第一方向R1上位于第一开口区域202A和第二开口区域202B之间。当然，在其他实施例中，第二开口区域202B也可以与第一开口区域202A沿第二方向R2排列，此时，开口间区域2014在第二方向R2上位于第一开口区域202A和第二开口区域202B之间。本公开实施例对第二开口区域202B与第一开口区域202A的排列方向不做限定。
显示区域201包括阵列排布的像素，每个像素包括一个或多个子像素，还包括用于向子像素传输各种电信号的各种信号线，以用于实现显示功能；边框区204包括各种驱动电路、电连接子像素的信号线、接触垫等，边框区204的信号线与显示区域201中的信号线(例如栅线、数据线等)电连接(或一体形成)以为子像素提供电信号(例如扫描信号、数据信号等)。
例如第一开口201A设置来允许来自显示基板的显示侧的光通过以到达摄像头、距离传感器，以实现光感应，从而实现图像拍摄、距离感应等功能；例如，第一开口201A所对应的区域中，在显示基板背侧(即与显示侧相对的一侧)可设置摄像头、距离传感器等器件，摄像头、距离传感器等至少部分通过第一开口201A暴露。
例如来自边框区204的各种信号线延伸穿过显示区域201，当遇到第一开口区域201A时，这些信号线穿过第一开口周边区域203A而绕过第一开口201A，然后再进入显示区域201中，以给途经的子像素提供电信号(例如扫描信号、数据信号等)，由此，可不在第一开口201A中设置这些信号线， 以增大第一开口201A的光透过率。
显示区域201包括第一显示区域2011和第二显示区域2012。第一显示区域2011位于第一开口区域202A的第一侧，第二显示区域2012位于第一开口区域202A的第二侧，该第一侧与该第二侧在第一方向R1(图中的水平方向)上彼此相对。例如，第一显示区域2011、第一开口周边区域203A和第二显示区域2012沿第一方向R1依次排列。第一显示区域2011和第二显示区域2012构成的整体包括第一像素阵列。例如，第一像素阵列包括多个呈阵列排布的像素，每个像素包括多个子像素，每个子像素包括像素电路。
以图2B中的第一信号线2301为例，例如显示基板包括多条第一信号线2301/2302/2303/2304/2305/2306，第一信号线2301配置为给第一像素阵列提供第一显示信号，且沿第一方向R1依次穿过第一显示区域2011、第一开口周边区域203A和第二显示区域2012，从而电连接位于第一开口201A的相对两侧的第一显示区域2011和第二显示区域2012中的子像素，例如为第一显示区域2011和第二显示区域2012中与第一开口周边区域203A中处于同一水平位置的多个像素的子像素提供第一显示信号。在各实施例中，该第一显示信号例如可以是栅扫描信号、发光控制信号或者复位电压信号等任何形式的电信号。例如，多条第一信号线2301/2302/2303/2304/2305/2306可以为显示区域第一显示区域2011和第二显示区域2012中的像素电路提供扫描信号、发光控制信号、复位电压信号等中的一种或多种。
例如，如图2A和图2B所示，显示基板20还包括第三显示区域2013。例如，第三显示区域2013包括在第二方向R2上位于第一显示区域2011和第二显示区域2012的第一侧的第一部分2013C以及在第二方向R2上位于第一显示区域2011和第二显示区域2012的第二侧的第二部分2013D，第一显示区域2011和第二显示区域2012的第一侧与第一显示区域2011和第二显示区域2012的第二侧在第二方向R2上彼此相对；第一部分2013C和第二部分2013D均与第一显示区域2011和第二显示区域2012相接。
例如，第三显示区域2013的第一部分2013C的在第二方向R2上彼此相对的两个边缘2013A和2013B，分别与第一显示区域2011的沿第二方向R2延伸且远离第一开口201A的边缘2011A、以及第二显示区域201的沿第二 方向R2延伸且远离第一开口201A的边缘2012A对齐。第三显示区域2013包括多行多列像素。显示基板20还包括多条第三信号线2307，多条第三信号线2307位于第三显示区域2013的第一部分2013C和第二部分2013D中。图2A和图2B示出一条位于第三显示区域2013的第一部分2031A的第三信号线2307，以作为示例。第三信号线2307配置为分别给第三显示区域2013的多行像素提供第三扫描信号且沿第一方向R1延伸；例如，在本实施例中，第二信号线24沿第二方向R2依次穿过第三显示区域2013的第二部分2013D、第一开口周边区域203A和第三显示区域2013的第一部分2013C，且配置为给第三显示区域2013的多列像素提供第二显示信号。
第三显示区域2013也包括多个像素，每个像素包括多个子像素，每个子像素包括像素电路。第三显示区域2013的每个像素可与第一显示区域和第二显示区域的每个像素的结构相同。例如，在一些实施例中，第三显示区域2013中的多行多列的子像素中的每一行像素所包括的像素数量基本相同。此时，多条第三信号线2037分别电连接的像素的数量基本相同，因此多条第三信号线2037具有基本相同的负载。例如，多行多列的像素中的每一行像素所包括的像素数量多于第一像素阵列的第一像素行包括的像素数量、多于第一像素阵列的第二像素行包括的像素数量。例如，经过负载补偿后的每条第一信号线2301/2302/2303/2304的负载与多条第三信号线2037的负载基本相同，进而每条第一信号线2301/2302/2303/2304与每条第三信号线2037传输信号的速度基本相同，传输给子像素的像素电路的实际显示信号与设计值之间的偏差基本一致，由此可以保持显示区域201的显示一致性，提高显示基板20的显示效果。
如图2B所示，例如，显示基板20还包括第一电源线VDD，第一电源线VDD连接第一电压端，且配置为给一个或多个子像素的像素电路提供第一电源电压。例如，第一电源线VDD包括沿第一方向R1延伸的多条第一子走线2421/2422和沿第二方向R2延伸的多条第二子走线2423/2424。多条第一子走线2421/2422中的第一部分第一子走线2421在第一开口区域202A断开，多条第一子走线2421/2422中的第二部分第一子走线2422贯穿第三显示区域。例如，在图2B中，第一子走线2422沿第一方向R1贯穿第三显示区 域2013的第一部分2013C。多条第二子走线2423/2424中的第一部分第二子走线2423在第一开口区域202A断开，多条第二子走线2423/2424中的第二部分第二子走线2424依次贯穿第一显示区域2011和第三显示区域2013，例如，在本实施例中依次贯穿第三显示区域2013的第二部分2013D、第一显示区域2011和第三显示区域2013的第一部分2013C。或者，第二子走线2424依次贯穿第二显示区域2012和第三显示区域2013，例如在本实施例中依次贯穿第三显示区域2013的第二部分2013D、第二显示区域2012和第三显示区域2013的第一部分2013C。第一部分第一子走线2421与第二部分第二子走线2424中的至少一条第二子走线2424分别在第一显示区域2011和第二显示区域2012电连接，第一部分第二子走线2423与第二部分第一子走线2422中的至少一条第一子走线2422在第三显示区域2013电连接，以给第一像素阵列和第二像素阵列的各行各列的子像素均提供第一电源电压。
本公开至少一实施例提供的显示基板的第一开口区域的平面形状不限于是圆形，例如也可以为矩形、椭圆形等规则图形，或者为跑道形(例如如图15)、水滴形等不规则图形。这些情形下，第一信号线和第二信号线的设置原则和技术效果与上述圆形的示例的相同或类似。
开口间区域2014、第一开口周边区域203A和第二开口周边区域203B三者中的至少一者包括第一虚拟子像素，例如，如图2C所示，本实施例以开口间区域2014包括第一虚拟子像素11为例，即第一虚拟子像素11位于图2C中局部A中，后文将详细介绍第一虚拟子像素的结构。当然，第一虚拟子像素11也可以位于第一开口周边区域203A或/和第二开口周边区域203B中。
下面对显示区域中的子像素，例如图3C中的局部B和局部C中的子像素12，的结构进行介绍。
图3A为显示基板的显示区域中的子像素的一种截面示意图。如图3A所示，显示基板20的显示区域201的每个子像素的像素电路包括晶体管，以薄膜晶体管(TFT)为例进行描述，以及发光元件180和存储电容CST。薄膜晶体管包括有源层120、栅极121和源漏极122/123；存储电容CST包括第一极板CE1和第二电容极板CE2。发光元件180包括阴极183、阳极181以 及阴极183和阳极181之间的发光层182，阳极181与薄膜晶体管TFT的源漏极122/123中之一，例如漏极123，电连接。例如，该发光元件例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)，相应地，发光层182为有机发光层或量子点发光层。
例如，如图3A所示，显示区域201还包括位于有源层120与栅极121之间的第一栅绝缘层151、位于栅极121上方的第二栅绝缘层152以及层间绝缘层160，第二栅绝缘层152位于第一极板CE1和第二电容极板CE2之间，使得第一极板CE1、第二栅绝缘层152和第二电容极板CE2构成存储电容CST。层间绝缘层160覆盖在第二电容极板CE2上。
例如，如图3A所示，显示区域201还包括覆盖像素电路的绝缘层113(例如钝化层)和第一平坦化层112。显示区域201还包括用于限定多个子像素的像素界定层170以及像素界定层170上的隔垫物(未示出)等结构。如图3A所示，在一些实施例中，绝缘层113位于源漏极122/123上方(例如钝化层，由氧化硅、氮化硅或者氮氧化硅等材料形成)，绝缘层113上方设置有第一平坦化层112，阳极181通过贯穿第一平坦化层112和绝缘层113的过孔与漏极123电连接。
例如，如图3A所示，显示基板20的第一开口周边区域203A还包括封装层291、292和293。显示区域201还包括封装层190，封装层190包括多个封装子层191/192/193。当然，封装层190不限于3层，还可以为2层，或者4层、5层或者更多层。例如，第一封装层291与封装层190中的第一封装子层191同层设置，第二封装层292与封装层190中的第二封装子层192同层设置，第三封装层293与封装层190中的第三封装子层193同层设置，例如，第一封装层291和第三封装层293均可以包括无机封装材料，例如包括氧化硅、氮化硅或者氮氧化硅等，第二封装层292可以包括有机材料，例如包括树脂材料等。显示区域201和第一开口周边区域203A多层封装结构可以达到更好的封装效果，以防止水汽或氧气等杂质渗入显示基板20内部。
在一些实施例中，如图3A所示，显示基板还包括位于衬底基板210上的缓冲层111，缓冲层111作为过渡层，可以防止衬底基板210中的有害物质侵入显示基板20的内部，又可以增加显示基板20中的膜层在衬底基板210 上的附着力。例如，缓冲层111的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料形成的单层或多层结构。
图3B为显示基板的显示区域中的子像素的另一种截面示意图。与图3A所示的显示区域不同的是，图3B示出的显示区域中，发光元件180的阳极181通过转接电极171与薄膜晶体管TFT的漏极123电连接。此时，转接电极171上覆盖有第二平坦化层114，例如，在第一平坦化层112上方覆盖有第二平坦化层114。
例如，在其他实施例中，显示基板的显示区域也可以不具有绝缘层113和第二平坦化层114。
例如，本公开的至少一个实施例中，衬底基板210可以为玻璃基板、石英基板、金属基板或树脂类基板等。例如，衬底基板210的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。例如，衬底基板210可以为柔性基板或非柔性基板，本公开的实施例对此不作限制。
例如，第一栅绝缘层151、第二栅绝缘层152、层间绝缘层160、第一平坦化层112、像素界定层170以及隔垫物中任一的材料可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对第一栅绝缘层151、第二栅绝缘层152、层间绝缘层160、第一平坦化层112、像素界定层170以及隔垫物的材料均不做具体限定。例如，第一栅绝缘层151、第二栅绝缘层152、层间绝缘层160、第一平坦化层112、第二平坦化层114、像素界定层170以及隔垫物的材料可以彼此相同或部分相同，也可以彼此不相同，本公开的实施例对此不作限制。
例如，如图2B所示，显示基板20还可以包括位于第一开口周边区域203A中且至少部分围绕第一开口201A的阻隔墙28。例如，在垂直于衬底基板210的方向上，阻隔墙28与第一信号线和第二信号线至少部分重叠。阻隔墙28能够在第一开口周边区域203A提供阻隔和支撑作用，维持第一开口201A的稳定以及保护第一开口201A中的摄像头等光电传感器件，同时阻挡 水汽、氧等有害杂质经由第一开口201A扩散到显示区域中，由此防止了有害杂质导致显示区域中的像素电路劣化。
图4A为本公开一实施例提供的一种显示基板中的第一虚拟像素电路的平面布局示意图，例如该第一虚拟像素电路为图2C中的局部A；图4B为沿图4A中的A2-B2线的截面示意图，图4C-4G为本公开一实施例提供的一种显示基板的第一虚拟像素电路的各层的示意图。
结合图2A-2C和图4A-4B，第一信号线2301的第一部分2301A穿过第一虚拟子像素11，第一虚拟子像素11包括虚拟像素电路，虚拟像素电路包括第一补偿电容COM1，第一补偿电容COM1包括：第一极板CE11和第二极板CE12。第一补偿电容COM1的第一极板CE11与第一信号线2301的第一部分2301A同层设置且与第一信号线2301电连接，且与存储电容CST的第二极板CE2同层设置；第一补偿电容COM1的第二极板CE12与第一补偿电容COM1的第一极板CE11异层设置且绝缘。第一补偿电容COM1的第二极板CE12在衬底基板210上的正投影与第一补偿电容COM1的第一极板CE11在衬底基板210上的正投影至少部分重叠。第一补偿电容COM1补偿了第一信号线2301上的负载，从而减小由于不同行像素的像素数量不同而导致连接不同行像素的第一信号线的负载不同而造成的显示差异，使第一显示区域2011和第二显示区域2012的显示效果与显示区域201中不设置有第一开口区域202A的像素行的显示效果一致，提升显示质量。并且，由于第一极板CE11与存储电容CST的第二极板CE2同层设置，从而，第一极板CE11不仅能够与位于其上方(远离衬底基板的方向)的金属层层形成补偿电容，而且还可以与其下方(靠近衬底基板的方向)的半导体层形成补偿电容。如果第一极板CE11与上述栅极121同层设置，则会与半导体层层形成TFT。
例如，如图4B和图4E所示，第一补偿电容COM1的第一极板CE11与第一信号线2301一体成型。
例如，如图4B所示，第一补偿电容COM1的第二极板CE12的材料包括半导体材料且为导体，且与上述有源层120同层设置。例如，第一补偿电容COM1的第二极板CE12的材料包括与有源层120相同的材料，例如包括a-Si、多晶硅等。例如，给第一补偿电容COM1的第二极板CE12进行重掺 杂以增强其导电性使其成为导体。例如可在对有源层120进行掺杂的同时进行，由于第一补偿电容COM1的第二极板CE12不会被遮挡而实现重掺杂。例如，掺杂材料为硼(B)。给第二极板CE12施加电压信号，半导体材料相当于导体，因此可以作为电容极板，而且充分利用了已有的层，其可以与有源层120通过同一次构图工艺同时形成。同一次构图工艺指采用同一个掩模板经过同一次曝光以进行构图。
如图4A-4B所示，虚拟像素电路还包括第二补偿电容COM2，第二补偿电容COM2包括第一极板CE21和第二极板CE22。第一补偿电容COM1的第一极板CE21复用作第二补偿电容COM2的第一极板CE21；第二极板CE22与第二补偿电容COM2的第一极板CE21异层设置且绝缘，且与上述源漏极122/123同层设置。第二补偿电容COM2的第二极板CE22在衬底基板210上的正投影与第二补偿电容CE22的第一极板CE21在衬底基板210上的正投影至少部分重叠。第二补偿电容进一步补偿了第一信号线2301上的负载，从而减小由于不同行像素的像素数量不同而导致连接不同行像素的第一信号线的负载不同而造成的显示差异，使第一显示区域2011和第二显示区域2012的显示效果与显示区域201中不设置有第一开口区域202A的像素行的显示效果一致，提升显示质量。同时，利用了已有的层，即源漏极122/123所在的导电层，可以与源漏极122/123通过对同一膜层进行一次构图工艺形成，简化显示极板的制作工艺，节省成本。
例如，第二补偿电容COM2的第二极板CE22与第一补偿电容COM1的第二极板CE12电连接，从而第一补偿电容与第二补偿电容并联，提供更有效的补偿和更大的补偿范围。
图4H为本公开一实施例提供的另一种显示基板的第一补偿电容的第一极板的示意图。如图4H所示，第一补偿电容COM1的第一极板CE11包括第一延伸部21和第二延伸部22。第一延伸部21与第一信号线2303的第一部分2301A连接，自第一信号线2303的第一部分2301A延伸且位于第一信号线2303的第一部分2301A在第二方向R2上的第一侧，第二方向R2与第一方向R1相交，例如垂直但不限于此；第二延伸部22与第一信号线2303的第一部分2301A连接，自第一信号线2303的第一部分2301A延伸且位于 第一信号线2303的第一部分2301A在第二方向R2上与第一侧相对的第二侧。由此，可以加大第一补偿电容的第一极板的面积，从而可根据需要提供更大的补偿范围。
例如，第一延伸部21、第二延伸部22和第一信号线2303的第一部分2301A一体成型。
例如，显示基板还包括第一电源线。第一电源线连接第一电压端，配置为给上述像素电路提供第一电源电压，且与存储电容CST的第二极板CE2连接，第一电源线包括：沿第一方向延伸的多条第一子走线，以及沿第二方向延伸的多条第二子走线，且多条第二子走线与多条第一子走线电连接。多条第二子走线中的第一部分第二子走线2424穿过开口间区域2014且穿过第一虚拟子像素11。如图4F所示，第二补偿电容COM2的第二极板CE22包括第一部分CE221和第二部分CE222，第一部分第二子走线2424与第二补偿电容的第二极板的第一部分CE221同层设置且电连接以作为第二补偿电容的第二极板的第二部分CE222，且第一部分第二子走线2424与第一补偿电容COM1的第二极板CE12电连接，由此实现第二补偿电容COM2的第二极板CE22与第一补偿电容COM1的第二极板CE12电连接。
例如，第一部分第二子走线2424与第二补偿电容COM2的第二极板CE22一体成型。
图4I为沿图4A中的A3-B3线的截面示意图。例如，如图4I所示，显示基板20还包括：位于第一补偿电容COM1的第二极板CE12与上述栅极121之间的第一绝缘层151(例如为上述第一栅绝缘层)、位于栅极121与第一补偿电容COM1的第一极板CE11之间的第二绝缘层152(例如为上述第二栅绝缘层)，以及位于第一补偿电容COM1的第一极板CE11与第二补偿电容COM2的第二极板CE22之间的第三绝缘层160(例如为上述层间绝缘层)。第一部分第二子走线2424通过贯穿第一绝缘层151、第二绝缘层152和第三绝缘层160且暴露第一补偿电容COM1的第二极板CE12的第一过孔VH10与第一补偿电容COM1的第二极板CE12电连接。
例如，如图2C所示，显示基板20还包括多条第二信号线24。多条第二信号线24配置为给所述多个子像素提供第二显示信号。多条第二信号线24 中的第一部分第二信号线2411沿第二方向R2穿过开口间区域2014且穿过第一虚拟子像素11。结合图4B，第一部分第二信号线2411位于第二补偿电容COM2的第二极板CE22的远离衬底基板210的一侧。结合图4A和图4B，第二补偿电容COM2的第二极板CE22的第一部分21具有镂空区域H1，穿过该第二补偿电容COM2的第二极板CE22所在的第一虚拟子像素11的第一部分第二信号线2411在衬底基板210上的正投影与镂空区域H1至少部分重叠，以减小第一部分第二信号线2411与第二补偿电容COM2的第二极板CE22的交叠面积，减小两者交叠所形成的电容，从而减小第一部分第二信号线2411的负载。
例如，结合图4A和图4B，第二补偿电容COM2的第二极板CE22具有多个所述镂空区域H1/H2，本实施例以包括两个镂空区域H1为例，多个镂空区域沿第二方向R2彼此间隔排列。由此，可根据不同的需要分梯度调节第一部分第二信号线2411的负载。
例如，结合图4A和图4F，多个镂空区域包括相邻的第一镂空区域H1和第二镂空区域H2，第一镂空区域H1的在第二方向R2上的长度与第二镂空区域H2的在第二方向R2上的长度不同，可根据第一部分第二信号线2411的不同部分的负载大小不同，而有区别地调节第一部分第二信号线2411的负载。
例如，结合图4A和图4F，第二补偿电容COM2的第二极板CE22的位于第一镂空区域H1与第二镂空区域H2之间的部分P沿第一方向R1是连续的；第二补偿电容COM2的第二极板CE22包括在第二方向R2上彼此相对的第一边缘和第二边缘，第一边缘和第二边缘中的至少之一被镂空区域断开。
例如，第一信号线包括栅扫描信号线和复位信号线。例如，第一信号线2303为栅扫描信号线，配置为给子像素提供栅扫描信号，对应地，第一显示信号为栅扫描信号；第一信号线2301为复位信号线，配置为给子像素提供复位电压信号，对应地，第一显示信号为复位电压信号。例如，第二信号线24为数据线，配置为给子像素提供用于控制子像素的发光灰度的数据信号。
例如，在一些实施例中，在一个第一虚拟子像素11中，第一补偿电容COM1的第二极板CE12的覆盖整个第一虚拟子像素11，第一补偿电容COM1 的第一极板CE11在衬底基板210上的正投影位于第一补偿电容COM1的第二极板CE12在衬底基板210上的正投影内。第一补偿电容COM1的大小小于所述第二补偿电容COM2的大小。并且，可以根据需要调节第一补偿电容COM1和第二补偿电容COM2的各个极板的有效尺寸以调节第一补偿电容COM1和第二补偿电容COM2的大小。
例如，如图2A和2B所示，显示区域201包括第一显示区域2011和第二显示区域2012。第一显示区域2011位于第一开口区域202A的远离开口间区域2014的一侧；第二显示区域2012位于第二开口区域202B的远离开口间区域2014的一侧。第一显示区域2011和第二显示区域2012均包括多个像素。如图4J所示，第一显示区域2011和第二显示区域2012构成的整体包括沿第一方向R1延伸的多个像素行，如图中的第一行、第二行、第三行……，该多个像素行被第一开口区域202A、开口间区域2014和第二开口区域202B三者构成的整体断开。例如，第一行像素的像素数量与第二行像素的像素数量不相同，对应于第一行像素的第一虚拟像素行中的第一补偿电容的数量与对应于第二行像素的第二虚拟像素行中的第一补偿电容的数量不相同，以使不同行像素的第一信号线的负载均匀化。
如图2B所示，第一信号线2303沿第一方向R1依次穿过第一显示区域2011、第一开口周边区域203A、开口间区域2014、第二开口周边区域203B和第二显示区域2012，第一信号线2303还包括穿过第一显示区域2011的第二部分2303B和穿过第二显示区域2012的第三部分2303C，第二部分2303B和第三部分2303C与栅极121同层设置。因此，第二部分2303B和第一部分2303A需要换层，第一部分2303A和第三部分2303C需要换层。
图5A为图2C中的局部C的放大示意图，图5B-5D分别为图2C中的局部D、局部E和局部F的放大示意图，图5E为第一信号线和第二信号线进行换层的区域的放大示意图，图5F-5H分别为沿图5E中的A4-B4线、A5-B5线和A6-B6线的截面示意图。
结合图5A-5B和图5E，显示基板20还包括第一连接结构，例如，第一连接结构包括第一子连接结构311和第二子连接结构312。例如，第一连接结构311/312位于第一开口周边区域203A，例如位于第一开口周边区域203A 与第一显示区域2011的交界处，且与第一信号线的第二部分2303B/2301B和第一信号线的第一部分2303A/2301A均异层设置，第一信号线的第二部分2303B/2301B与第一连接结构311/312电连接，第一信号线的第一部分2303A/2301A与第一连接结构311/312电连接，实现第一信号线2303/2301由第一显示区2011进入第一开口周边区域203A时的换层。
例如，第一信号线2303为栅扫描信号线、第一信号线2301为复位信号线。结合图5E与图5F，复位信号线的第二部分2301B与复位信号线的第一部分2301A异层设置，复位信号线的第二部分2301B通过过孔VH11与第二子连接结构312电连接，复位信号线的第一部分2301A通过过孔VH12与第二子连接结构312电连接，从而实现复位信号线的第二部分2301B与复位信号线的第一部分2301A电连接，从而实现复位信号线2301经过换层后而围绕第一开口布线。
类似地，结合图5E与图5G，栅扫描信号线的第二部分2303B与栅扫描信号线的第一部分2303A异层设置，栅扫描信号线的第二部分2303B通过过孔VH13与第一子连接结构311电连接，栅扫描信号线的第一部分2303A通过过孔VH14与第一子连接结构311电连接，从而实现栅扫描信号线的第二部分2303B与栅扫描信号线的第一部分2303A电连接，从而实现栅扫描信号线2303经过换层后而围绕第一开口布线。
例如，第一连接结构和第二连接结构与源漏极122/123同层设置。
显示基板20还包括第二连接结构。例如第二连接结构位于第二开口周边区域203B，例如位于第二开口周边区域203B与第一显示区域的交界处。且与第一信号线的第一部分2303A/2301A和第一信号线的第三部分2303C/2301C均异层设置；第一信号线的第一部分2303A/2301A与第二连接结构(图未示出)电连接，第一信号线的第三部分2303C/2301C与第二连接结构电连接，实现第一信号线2303的再一次换层，即第一信号线2303由第二开口周边区域203B进入第二显示区2012时的换层。例如，第二连接结构包括第三子连接结构和第四子连接结构，分别对应于栅扫描信号线2303和复位信号线2301分别设置，以分别用于实现栅扫描信号线2303和复位信号线2301的再一次换层。例如，第三子连接结构和第四子连接结构的设置可参考 上述第一子连接结构和第二子连接结构的设置方式。例如，在一些实施例中第三子连接结构和第四子连接结构，与第一子连接结构和第二子连接结构基本对称。
例如，如图5E所示，给同一行子像素12提供栅扫描信号的第一栅线GLn和第二栅线GLn-1通过同一个第一子连接结构311进行换层，以节省空间。例如，给多行子像素提供复位电压信号的复位信号线可通过同一个第二连接结构312进行换层，以节省空间。例如该同一个第二连接结构312沿第一显示区域与第一开口周边区域的交界区呈折线走线，以合理利用空间，给设置其他结构例如第一连接结构和第二连接结构留出充足的空间。当然，在其他实施例中，也可通过彼此分隔开的多个第二连接结构312进行换层。
结合图5C-5D和图5E，一部分第二信号线2410由显示区域进入第一开口周边区域(对于第二开口也是如此，以第一开口为例)，始终位于上述源漏极122/123的远离衬底基板210的一侧，不进行换层。一部分第二信号线2412由显示区域进入第一开口周边区域(对于第二开口也是如此，以第一开口为例)，第二信号线2412包括穿过显示区域的第一部分2412A与穿过第一开口周边区域203A的第二部分2412B，第二信号线2412的第一部分2412A位于上述源漏极122/123的远离衬底基板210的一侧，第二信号线2412的第二部分2412B与源漏极122/123同层设置。因此，第二信号线2412需要进行换层。
结合图5E和图5H，第二信号线2412的第一部分2412A通过穿过绝缘层113的过孔VH15直接与第二信号线2412的第二部分2412B，无需再设置额外的连接电极，以简化制作工艺。
例如不换层的数据线2410与进行换层的数据线2412在第一方向上相邻。
图6为本公开一实施例提供的一种阵列基板中的像素电路的等效电路图，图7A为本公开一实施例提供的一种阵列基板中的像素电路的平面布局示意图。图7A以相邻的两个子像素中的像素电路的层结构为例。
下文中的数据线1为上述第二信号线24的一种示例。
多个子像素1030的每个包括像素电路，像素电路包括发光器件、存储电容CST、驱动晶体管T1(下文又称第一晶体管)和数据写入晶体管T2(下 文又称第二晶体管)，以及数据线1和第一连接结构CP1。驱动晶体管T1和数据写入晶体管的每个包括有源层、栅极、第一极和第二极，驱动晶体管T1配置为控制所述发光器件发光，例如控制驱动发光器件发光的驱动电流。数据线1与数据写入晶体管T2的第一极连接且配置为给数据写入晶体管T2提供用于控制子像素1030的显示灰度的数据信号。数据写入晶体管T2配置为响应于施加在数据写入晶体管T2的栅极的第一扫描信号而将数据信号写入驱动晶体管T1的栅极。第一连接结构CP1与驱动晶体管T1的栅极以及存储电容CST的第一极板连接，第一连接结构CP1与数据线1异层设置，即第一连接结构CP1与数据线1分别设置于不同的层，且在垂直于衬底基板210的方向上第一连接结构CP1与数据线1之间存在绝缘层。在图6和图7A所示的像素电路中，如果第一连接结构CP1与数据线1同层设置，则这两者之间的间距较小，将会导致在横向上，第一连接结构CP1与数据线1之间形成较大的寄生电容，尤其是在高分辨率显示面板中，这种现象尤其严重。该寄生电容将会直接导致显示效果不理想。且第一连接结构CP1与数据线1之间形成的寄生电容不稳定，因为在显示过程中，数据线1上的数据信号是不断变化的，随着该数据信号被写入驱动晶体管T1的栅极，即该数据信号被写入图6中的N1节点，从而引起N1节点信号的跳变，从而影响流过N1节点的电流的波动，影响显示效果。而第一连接结构CP1是图6中的N1节点所对应的实际结构，因此，在本公开实施例提供的阵列基板中，将第一连接结构CP1与数据线1异层设置可以减小或避免两者之间形成该寄生电容，从而可改善或避免由此给显示效果造成的不良影响，达到更加理想的显示效果。
需要说明的是，由于像素的阵列排列，对应于同一个子像素1030的数据线1与第一连接结构CP1之间会形成上述寄生电容(以下用寄生电容1代表)，分别对应于相邻的两个子像素中的数据线1与第一连接结构CP1之间也会形成上述寄生电容(以下用寄生电容2代表)。经模拟试验，在第一连接结构CP1与数据线1同层设置的情况下，寄生电容1的值可达0.07971fF，寄生电容2的值可达0.05627fF，两者对N1节点产生的串扰程度为0.678％。串扰程度的值越大，说明形成的干扰越大，对显示造成的不良影响也越大。
在本公开实施例提供的阵列基板中，寄生电容1的值约为0.0321fF，寄 生电容2的值可达0.0242fF，两者对N1节点产生的串扰程度为0.218％。由此可见，本公开实施例提供的阵列基板中的寄生电容1和寄生电容2的值相对于将两者同层设置的情况有明显下降，对N1节点产生的串扰程度明显下降，从而对显示造成的不良影响具有明显改善作用。
如图6所示，在一些实施例中，像素电路包括多个薄膜晶体管：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的多条信号线和存储电容CST，也即，该实施例中像素电路为7T1C结构。相应地，多条信号线包括栅线GLn/GLn-1(即扫描信号线)、发光控制线EM、复位信号线RL、数据线DAT和第一电源线VDD。栅线GLn/GLn-1可包括第一栅线GLn和第二栅线GLn-1。例如，第一栅线GLn用于传输栅极扫描信号，第二栅线GLn-1用于传输复位电压信号发光控制线EM用于传输发光控制信号，例如连接到第一发光控制端EM1和第二发光控制端EM2。第五晶体管T5的栅极与第一发光控制端EM1连接，或作为第一发光控制端EM1，以接收第一发光控制信号；第六晶体管T6的栅极与第二发光控制端EM2连接，或作为第二发光控制端EM2，以接收第二发光控制信号。
需要说明的是，本公开实施例包括但并不限于上述7T1C结构的像素电路，像素电路也可采用其他类型的电路结构，例如7T2C结构或者9T2C结构等，本公开实施例对此不作限制。
例如，如图6所示，第一薄膜晶体管T1的第一栅极与第三薄膜晶体管T3的第三漏极D3和第四薄膜晶体管T4的第四漏极D4电连接。第一薄膜晶体管T1的第一源极S1与第二薄膜晶体管T2的第二漏极D2和第五薄膜晶体管T5的第五漏极D5电连接。第一薄膜晶体管T1的第一漏极D1与第三薄膜晶体管T3的第三源极S3和第六薄膜晶体管T6的第六源极S6电连接。
例如，如图6所示，第二薄膜晶体管T2的第二栅极被配置为与第一栅线GLn电连接，以接收栅极扫描信号；第二薄膜晶体管T2的第二源极S2被配置为与数据线DAT电连接，以接收数据信号；第二薄膜晶体管T2的第二漏极D2与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图6所示，第三薄膜晶体管T3的第三栅极被配置为与第一栅线GLn电连接，第三薄膜晶体管T3的第三源极S3与第一薄膜晶体管T1的第一漏电极D1电连接，第三薄膜晶体管T3的第三漏极D3与第一薄膜晶体管T1的第一栅极电连接。
例如，如图6所示，第四薄膜晶体管T4的第四栅极被配置为与第二栅线GLn-1电连接以接收复位电压信号，第四薄膜晶体管T4的第四源极S4被配置为与复位信号线RL电连接以接收复位电压信号，第四薄膜晶体管T4的第四漏极D4与第一薄膜晶体管T1的第一栅极电连接。
例如，如图6所示，第五薄膜晶体管T5的第五栅极被配置为与发光控制线EM电连接以接收发光控制信号，第五薄膜晶体管T5的第五源极S5被配置为与第一电源线VDD电连接以接收第一电源信号，第五薄膜晶体管T5的第五漏极D5与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图6所示，第六薄膜晶体管T6的第六栅极被配置为与发光控制线EM电连接以接收发光控制信号，第六薄膜晶体管T6的第六源极S6与第一薄膜晶体管T1的第一漏极D1电连接，第六薄膜晶体管T6的第六漏极D6与发光器件(例如图6所示发光器件180)的第一显示电极(例如图6所示的阳极181)电连接。图7A-7C中的薄膜晶体管TFT即第六薄膜晶体管T6。
例如，如图6所示，第七薄膜晶体管T7的第七栅极被配置为与第二栅线GLn-1电连接以接收复位电压信号，第七薄膜晶体管T7的第七源极S7与发光器件的第一显示电极(例如图6所示的阳极181)电连接，第七薄膜晶体管T7的第七漏极D7被配置为与复位信号线RL电连接以接收复位电压信号。例如，第七薄膜晶体管T7的第七漏极D7可以通过连接到第四薄膜晶体管T4的第四源极S4以实现与复位信号线RL电连接。
在本实施例中，第四晶体管T4和第七晶体管T7为复位晶体管，配置为给子像素提供复位信号。
需要说明的是，上述的复位电压信号和上述的复位电压信号可为同一信号。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场 效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。在本公开实施例中，任何一个晶体管的第一极为源极，则第二极为漏极；或者，任何一个晶体管的第一极为漏极，则第二极为源极。各个晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的，本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
图7B-7F为本公开一实施例提供的一种阵列基板的像素电路的各层的示意图，图8A为沿图7A中的A-A’线的一种截面示意图。
在一些实施例中，如图7A所示，像素电路包括上述的薄膜晶体管T3、T4、T5、T6和T7、存储电容CST、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的第一栅线GLn、第二栅线GLn-1、发光控制线EM、复位信号线RL、数据线DAT和第一电源线VDD。
下面，结合图7A-7F和图8A对本公开实施例的像素电路的结构的具体特征进行说明。
如图7A和图8A所示，数据线1和第一连接结构CP1均沿第一方向延伸，且第一连接结构CP1在衬底基板210上的正投影与数据线1在衬底基板210上的正投影在横向R2上至少部分彼此相对，这种结构利于像素电路结构的紧凑，在这种情况下，如果数据线1与第一连接结构CP1同层设置，两者之间的寄生电容现象将尤为明显，这种设置不仅能够改善或避免上述寄生电容，还能够实现像素电路结构的紧凑，利于实现阵列基板的高分辨率。横向R2平行于衬底基板210且垂直于第一方向R1。
例如，第一连接结构CP1在衬底基板210上的正投影与数据线1在衬底基板210上的正投影之间的距离(第一连接结构CP1在衬底基板210上的正投影的靠近数据线1在衬底基板210上的正投影的边到数据线1在衬底基板210上的正投影的靠近第一连接结构CP1在衬底基板210上的正投影的边的最大距离)小于一个子像素1030的在所述横向上的尺寸，以更加利于像素电路结构的紧凑，即使在第一连接结构CP1与数据线1在横向R2上的间距很小的情况下，也不会产生上述寄生电容现象。例如，对应于同一个子像素1030的数据线1与第一连接结构CP1之间的距离小于一个子像素1030的在横向 R2上的尺寸，且分别对应于相邻的两个子像素中的数据线1与第一连接结构CP1之间的距离小于一个子像素1030的在横向R2上的尺寸。例如，一个子像素1030的在所述横向R2上的尺寸为30μm～90μm。
进一步地，例如，第一连接结构CP1在衬底基板210上的正投影与数据线1在衬底基板210上的正投影之间存在间隔。或者，在一些实施例中，第一连接结构CP1在衬底基板210上的正投影与数据线1在衬底基板210上的正投影之间基本不存在间隔。即基本相接，利于在实现高分辨率，在这种情况下，本公开实施例提供的阵列基板同时能够防止上述寄生电容现象。
例如，像素电路包括半导体层、第一导电层、第二导电层和第三导电层。图7A示出了像素电路的半导体层、第一导电层、第二导电层和第三导电层的层叠位置关系的布局示意图。
图7B示出了像素电路的半导体层。例如，图7B所示的该半导体层包括第一薄膜晶体管T1的有源层A1、第二薄膜晶体管T2的有源层A2、第三薄膜晶体管T3的有源层A3、第四薄膜晶体管T4的有源层A4、第五薄膜晶体管T5的有源层A5、第六薄膜晶体管T6的有源层A6和第七薄膜晶体管T7的有源层A7。如图7B所示，半导体层可采用半导体材料层通过构图工艺形成。半导体层可用于制作上述的，各个晶体管的有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，半导体层可采用非晶硅、多晶硅、氧化物半导体材料(例如，氧化铟镓锡(IGZO))等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
在本公开一些实施例提供的阵列基板中，在上述的半导体层上形成有第一绝缘层。为了清楚起见，图7A、图7B-7K中未示出各个绝缘层。例如，结合图7B和图8A，像素电路的第一绝缘层151设置在第一导电层的远离衬底基板210的一侧。
图7C示出了像素电路的第一导电层，图7G示出了第一导电层与半导体层层叠后的示意图。第一导电层位于半导体层的远离衬底基板210的一侧。结合图7C、图7G和图8A，第一绝缘层151位于各个晶体管的有源层与第一导电层之间。例如，第一导电层包括存储电容CST的第一极板CE1、第一 栅线GLn、第二栅线GLn-1、发光控制线EM、以及第一薄膜晶体管T1的栅极、第二薄膜晶体管T2的栅极、第三薄膜晶体管T3的栅极、第四薄膜晶体管T4的栅极、第五薄膜晶体管T5的栅极、第六薄膜晶体管T6的栅极和第七薄膜晶体管T7的栅极。因此，上述各个晶体管的有源层同层设置，且上述各个晶体管的栅极与存储电容CST的第一极板CE1同层设置，从而第一绝缘层151位于各个晶体管的有源层与各个晶体管的栅极和存储电容CST的第一极板CE1之间。由此可见，驱动晶体管即第一晶体管T1的栅极(或各个晶体管的栅极)和存储电容CST的第一极板CE1位于驱动晶体管的有源层(或各个晶体管的有源层)的远离衬底基板210的一侧。
结合图7A-图7C和图7G所示，第二薄膜晶体管T2的栅极、第四薄膜晶体管T4的栅极、第五薄膜晶体管T5的栅极、第六薄膜晶体管T6的栅极和第七薄膜晶体管T7的栅极分别为第一栅线GLn、第二栅线GLn-1与半导体层交叠的部分。在一些实施例中，例如，第三薄膜晶体管T3可为双栅结构的薄膜晶体管，第三薄膜晶体管T3的一个栅极可为第一栅线GLn与半导体层交叠的部分，第三薄膜晶体管T3的另一个栅极可为从第一栅线GLn突出的突出部；第一薄膜晶体管T1的栅极可以与第一极板CE1一体成型，即第一极板CE1复用作第一薄膜晶体管T1的栅极。例如第四薄膜晶体管T4可为双栅结构的薄膜晶体管，两个栅极分别为第二栅线GLn-1与半导体层交叠的部分。
例如上述各个薄膜晶体管的栅极分别与相应的第一栅线GLn或第二栅线GLn-1一体成型。在本实施例中，第一栅线GLn、第二栅线GLn-1和各个薄膜晶体管的栅极与存储电容CST的第一极板CE1同层设置，可通过同一次构图工艺同时形成。
例如，如图7A所示，阵列基板100还包括第一电源线VDD，第一电源线连VDD接第一电压端以及存储电容CST的第二极板CE2，且配置为给发光控制晶体管即第一晶体管T1提供第一电压。例如，第一电源线VDD包括沿第一方向R1延伸的第一子走线21和沿第二方向延伸的第二子走线22，第一方向R1与第二方向相交，例如第二方向为横向R2。第一子走线21与第二子走线22电连接。
图7D示出了像素电路的第二导电层，图7H示出了第二导电层与半导体层层叠后的示意图。第二导电层位于第一导电层的远离衬底基板210的一侧。例如，结合图7D、图7H与图8A，像素电路的第二导电层包括存储电容CST的第二极板CE2、复位信号线RL和第二子走线22，由此可见第二子走线22与存储电容CST的第二极板CE2同层设置，且存储电容CST的第二极板CE2位于驱动晶体管即第一晶体管T1的栅极(或各个晶体管的栅极)和存储电容CST的第一极板CE1的远离所述有源层的一侧。例如，第二子走线22与存储电容CST的第二极板CE2一体成型，从而可通过同一构图工艺形成。第二极板CE2与第一极板CE1至少部分重叠以形成存储电容CST。
例如，在一些实施例中，结合图7A和图7D，第二导电层还可包括遮光部791。遮光部791在衬底基板210上的正投影覆盖第二薄膜晶体管T2的至少部分有源层、第三薄膜晶体管T3的漏极和第四薄膜晶体管T4的漏极之间的有源层，从而防止外界光线对第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4的有源层产生影响。遮光部791可通过贯穿绝缘层中的过孔VH9与第一电源线VDD电连接，如图7A和图8C所示。
在本公开至少一实施例中，如图7A和图7K所示，例如，在一个子像素中，在横向R2上，第一连接结构CP1位于第一子走线21与数据线1(与第一连接结构CP1和第一子走线21属于同一个子像素的像素电路)之间。这种情况下，在横向上，第一连接结构CP1与数据线1之间不存在例如第一电源线这种沿第一方向R1延伸的结构，则第一连接结构CP1与数据线1之间的间距更小，将会导致在横向上，第一连接结构CP1与数据线1之间形成更为明显的寄生电容。因此这种情况下本申请实施例提供的阵列基板中，将第一连接结构CP1与数据线1异层设置具有更加明显的减小数据线1对第一连接结构CP1的信号干扰的效果。
另外，这种方案相比于第一子走线21位于第一连接结构CP1与数据线(与第一连接结构CP1和第一子走线21属于同一个子像素的像素电路)之间的情况，第一连接结构CP1的在第一方向R1上的长度较小，第一连接结构CP1的在横向R2上的宽度也较小，因此，利用位于第二导电层还可包括上述遮光部791，以遮挡第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄 膜晶体管T4的有源层，可以利用第二导电层实现这一目的，从而简化阵列基板的制作工艺。
例如，如图8A所示，阵列基板100还包括第二绝缘层152，第二绝缘层152位于存储电容CST的第一极板CE1与存储电容CST的第二极板CE2之间，即位于第一导电层与第二导电层之间。为了清楚，图7B-7F中也未示出第二绝缘层152。
阵列基板100还包括第二电源线VSS。例如第一电源线VDD为给像素电路提供高电压的电源线，第二电源线VSS连接第二电压端第二电源线VSS为像素电路提供低电压(低于前述高电压)的电源线。在如图6所示的实施例中，第一电源线VDD提供恒定的第一电源电压，第一电源电压为正电压；第二电源线VSS提供恒定的第二电源电压，第二电源电压可以为负电压等。例如，在一些示例中，第二电源电压可以为接地电压。
在一些实施例中，例如，如图8A所示，数据线1(DATA)位于第一连接结构CP1的远离衬底基板210的一侧。这种情况下，例如，图7E示出了像素电路的第三导电层，图7I示出了第三导电层与半导体层层叠后的示意图。第三导电层位于第二导电层的远离衬底基板1的一侧。例如，如图7E和图7I所示，像素电路的第三导电层包括第一连接结构CP1和第一电源线VDD的第一子走线21，即第一连接结构CP1与第一子走线21同层设置。如图8A所示，阵列基板100还包括第三绝缘层160，第三绝缘层160位于存储电容CST的第二极板CE2与第一连接结构CP1之间，即位于第二导电层与第三导电层之间。
例如，第一子走线21通过贯穿第三绝缘层160的过孔(例如过孔VH3)与第二子走线22电连接。
例如，结合图7A、图7E和图8A和图8C，第三导电层还包括第二连接结构CP2、第三连接结构CP3和第四连接结构CP4。第一连接结构CP1的一端通过贯穿第二绝缘层152和第三绝缘层160且暴露部分存储电容CST的第一极板CE1的过孔(例如过孔VH5)与存储电容CST的第一极板CE1连接。第一连接结构CP1的另一端通过贯穿第一绝缘层151、第二绝缘层152和第三绝缘层160的至少一个过孔(例如过孔VH4)与半导体层连接，例如与半 导体层中对应第三薄膜晶体管T3的漏极区域相连。第二连接结构CP2的一端通过贯穿第三绝缘层160的过孔(例如过孔VH6)与复位信号线RL相连，第二连接结构CP2的另一端通过贯穿第一绝缘层151、第二绝缘层152和第三绝缘层160的至少一个过孔(例如过孔VH7)与半导体层连接，例如与半导体层中的第七薄膜晶体管T7的源极区域和第四薄膜晶体管T4的源极区域相连。第三连接结构CP3通过贯穿第一绝缘层151、第二绝缘层152和第三绝缘层160的至少一个过孔(例如过孔VH8)与半导体层中的第六薄膜晶体管T6的漏极区域相连。第四连接结构CP4通过贯穿第一绝缘层151、第二绝缘层152和第三绝缘层160的至少一个过孔(例如过孔VH2)与半导体层中的第五薄膜晶体管T5的漏极区域相连。第五连接结构CP5通过贯穿第一绝缘层151、第二绝缘层152和第三绝缘层160且暴露部分半导体层的至少一个过孔(例如过孔VH1)与半导体层中的第三薄膜晶体管T3的漏极区域相连。
例如，图7F示出了像素电路的第四导电层，图7J示出了第四导电层与半导体层层叠后的示意图，图7K示出了第四导电层、第三导电层与半导体层层叠后的示意图。例如，结合图7A、图7E-图7F、图7J-图7K和图8A所示，第四导电层位于第三导电层的远离衬底基板210的一侧。第四导电层包括数据线1(DATA)、第六连接结构CP6和第七连接结构CP7。阵列基板100还包括第四绝缘层113，第四绝缘层113位于第三导电层与第四导电层之间，即位于第一连接结构CP1与数据线1(DATA)之间。例如，第四绝缘层113为平坦层。过孔VH1还贯穿第四绝缘层113而暴露至少部分第五连接结构CP5，数据线1(DATA)通过过孔VH1与第五连接结构CP5电连接，从而实现数据线1(DATA)与半导体层中的第三薄膜晶体管T3的漏极区域电连接。例如，第七连接结构CP7与数据线1直接接触以实现这两者电连接。由于数据线1的线宽较小例如明显小于第一子走线21的线宽，第七连接结构CP7能够加宽数据线1的需要与半导体层连接的部位，例如数据线1与第七连接结构CP7的构成的整体通过过孔VH1与第五连接结构CP5电连接，从而实现数据线1(DATA)与半导体层中的第三薄膜晶体管T3的漏极区域电连接。例如，第七连接结构CP7与数据线1一体成型。例如，过孔VH2还 贯穿第四绝缘层113而暴露至少部分第四连接结构CP4，第六连接结构CP6通过过孔VH2与第四连接结构CP4电连接，从而实现第六连接结构CP6与有源层中对应第五薄膜晶体管T5的漏极区域相连，以作为第五薄膜晶体管T5的漏极，例如第六连接结构CP6用于与发光器件的阳极(例如图6所示的阳极181)接。例如，在不同的子像素1030中，例如在图7A所示的相邻的两个子像素1030中，第六连接结构CP6的形状、大小和位置未必完全相同，以适应对应有不同的子像素的阳极位置的需求。例如，在图7A所示的左侧的子像素1030中的第六连接结构CP6的形状、大小和位置与右侧的子像素1030中的第六连接结构CP6的形状、大小和位置分别不相同。这是因为这两个子像素中的阳极的位置不同，的第六连接结构CP6的形状、大小和位置沿与第一方向R1和横向R2相交的方向延伸，其上端(非与第四连接结构CP4连接的一端)的位置如此是为了与位于该上端处的阳极相连。
例如，第四绝缘层113的在垂直于衬底基板210的方向上的厚度大于第一绝缘层151的在垂直于衬底基板210的方向上的厚度、第二绝缘层152的在垂直于衬底基板210的方向上的厚度、第三绝缘层160的在垂直于衬底基板210的方向上的厚度和第四绝缘层113的在垂直于衬底基板210的方向上的厚度三者中的至少之一。以增强第四绝缘层113的绝缘作用，更好地减小或避免数据线1与第一连接结构CP1之间的寄生电容。
例如第四绝缘层113的在垂直于衬底基板210的方向上的厚度为几微米，例如小于5μm～10μm，该厚度范围能够达到较好的减小或避免数据线1与第一连接结构CP1之间的寄生电容的效果，且不会过度增厚阵列基板100的尺寸。
在上述实施例中，第一子走线21与数据线1异层设置，由于相邻的在第一子走线21与数据线1之间的间距比较小，如此设计可避免第一子走线21与数据线之间产生寄生电容，从而避免该寄生电容影响显示效果。例如，该相邻的第一子走线21与数据线1分别对应于相邻的两个子像素。
参考图7A和图8A，例如，第一连接结构CP1在衬底基板210上的正投影与数据线1在衬底基板210上的正投影不重叠，第一走线21在衬底基板210上的正投影与数据线1在衬底基板210上的正投影上不重叠。相比于以 上信号线在垂直于衬底基板210的方向上有重叠的情况，本公开实施例的该方案能够更好地防止这些信号线上的信号之间的串扰。
例如，为了减小数据线和第一连接结构的电阻，例如数据线1和第一连接结构CP1的材料均为金属材料。例如形成数据线1的第四导电层采用包括三层金属的叠层结构Ti/Al/Ti。
图8C为沿图7A中的B-B’线的一种截面示意图。多个子像素包括第一子像素和与所述第一子像素相邻的第二子像素。图7A示出了两个相邻的子像素，第一子像素为图7A中左侧的子像素，第二子像素为图7A中右侧的子像素，即第一子像素和第二子像素在横向上相邻；当然，在其他实施例中，第一子像素和第二子像素也可以在纵向上相邻，其他结构的方向和位置适应性调整即可。结合图7A、图7G和图8C，第一复位晶体管T4包括有源层A4、栅极(GLn-1的与有源层A4重叠的部分)、第一电极(例如为源极)和第二电极(例如为漏极)；第二复位晶体管T7包括有源层A7、栅极(栅线GLn-1的与有源层A7重叠的部分)、第一电极(例如为源极)和第二电极(例如为漏极)。第一复位晶体管T4复位晶体管的有源层包括沟道区(有源层A4的与栅线GLn-1重叠的部分)和电极区E1。第二复位晶体管T7的有源层A7包括沟道区(有源层A7的与栅线GLn-1重叠的部分)和电极区E1。第一复位晶体管T4和第二复位晶体管T7共用同一电极区E1。例如，第二连接结构CP2沿第一方向R1延伸，包括在第一方向R1上彼此相对的第一端和第二端；第二子像素的像素电路的第二连接结构CP2在横向R2上位于第一子像素的像素电路的第一复位晶体管T4的有源层的沟道区和第二复位晶体管T7的有源层的沟道区的靠近第一子像素的像素电路的数据线1的一侧。第二连接结构CP2的第一端通过过孔VH6与复位信号线RL电连接，第二连接结构CP2的第二端通过过孔VH7与第二子像素的像素电路的复位晶体管(T4和T7)的有源层的电极区E1电连接。从而，第二连接结构CP2构成第一复位晶体管T4和第二复位晶体管T7的第一电极和第二电极。
结合图7A、图7G和图8C，第二子像素的像素电路的第一复位晶体管T4和第二复位晶体管T7的有源层的电极区E1从第一子像素沿横向延伸到与其相邻的第二子像素中，且第二子像素的像素电路的第一复位晶体管T4 和第二复位晶体管T7的有源层的电极区E1在衬底基板上的正投影与属于第一子像素的像素电路的数据线1在衬底基板上的正投影至少部分重叠。即，该第一复位晶体管T4和该第二复位晶体管T7的有源层的电极区E1与该数据线1相交，以更充分灵活地利用有限的像素区域，形成所需要的便于实现与其他结构连接的半导体层图案。由于与该数据线1的投影交叠的有源层的电极区E1在垂直于衬底基板的方向上距离数据线1所在的第二导电层较远，所以这两者相交不会对彼此之间的信号产生干扰。
需要说明的是，在图7A、图7F、图7J和图7K分别示出了三条数据线1，这三条数据线1分别属于三个相邻的子像素的像素电路；位于中间的数据线1属于第一子像素的像素电路，位于右侧的数据线1属于第二子像素的像素电路。
图9为图6所示像素电路的信号时序图。下面结合图9所示的信号时序图，对图6所示的像素电路的工作原理进行说明。例如，在此以图6中的第一发光控制线EM1与第二发光控制线EM2为同一条共用的发光控制线作为示例。在其他一些实施例中，第一发光控制线EM1与第二发光控制线EM2也可以分别为不同的信号线，分别提供不同的第一发光控制信号和第二发光控制信号。
另外，在此以图9所示的晶体管均为P型晶体管为例。各个P型晶体管的栅极在接入低电平时导通，而在接入高电平时截止。以下实施例与此相同，不再赘述。
如图9所示，像素电路的工作过程包括三个阶段，分别为复位阶段P1、数据写入和补偿阶段P2以及发光阶段P3，图中示出了每个阶段中各个信号的时序波形。
在复位阶段P1，第二栅线Gn-1提供复位信号Rst，第四晶体管T4和第七晶体管T7被复位信号的低电平导通，将复位信号(低电平信号，例如可以接地或为其他低电平信号)施加至第一晶体管T1的第一栅极，并将复位信号施加至N4节点，即将发光元件180复位，从而可以使发光元件180在发光阶段P3之前显示为黑态不发光，改善采用该像素电路的显示装置的对比度等显示效果。同时，第二晶体管T2、第三晶体管T3、第五晶体管T5和 第六晶体管T6被各自接入的高电平信号截止。
在数据写入和补偿阶段P2，第一栅线GLn提供扫描信号Gn-1，数据线DAT提供数据信号Data，第二晶体管T2以及第三晶体管T3导通。同时，第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7被各自接入的高电平信号截止。数据信号Data经过第二晶体管T2、第一晶体管T1和第三晶体管T3后对第一节点N1进行充电(即对存储电容CST充电)，也就是说第一节点N1的电位逐渐增大。容易理解，由于第二晶体管T2开启，第二节点N2的电位保持为Vdata，同时根据第一晶体管T1的自身特性，当第一节点N1的电位增大到Vdata+Vth时，第一晶体管T1截止，充电过程结束。需要说明的是，Vdata表示数据信号Data的电压值，Vth表示第一晶体管T1的阈值电压，由于在本实施例中，第一晶体管T1是以P型晶体管为例就行说明的，所以此处阈值电压Vth可以是负值。
经过数据写入和补偿阶段P2后，第一节点N1和第三节点N3的电位均为Vdata+Vth，也就是说将带有数据信号Data和阈值电压Vth的电压信息被存储在存储电容CST中，以用于后续在发光阶段时，提供灰度显示数据和对第一晶体管T1自身的阈值电压进行补偿。
在发光阶段P3，发光控制线提供发光控制信号EM，第五晶体管T5和第六晶体管T6被发光控制信号EM的低电平导通。第二晶体管T2、第三晶体管T3、第四晶体管T4和第七晶体管T7被各自接入的高电平而截止。同时，第一节点N1的电位Vdata+Vth，第二节点N2的电位为VDD，所以在此阶段第一晶体管T1也保持导通。发光元件180的阳极和阴极分别接入了第一电源线VDD提供的第一电源电压(高电压)和第二电压VSS(低电压)，从而，发光元件180在流经第一晶体管T1的驱动电流的作用下发光。
例如，显示基板还包括：第三信号线，沿所述第一方向延伸，包括穿过所述第一开口周边区域、所述开口间区域和所述第二开口周边区域的第一部分，配置为给所述像素电路提供第三显示信号。所述第三信号线的第一部分与所述栅极同层设置；例如第三显示信号为发光驱动扫描信号(EM线)。
例如，显示基板还包括第二虚拟子像素，第二虚拟子像素包括如图16A所示的第二虚拟像素电路。所述第二虚拟像素电路包括虚拟半导体层，与所 述有源层同层设置，与所述第一部分第二子走线电连接，其中，所述第三信号线的第一部分在所述衬底基板上的正投影与所述虚拟半导体层在所述衬底基板上的正投影至少部分重叠以形成第三补偿电容。
图16A为本公开一实施例提供的一种显示基板中的一个第二虚拟子像素(图中右侧的在虚拟子像素)中的第二虚拟像素电路的平面布局示意图；图16B为沿图16A中的A3-B3线的截面示意图；图16C-图16F为本公开一实施例提供的一种显示基板的第二虚拟像素电路的各层的示意图。
在一些实施例中，例如，开口间区域2014还包括第二虚拟子像素，第二虚拟子像素包括第二虚拟像素电路，如图16A所示。第二虚拟像素电路包括第二补偿电容COM10，第二补偿电容COM10包括第一极板CE10和第二极板CE20。
图16D示出了第二虚拟像素电路的位于第一导电层的一种结构，图16E示出了第二虚拟像素电路的位于第二导电层的结构。
结合图16A-图16B和图16D-图16E，第四补偿电容COM10的第一极板CE10与第一信号线2301同层设置，例如均位于第一导电层，并且，第四补偿电容COM10的第一极板CE10与第一信号线2301电连接。第一信号线2301在衬底基板210上的正投影与第四补偿电容COM10的第二极板CE20在衬底基板210上的正投影至少部分重叠。
如图16D所示，第四补偿电容COM10的第一极CE10板包括：第二主体部分CE100和第三延伸部CE101。第二主体部分CE100位于第一信号线2301的在第二方向R2上的第一侧；第三延伸部CE101自第二主体部分CE100在第二方向R2上朝向第一信号线2301延伸，位于第一信号线2301在第二方向上的第一侧，且位于第二主体部分CE100与第一信号线2301的之间，第二主体部分CE100通过第三延伸部CE101与第一信号线2301电连接。例如，第四补偿电容COM10的第一极CE20板包括第四延伸部CE102，第四延伸部CE102自第一信号线2301朝向远离第二主体部分CE100的方向延伸，位于第一信号线2301的在第二方向R2上的第二侧且与第一信号线2301电连接，第一信号线2301的第二侧与第一信号线2301的第一侧相对，从而进一步增大第四补偿电容COM10的第一极板CE10的面积，如果同时增大第四补偿电容COM10的第二极板的面积，则可进一步增大第四补偿电容COM10，满足对 第一信号线的不同补偿程度的需求。
例如，第二主体部分CE100、第三延伸部CE101、第一信号线2301和第四延伸部CE102一体成型，从而可利用同一次构图工艺形成这些结构，简化显示基板的制作工艺。
结合图16A-图16B与图16E，第四补偿电容COM10的第二极板CE20包括第三主体部分CE200和第五延伸部CE201。第三主体部分CE200位于第一信号线2301的在第二方向R2上的第一侧；第五延伸部CE201自第三主体部分CE200在第二方向R2上朝向第一信号线2301延伸，第一信号线2301在衬底基板210上的正投影与第五延伸部CE201在衬底基板210上的正投影至少部分重叠。
例如，如图16B所示，第四补偿电容COM10的第一极板CE10在衬底基板210上的正投影位于第四补偿电容COM10的第二极板CE20在所述衬底基板210上的正投影内，以最大化利用第四补偿电容COM10的第一极板CE10的面积，利用有限的空间形成所需的第四补偿电容的大小。
例如，如图16E所示，第四补偿电容COM10的第二极板CE20的一部分7921可以与显示区像素电路中的遮光部的位置和图案相同，以保持刻蚀均一性。
例如，第二虚拟子像素包括第二虚拟半导体层，第二虚拟半导体层位于第四补偿电容的第一极板的靠近衬底基板的一侧。图16C示出了第二虚拟子像素的图案，第二虚拟子像素为图16C中右侧的在虚拟子像素A02。结合图16A和图16C所示，第二虚拟半导体层包括间隔开以彼此不连接的第一部分AP21和第二部分AP22；第一部分AP21位于第一信号线2301的第一侧，第二部分AP22位于第一信号线2301的第二侧；第一信号线2301在衬底基板210上的正投影与第一虚拟半导体层在衬底基板210上的正投影不重叠，从而第二虚拟像素电路中不存在真正的薄膜晶体管，不实现显示功能。例如，第四补偿电容COM10在衬底基板210上的正投影与第一虚拟半导体层在衬底基板上的正投影不重叠。
图16F示出了第二虚拟像素电路的位于第三导电层的结构。结合图16A-图16B、图16E和图16F，第二虚拟像素电路包括第二转接电极CP10，第二转接电极CP10与第一虚拟像素电路的第一转接电极，以及显示区域的像素电 路的第一连接部CP1同层设置，例如均位于第三导电层，且与第四补偿电容COM10的第二极板CE20电连接，例如，第二转接电极CP10通过过孔VH40和过孔VH50与第四补偿电容COM10的第二极板CE20电连接，以保持此处与显示基板的显示区域等其他位置的刻蚀均一性。
例如，结合图16A-图16B与图16E，第四补偿电容COM10的第二极板CE20通过过孔VH40和过孔VH50与第一电源线VDD连接，例如与第一电源线VDD的第一走线2424连接，以给第四补偿电容COM10的第二极板CE20提供第一电源电压，以形成第四补偿电容COM10。
例如，第二虚拟半导体层的第二部分AP22均配置为通过第二虚拟像素电路被寄予电信号；第一虚拟半导体层的第一部分AP21在第一方向R1上具有彼此相对的第一端P21和第二端P22，第二端P22配置为通过第二虚拟像素电路被寄予所述电信号，第一端P21与第二端P22连接，从而可将来自第二端P2的电信号传输给第一端P21，防止由于第一端P21无信号输入导致的信号漂移。例如，如图16A所示，第二端P22与第一电源线VDD的第二子走线2424电连接，例如通过过孔VH20电连接，从而将来自第一电源线VDD的第二子走线2424的第一电源电压传输给第二端P22和第一端P21。该第一电源线VDD的结构不限于图16A-16F中的情况，只要将第一电源线VDD与第二端P22连接即可。
例如，如图16A所示，所述第三信号线例如发光扫描信号线EM的第一部分在衬底基板210上的正投影与虚拟半导体层在衬底基板210上的正投影至少部分重叠以形成第三补偿电容，以对第三信号线的负载进行补偿，获得更加均匀的显示效果。
当然，第二虚拟像素结构不限于是图16A-16F所示的情况，图16A-16F中，数据线与源漏极122/123同层。例如，当数据线位于源漏极122/123的远离衬底基板的一侧时，也可以设置上述虚拟半导体层与第三信号线例如发光扫描信号线EM重叠，以形成第三补偿电容。本公开实施例对此不作限定。
在如图2B和图2C所示的实施例中，第二开口区域202B与第一开口区域202A沿第一方向R1排列，由此，开口间区域2014在第一方向R1上位于第一开口区域202A和第二开口区域202B之间。第一显示区域2011位于第一开口区域202A的远离开口间区域2014的一侧，第二显示区域2012位 于第二开口区域202B的远离开口间区域2014的一侧。这种情况下，第一显示区域2011位于第一开口区域202A的第一侧，第二显示区域2012位于第二开口区域201B的第二侧。即，第一显示区域、第一开口区域、开口间区域、第二开口区域和第二显示区域沿所述第一方向依次排列。分别对于第一开口区域202A和第二开口区域201B来说，仍然满足第一显示区域2011位于第一开口区域202A的第一侧，第二显示区域2012位于第一开口区域202A的第二侧，该第一侧与该第二侧在第一方向R1上彼此相对。第一信号线23沿第一方向R1依次穿过第一显示区域2011、第一开口周边区域203A、开口间区域2014、第二开口周边区域203B和第二显示区域2012。
如图2B所示，第一信号线2301包括位于第一开口周边区域203A的第一引线部E1A1/E2A2(即,以一条第一信号线为例，例如第一引线部为图2B中的直线段E1A1和直线段E2A2)和位于第一开口周边区域203A的横向绕线部A1A2(即横向绕线部为图2B中的曲线段A1A2)；横向绕线部A1A2部分围绕第一开口201A设置。第二信号线24配置为给第一像素阵列提供第二显示信号，沿与第一方向R1相交的第二方向R2穿过第一开口周边区域203A，包括位于第一开口周边区域203A的纵向绕线部C1C2，即纵向绕线部为图2B中的曲线段C1C2；纵向绕线部C1C2部分围绕第一开口201A设置。第一引线部E1A1/E2A2在衬底基板上的正投影与第二信号线24在衬底基板上的正投影分别具有第一重叠区S1/S2，即两者交叉处的区域。横向绕线部A1A2在衬底基板上的正投影与纵向绕线部C1C2在衬底基板上的正投影具有第二重叠区，例如这两者在A1C1段和D1A2段重叠，第二重叠区为A1C1和D1A2所代表的区域。如此，由于第一重叠区和第二重叠区的形成，在垂直于衬底基板的方向上彼此重叠的第一信号线2301与第二信号线24之间形成补偿电容，补偿了第一信号线上的负载，从而减小由于第一像素阵列中不同行像素的像素数量不同而导致连接不同行像素的第一信号线的负载不同而造成的显示差异，使第一显示区域2011和第二显示区域2012的显示效果与显示区域201中不设置有第一开口区域202A的像素行的显示效果一致，提升显示质量。同时，上述走线方式还能够减小第一信号线与第二信号线的排布空间，尽可能减小当第一开口周边区域203A占用的面积。因此，例如 当通过第一开口区域202A实现屏下摄像功能时减小第一开口区域202A对该区域显示效果的影响，或者，在其他实施例中，当第一开口周边区域203A位于边框区204中时，也可减小边框区204的宽度，进而有助于实现显示基板20的窄边框、大屏化设计。例如，如图2B所示，第一信号线2301的引线部E1A1在衬底基板上的正投影与第二信号线24的纵向绕线部在衬底基板上的正投影具有第一重叠区。即，所述多条第一信号线中的每条沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域和所述第二显示区域，且包括位于所述第一开口周边区域的第一引线部和横向绕线部，所述横向绕线部部分围绕所述第一开口设置，所述第一引线部与所述横向绕线部连接；所述多条第一信号线的横向绕线部在所述衬底基板上的正投影分别与所述多条第二信号线的所述部分的纵向绕线部在所述衬底基板上的正投影具有重叠区。
图17为本公开一实施例提供的一种显示基板中的一个第二虚拟子像素中的第二虚拟像素电路的平面布局示意图。图17与图16A的区别主要在于，数据线DATA位于源漏极122/123的远离衬底基板的一侧，且数据线DATA在第一方向上与第一电源线VDD的相对位置不同。其他结构可参考图16A。
图10A是本公开一实施例提供的一种显示基板的第一开口区域的放大示意图。图10A和图2B-2C相比的区别在于，显示基板还包括第一浮置电极41/42。多条第二信号线的纵向绕线部中最靠近第一开口201A的纵向绕线部为边缘纵向绕线部2401/2402，第一浮置电极41/42与边缘纵向绕线部同层设置且位于边缘纵向绕线部2401/2402的靠近第一开口201A的一侧。第一浮置(floating)电极41/42与边缘纵向绕线部同层设置且位于边缘纵向绕线部2401/2402的靠近第一开口201A的一侧，由此，可以避免边缘纵向绕线部刻蚀性差异，增大刻蚀均一性。第一浮置电极不加载任何电信号，不会对其周围的其他信号线造成干扰。
例如，如图10所示，多个像素包括分别沿第二方向R2延伸的第一像素列和第二像素列；第一开口201A具有在第一方向R2上彼此相对的第一侧和第二侧，以及在第二方向R2上彼此相对的第三侧和第四侧。显示基板包括与第一开口201A对应设置的两条边缘纵向绕线部，两条边缘纵向绕线部包括： 配置为给第一像素列提供第二显示信号的边缘纵向绕线部，给第一像素列提供所述第二显示信号的所述边缘纵向绕线部在所述第一开口的第一侧部分地围绕所述第一开口；配置为给第二像素列提供第二显示信号的边缘纵向绕线部，给第二像素列提供第二显示信号的边缘纵向绕线部在第一开口的第二侧部分地围绕所述第一开口；第一浮置电极包括：第一部分41和第二部分42。第一部分41位于给第一像素列提供第二显示信号的边缘纵向绕线部的靠近第一开口201A的一侧；第二部分42位于给第二像素列提供第二显示信号的边缘纵向绕线部的靠近第一开口201A的一侧。
例如，第一浮置电极与边缘纵向绕线部的线宽和延伸方向基本相同，以进一步增大刻边缘纵向绕线部的蚀均一性。
例如，多条第二信号线中相邻两条第二信号线之间具有第一间隔，例如，相邻两条第二信号线的纵向绕线部之间具有第一间隔，第一浮置电极与边缘纵向绕线部之间的间隔与第一间隔基本相等，以进一步增大边缘纵向绕线部的刻蚀均一性。
例如，在一些实施例中，如图10A所示，第一浮置电极的第一部分41与第一浮置电极的第二部分42彼此间隔开。在另一些实施例中，如图10B和图10C所示，第一浮置电极的第一部分41与第一浮置电极的第二部分一体成型。
例如，如图10B所示，第一浮置电极的第一部分41与第一浮置电极的第二部分42构成的整体的平面形状为围绕第一开口201A的不封闭的环形，该不封闭的环形具有的开口可以更好地释放聚集的电荷，避免对周边信号线的信号干扰。当然，在一些实施例中，例如，如图10C所示，第一浮置电极的第一部分41与第一浮置电极的第二部分42构成的整体的平面形状也可以为封闭的环形。
图11是图10A中的局部H的放大示意图，图16是图11中的局部G的放大示意图，图13是图16中的局部I的放大示意图，图14是图13中的局部J的放大示意图。所述显示基板还包括第二浮置电极，多条第一信号线的横向绕线部中最靠近第一开口201A的横向绕线部为边缘横向绕线部，第二浮置电极与边缘横向绕线部同层设置且与第一浮置电极异层设置，第二浮置电极位于边缘横向绕线部的靠近第一开口的一侧，第二浮置电极在衬底基板 210上的正投影与第一浮置电极在衬底基板210上的正投影具有重叠区，由此，可以避免边缘横向绕线部刻蚀性差异，增大刻蚀均一性。与第一浮置电极类似，第二浮置电极与边缘横向绕线部的线宽和延伸方向基本相同，以进一步增大边缘横向绕线部的刻蚀均一性。
例如，多条第一信号线中相邻两条第二信号线之间具有第二间隔，例如，相邻两条第一信号线的横向绕线部之间具有第二间隔，第二浮置电极与边缘横向绕线部之间的间隔与第二间隔基本相等，以进一步增大边缘横向绕线部的刻蚀均一性。
例如，第一信号线包括多条栅扫描信号线和多条复位信号线。如图13所示，栅扫描信号线2303A(这种情况下该部分为栅扫描信号线的第一部分2303A)与复位信号线2301A(这种情况下该部分为栅扫描信号线的第一部分2301A)异层设置，并且，栅扫描信号线2303A的横向绕线部2303A-1与复位信号线2301A的横向绕线部2301A-1在第二方向上交替排布。多条栅扫描信号线2303A中最靠近第一开口201A的栅扫描信号线2303A为边缘栅扫描信号线2303A-0，多条复位信号线2301A中最靠近第一开口201A的复位信号线为边缘复位信号线2301A-0。第二浮置电极包括：第一子浮置电极511和第二子浮置电极512。第一子浮置电极511与栅扫描信号线同层设置且位于边缘栅扫描信号线2303A的靠近第一开口201A的一侧；第二子浮置电极512与复位信号线2301A-0同层设置且位于边缘复位信号线2301A-0的靠近第一开口201A的一侧；边缘栅扫描信号线2303A-0比边缘复位信号线2301A-0远离第一开口201A，第一子浮置电极511比第二子浮置电极512远离第一开口201A，第一浮置电极在衬底基板上的正投影至少与所第一子浮置电极具有重叠区，即可解决边缘复位信号线2301A-0和边缘复位信号线2301A-0的刻蚀均一性问题。或者，边缘复位信号线2301A-0比边缘栅扫描信号线2303A-0远离第一开口201A，第二子浮置电极512比第一子浮置电极511远离第一开口201A，第一浮置电极在衬底基板上的正投影至少与第二子浮置电极具有重叠区，也可解决边缘复位信号线2301A-0和边缘复位信号线2301A-0的刻蚀均一性问题。
在一些实施例中，例如，如图13所示，多条第二信号线的所述部分包括第一部分第二信号线2410和第二部分第二信号线2412，第一部分第二信号线 2410与第二部分第二信号线2412异层设置且在所述第一方向上交替排布，其所处的层请见之前的描述。第一部分第二信号线2410中最靠近所述第一开口的第二信号线为边缘第一子数据信号线，第二部分第二信号线2412中最靠近第一开口的第二信号线为边缘第二子数据信号线；第一部分第二信号线中的每条第二信号线的纵向绕线部在衬底基板210上的正投影与一条栅驱动扫描信号线的横向绕线部在衬底基板上的正投影具有重叠区，第二部分第二信号线中的每条第二信号线的纵向绕线部在所述衬底基板上的正投影与每条所述复位信号线的横向绕线部在所述衬底基板上的正投影具有重叠区；第一浮置电极包括：第三子浮置电极411和第四子浮置电极412。第三子浮置电极411与第一部分第二信号线2410同层设置且位于边缘第一子数据信号线的靠近第一开口的一侧；第四子浮置电极412与第二部分第二信号线2412同层设置且位于边缘第二子数据信号线的靠近第一开口201A的一侧；第三子浮置电极411在衬底基板上的正投影与第一子浮置电极511具有重叠区，第四子浮置电极412在衬底基板上的正投影与第二子浮置电极512具有重叠区。
例如，第一部分第二信号线2410(此处指其纵向绕线部)与源漏极122/123同层设置，述第二部分第二信号线2412(此处指其纵向绕线部)位于第一部分第二信号线2410的远离衬底基板的一侧；多条栅扫描信号线与所储电容的第二极板同层设置，多条复位信号线与所述存储电容CST的第一极板CE1同层设置；或者，所述多条栅扫描信号线与所述存储电容CST的第一极板CE1同层设置，所述多条复位信号线与所述存储电容CST的第二极板CE2同层设置。
上述实施例中，栅扫描信号线和复位信号线在第一开口处均绕线设置，而非在第一开口处断开。
例如，在一些实施例中，所述多条第一信号线包括多条栅扫描信号线和多条复位信号线，所述栅扫描信号线与所述复位信号线异层设置；每条所述栅扫描信号线沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域和所述第二显示区域，且包括位于所述第一开口周边区域的第一引线部和横向绕线部，其中，所述横向绕线部部分地围绕所述第一开口设置，所述第一引线部与所述横向绕线部连接；每条所述复位信号线包括：第一部分和第二部分。第一部分沿所述第一方向穿过所述第一显示区域；第二部分沿 所述第一方向穿过所述第二显示区域，与所述第一部分被所述第一开口区域间隔。即，栅扫描信号线在第一开口处绕线，复位信号线在第一开口处断开。
例如，在一些实施例中，所述多条第一信号线包括多条栅扫描信号线和多条复位信号线，所述栅扫描信号线与所述复位信号线异层设置；每条所述复位信号线沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域和所述第二显示区域，且包括位于所述第一开口周边区域的第一引线部和横向绕线部，其中，所述横向绕线部部分地围绕所述第一开口设置，所述第一引线部与所述横向绕线部连接；每条所述栅扫描信号线包括：第一部分和第二部分。该第一部分沿所述第一方向穿过所述第一显示区域；该第二部分沿所述第一方向穿过所述第二显示区域，与所述第一部分被所述第一开口区域间隔。即，复位信号线在第一开口处绕线，栅扫描信号线在第一开口处断开。
例如，在一些实施例中，所述多条第一信号线包括多条栅扫描信号线和多条复位信号线，所述栅扫描信号线与所述复位信号线异层设置；每条所述栅扫描信号线包括：第一部分和第二部分。该第一部分沿所述第一方向穿过所述第一显示区域；该第二部分沿所述第一方向穿过所述第二显示区域，与所述第一部分被所述第一开口区域间隔；并且，每条所述复位信号线包括：第一部分和第二部分，该第一部分沿所述第一方向穿过所述第一显示区域；该第二部分沿所述第一方向穿过所述第二显示区域，与所述第一部分被所述第一开口区域间隔。即，栅扫描信号线和复位信号线在第一开口处均断开。
当栅扫描信号线和/或复位信号线在第一开口处断开时，可采用双边驱动的方式给断开的信号线分别从基板的在第一方向上的两侧加载驱动信号，具体参考常规技术。
例如，在一些实施例中，显示基板还可以包括外侧浮置电极。所述多条第二信号线的所述部分的纵向绕线部中最远离所述第一开口的纵向绕线部为外边缘纵向绕线部，所述外侧浮置电极与所述外边缘纵向绕线部同层设置且位于所述外边缘纵向绕线部的远离所述第一开口的一侧，以增大外边缘纵向绕线部的刻蚀均一性。
例如，多条第二信号线的所述部分的每条所述第二信号线还包括第二引线部。第二引线部沿所述第二方向延伸且与所述纵向绕线部连，。所述第二引 线部的排布密度大于所述纵向绕线部的排布密度。所述第二引线部的线宽与所述纵向绕线部的线宽基本相等，由于排布密度的差异和刻蚀工艺的限制，制作工艺中使第二引线部的设计线宽小大于纵向绕线部的设计线宽，才能够使得形成的两者最终的线宽基本相等。或者，如果不做设计线宽的差异，则所述第二引线部的线宽小于所述纵向绕线部的线宽。
本公开至少一实施例提供一种显示装置，包括上述任一的显示基板。该显示装置例如可以为有机发光二极管显示装置、量子点发光二极管显示装置等具有显示功能的装置或其他类型的装置，本公开的实施例对此不作限制。
本公开实施例提供的显示装置的结构、功能及技术效果等可以参考上述本公开实施例提供的显示基板中的相应描述，在此不再赘述。
例如，本公开至少一实施例提供的显示装置可以为显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板，包括：
    第一开口区域，包括第一开口和围绕所述第一开口的第一开口周边区域；
    第二开口区域，与所述第一开口区域沿所述第一方向相邻设置，且包括第二开口和围绕所述第二开口的第二开口周边区域；
    开口间区域，位于所述第一开口区域和所述第二开口区域之间，其中，所述开口间区域、所述第一开口周边区域和所述第二开口周边区域三者中的至少一者包括第一虚拟子像素；
    显示区域，至少部分围绕所述第一开口区域、所述第二开口区域和所述开口间区域，且包括多个像素，每个所述像素包括多个子像素，每个所述子像素包括像素电路，所述像素电路包括：
    晶体管，包括有源层、栅极和源漏极；
    发光元件，与所述晶体管的源漏极之一连接；以及
    存储电容，包括第一极板和第二极板，其中，所述栅极、所述存储电容的第一极板同层设置；以及
    第一信号线，沿第一方向延伸，包括穿过所述第一开口周边区域、所述开口间区域和所述第二开口周边区域的第一部分，配置为给所述像素电路提供第一显示信号，其中，所述第一信号线的第一部分穿过所述第一虚拟子像素，所述第一虚拟子像素包括虚拟像素电路，所述虚拟像素电路包括第一补偿电容，所述第一补偿电容包括：
    第一极板，与所述第一信号线的第一部分同层设置且与第一信号线电连接，且与所述存储电容的第二极板同层设置；以及
    第二极板，与所述第一补偿电容的第一极板异层设置且绝缘，其中，所述第一补偿电容的第二极板在所述衬底基板上的正投影与所述第一补偿电容的第一极板在所述衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示基板，其中，所述第一补偿电容的第一极板包括：
    第一延伸部，与所述第一信号线的第一部分连接，自所述第一信号线的第一部分延伸且位于所述第一信号线的第一部分在第二方向上的第一侧，所述第二方向与所述第一方向相交；
    第二延伸部，与所述第一信号线的第一部分连接，自所述第一信号线的第一部分延伸且位于所述第一信号线的第一部分在所述第二方向上与所述第一侧相对的第二侧。
  3. 根据权利要求2所述的显示基板，其中，所述第一延伸部、所述第二延伸部和所述第一信号线的第一部分一体成型。
  4. 根据权利要求1所述的显示基板，其中，所述第一补偿电容的第二极板的材料包括半导体材料，且与所述有源层同层设置。
  5. 根据权利要求1所述的显示基板，其中，所述虚拟像素电路还包括第二补偿电容，所述第二补偿电容包括：
    第一极板，其中，所述第一补偿电容的第一极板复用作所述第二补偿电容的第一极板；以及
    第二极板，与所述第二补偿电容的第一极板异层设置且绝缘，且与所述源漏极同层设置，其中，所述第二补偿电容的第二极板在所述衬底基板上的正投影与所述第二补偿电容的第一极板在所述衬底基板上的正投影至少部分重叠。
  6. 根据权利要求5所述的显示基板，其中，所述第二补偿电容的第二极板与所述第一补偿电容的第二极板电连接。
  7. 根据权利要求6所述的显示基板，其中，所述显示基板还包括第一电源线，其中，所述第一电源线连接第一电压端，配置为给所述像素电路提供第一电源电压，且与所述存储电容的第二极板连接，所述第一电源线包括：
    多条第一子走线，沿所述第一方向延伸；以及
    多条第二子走线，沿与所述第一方向相交的第二方向延伸，且与所述多条第一子走线电连接，其中，
    所述多条第二子走线中的第一部分第二子走线穿过所述开口间区域且穿过所述第一虚拟子像素，所述第二补偿电容的第二极板包括第一部分和第二部分，所述第一部分第二子走线与所述第二补偿电容的第二极板的第一部分 同层设置且电连接以作为所述第二补偿电容的第二极板的第二部分，且所述第一部分第二子走线与所述第一补偿电容的第二极板电连接。
  8. 根据权利要求7所述的显示基板，还包括：
    第一绝缘层，位于所述第一补偿电容的第二极板与所述栅极之间；
    第二绝缘层，位于所述栅极与所述第一补偿电容的第一极板之间；以及
    第三绝缘层，位于所述第一补偿电容的第一极板与所述第二补偿电容的第二极板之间，其中，
    所述第一部分第二子走线通过贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层且暴露所述第一补偿电容的第二极板的第一过孔与所述第一补偿电容的第二极板电连接。
  9. 根据权利要求7所述的显示基板，其中，所述第一部分第二子走线与所述第二补偿电容的第二极板一体成型。
  10. 根据权利要求7所述的显示基板，还包括：
    多条第二信号线，配置为给所述多个子像素提供第二显示信号，其中，所述多条第二信号线中的第一部分第二信号线沿所述第二方向穿过所述开口间区域且穿过所述第一虚拟子像素，所述第一部分第二信号线位于所述第二补偿电容的第二极板的远离所述衬底基板的一侧；
    所述第二补偿电容的第二极板的第一部分具有镂空区域，穿过所述第二补偿电容的第二极板所在的第一虚拟子像素的所述第一部分第二信号线在所述衬底基板上的正投影与所述镂空区域至少部分重叠。
  11. 根据权利要求10所述的显示基板，其中，所述第二补偿电容的第二极板具有多个所述镂空区域，所述多个镂空区域沿所述第二方向彼此间隔排列。
  12. 根据权利要求11所述的显示基板，其中，所述多个镂空区域包括相邻的第一镂空区域和第二镂空区域，所述第一镂空区域的在所述第二方向上的长度与所述第二镂空区域的在所述第二方向上的长度不同。
  13. 根据权利要求11所述的显示基板，其中，所述第二补偿电容的第二极板的位于所述第一镂空区域与所述第二镂空区域之间的部分沿所述第一方向是连续的；
    所述第二补偿电容的第二极板包括在所述第二方向上彼此相对的第一边缘和第二边缘，所述第一边缘和第二边缘中的至少之一被所述镂空区域断开。
  14. 根据权利要求10所述的显示基板，其中，所述第一虚拟子像素中，所述第一补偿电容的第二极板的覆盖整个所述第一虚拟子像素，所述第一补偿电容的第一极板在所述衬底基板上的正投影位于所述第一补偿电容的第二极板在所述衬底基板上的正投影内；
    所述第一补偿电容的大小小于所述第二补偿电容的大小。
  15. 根据权利要求1所述的显示基板，其中，所述显示区域包括：
    第一显示区域，位于所述第一开口区域的远离所述开口间区域的一侧；以及
    第二显示区域，位于所述第二开口区域的远离所述开口间区域的一侧，其中，所述第一显示区域和所述第二显示区域均包括所述多个像素，所述第一显示区域和所述第二显示区域构成的整体包括沿第一方向延伸的多个像素行，所述多个像素行被所述第一开口区域、所述开口间区域和所述第二开口区域三者构成的整体断开；
    所述第一信号线沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域、所述开口间区域、所述第二开口周边区域和所述第二显示区域，所述第一信号线还包括穿过所述第一显示区域的第二部分和穿过所述第二显示区域的第三部分，所述第二部分和所述第三部分与所述栅极同层设置。
  16. 根据权利要求15所述的显示基板，还包括：
    第一连接结构，位于所述第一开口周边区域，且与所述第一信号线的第二部分和所述第一信号线的第一部分均异层设置，其中，所述第一信号线的第二部分与所述第一连接结构电连接，所述第一信号线的第一部分与所述第一连接结构电连接；以及
    第二连接结构，位于所述第二开口周边区域，且与所述第一信号线的第一部分和所述第一信号线的第三部分均异层设置，其中，所述第一信号线的第一部分与所述第二连接结构电连接，所述第一信号线的第三部分与所述第二连接结构电连接。
  17. 根据权利要求16所述的显示基板，其中，所述第一连接结构和所述 第二连接结构与所述源漏极同层设置。
  18. 根据权利要求1-17任一所述的显示基板，其中，所述第一信号线为栅扫描信号线，所述第一显示信号为栅扫描信号。
  19. 根据权利要求7-17任一所述的显示基板，还包括：
    第三信号线，沿所述第一方向延伸，包括穿过所述第一开口周边区域、所述开口间区域和所述第二开口周边区域的第一部分，配置为给所述像素电路提供第三显示信号，其中，所述第三信号线的第一部分与所述栅极同层设置；
    所述虚拟像素电路包括：
    虚拟半导体层，与所述有源层同层设置，与所述第一部分第二子走线电连接，其中，所述第三信号线的第一部分在所述衬底基板上的正投影与所述虚拟半导体层在所述衬底基板上的正投影至少部分重叠以形成第三补偿电容。
  20. 一种显示装置，包括根据权利要求1-19任一所述的显示基板。
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