WO2021243876A1 - 显示基板以及显示装置 - Google Patents
显示基板以及显示装置 Download PDFInfo
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- WO2021243876A1 WO2021243876A1 PCT/CN2020/114625 CN2020114625W WO2021243876A1 WO 2021243876 A1 WO2021243876 A1 WO 2021243876A1 CN 2020114625 W CN2020114625 W CN 2020114625W WO 2021243876 A1 WO2021243876 A1 WO 2021243876A1
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Definitions
- the embodiment of the present disclosure relates to a display substrate and a display device.
- the display screen of the display device is developing in the direction of large-screen and full-screen.
- a display device such as a mobile phone, a tablet computer, etc.
- the camera device is usually arranged on a side outside the display area of the display screen.
- the camera device can be combined and overlapped with the display area of the display screen to reserve a place for the camera device in the display area to maximize the display area of the display screen.
- At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a first opening area, a second opening area, an area between openings, a display area, and a first signal line.
- the first opening area includes a first opening and a first opening peripheral area surrounding the first opening;
- a second opening area is arranged adjacent to the first opening area along the first direction, and includes a second opening and a surrounding area.
- the second opening peripheral area of the second opening; the inter-opening area is located between the first opening area and the second opening area, the inter-opening area, the first opening peripheral area and the second opening area
- At least one of the three opening peripheral regions includes a first dummy sub-pixel; a display region at least partially surrounds the first opening region, the second opening region, and the inter-opening region, and includes a plurality of pixels, each The pixel includes a plurality of sub-pixels, each of the sub-pixels includes a pixel circuit, the pixel circuit includes: a transistor, a light-emitting element, and a storage capacitor, including an active layer, a gate, and a source and drain; a light-emitting element and the transistor One of the source and drain of the storage capacitor is connected; the storage capacitor includes a first plate and a second plate, the gate and the first plate of the storage capacitor are arranged in the same layer; the first signal line extends along the first direction, including A first portion passing through the peripheral area of the first opening
- the first electrode plate is provided on the same layer as the first part of the first signal line and is electrically connected to the first signal line, and is provided on the same layer as the second electrode plate of the storage capacitor; the second electrode plate is the same layer as the first part of the first signal line.
- the first plate of the compensation capacitor is arranged in different layers and insulated, wherein the orthographic projection of the second plate of the first compensation capacitor on the base substrate and the first plate of the first compensation capacitor are in place. The orthographic projections on the base substrate at least partially overlap.
- At least one embodiment of the present disclosure further provides a display substrate.
- the display substrate includes a base substrate.
- the base substrate includes a first opening area, a display area, a plurality of first signal lines, a plurality of second signal lines, and a first opening area.
- Floating electrode is a first electrode.
- the first opening area includes a first opening and a first opening peripheral area surrounding the first opening; a display area at least partially surrounds the first opening area, and includes: a first display area located at the second opening area of the first opening area And a second display area located on the second side of the first opening area, wherein the first side and the second side are opposite to each other in the first direction, and the first display area and the
- the second display area includes a plurality of pixels; a plurality of first signal lines are configured to provide first display signals to the plurality of pixels, extend along the first direction and pass through the first display area and the first display area.
- the plurality of second signal lines are configured to provide second display signals to the plurality of pixels, extend in a second direction intersecting the first direction, and a portion of the plurality of second signal lines extends along the The second direction passes through the peripheral area of the first opening, and each second signal line of the portions of the plurality of second signal lines includes a longitudinal winding portion located in the peripheral area of the first opening, wherein The longitudinal winding portion is partially arranged around the first opening; the longitudinal winding portion closest to the first opening among the longitudinal winding portions of the plurality of second signal lines is an edge longitudinal winding portion, The first floating electrode and the edge longitudinal winding portion are arranged in the same layer and located on a side of the edge longitudinal winding portion close to the first opening.
- At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
- Figure 1 is a schematic plan view of a display substrate
- FIG. 2A is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
- FIG. 2B is a partial enlarged schematic diagram of FIG. 2A including a first opening area and a second opening area;
- FIG. 2C is a partial enlarged schematic diagram of FIG. 2A including the first opening area and the area between the openings;
- 3A is a schematic cross-sectional view of sub-pixels in the display area of the display substrate
- 3B is another schematic cross-sectional view of sub-pixels in the display area of the display substrate
- FIG. 4A is a schematic diagram of a planar layout of a first dummy pixel circuit in a display substrate according to an embodiment of the present disclosure
- Fig. 4B is a schematic cross-sectional view taken along line A2-B2 in Fig. 4A;
- 4C-4G are schematic diagrams of various layers of a first dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure
- 4H is a schematic diagram of another first electrode plate of a first compensation capacitor of a display substrate provided by an embodiment of the present disclosure
- Figure 4J is a partial view showing the substrate
- FIG. 5A is an enlarged schematic diagram of part C in FIG. 2C;
- FIG. 5B is an enlarged schematic diagram of part D in FIG. 2C;
- FIG. 5C is an enlarged schematic diagram of part E in FIG. 2C;
- FIG. 5D is an enlarged schematic diagram of part F in FIG. 2C;
- FIG. 5E is an enlarged schematic diagram of the area where the first signal line and the second signal line are changed layers
- Figures 5F-5H are schematic cross-sectional views taken along lines A4-B4, A5-B5, and A6-B6 in Figure 5E, respectively;
- FIG. 6 is an equivalent circuit diagram of a pixel circuit in an array substrate provided by an embodiment of the disclosure.
- FIG. 7A is a schematic diagram of a planar layout of a pixel circuit in an array substrate provided by an embodiment of the present disclosure
- 7B-7K are schematic diagrams of various layers of a pixel circuit of an array substrate provided by an embodiment of the present disclosure.
- Fig. 8A is a schematic cross-sectional view taken along the line A-A' in Fig. 7A;
- Fig. 8B is a schematic cross-sectional view taken along the line B-B' in Fig. 7A;
- FIG. 9 is a signal timing diagram of the working process of the pixel circuit shown in FIG. 6;
- FIG. 10A is an enlarged schematic diagram of a first opening area of a display substrate provided by an embodiment of the present disclosure
- 10B is an enlarged schematic diagram of a first opening area of another display substrate provided by an embodiment of the present disclosure.
- FIG. 10C is an enlarged schematic diagram of a first opening area of another display substrate provided by an embodiment of the present disclosure.
- FIG. 11 is an enlarged schematic diagram of part H in FIG. 10A;
- FIG. 12 is an enlarged schematic diagram of part G in FIG. 11;
- FIG. 13 is an enlarged schematic diagram of part I in FIG. 16;
- FIG. 14 is an enlarged schematic diagram of part J in FIG. 13;
- FIG. 15 is a schematic plan view of yet another display substrate according to an embodiment of the disclosure.
- 16A is a schematic plan view of a second virtual pixel circuit in a second virtual sub-pixel in a display substrate according to an embodiment of the present disclosure
- Fig. 16B is a schematic cross-sectional view taken along line A3-B3 in Fig. 16A
- 16C-16F is a schematic diagram of each layer of a second dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure
- FIG. 17 is a schematic plan view of a second virtual pixel circuit in a second virtual sub-pixel in a display substrate according to an embodiment of the present disclosure.
- Fig. 1 is a schematic plan view of a display substrate.
- the display substrate 10 includes a display area 101 and a peripheral area 102 surrounding the display area 101.
- the display area 101 is designed, for example, in an irregular shape with a notch 103 on at least one side.
- Devices such as cameras, distance sensors, etc. are arranged in the area of the notch 103, thereby contributing to the realization of the narrow frame design of the display substrate 10.
- the display area 101 includes a first display area 1011 and a second display area 1012 located on the left and right sides of the notch 103.
- the first display area 1011 and the second display area 1012 are opposite to the bottom of the display area 101.
- the sides are at the same horizontal position, and are driven by one or more scanning signal lines (gate lines) that extend horizontally from the left and right in the figure, for example.
- the first display area and the second display area may also be in different horizontal positions.
- the first display area and the second display area are arranged along the curved edge of the display screen, and the first display area and the second display area may not be in the same horizontal position.
- the number of pixels in the same row of pixels in the first display area 1011 and the second display area 1012 is greater than that in the display area 101 except for the first display area 1011 and the second display area 1012.
- the number of pixels in a row of pixels in a part is small.
- the number of pixels connected to the horizontally extending signal lines used to provide display signals (such as scanning signals) for pixels in the same row of the first display area 1011 and the second display area 1012 It is different from the number of pixels connected to the signal lines used to provide electrical signals (such as scanning signals) for a row of pixels in other parts of the display area 101 except for the first display area 1011 and the second display area 1012, and the number of pixels connected in the notch
- the number of pixels in different rows of pixels in the first display area 1011 and the second display area 1012 may also be different.
- the display substrate 10 because the number of pixels in different rows of pixels is different, the load of the signal lines connecting the pixels of different rows is different, and the signal transmission speeds of these signal lines are different. The difference between the actual display signal and the design value is The deviation is different, which will affect the display effect of the display substrate.
- load compensation can be performed on these signal lines with different loads, so that the loads of these signal lines are basically the same, thereby reducing the adverse effect of the notch 103 on the display quality.
- At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a first opening area, a second opening area, an area between openings, a display area, and a first signal line.
- the first opening area includes a first opening and a first opening peripheral area surrounding the first opening;
- a second opening area is arranged adjacent to the first opening area along the first direction, and includes a second opening and a surrounding area.
- the second opening peripheral area of the second opening; the inter-opening area is located between the first opening area and the second opening area, the inter-opening area, the first opening peripheral area and the second opening area
- At least one of the three opening peripheral regions includes a first dummy sub-pixel; a display region at least partially surrounds the first opening region, the second opening region, and the inter-opening region, and includes a plurality of pixels, each The pixel includes a plurality of sub-pixels, each of the sub-pixels includes a pixel circuit, and the pixel circuit includes: a transistor, a light-emitting element, and a storage capacitor, including an active layer, a gate, and a source and drain; a light-emitting element and the transistor One of the source and drain of the storage capacitor is connected; the storage capacitor includes a first plate and a second plate, the gate and the first plate of the storage capacitor are arranged in the same layer; the first signal line extends along the first direction, including A first portion passing through the peripheral area of the first
- the first electrode plate is provided on the same layer as the first part of the first signal line and is electrically connected to the first signal line, and is provided on the same layer as the second electrode plate of the storage capacitor; the second electrode plate is the same layer as the first part of the first signal line.
- the first plate of the compensation capacitor is arranged in different layers and insulated, wherein the orthographic projection of the second plate of the first compensation capacitor on the base substrate and the first plate of the first compensation capacitor are in place. The orthographic projections on the base substrate at least partially overlap.
- At least one embodiment of the present disclosure further provides a display substrate.
- the display substrate includes a base substrate.
- the base substrate includes a first opening area, a display area, a plurality of first signal lines, a plurality of second signal lines, and a first opening area.
- Floating electrode is a first electrode.
- the first opening area includes a first opening and a first opening peripheral area surrounding the first opening; a display area at least partially surrounds the first opening area, and includes: a first display area located at the second opening area of the first opening area And a second display area located on the second side of the first opening area, wherein the first side and the second side are opposite to each other in the first direction, and the first display area and the
- the second display area includes a plurality of pixels; a plurality of first signal lines are configured to provide first display signals to the plurality of pixels, extend along the first direction and pass through the first display area and the first display area.
- the plurality of second signal lines are configured to provide second display signals to the plurality of pixels, extend in a second direction intersecting the first direction, and a portion of the plurality of second signal lines extends along the The second direction passes through the peripheral area of the first opening, and each second signal line of the portions of the plurality of second signal lines includes a longitudinal winding portion located in the peripheral area of the first opening, wherein The longitudinal winding portion is partially arranged around the first opening; the longitudinal winding portion closest to the first opening among the longitudinal winding portions of the plurality of second signal lines is an edge longitudinal winding portion, The first floating electrode and the edge longitudinal winding portion are arranged in the same layer and located on a side of the edge longitudinal winding portion close to the first opening.
- FIG. 2A is a schematic plan view of a display substrate according to an embodiment of the disclosure
- FIG. 2B is a partial enlarged schematic view of FIG. 2A including a first opening area and a second opening area.
- the display substrate 20 includes a base substrate, and the base substrate includes a first opening area 202A, a second opening area 202B, an inter-opening area 2014, a display area 201, and a first signal line 23.
- the first opening area 202A includes a first opening 201A and a first opening peripheral area 203A surrounding the first opening 201A; the second opening area 202B and the first opening area 202A are adjacently arranged along the first direction R1 and include a second opening 201B And the second opening peripheral area 203B surrounding the second opening 201B.
- the inter-opening area 2014 is located between the first opening area 202A and the second opening area 202B.
- the display area 201 at least partially surrounds the first opening area 202A, the second opening area 202B, and the inter-opening area 2014, and includes a plurality of pixels, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit.
- the first signal line 23 extends along the first direction R1, and includes a first portion passing through the first opening peripheral region 202A, the inter-opening region 2014, and the second opening peripheral region 203B, and is configured to provide the pixel circuit with a first portion.
- One display signal is configured to provide the pixel circuit with a first portion.
- the second opening region 202B and the first opening region 202A are arranged along the first direction R1, and thus, the inter-opening region 2014 is located in the first opening in the first direction R1.
- the second opening area 202B can also be arranged along the second direction R2 with the first opening area 202A.
- the inter-opening area 2014 is located between the first opening area 202A and the second opening area 202A in the second direction R2. Between the opening areas 202B.
- the embodiment of the present disclosure does not limit the arrangement direction of the second opening area 202B and the first opening area 202A.
- the display area 201 includes pixels arranged in an array, and each pixel includes one or more sub-pixels, and also includes various signal lines for transmitting various electrical signals to the sub-pixels to realize the display function; the frame area 204 includes various sub-pixels.
- a driving circuit, signal lines that electrically connect the sub-pixels, contact pads, etc., and the signal lines of the frame area 204 are electrically connected (or integrally formed) with the signal lines (such as gate lines, data lines, etc.) in the display area 201 to provide the sub-pixels. Electrical signals (such as scan signals, data signals, etc.).
- the first opening 201A is set to allow light from the display side of the display substrate to pass through to reach the camera and the distance sensor to realize light sensing, thereby realizing functions such as image shooting and distance sensing; for example, in the area corresponding to the first opening 201A
- a camera, a distance sensor, and other devices can be arranged on the back side of the display substrate (that is, the side opposite to the display side), and the camera, the distance sensor, etc. are at least partially exposed through the first opening 201A.
- various signal lines from the frame area 204 extend through the display area 201.
- these signal lines pass through the first opening peripheral area 203A and bypass the first opening 201A, and then enter the display area.
- electrical signals (such as scan signals, data signals, etc.) are provided to the passing sub-pixels. Therefore, these signal lines may not be provided in the first opening 201A to increase the light transmittance of the first opening 201A .
- the display area 201 includes a first display area 2011 and a second display area 2012.
- the first display area 2011 is located on the first side of the first opening area 202A
- the second display area 2012 is located on the second side of the first opening area 202A.
- the first side and the second side are in the first direction R1 (in the figure) In the horizontal direction) are opposite to each other.
- the first display area 2011, the first opening peripheral area 203A, and the second display area 2012 are sequentially arranged along the first direction R1.
- the whole formed by the first display area 2011 and the second display area 2012 includes a first pixel array.
- the first pixel array includes a plurality of pixels arranged in an array, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit.
- the display substrate includes a plurality of first signal lines 2301/2302/2303/2304/2305/2306, and the first signal line 2301 is configured to provide a first pixel array with a Display signals, and sequentially pass through the first display area 2011, the first opening peripheral area 203A, and the second display area 2012 along the first direction R1, thereby electrically connecting the first display area 2011 and the first display area 2011 on opposite sides of the first opening 201A.
- the sub-pixels in the second display area 2012 for example, provide the first display signal for the sub-pixels of the plurality of pixels in the first display area 2011 and the second display area 2012 that are at the same horizontal position as the first opening peripheral area 203A.
- the first display signal may be, for example, a gate scan signal, a light emission control signal, or a reset voltage signal in any form of electrical signal.
- a plurality of first signal lines 2301/2302/2303/2304/2305/2306 can provide scan signals, light emission control signals, reset voltage signals, etc. for the pixel circuits in the first display area 2011 and the second display area 2012 of the display area.
- the display substrate 20 further includes a third display area 2013.
- the third display area 2013 includes a first portion 2013C located on the first side of the first display area 2011 and the second display area 2012 in the second direction R2, and a first portion 2013C located on the first side of the first display area 2011 and the second display area 2012 in the second direction R2.
- the second portion 2013D of the second side of the display area 2012, the first side of the first display area 2011 and the second display area 2012 and the second side of the first display area 2011 and the second display area 2012 are in the second direction R2 Opposite each other; the first part 2013C and the second part 2013D are both connected to the first display area 2011 and the second display area 2012.
- the two edges 2013A and 2013B of the first portion 2013C of the third display area 2013 that are opposite to each other in the second direction R2 are respectively aligned with the edges of the first display area 2011 that extend along the second direction R2 and are away from the first opening 201A.
- 2011A and the edge 2012A of the second display area 201 extending along the second direction R2 and away from the first opening 201A are aligned.
- the third display area 2013 includes multiple rows and multiple columns of pixels.
- the display substrate 20 further includes a plurality of third signal lines 2307, and the plurality of third signal lines 2307 are located in the first portion 2013C and the second portion 2013D of the third display area 2013.
- the third signal lines 2307 are configured to respectively provide third scanning signals to the rows of pixels in the third display area 2013 and extend along the first direction R1; for example, in this embodiment, the second signal lines 24 are sequentially along the second direction R2. It passes through the second portion 2013D of the third display area 2013, the first opening peripheral area 203A, and the first portion 2013C of the third display area 2013, and is configured to provide a second display signal to a plurality of columns of pixels in the third display area 2013.
- the third display area 2013 also includes a plurality of pixels, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit.
- Each pixel of the third display area 2013 may have the same structure as each pixel of the first display area and the second display area.
- the number of pixels included in each row of pixels in multiple rows and multiple columns of sub-pixels in the third display area 2013 is substantially the same.
- the number of pixels electrically connected to the plurality of third signal lines 2037 is substantially the same, so the plurality of third signal lines 2037 have substantially the same load.
- each row of pixels in multiple rows and multiple columns includes more pixels than the first pixel row of the first pixel array and more pixels than the second pixel row of the first pixel array.
- the load of each first signal line 2301/2302/2303/2304 after load compensation is basically the same as the load of the multiple third signal lines 2037, and each first signal line 2301/2302/2303/2304 is
- the signal transmission speed of each third signal line 2037 is basically the same, and the deviation between the actual display signal transmitted to the pixel circuit of the sub-pixel and the design value is basically the same, so that the display consistency of the display area 201 can be maintained, and the display substrate can be improved. 20 display effect.
- the display substrate 20 further includes a first power line VDD
- the first power line VDD is connected to the first voltage terminal and is configured to provide a first power voltage to the pixel circuits of one or more sub-pixels.
- the first power supply line VDD includes a plurality of first sub-wiring lines 2421/2422 extending in the first direction R1 and a plurality of second sub-wiring lines 2423/2424 extending in the second direction R2.
- the first part of the first sub-wiring 2421 among the plurality of first sub-wiring 2421/2422 is disconnected in the first opening area 202A, and the second part of the first sub-wiring 2422 among the plurality of first sub-wiring 2421/2422 Through the third display area.
- the first sub-wiring 2422 penetrates the first portion 2013C of the third display area 2013 along the first direction R1.
- the first part of the second sub-wiring 2423 of the multiple second sub-wiring 2423/2424 is disconnected in the first opening area 202A, and the second part of the second sub-wiring 2424 of the multiple second sub-wiring 2423/2424
- the first display area 2011 and the third display area 2013 are sequentially passed through, for example, in this embodiment, the second portion 2013D of the third display area 2013, the first display area 2011, and the first portion 2013C of the third display area 2013 are sequentially passed through.
- the second sub-wiring 2424 sequentially passes through the second display area 2012 and the third display area 2013, for example, in this embodiment, passes through the second portion 2013D, the second display area 2012, and the third display area of the third display area 2013 in order.
- the first part of area 2013 is 2013C.
- At least one of the first sub-wiring 2421 of the first part and the second sub-wiring 2424 of the second part 2424 is electrically connected in the first display area 2011 and the second display area 2012, and the second sub-travel of the first part
- the line 2423 is electrically connected to at least one of the first sub-wiring 2422 in the second part of the first sub-wiring 2422 in the third display area 2013, so as to provide uniformity for the sub-pixels in each row and column of the first pixel array and the second pixel array.
- the planar shape of the first opening area of the display substrate is not limited to a circle, for example, it may also be a regular pattern such as a rectangle, an ellipse, or the like, or a racetrack shape (for example, as shown in FIG. 15), a drop shape, etc. irregular shape.
- the arrangement principles and technical effects of the first signal line and the second signal line are the same as or similar to those of the circular example described above.
- At least one of the inter-opening area 2014, the first opening peripheral area 203A, and the second opening peripheral area 203B includes a first dummy sub-pixel.
- the inter-opening area 2014 includes the first dummy sub-pixel.
- a virtual sub-pixel 11 as an example, that is, the first virtual sub-pixel 11 is located in part A in FIG. 2C. The structure of the first virtual sub-pixel will be described in detail later.
- the first dummy sub-pixel 11 may also be located in the first opening peripheral area 203A or/and the second opening peripheral area 203B.
- the structure of the sub-pixels in the display area such as the sub-pixels 12 in the part B and the part C in FIG. 3C, will be introduced below.
- the pixel circuit of each sub-pixel in the display area 201 of the display substrate 20 includes a transistor, which is described by taking a thin film transistor (TFT) as an example, a light-emitting element 180 and a storage capacitor CST.
- the thin film transistor includes an active layer 120, a gate 121, and source and drain electrodes 122/123;
- the storage capacitor CST includes a first plate CE1 and a second capacitor plate CE2.
- the light emitting element 180 includes a cathode 183, an anode 181, and a light emitting layer 182 between the cathode 183 and the anode 181.
- the anode 181 is electrically connected to one of the source and drain electrodes 122/123 of the thin film transistor TFT, such as the drain electrode 123.
- the light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and correspondingly, the light-emitting layer 182 is an organic light-emitting layer or a quantum dot light-emitting layer.
- the display area 201 further includes a first gate insulating layer 151 located between the active layer 120 and the gate electrode 121, a second gate insulating layer 152 located above the gate electrode 121, and an interlayer insulating layer 160.
- the second gate insulating layer 152 is located between the first electrode plate CE1 and the second capacitor electrode plate CE2, so that the first electrode plate CE1, the second gate insulating layer 152 and the second capacitor electrode plate CE2 constitute a storage capacitor CST.
- the interlayer insulating layer 160 covers the second capacitor plate CE2.
- the display area 201 further includes an insulating layer 113 (for example, a passivation layer) covering the pixel circuit and a first planarization layer 112.
- the display area 201 further includes a pixel defining layer 170 for defining a plurality of sub-pixels, and spacers (not shown) on the pixel defining layer 170 and other structures. As shown in FIG. 3A, the display area 201 further includes an insulating layer 113 (for example, a passivation layer) covering the pixel circuit and a first planarization layer 112.
- the display area 201 further includes a pixel defining layer 170 for defining a plurality of sub-pixels, and spacers (not shown) on the pixel defining layer 170 and other structures. As shown in FIG.
- the insulating layer 113 is located above the source and drain electrodes 122/123 (for example, the passivation layer is formed of silicon oxide, silicon nitride, or silicon oxynitride), and the insulating layer 113 is located above There is a first planarization layer 112, and the anode 181 is electrically connected to the drain 123 through a via hole penetrating the first planarization layer 112 and the insulating layer 113.
- the first opening peripheral area 203A of the display substrate 20 further includes encapsulation layers 291, 292, and 293.
- the display area 201 further includes an encapsulation layer 190, and the encapsulation layer 190 includes a plurality of encapsulation sublayers 191/192/193.
- the encapsulation layer 190 is not limited to three layers, and may also be two layers, or four, five or more layers.
- the first encapsulation layer 291 and the first encapsulation sublayer 191 in the encapsulation layer 190 are provided on the same layer
- the second encapsulation layer 292 is provided on the same layer as the second encapsulation sublayer 192 in the encapsulation layer 190
- the third encapsulation layer 293 is provided on the same layer as the first encapsulation sublayer 191 in the encapsulation layer 190.
- the third encapsulation sublayer 193 in the encapsulation layer 190 is arranged in the same layer.
- both the first encapsulation layer 291 and the third encapsulation layer 293 may include inorganic encapsulation materials, such as silicon oxide, silicon nitride, or silicon oxynitride.
- the second encapsulation layer 292 may include organic materials, such as resin materials.
- the multi-layer packaging structure of the display area 201 and the first opening peripheral area 203A can achieve a better packaging effect to prevent impurities such as water vapor or oxygen from penetrating into the display substrate 20.
- the display substrate further includes a buffer layer 111 on the base substrate 210.
- the buffer layer 111 serves as a transition layer to prevent harmful substances in the base substrate 210 from intruding into the interior of the display substrate 20. , It can increase the adhesion of the film in the display substrate 20 on the base substrate 210.
- the material of the buffer layer 111 may include a single-layer or multi-layer structure formed of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
- 3B is another schematic cross-sectional view of the sub-pixels in the display area of the display substrate.
- the difference from the display area shown in FIG. 3A is that in the display area shown in FIG.
- the transfer electrode 171 is covered with the second planarization layer 114, for example, the second planarization layer 114 is covered on the first planarization layer 112.
- the display area of the display substrate may not have the insulating layer 113 and the second planarization layer 114.
- the base substrate 210 may be a glass substrate, a quartz substrate, a metal substrate, a resin substrate, or the like.
- the material of the base substrate 210 may include an organic material.
- the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and polyethylene terephthalate. Resin materials such as esters and polyethylene naphthalate.
- the base substrate 210 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiment of the present disclosure.
- the material of any one of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarization layer 112, the pixel defining layer 170, and the spacers may include silicon oxide, silicon nitride , Inorganic insulating materials such as silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin.
- the embodiments of the present disclosure do not specifically limit the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarization layer 112, the pixel defining layer 170, and the spacers.
- the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarization layer 112, the second planarization layer 114, the pixel defining layer 170, and the spacers may be the same or the same as each other.
- the parts are the same, and may also be different from each other, which is not limited in the embodiments of the present disclosure.
- the display substrate 20 may further include a barrier wall 28 located in the peripheral area 203A of the first opening and at least partially surrounding the first opening 201A.
- the barrier wall 28 at least partially overlaps the first signal line and the second signal line.
- the barrier wall 28 can provide barrier and support in the peripheral area 203A of the first opening, maintain the stability of the first opening 201A, protect the photoelectric sensor components such as the camera in the first opening 201A, and block harmful impurities such as water vapor and oxygen from passing through the first opening.
- 201A diffuses into the display area, thereby preventing harmful impurities from deteriorating the pixel circuit in the display area.
- FIG. 4A is a schematic diagram of a plan layout of a first dummy pixel circuit in a display substrate provided by an embodiment of the present disclosure.
- the first dummy pixel circuit is part A in FIG. 2C; -B2 line cross-sectional schematic diagram, FIGS. 4C-4G are schematic diagrams of each layer of a first dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure.
- the first portion 2301A of the first signal line 2301 passes through the first dummy sub-pixel 11, the first dummy sub-pixel 11 includes a dummy pixel circuit, and the dummy pixel circuit includes a first compensation capacitor COM1,
- the first compensation capacitor COM1 includes: a first electrode plate CE11 and a second electrode plate CE12.
- the first electrode plate CE11 of the first compensation capacitor COM1 is provided on the same layer as the first portion 2301A of the first signal line 2301 and is electrically connected to the first signal line 2301, and is provided on the same layer as the second electrode plate CE2 of the storage capacitor CST;
- the second electrode plate CE12 of a compensation capacitor COM1 and the first electrode plate CE11 of the first compensation capacitor COM1 are arranged in different layers and insulated from each other.
- the orthographic projection of the second electrode plate CE12 of the first compensation capacitor COM1 on the base substrate 210 and the orthographic projection of the first electrode plate CE11 of the first compensation capacitor COM1 on the base substrate 210 at least partially overlap.
- the first compensation capacitor COM1 compensates the load on the first signal line 2301, thereby reducing the display difference caused by the different loads on the first signal line connected to the pixels of different rows due to the different numbers of pixels in different rows, so that the first The display effect of the display area 2011 and the second display area 2012 is consistent with the display effect of the pixel rows in the display area 201 where the first opening area 202A is not provided, and the display quality is improved.
- the first electrode plate CE11 and the second electrode plate CE2 of the storage capacitor CST are arranged in the same layer, the first electrode plate CE11 can not only form a compensation capacitor with the metal layer above it (in the direction away from the base substrate) , And can also form a compensation capacitor with the semiconductor layer below it (in the direction close to the base substrate). If the first electrode plate CE11 and the gate electrode 121 are arranged in the same layer, it will form a TFT with the semiconductor layer.
- the first electrode plate CE11 of the first compensation capacitor COM1 and the first signal line 2301 are integrally formed.
- the material of the second electrode plate CE12 of the first compensation capacitor COM1 includes a semiconductor material and is a conductor, and is provided in the same layer as the above-mentioned active layer 120.
- the material of the second electrode plate CE12 of the first compensation capacitor COM1 includes the same material as the active layer 120, such as a-Si, polysilicon, and the like.
- the second plate CE12 of the first compensation capacitor COM1 is heavily doped to enhance its conductivity and make it a conductor.
- the active layer 120 can be doped at the same time, since the second electrode plate CE12 of the first compensation capacitor COM1 will not be blocked, and heavy doping can be realized.
- the doping material is boron (B).
- a voltage signal is applied to the second electrode plate CE12.
- the semiconductor material is equivalent to a conductor, so it can be used as a capacitor electrode plate, and the existing layers are fully utilized. It can be formed simultaneously with the active layer 120 through the same patterning process.
- the same patterning process refers to using the same mask to pass the same exposure for patterning.
- the virtual pixel circuit further includes a second compensation capacitor COM2, and the second compensation capacitor COM2 includes a first electrode plate CE21 and a second electrode plate CE22.
- the first electrode plate CE21 of the first compensation capacitor COM1 is reused as the first electrode plate CE21 of the second compensation capacitor COM2; the second electrode plate CE22 and the first electrode plate CE21 of the second compensation capacitor COM2 are arranged in different layers and insulated, and It is arranged on the same layer as the above-mentioned source and drain electrodes 122/123.
- the orthographic projection of the second electrode plate CE22 of the second compensation capacitor COM2 on the base substrate 210 and the orthographic projection of the first electrode plate CE21 of the second compensation capacitor CE22 on the base substrate 210 at least partially overlap.
- the second compensation capacitor further compensates the load on the first signal line 2301, thereby reducing the display difference caused by the different loads on the first signal line connecting the pixels of different rows due to the different numbers of pixels in different rows.
- the display effect of the display area 2011 and the second display area 2012 is consistent with the display effect of the pixel rows in the display area 201 where the first opening area 202A is not provided, and the display quality is improved.
- the existing layer that is, the conductive layer where the source and drain electrodes 122/123 are located
- it can be formed with the source and drain electrodes 122/123 by performing a patterning process on the same film layer, simplifying the manufacturing process of the display plate and saving costs.
- the second plate CE22 of the second compensation capacitor COM2 is electrically connected to the second plate CE12 of the first compensation capacitor COM1, so that the first compensation capacitor and the second compensation capacitor are connected in parallel to provide more effective compensation and greater compensation Scope.
- FIG. 4H is a schematic diagram of another first electrode plate of the first compensation capacitor of the display substrate provided by an embodiment of the present disclosure.
- the first plate CE11 of the first compensation capacitor COM1 includes a first extension 21 and a second extension 22.
- the first extension 21 is connected to the first portion 2301A of the first signal line 2303, extends from the first portion 2301A of the first signal line 2303 and is located on the first side of the first portion 2301A of the first signal line 2303 in the second direction R2,
- the second direction R2 intersects the first direction R1, such as perpendicular but not limited to this;
- the second extension 22 is connected to the first portion 2301A of the first signal line 2303, extends from the first portion 2301A of the first signal line 2303 and is located at the first portion 2301A of the first signal line 2303.
- the first portion 2301A of the signal line 2303 is a second side opposite to the first side in the second direction R2.
- first extension 21, the second extension 22 and the first portion 2301A of the first signal line 2303 are integrally formed.
- the display substrate further includes a first power line.
- the first power line is connected to the first voltage terminal and is configured to provide a first power voltage to the pixel circuit and is connected to the second plate CE2 of the storage capacitor CST.
- the first power line includes: a plurality of first power lines extending in a first direction.
- a sub-wiring line and a plurality of second sub-wiring lines extending along the second direction, and the plurality of second sub-wiring lines are electrically connected with the plurality of first sub-wiring lines.
- the first part of the second sub-wiring 2424 among the plurality of second sub-wiring passes through the inter-opening area 2014 and passes through the first dummy sub-pixel 11.
- the second plate CE22 of the second compensation capacitor COM2 includes a first part CE221 and a second part CE222.
- the first part of the second sub-wiring 2424 is the same as the first part CE221 of the second plate of the second compensation capacitor.
- Layer is arranged and electrically connected to serve as the second part CE222 of the second plate of the second compensation capacitor, and the first part of the second sub-wiring 2424 is electrically connected to the second plate CE12 of the first compensation capacitor COM1, thereby realizing the first
- the second plate CE22 of the two compensation capacitor COM2 is electrically connected to the second plate CE12 of the first compensation capacitor COM1.
- the first part of the second sub-wiring 2424 and the second plate CE22 of the second compensation capacitor COM2 are integrally formed.
- Fig. 4I is a schematic cross-sectional view taken along the line A3-B3 in Fig. 4A.
- the display substrate 20 further includes: a first insulating layer 151 (for example, the aforementioned first gate insulating layer) between the second electrode plate CE12 of the first compensation capacitor COM1 and the aforementioned gate 121, The second insulating layer 152 (for example, the above-mentioned second gate insulating layer) between the gate 121 and the first electrode plate CE11 of the first compensation capacitor COM1, and the first electrode plate CE11 and the first electrode plate CE11 of the first compensation capacitor COM1
- the third insulating layer 160 (for example, the aforementioned interlayer insulating layer) between the second plate CE22 of the two compensation capacitors COM2.
- the first part of the second sub-wiring 2424 passes through the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160 and exposes the first via hole VH10 of the second electrode plate CE12 of the first compensation capacitor COM1 and the first compensation
- the second plate CE12 of the capacitor COM1 is electrically connected.
- the display substrate 20 further includes a plurality of second signal lines 24.
- the plurality of second signal lines 24 are configured to provide second display signals to the plurality of sub-pixels.
- the first part of the second signal line 2411 of the plurality of second signal lines 24 passes through the inter-opening area 2014 and passes through the first dummy sub-pixel 11 along the second direction R2.
- the first part of the second signal line 2411 is located on the side of the second electrode plate CE22 of the second compensation capacitor COM2 away from the base substrate 210.
- the first part 21 of the second plate CE22 of the second compensation capacitor COM2 has a hollow area H1, passing through the first virtual sub-pixel 11 where the second plate CE22 of the second compensation capacitor COM2 is located
- the orthographic projection of the first part of the second signal line 2411 on the base substrate 210 at least partially overlaps the hollow area H1, so as to reduce the overlapping area of the first part of the second signal line 2411 and the second electrode plate CE22 of the second compensation capacitor COM2 , Reduce the capacitance formed by the overlap of the two, thereby reducing the load of the first part of the second signal line 2411.
- the second electrode plate CE22 of the second compensation capacitor COM2 has a plurality of hollow areas H1/H2.
- two hollow areas H1 are taken as an example.
- the two directions R2 are spaced apart from each other. In this way, the load of the first part of the second signal line 2411 can be adjusted in steps according to different needs.
- the plurality of hollow areas include adjacent first hollow areas H1 and second hollow areas H2, the length of the first hollow area H1 in the second direction R2 and the length of the second hollow area H2
- the length in the second direction R2 is different, and the load of the first part of the second signal line 2411 can be adjusted differently according to the different parts of the load of the first part of the second signal line 2411.
- the portion P of the second electrode plate CE22 of the second compensation capacitor COM2 located between the first hollow area H1 and the second hollow area H2 is continuous along the first direction R1; the second compensation The second plate CE22 of the capacitor COM2 includes a first edge and a second edge opposite to each other in the second direction R2, and at least one of the first edge and the second edge is cut off by a hollow area.
- the first signal line includes a gate scan signal line and a reset signal line.
- the first signal line 2303 is a gate scan signal line and is configured to provide a gate scan signal to the sub-pixel.
- the first display signal is a gate scan signal;
- the first signal line 2301 is a reset signal line and is configured to provide a gate scan signal to the sub-pixel.
- a reset voltage signal is provided, and correspondingly, the first display signal is a reset voltage signal.
- the second signal line 24 is a data line and is configured to provide the sub-pixel with a data signal for controlling the light-emitting gray level of the sub-pixel.
- the second plate CE12 of the first compensation capacitor COM1 covers the entire first virtual sub-pixel 11, and the first plate CE11 of the first compensation capacitor COM1
- the orthographic projection on the base substrate 210 is located within the orthographic projection of the second electrode plate CE12 of the first compensation capacitor COM1 on the base substrate 210.
- the size of the first compensation capacitor COM1 is smaller than the size of the second compensation capacitor COM2.
- the effective size of each plate of the first compensation capacitor COM1 and the second compensation capacitor COM2 can be adjusted as needed to adjust the sizes of the first compensation capacitor COM1 and the second compensation capacitor COM2.
- the display area 201 includes a first display area 2011 and a second display area 2012.
- the first display area 2011 is located on the side of the first opening area 202A away from the inter-opening area 2014; the second display area 2012 is located on the side of the second opening area 202B away from the inter-opening area 2014.
- Both the first display area 2011 and the second display area 2012 include a plurality of pixels.
- the whole formed by the first display area 2011 and the second display area 2012 includes a plurality of pixel rows extending along the first direction R1, such as the first row, the second row, the third row...
- the plurality of pixel rows are cut off by the whole constituted by the first opening area 202A, the inter-opening area 2014, and the second opening area 202B.
- the number of pixels in the first row of pixels is different from the number of pixels in the second row
- the number of first compensation capacitors in the first virtual pixel row corresponding to the pixels in the first row is different from the number of pixels corresponding to the second row of pixels in the second row.
- the number of the first compensation capacitors in the virtual pixel rows is different, so as to make the load of the first signal lines of the pixels of different rows uniform.
- the first signal line 2303 sequentially passes through the first display area 2011, the first opening peripheral area 203A, the inter-opening area 2014, the second opening peripheral area 203B, and the second display area 2012 along the first direction R1.
- the first signal line 2303 also includes a second portion 2303B passing through the first display area 2011 and a third portion 2303C passing through the second display area 2012, and the second portion 2303B and the third portion 2303C are arranged in the same layer as the gate electrode 121. Therefore, the second part 2303B and the first part 2303A need to be changed layers, and the first part 2303A and the third part 2303C need to be changed layers.
- Fig. 5A is an enlarged schematic diagram of part C in Fig. 2C
- Figs. 5B-5D are enlarged schematic diagrams of part D, part E, and part F in Fig. 2C, respectively
- Fig. 5E is a layer change of the first signal line and the second signal line
- Figures 5F-5H are schematic cross-sectional views taken along lines A4-B4, A5-B5, and A6-B6 in Figure 5E, respectively.
- the display substrate 20 further includes a first connection structure, for example, the first connection structure includes a first sub-connection structure 311 and a second sub-connection structure 312.
- the first connection structure 311/312 is located in the first opening peripheral area 203A, for example, at the junction of the first opening peripheral area 203A and the first display area 2011, and is connected to the second portion 2303B/2301B and the first signal line of the first signal line.
- the first part 2303A/2301A of a signal line are arranged in different layers
- the second part 2303B/2301B of the first signal line is electrically connected to the first connection structure 311/312, and the first part 2303A/2301A of the first signal line is connected to the first connection.
- the structure 311/312 is electrically connected to realize the layer change when the first signal line 2303/2301 enters the first opening peripheral area 203A from the first display area 2011.
- the first signal line 2303 is a gate scan signal line
- the first signal line 2301 is a reset signal line.
- 5E and 5F the second part 2301B of the reset signal line and the first part 2301A of the reset signal line are arranged in different layers, and the second part 2301B of the reset signal line is electrically connected to the second sub-connection structure 312 through the via hole VH11 to reset
- the first part 2301A of the signal line is electrically connected to the second sub-connection structure 312 through the via VH12, so that the second part 2301B of the reset signal line is electrically connected to the first part 2301A of the reset signal line, so that the reset signal line 2301 undergoes a layer change
- the wiring is routed around the first opening.
- the second part 2303B of the gate scan signal line and the first part 2303A of the gate scan signal line are arranged in different layers, and the second part 2303B of the gate scan signal line is connected to the first sub through the via hole VH13.
- the structure 311 is electrically connected, and the first part 2303A of the gate scan signal line is electrically connected to the first sub-connection structure 311 through the via hole VH14, so that the second part 2303B of the gate scan signal line is electrically connected to the first part 2303A of the gate scan signal line.
- the gate scan signal line 2303 is routed around the first opening after changing the layer.
- first connection structure and the second connection structure are arranged on the same layer as the source and drain electrodes 122/123.
- the display substrate 20 also includes a second connection structure.
- the second connection structure is located in the second opening peripheral area 203B, for example, at the junction of the second opening peripheral area 203B and the first display area.
- the first part 2303A/2301A of the first signal line and the third part 2303C/2301C of the first signal line are arranged in different layers; the first part 2303A/2301A of the first signal line and the second connection structure (not shown) Electrically connected, the third portion 2303C/2301C of the first signal line is electrically connected to the second connection structure to realize another layer change of the first signal line 2303, that is, the first signal line 2303 enters the second signal line from the peripheral area 203B of the second opening.
- the second connection structure includes a third sub-connection structure and a fourth sub-connection structure, which are respectively provided corresponding to the gate scan signal line 2303 and the reset signal line 2301, so as to realize the gate scan signal line 2303 and the reset signal line 2301, respectively.
- the arrangement of the third sub-connection structure and the fourth sub-connection structure can refer to the arrangement of the above-mentioned first sub-connection structure and the second sub-connection structure.
- the third sub-connection structure and the fourth sub-connection structure are substantially symmetrical to the first sub-connection structure and the second sub-connection structure.
- the first gate line GLn and the second gate line GLn-1 that provide gate scan signals to the sub-pixels 12 in the same row are exchanged through the same first sub-connection structure 311 to save space.
- the reset signal lines that provide reset voltage signals to multiple rows of sub-pixels can be layered through the same second connection structure 312 to save space.
- the same second connecting structure 312 is routed along the boundary area between the first display area and the peripheral area of the first opening in a zigzag line, so as to make reasonable use of space and leave enough space for other structures such as the first connecting structure and the second connecting structure. Space.
- a plurality of second connection structures 312 separated from each other can also be used for layer change.
- a part of the second signal line 2410 enters the peripheral area of the first opening from the display area (the same is true for the second opening, taking the first opening as an example), always located at the source and drain 122/123 The side away from the base substrate 210 does not change the layer.
- a part of the second signal line 2412 enters the peripheral area of the first opening from the display area (the same is true for the second opening, taking the first opening as an example).
- the second signal line 2412 includes a first portion 2412A passing through the display area and a first portion 2412A passing through the first opening.
- the second portion 2412B of the opening peripheral region 203A, the first portion 2412A of the second signal line 2412 is located on the side of the source and drain 122/123 away from the base substrate 210, and the second portion 2412B of the second signal line 2412 is connected to the source and drain
- the pole 122/123 is set on the same floor. Therefore, the second signal line 2412 needs to be layer changed.
- the first part 2412A of the second signal line 2412 is directly connected to the second part 2412B of the second signal line 2412 through the via hole VH15 passing through the insulating layer 113, and no additional connection electrodes are required to simplify the production. Craft.
- the data line 2410 without layer change is adjacent to the data line 2412 with layer change in the first direction.
- FIG. 6 is an equivalent circuit diagram of a pixel circuit in an array substrate provided by an embodiment of the present disclosure
- FIG. 7A is a schematic diagram of a planar layout of a pixel circuit in an array substrate provided by an embodiment of the present disclosure.
- FIG. 7A takes the layer structure of pixel circuits in two adjacent sub-pixels as an example.
- the data line 1 below is an example of the second signal line 24 described above.
- Each of the plurality of sub-pixels 1030 includes a pixel circuit, and the pixel circuit includes a light-emitting device, a storage capacitor CST, a driving transistor T1 (hereinafter also referred to as a first transistor), a data writing transistor T2 (hereinafter also referred to as a second transistor), and a data line 1 and the first connection structure CP1.
- Each of the driving transistor T1 and the data writing transistor includes an active layer, a gate, a first electrode, and a second electrode.
- the driving transistor T1 is configured to control the light emitting device to emit light, for example, to control a driving current for driving the light emitting device to emit light.
- the data line 1 is connected to the first pole of the data writing transistor T2 and is configured to provide the data writing transistor T2 with a data signal for controlling the display gray scale of the sub-pixel 1030.
- the data writing transistor T2 is configured to write a data signal to the gate of the driving transistor T1 in response to a first scan signal applied to the gate of the data writing transistor T2.
- the first connection structure CP1 is connected to the gate of the driving transistor T1 and the first plate of the storage capacitor CST.
- the first connection structure CP1 and the data line 1 are arranged in different layers, that is, the first connection structure CP1 and the data line 1 are arranged in different layers.
- first connection structure CP1 There is an insulating layer between the first connection structure CP1 and the data line 1 in a direction perpendicular to the base substrate 210.
- the distance between the two is small, which will cause the first connection structure CP1 to be horizontally
- a large parasitic capacitance is formed between the data line 1 and the data line 1, especially in a high-resolution display panel, this phenomenon is particularly serious. This parasitic capacitance will directly lead to unsatisfactory display effects.
- the parasitic capacitance formed between the first connection structure CP1 and the data line 1 is unstable, because during the display process, the data signal on the data line 1 is constantly changing, and as the data signal is written into the gate of the driving transistor T1 It means that the data signal is written into the N1 node in FIG. 6, which causes the N1 node signal to jump, thereby affecting the fluctuation of the current flowing through the N1 node and affecting the display effect.
- the first connection structure CP1 is the actual structure corresponding to the N1 node in FIG.
- disposing the first connection structure CP1 and the data line 1 in different layers can reduce or avoid The parasitic capacitance is formed between the two, thereby improving or avoiding the adverse effects on the display effect and achieving a more ideal display effect.
- the above-mentioned parasitic capacitances are formed between the data line 1 corresponding to the same sub-pixel 1030 and the first connection structure CP1, which correspond to two adjacent ones respectively.
- the above-mentioned parasitic capacitance (represented by parasitic capacitance 2 below) is also formed between the data line 1 in each sub-pixel and the first connection structure CP1.
- the degree of crosstalk between the two on node N1 It is 0.678%. The greater the value of the crosstalk degree, the greater the interference formed, and the greater the adverse effect on the display.
- the value of the parasitic capacitance 1 is about 0.0321fF, and the value of the parasitic capacitance 2 can reach 0.0242fF, and the degree of crosstalk between the two on the N1 node is 0.218%. It can be seen that the values of the parasitic capacitance 1 and the parasitic capacitance 2 in the array substrate provided by the embodiment of the present disclosure are significantly reduced compared to the situation where the two are arranged in the same layer, and the degree of crosstalk generated to the N1 node is significantly reduced, thereby affecting the display The adverse effects caused have a significant improvement effect.
- the pixel circuit includes a plurality of thin film transistors: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and The seventh transistor T7, the multiple signal lines connected to the multiple thin film transistors T1, T2, T3, T4, T5, T6, and T7, and the storage capacitor CST, that is, the pixel circuit in this embodiment has a 7T1C structure.
- the plurality of signal lines include gate lines GLn/GLn-1 (ie, scan signal lines), light emission control lines EM, reset signal lines RL, data lines DAT, and first power supply lines VDD.
- the gate line GLn/GLn-1 may include a first gate line GLn and a second gate line GLn-1.
- the first gate line GLn is used to transmit the gate scan signal
- the second gate line GLn-1 is used to transmit the reset voltage signal.
- the emission control line EM is used to transmit the emission control signal, for example, is connected to the first emission control terminal EM1 and the Two light-emitting control terminal EM2.
- the gate of the fifth transistor T5 is connected to the first light emission control terminal EM1, or used as the first light emission control terminal EM1 to receive the first light emission control signal;
- the gate of the sixth transistor T6 is connected to the second light emission control terminal EM2, or As the second light emission control terminal EM2, to receive the second light emission control signal.
- the embodiments of the present disclosure include, but are not limited to, the above-mentioned 7T1C structure pixel circuit.
- the pixel circuit may also adopt other types of circuit structures, such as 7T2C structure or 9T2C structure, which is not limited by the embodiment of the present disclosure.
- the first gate of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4.
- the first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5.
- the first drain electrode D1 of the first thin film transistor T1 is electrically connected to the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6.
- the second gate of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive the gate scan signal;
- the second source S2 of the second thin film transistor T2 is configured To be electrically connected to the data line DAT to receive data signals;
- the second drain electrode D2 of the second thin film transistor T2 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
- the third gate of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, and the third source S3 of the third thin film transistor T3 is connected to the first gate line GLn of the first thin film transistor T1.
- the drain electrode D1 is electrically connected, and the third drain electrode D3 of the third thin film transistor T3 is electrically connected to the first gate electrode of the first thin film transistor T1.
- the fourth gate of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal
- the fourth source S4 of the fourth thin film transistor T4 is configured
- the fourth drain electrode D4 of the fourth thin film transistor T4 is electrically connected to the first gate electrode of the first thin film transistor T1.
- the fifth gate of the fifth thin film transistor T5 is configured to be electrically connected to the light emission control line EM to receive the light emission control signal
- the fifth source S5 of the fifth thin film transistor T5 is configured to be connected to the light emission control line EM.
- a power line VDD is electrically connected to receive the first power signal
- the fifth drain electrode D5 of the fifth thin film transistor T5 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
- the sixth gate of the sixth thin film transistor T6 is configured to be electrically connected to the emission control line EM to receive the emission control signal, and the sixth source S6 of the sixth thin film transistor T6 is connected to the first thin film transistor.
- the first drain D1 of T1 is electrically connected, and the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first display electrode (for example, the anode 181 shown in FIG. 6) of the light emitting device (for example, the light emitting device 180 shown in FIG. 6). connect.
- the thin film transistor TFT in FIGS. 7A-7C is the sixth thin film transistor T6.
- the seventh gate of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal
- the seventh source S7 of the seventh thin film transistor T7 is The first display electrode (for example, the anode 181 shown in FIG. 6) of the device is electrically connected
- the seventh drain electrode D7 of the seventh thin film transistor T7 is configured to be electrically connected to the reset signal line RL to receive the reset voltage signal.
- the seventh drain electrode D7 of the seventh thin film transistor T7 may be electrically connected to the reset signal line RL by being connected to the fourth source electrode S4 of the fourth thin film transistor T4.
- the fourth transistor T4 and the seventh transistor T7 are reset transistors, which are configured to provide a reset signal to the sub-pixel.
- the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
- the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
- the first electrode of any transistor has a source electrode
- the second electrode has a drain electrode; or, if any transistor has a first electrode electrode that has a drain electrode, the second electrode has a source electrode.
- the source and drain of each transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure.
- the source and drain of all or part of the transistors are based on Needs are interchangeable.
- FIG. 7B-7F are schematic diagrams of various layers of a pixel circuit of an array substrate provided by an embodiment of the present disclosure
- FIG. 8A is a schematic cross-sectional view taken along the line A-A' in FIG. 7A.
- the pixel circuit includes the aforementioned thin film transistors T3, T4, T5, T6, and T7, a storage capacitor CST, and a plurality of thin film transistors T1, T2, T3, T4, T5, T6. And T7 of the first gate line GLn, the second gate line GLn-1, the light emission control line EM, the reset signal line RL, the data line DAT, and the first power supply line VDD.
- FIGS. 7A-7F and FIG. 8A the specific features of the structure of the pixel circuit of the embodiment of the present disclosure will be described with reference to FIGS. 7A-7F and FIG. 8A.
- the data line 1 and the first connection structure CP1 both extend along the first direction, and the orthographic projection of the first connection structure CP1 on the base substrate 210 is the same as that of the data line 1 on the base substrate 210.
- the orthographic projections are at least partially opposite to each other in the lateral direction R2. This structure is conducive to the compactness of the pixel circuit structure.
- the lateral direction R2 is parallel to the base substrate 210 and perpendicular to the first direction R1.
- the distance between the orthographic projection of the first connection structure CP1 on the base substrate 210 and the orthographic projection of the data line 1 on the base substrate 210 (the proximity of the orthographic projection of the first connection structure CP1 on the base substrate 210)
- the maximum distance from the side of the orthographic projection of the data line 1 on the base substrate 210 to the side of the orthographic projection of the data line 1 on the base substrate 210 that is close to the orthographic projection of the first connection structure CP1 on the base substrate 210) is less than
- the size of one sub-pixel 1030 in the lateral direction is more conducive to the compactness of the pixel circuit structure.
- the distance between the first connection structure CP1 and the data line 1 in the lateral direction R2 is small, the above-mentioned Parasitic capacitance phenomenon.
- the distance between the data line 1 corresponding to the same sub-pixel 1030 and the first connection structure CP1 is smaller than the size of one sub-pixel 1030 in the lateral direction R2, and respectively corresponds to the data line 1 in two adjacent sub-pixels.
- the distance from the first connection structure CP1 is smaller than the size of one sub-pixel 1030 in the lateral direction R2.
- the size of one sub-pixel 1030 in the lateral direction R2 is 30 ⁇ m to 90 ⁇ m.
- the array substrate provided by the embodiment of the present disclosure can simultaneously prevent the above-mentioned parasitic capacitance phenomenon.
- the pixel circuit includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer.
- FIG. 7A shows a schematic layout diagram of the stacked position relationship of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer of the pixel circuit.
- FIG. 7B shows the semiconductor layer of the pixel circuit.
- the semiconductor layer shown in FIG. 7B includes the active layer A1 of the first thin film transistor T1, the active layer A2 of the second thin film transistor T2, the active layer A3 of the third thin film transistor T3, and the active layer A3 of the fourth thin film transistor T4.
- the semiconductor layer can be formed by a patterning process using a semiconductor material layer.
- the semiconductor layer can be used to make the above, and the active layer of each transistor can include a source region, a drain region, and a channel region between the source region and the drain region.
- the semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials (for example, indium gallium tin oxide (IGZO)), or the like.
- IGZO indium gallium tin oxide
- the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
- a first insulating layer is formed on the above-mentioned semiconductor layer.
- various insulating layers are not shown in FIGS. 7A and 7B-7K.
- the first insulating layer 151 of the pixel circuit is disposed on the side of the first conductive layer away from the base substrate 210.
- FIG. 7C shows the first conductive layer of the pixel circuit
- FIG. 7G shows a schematic diagram after the first conductive layer and the semiconductor layer are laminated.
- the first conductive layer is located on the side of the semiconductor layer away from the base substrate 210.
- the first insulating layer 151 is located between the active layer and the first conductive layer of each transistor.
- the first conductive layer includes the first plate CE1 of the storage capacitor CST, the first gate line GLn, the second gate line GLn-1, the light emission control line EM, and the gate of the first thin film transistor T1, the second thin film transistor The gate of T2, the gate of the third thin film transistor T3, the gate of the fourth thin film transistor T4, the gate of the fifth thin film transistor T5, the gate of the sixth thin film transistor T6, and the gate of the seventh thin film transistor T7.
- the active layers of the above-mentioned transistors are arranged in the same layer, and the gates of the above-mentioned transistors and the first plate CE1 of the storage capacitor CST are arranged in the same layer, so that the first insulating layer 151 is located on the active layer of each transistor and each transistor. Between the gate and the first plate CE1 of the storage capacitor CST. It can be seen that the driving transistor, that is, the gate of the first transistor T1 (or the gate of each transistor) and the first plate CE1 of the storage capacitor CST are located far away from the active layer of the driving transistor (or the active layer of each transistor). One side of the base substrate 210.
- the gate of the thin film transistor T7 is the overlapped portion of the first gate line GLn, the second gate line GLn-1 and the semiconductor layer, respectively.
- the third thin film transistor T3 may be a thin film transistor with a double gate structure, and a gate of the third thin film transistor T3 may be a portion where the first gate line GLn overlaps the semiconductor layer, and the third thin film transistor
- the other gate electrode of T3 may be a protrusion protruding from the first gate line GLn;
- the gate electrode of the first thin film transistor T1 may be integrally formed with the first electrode plate CE1, that is, the first electrode plate CE1 is reused as the first thin film transistor The gate of T1.
- the fourth thin film transistor T4 may be a thin film transistor with a double-gate structure, and the two gates are respectively the overlapping parts of the second gate line GLn-1 and the semiconductor layer.
- the gates of the above-mentioned thin film transistors are respectively integrally formed with the corresponding first gate line GLn or the second gate line GLn-1.
- the first gate line GLn, the second gate line GLn-1, and the gate of each thin film transistor are arranged in the same layer as the first electrode plate CE1 of the storage capacitor CST, and can be formed simultaneously by the same patterning process.
- the array substrate 100 further includes a first power line VDD, the first power line is connected to the first voltage terminal VDD and the second plate CE2 of the storage capacitor CST, and is configured to provide the light-emitting control transistor, that is, the second plate CE2 of the storage capacitor CST.
- a transistor T1 provides the first voltage.
- the first power line VDD includes a first sub-wiring 21 extending in a first direction R1 and a second sub-wiring 22 extending in a second direction, the first direction R1 intersects the second direction, for example, the second direction is Lateral R2.
- the first sub-wire 21 is electrically connected to the second sub-wire 22.
- FIG. 7D shows the second conductive layer of the pixel circuit
- FIG. 7H shows a schematic diagram after the second conductive layer and the semiconductor layer are laminated.
- the second conductive layer is located on the side of the first conductive layer away from the base substrate 210.
- the second conductive layer of the pixel circuit includes the second plate CE2 of the storage capacitor CST, the reset signal line RL, and the second sub-wiring 22, which shows that the second sub-wiring 22 is arranged on the same layer as the second plate CE2 of the storage capacitor CST, and the second plate CE2 of the storage capacitor CST is located at the gate of the driving transistor, that is, the gate of the first transistor T1 (or the gate of each transistor) and the first of the storage capacitor CST.
- the second sub-wiring 22 and the second plate CE2 of the storage capacitor CST are integrally formed, so that they can be formed by the same patterning process.
- the second electrode plate CE2 and the first electrode plate CE1 at least partially overlap to form a storage capacitor CST.
- the second conductive layer may further include a light shielding portion 791.
- the orthographic projection of the light shielding portion 791 on the base substrate 210 covers at least part of the active layer of the second thin film transistor T2, the active layer between the drain of the third thin film transistor T3 and the drain of the fourth thin film transistor T4, thereby Prevent external light from affecting the active layers of the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4.
- the light-shielding portion 791 may be electrically connected to the first power line VDD through the via hole VH9 in the insulating layer, as shown in FIGS. 7A and 8C.
- the first connection structure CP1 is located between the first sub-wiring 21 and the data line 1 (and the first sub-wiring 21 and the data line 1).
- a connecting structure CP1 and the first sub-wiring 21 belong to the pixel circuit of the same sub-pixel.
- the second conductive layer may also include the aforementioned light-shielding portion 791 to To shield the active layer of the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4, the second conductive layer can be used to achieve this purpose, thereby simplifying the manufacturing process of the array substrate.
- the array substrate 100 further includes a second insulating layer 152.
- the second insulating layer 152 is located between the first plate CE1 of the storage capacitor CST and the second plate CE2 of the storage capacitor CST. Between a conductive layer and a second conductive layer. For clarity, the second insulating layer 152 is also not shown in FIGS. 7B-7F.
- the array substrate 100 further includes a second power supply line VSS.
- the first power line VDD is a power line that provides a high voltage to the pixel circuit
- the second power line VSS is connected to the second voltage terminal and the second power line VSS provides a low voltage (lower than the aforementioned high voltage) power line to the pixel circuit.
- the first power supply line VDD provides a constant first power supply voltage
- the first power supply voltage is a positive voltage
- the second power supply line VSS provides a constant second power supply voltage
- the second power supply voltage can be It is negative voltage and so on.
- the second power supply voltage may be a ground voltage.
- the data line 1 is located on the side of the first connection structure CP1 away from the base substrate 210.
- FIG. 7E shows the third conductive layer of the pixel circuit
- FIG. 7I shows a schematic diagram after the third conductive layer and the semiconductor layer are laminated.
- the third conductive layer is located on the side of the second conductive layer away from the base substrate 1.
- the third conductive layer of the pixel circuit includes the first connection structure CP1 and the first sub-wiring 21 of the first power line VDD, that is, the first connection structure CP1 and the first sub-wiring 21 21 Same layer settings. As shown in FIG.
- the array substrate 100 further includes a third insulating layer 160.
- the third insulating layer 160 is located between the second plate CE2 of the storage capacitor CST and the first connection structure CP1, that is, between the second conductive layer and the third conductive layer. Between conductive layers.
- the first sub-wiring 21 is electrically connected to the second sub-wiring 22 through a via hole (for example, via VH3) penetrating the third insulating layer 160.
- a via hole for example, via VH3
- the third conductive layer further includes a second connection structure CP2, a third connection structure CP3, and a fourth connection structure CP4.
- One end of the first connection structure CP1 passes through the via hole (for example via hole VH5) of the first electrode plate CE1 of the storage capacitor CST and the first electrode plate of the storage capacitor CST which penetrates through the second insulating layer 152 and the third insulating layer 160 and exposes part of the storage capacitor CST.
- CE1 connection for example via hole VH5
- the other end of the first connection structure CP1 is connected to the semiconductor layer through at least one via hole (for example, via hole VH4) penetrating through the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160, for example, with the corresponding first insulating layer in the semiconductor layer.
- the drain regions of the three thin film transistors T3 are connected.
- One end of the second connection structure CP2 is connected to the reset signal line RL through a via hole (for example, via hole VH6) penetrating the third insulating layer 160, and the other end of the second connection structure CP2 is connected to the reset signal line RL by penetrating the first insulating layer 151 and the second insulating layer.
- At least one via (for example, via VH7) of 152 and third insulating layer 160 is connected to the semiconductor layer, for example, connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer.
- the third connection structure CP3 is connected to the drain region of the sixth thin film transistor T6 in the semiconductor layer through at least one via hole (for example, via hole VH8) penetrating through the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160 .
- the fourth connection structure CP4 is connected to the drain region of the fifth thin film transistor T5 in the semiconductor layer through at least one via hole (for example, via hole VH2) penetrating through the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160 .
- the fifth connection structure CP5 passes through the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160 and exposes part of the semiconductor layer through at least one via hole (for example, via hole VH1) and the third thin film transistor T3 in the semiconductor layer.
- the drain area is connected.
- FIG. 7F shows the fourth conductive layer of the pixel circuit
- FIG. 7J shows a schematic diagram after the fourth conductive layer and the semiconductor layer are laminated
- FIG. 7K shows the fourth conductive layer, the third conductive layer and the semiconductor layer are laminated Schematic diagram after.
- the fourth conductive layer is located on the side of the third conductive layer away from the base substrate 210.
- the fourth conductive layer includes a data line 1 (DATA), a sixth connection structure CP6, and a seventh connection structure CP7.
- DATA data line 1
- CP6 sixth connection structure
- CP7 seventh connection structure
- the array substrate 100 further includes a fourth insulating layer 113, which is located between the third conductive layer and the fourth conductive layer, that is, between the first connection structure CP1 and the data line 1 (DATA).
- the fourth insulating layer 113 is a flat layer.
- the via hole VH1 also penetrates the fourth insulating layer 113 to expose at least part of the fifth connection structure CP5, and the data line 1 (DATA) is electrically connected to the fifth connection structure CP5 through the via hole VH1, thereby realizing the data line 1 (DATA) and the semiconductor layer
- the drain region of the third thin film transistor T3 in is electrically connected.
- the seventh connection structure CP7 directly contacts the data line 1 to realize electrical connection between the two.
- the seventh connection structure CP7 can widen the part of the data line 1 that needs to be connected to the semiconductor layer, such as the data line 1 and the seventh connection.
- the entire structure of the structure CP7 is electrically connected to the fifth connection structure CP5 through the via hole VH1, so that the data line 1 (DATA) is electrically connected to the drain region of the third thin film transistor T3 in the semiconductor layer.
- the seventh connection structure CP7 and the data line 1 are integrally formed.
- the via hole VH2 also penetrates the fourth insulating layer 113 to expose at least part of the fourth connection structure CP4, and the sixth connection structure CP6 is electrically connected to the fourth connection structure CP4 through the via hole VH2, thereby realizing the sixth connection structure CP6 and the active
- the drain region corresponding to the fifth thin film transistor T5 in the layer is connected to serve as the drain of the fifth thin film transistor T5.
- the sixth connection structure CP6 is used to connect to the anode of the light emitting device (for example, the anode 181 shown in FIG. 6).
- the anode of the light emitting device for example, the anode 181 shown in FIG. 6
- the sixth connection structure CP6 is used to connect to the anode of the light emitting device (for example, the anode 181 shown in FIG. 6).
- the anode of the light emitting device for example, the anode 181 shown in FIG. 6
- the sixth connection structure CP6 is used to connect to the anode
- the shape, size, and position of the sixth connection structure CP6 in the left sub-pixel 1030 shown in FIG. 7A are different from the shape, size, and position of the sixth connection structure CP6 in the right sub-pixel 1030, respectively. .
- the shape, size, and position of the sixth connection structure CP6 extends in the direction intersecting the first direction R1 and the lateral direction R2, and its upper end (not the same as the fourth connection structure CP4 The position of the connected end) is such that it is connected to the anode located at the upper end.
- the thickness of the fourth insulating layer 113 in the direction perpendicular to the base substrate 210 is greater than the thickness of the first insulating layer 151 in the direction perpendicular to the base substrate 210, and the thickness of the second insulating layer 152 in the direction perpendicular to the base substrate 210.
- the thickness in the direction of the base substrate 210, the thickness of the third insulating layer 160 in the direction perpendicular to the base substrate 210, and the thickness of the fourth insulating layer 113 in the direction perpendicular to the base substrate 210. At least one. In order to enhance the insulating effect of the fourth insulating layer 113, the parasitic capacitance between the data line 1 and the first connection structure CP1 can be better reduced or avoided.
- the thickness of the fourth insulating layer 113 in the direction perpendicular to the base substrate 210 is a few microns, for example, less than 5 ⁇ m to 10 ⁇ m. This thickness range can achieve a better reduction or avoid the data line 1 and the first connection structure CP1 The effect of the parasitic capacitance between them does not increase the size of the array substrate 100 excessively.
- the first sub-wiring 21 and the data line 1 are arranged in different layers. Since the adjacent distance between the first sub-wiring 21 and the data line 1 is relatively small, this design can avoid the first sub-wiring. A parasitic capacitance is generated between the line 21 and the data line, so as to prevent the parasitic capacitance from affecting the display effect.
- the adjacent first sub-wiring 21 and the data line 1 respectively correspond to two adjacent sub-pixels.
- the orthographic projection of the first connection structure CP1 on the base substrate 210 and the orthographic projection of the data line 1 on the base substrate 210 do not overlap, and the first trace 21 is on the base substrate 210
- the orthographic projection of and the orthographic projection of the data line 1 on the base substrate 210 do not overlap.
- the solution of the embodiment of the present disclosure can better prevent the crosstalk between the signals on these signal lines.
- the materials of the data line 1 and the first connection structure CP1 are both metallic materials.
- the fourth conductive layer forming the data line 1 adopts a stacked structure Ti/Al/Ti including three layers of metal.
- Fig. 8C is a schematic cross-sectional view taken along the line B-B' in Fig. 7A.
- the plurality of sub-pixels includes a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel.
- FIG. 7A shows two adjacent sub-pixels, the first sub-pixel is the sub-pixel on the left in FIG. 7A, and the second sub-pixel is the sub-pixel on the right in FIG. 7A, that is, the first sub-pixel and the second sub-pixel.
- the pixels are adjacent in the horizontal direction; of course, in other embodiments, the first sub-pixel and the second sub-pixel may also be adjacent in the vertical direction, and the directions and positions of other structures can be adjusted adaptively.
- the first reset transistor T4 includes an active layer A4, a gate (the part of GLn-1 that overlaps the active layer A4), a first electrode (for example, a source), and a second Electrode (for example, a drain);
- the second reset transistor T7 includes an active layer A7, a gate (a portion of the gate line GLn-1 that overlaps the active layer A7), a first electrode (for example, a source), and a second Electrode (e.g. drain).
- the active layer of the reset transistor of the first reset transistor T4 includes a channel region (a portion of the active layer A4 overlapping the gate line GLn-1) and an electrode region E1.
- the active layer A7 of the second reset transistor T7 includes a channel region (a portion of the active layer A7 overlapping the gate line GLn-1) and an electrode region E1.
- the first reset transistor T4 and the second reset transistor T7 share the same electrode region E1.
- the second connection structure CP2 extends along the first direction R1 and includes a first end and a second end opposite to each other in the first direction R1; the second connection structure CP2 of the pixel circuit of the second sub-pixel is located in the lateral direction R2.
- One of the channel region of the active layer of the first reset transistor T4 of the pixel circuit of the first sub-pixel and the channel region of the active layer of the second reset transistor T7 is close to one of the data lines 1 of the pixel circuit of the first sub-pixel side.
- the first end of the second connection structure CP2 is electrically connected to the reset signal line RL through the via hole VH6, and the second end of the second connection structure CP2 is connected to the reset transistor (T4 and T7) of the pixel circuit of the second sub-pixel through the via hole VH7.
- the electrode area E1 of the active layer is electrically connected.
- the second connection structure CP2 constitutes the first electrode and the second electrode of the first reset transistor T4 and the second reset transistor T7.
- the first reset transistor T4 and the second reset transistor T7 of the second sub-pixel of the pixel circuit of the active layer electrode area E1 extends from the first sub-pixel to adjacent to it in the lateral direction
- the orthographic projection of the electrode area E1 of the active layer of the first reset transistor T4 and the second reset transistor T7 of the pixel circuit of the second sub-pixel on the base substrate and the pixel belonging to the first sub-pixel The orthographic projection of the data line 1 of the circuit on the base substrate at least partially overlaps.
- the electrode area E1 of the active layer of the first reset transistor T4 and the second reset transistor T7 intersects the data line 1, so as to more fully and flexibly use the limited pixel area, and form the required easy implementation and other structures Connected semiconductor layer pattern. Since the electrode area E1 of the active layer that overlaps the projection of the data line 1 is far from the second conductive layer where the data line 1 is located in the direction perpendicular to the base substrate, the intersection of the two will not interfere with each other. Interference occurs between the signals.
- FIGS. 7A, 7F, 7J, and 7K three data lines 1 are shown respectively, and the three data lines 1 belong to the pixel circuits of three adjacent sub-pixels; the data line 1 in the middle is The pixel circuit belonging to the first sub-pixel, and the data line 1 on the right side belongs to the pixel circuit of the second sub-pixel.
- FIG. 9 is a signal timing diagram of the pixel circuit shown in FIG. 6.
- the working principle of the pixel circuit shown in FIG. 6 will be described below in conjunction with the signal timing diagram shown in FIG. 9.
- the first emission control line EM1 and the second emission control line EM2 in FIG. 6 are the same common emission control line as an example.
- the first light-emitting control line EM1 and the second light-emitting control line EM2 may also be different signal lines, respectively, which provide different first light-emitting control signals and second light-emitting control signals.
- the transistors shown in FIG. 9 are all P-type transistors.
- the gate of each P-type transistor is turned on when it is connected to a low level, and is turned off when it is connected to a high level.
- the following embodiments are the same as this, and will not be repeated here.
- the working process of the pixel circuit includes three stages, namely the reset stage P1, the data writing and compensation stage P2, and the light-emitting stage P3.
- the figure shows the timing waveform of each signal in each stage.
- the second gate line Gn-1 provides a reset signal Rst
- the fourth transistor T4 and the seventh transistor T7 are turned on by the low level of the reset signal
- the reset signal low level signal, for example, can be grounded or Other low-level signals
- the reset signal is applied to the N4 node, that is, the light-emitting element 180 is reset, so that the light-emitting element 180 can be displayed in a black state and does not emit light before the light-emitting stage P3 , Improve the display effect such as the contrast of the display device using the pixel circuit.
- the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off by the high-level signals respectively connected to them.
- the first gate line GLn provides the scan signal Gn-1
- the data line DAT provides the data signal Data
- the second transistor T2 and the third transistor T3 are turned on.
- the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off by the high-level signals respectively connected to them.
- the first transistor T1, and the third transistor T3 the first node N1 is charged (that is, the storage capacitor CST is charged), that is, the potential of the first node N1 gradually increases. It is easy to understand that since the second transistor T2 is turned on, the potential of the second node N2 remains at Vdata.
- Vdata represents the voltage value of the data signal Data
- Vth represents the threshold voltage of the first transistor T1.
- the first transistor T1 is described as a P-type transistor, so the threshold here The voltage Vth may be a negative value.
- the potentials of the first node N1 and the third node N3 are both Vdata+Vth, that is to say, the voltage information with the data signal Data and the threshold voltage Vth is stored in the storage capacitor CST , To provide gray scale display data and compensate the threshold voltage of the first transistor T1 during the subsequent light-emitting stage.
- the light emitting control line provides the light emitting control signal EM, and the fifth transistor T5 and the sixth transistor T6 are turned on by the low level of the light emitting control signal EM.
- the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned off when the high level is connected to each of them.
- the potential of the first node N1 is Vdata+Vth, and the potential of the second node N2 is VDD, so the first transistor T1 is also kept on at this stage.
- the anode and cathode of the light-emitting element 180 are respectively connected to the first power supply voltage (high voltage) and the second voltage VSS (low voltage) provided by the first power line VDD, so that the light-emitting element 180 is driven by the first transistor T1. Glows under the action of electric current.
- the display substrate further includes: a third signal line extending along the first direction, including a first portion passing through the peripheral area of the first opening, the area between the openings, and the peripheral area of the second opening, configured to A third display signal is provided to the pixel circuit.
- the first part of the third signal line is arranged in the same layer as the gate; for example, the third display signal is a light-emitting drive scan signal (EM line).
- EM line light-emitting drive scan signal
- the display substrate further includes a second dummy sub-pixel, and the second dummy sub-pixel includes a second dummy pixel circuit as shown in FIG. 16.
- the second dummy pixel circuit includes a dummy semiconductor layer, which is provided in the same layer as the active layer, and is electrically connected to the first part of the second sub-wiring, wherein the first part of the third signal line is on the substrate.
- FIGS. 16A-16F are schematic diagrams of various layers of a second dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure.
- the inter-opening area 2014 further includes a second dummy sub-pixel, and the second dummy sub-pixel includes a second dummy pixel circuit, as shown in FIG. 16A.
- the second virtual pixel circuit includes a second compensation capacitor COM10, and the second compensation capacitor COM10 includes a first electrode plate CE10 and a second electrode plate CE20.
- FIG. 16D shows a structure of the second dummy pixel circuit in the first conductive layer
- FIG. 16E shows a structure of the second dummy pixel circuit in the second conductive layer.
- the first electrode plate CE10 of the fourth compensation capacitor COM10 and the first signal line 2301 are arranged on the same layer, for example, are located on the first conductive layer, and the fourth compensation capacitor COM10
- the first electrode plate CE10 is electrically connected to the first signal line 2301.
- the orthographic projection of the first signal line 2301 on the base substrate 210 and the orthographic projection of the second electrode plate CE20 of the fourth compensation capacitor COM10 on the base substrate 210 at least partially overlap.
- the first pole CE10 board of the fourth compensation capacitor COM10 includes: a second body portion CE100 and a third extension portion CE101.
- the second body portion CE100 is located on the first side of the first signal line 2301 in the second direction R2; the third extension portion CE101 extends from the second body portion CE100 in the second direction R2 toward the first signal line 2301, and is located in the second direction R2.
- a signal line 2301 is on the first side in the second direction and is located between the second body part CE100 and the first signal line 2301, and the second body part CE100 is electrically connected to the first signal line 2301 through the third extension part CE101 .
- the first pole CE20 board of the fourth compensation capacitor COM10 includes a fourth extension portion CE102, which extends from the first signal line 2301 toward a direction away from the second body portion CE100, and is located at the end of the first signal line 2301.
- the second side in the second direction R2 is electrically connected to the first signal line 2301, and the second side of the first signal line 2301 is opposite to the first side of the first signal line 2301, thereby further increasing the fourth compensation capacitor COM10 If the area of the first electrode plate CE10 is increased at the same time as the area of the second electrode plate of the fourth compensation capacitor COM10, the fourth compensation capacitor COM10 can be further increased to meet the requirements for different compensation levels of the first signal line.
- the second body portion CE100, the third extension portion CE101, the first signal line 2301, and the fourth extension portion CE102 are integrally formed, so that these structures can be formed by the same patterning process, simplifying the manufacturing process of the display substrate.
- the second electrode plate CE20 of the fourth compensation capacitor COM10 includes a third body portion CE200 and a fifth extension portion CE201.
- the third body portion CE200 is located on the first side of the first signal line 2301 in the second direction R2; the fifth extension portion CE201 extends from the third body portion CE200 in the second direction R2 toward the first signal line 2301, the first The orthographic projection of the signal line 2301 on the base substrate 210 and the orthographic projection of the fifth extension portion CE201 on the base substrate 210 at least partially overlap.
- the orthographic projection of the first plate CE10 of the fourth compensation capacitor COM10 on the base substrate 210 is located on the front of the second plate CE20 of the fourth compensation capacitor COM10 on the base substrate 210.
- a limited space is used to form the required size of the fourth compensation capacitor.
- a part 7921 of the second electrode plate CE20 of the fourth compensation capacitor COM10 may be the same as the position and pattern of the light shielding part in the pixel circuit of the display area to maintain uniformity of etching.
- the second dummy sub-pixel includes a second dummy semiconductor layer, and the second dummy semiconductor layer is located on a side of the first plate of the fourth compensation capacitor close to the base substrate.
- FIG. 16C shows the pattern of the second virtual sub-pixel, and the second virtual sub-pixel is the virtual sub-pixel A02 on the right side in FIG. 16C. As shown in conjunction with FIGS.
- the second virtual semiconductor layer includes a first portion AP21 and a second portion AP22 spaced apart so as not to be connected to each other; the first portion AP21 is located on the first side of the first signal line 2301, and the second portion AP22 is located The second side of the first signal line 2301; the orthographic projection of the first signal line 2301 on the base substrate 210 and the orthographic projection of the first dummy semiconductor layer on the base substrate 210 do not overlap, so that the second dummy pixel circuit is not There are real thin film transistors that do not realize the display function. For example, the orthographic projection of the fourth compensation capacitor COM10 on the base substrate 210 and the orthographic projection of the first virtual semiconductor layer on the base substrate do not overlap.
- FIG. 16F shows the structure of the second dummy pixel circuit on the third conductive layer.
- the second dummy pixel circuit includes a second transfer electrode CP10, the second transfer electrode CP10 and the first transfer electrode of the first dummy pixel circuit, and pixels in the display area
- the first connection portion CP1 of the circuit is arranged in the same layer, for example, they are all located on the third conductive layer, and are electrically connected to the second electrode plate CE20 of the fourth compensation capacitor COM10, for example, the second transfer electrode CP10 passes through the via hole VH40 and the via hole
- the VH50 is electrically connected to the second plate CE20 of the fourth compensation capacitor COM10 to maintain the etching uniformity between this and other positions such as the display area of the display substrate.
- the second plate CE20 of the fourth compensation capacitor COM10 is connected to the first power supply line VDD through the via hole VH40 and the via hole VH50, for example, with the first line of the first power supply line VDD.
- the line 2424 is connected to provide the first power voltage to the second plate CE20 of the fourth compensation capacitor COM10 to form the fourth compensation capacitor COM10.
- the second part AP22 of the second dummy semiconductor layer is configured to be sent an electrical signal through the second dummy pixel circuit;
- the first part AP21 of the first dummy semiconductor layer has a first end P21 and a
- the second terminal P22 and the second terminal P22 are configured to be sent the electrical signal through the second dummy pixel circuit.
- the first terminal P21 is connected to the second terminal P22, so that the electrical signal from the second terminal P2 can be transmitted to the first terminal P2.
- the terminal P21 prevents signal drift caused by no signal input at the first terminal P21. For example, as shown in FIG.
- the second terminal P22 is electrically connected to the second sub-wiring 2424 of the first power line VDD, for example, through the via hole VH20, thereby connecting the second sub-wiring from the first power line VDD.
- the first power supply voltage of 2424 is transmitted to the second terminal P22 and the first terminal P21.
- the structure of the first power supply line VDD is not limited to those shown in FIGS. 16A-16F, as long as the first power supply line VDD is connected to the second terminal P22.
- the orthographic projection of the first portion of the third signal line, such as the light-emitting scan signal line EM, on the base substrate 210 and the orthographic projection of the dummy semiconductor layer on the base substrate 210 at least partially overlap to form
- the third compensation capacitor is used to compensate the load of the third signal line to obtain a more uniform display effect.
- the second virtual pixel structure is not limited to the situation shown in FIGS. 16A-16F.
- the data lines are in the same layer as the source and drain 122/123.
- the dummy semiconductor layer can also be arranged to overlap the third signal line, such as the light-emitting scanning signal line EM, to form a third compensation capacitor.
- the embodiment of the present disclosure does not limit this.
- the second opening area 202B and the first opening area 202A are arranged along the first direction R1, so that the inter-opening area 2014 is located in the first opening area in the first direction R1 Between 202A and the second opening area 202B.
- the first display area 2011 is located on the side of the first opening area 202A away from the inter-opening area 2014
- the second display area 2012 is located on the side of the second opening area 202B away from the inter-opening area 2014.
- the first display area 2011 is located on the first side of the first opening area 202A
- the second display area 2012 is located on the second side of the second opening area 201B.
- the first display area, the first opening area, the inter-opening area, the second opening area, and the second display area are sequentially arranged along the first direction.
- the first opening area 202A and the second opening area 201B respectively, it is still satisfied that the first display area 2011 is located on the first side of the first opening area 202A, and the second display area 2012 is located on the second side of the first opening area 202A, The first side and the second side are opposite to each other in the first direction R1.
- the first signal line 23 sequentially passes through the first display area 2011, the first opening peripheral area 203A, the inter-opening area 2014, the second opening peripheral area 203B, and the second display area 2012 along the first direction R1.
- the first signal line 2301 includes a first lead portion E1A1/E2A2 located in the peripheral area 203A of the first opening (ie, taking a first signal line as an example, for example, the first lead portion is the straight line in FIG. 2B
- the section E1A1 and the straight section E2A2 and the lateral winding portion A1A2 located in the first opening peripheral area 203A that is, the lateral winding portion is the curved section A1A2 in FIG. 2B
- the lateral winding portion A1A2 is partially arranged around the first opening 201A.
- the second signal line 24 is configured to provide a second display signal to the first pixel array, and passes through the first opening peripheral area 203A in a second direction R2 that intersects the first direction R1, and includes a longitudinal winding located in the first opening peripheral area 203A.
- the line part C1C2, that is, the longitudinal winding part is the curved section C1C2 in FIG. 2B; the longitudinal winding part C1C2 is partially arranged around the first opening 201A.
- the orthographic projection of the first lead portion E1A1/E2A2 on the base substrate and the orthographic projection of the second signal line 24 on the base substrate respectively have a first overlap area S1/S2, that is, an area where the two intersect.
- the orthographic projection of the horizontal winding portion A1A2 on the base substrate and the orthographic projection of the longitudinal winding portion C1C2 on the base substrate have a second overlap area.
- the two overlap in the A1C1 section and the D1A2 section, and the second overlap area is The area represented by A1C1 and D1A2.
- a compensation capacitor is formed between the first signal line 2301 and the second signal line 24 that overlap each other in a direction perpendicular to the base substrate, thereby compensating for the first signal line Therefore, the display difference caused by the different loads of the first signal lines connecting the pixels of different rows due to the different numbers of pixels in different rows of the pixels in the first pixel array is reduced, so that the first display area 2011 and the second display
- the display effect of the area 2012 is consistent with the display effect of the pixel rows in the display area 201 where the first opening area 202A is not provided, and the display quality is improved.
- the above wiring method can also reduce the arrangement space of the first signal line and the second signal line, and reduce the area occupied by the peripheral area 203A of the first opening as much as possible. Therefore, for example, when the under-screen camera function is implemented through the first opening area 202A, the influence of the first opening area 202A on the display effect of the area is reduced, or, in other embodiments, when the first opening peripheral area 203A is located in the frame area 204 In the middle, the width of the frame area 204 can also be reduced, thereby helping to achieve a narrow frame and large-screen design of the display substrate 20. For example, as shown in FIG.
- the orthographic projection of the lead portion E1A1 of the first signal line 2301 on the base substrate and the orthographic projection of the longitudinal winding portion of the second signal line 24 on the base substrate have a first overlap area. That is, each of the plurality of first signal lines sequentially passes through the first display area, the first opening peripheral area, and the second display area along the first direction, and includes A first lead part and a lateral winding part in the peripheral area of the first opening, the lateral winding part is partially arranged around the first opening, and the first lead part is connected to the lateral winding part; the plurality of The orthographic projection of the lateral winding portion of the first signal line on the base substrate overlaps with the orthographic projection of the longitudinal winding portion of the plurality of second signal lines on the base substrate, respectively Area.
- FIG. 17 is a schematic plan view of a second virtual pixel circuit in a second virtual sub-pixel in a display substrate according to an embodiment of the present disclosure.
- the main difference between FIG. 17 and FIG. 16A is that the data line DATA is located on the side of the source and drain electrodes 122/123 away from the base substrate, and the relative position of the data line DATA and the first power line VDD in the first direction is different. Refer to Figure 16A for other structures.
- FIG. 10A is an enlarged schematic diagram of a first opening area of a display substrate provided by an embodiment of the present disclosure.
- the display substrate further includes first floating electrodes 41/42.
- the longitudinal winding part closest to the first opening 201A is the edge longitudinal winding part 2401/2402
- the first floating electrodes 41/42 are arranged in the same layer as the edge longitudinal winding part And it is located on the side of the edge longitudinal winding portion 2401/2402 close to the first opening 201A.
- the first floating electrodes 41/42 are arranged in the same layer as the edge longitudinal winding part and are located on the side of the edge longitudinal winding part 2401/2402 close to the first opening 201A, thereby avoiding the edge longitudinal winding part
- the difference in etchability increases the uniformity of etching.
- the first floating electrode is not loaded with any electrical signal and will not cause interference to other signal lines around it.
- the plurality of pixels includes a first pixel column and a second pixel column respectively extending in a second direction R2;
- the first opening 201A has a first side and a second pixel column opposite to each other in the first direction R2.
- the display substrate includes two edge longitudinal winding portions corresponding to the first opening 201A, and the two edge longitudinal winding portions include: an edge longitudinal winding portion configured to provide a second display signal to the first pixel column, and The edge longitudinal winding portion of the pixel column providing the second display signal partially surrounds the first opening on the first side of the first opening; an edge configured to provide the second display signal to the second pixel column
- the longitudinal winding part, the edge longitudinal winding part that provides the second display signal to the second pixel column partially surrounds the first opening on the second side of the first opening;
- the first floating electrode includes: a first part 41 and a first part 41 Two part 42.
- the first part 41 is located at the side of the edge longitudinal winding part that provides the second display signal to the first pixel column near the first opening 201A; the second part 42 is located at the edge longitudinal winding that provides the second display signal to the second pixel column The side of the part close to the first opening 201A.
- the line width and extension direction of the first floating electrode and the longitudinal winding portion of the edge are substantially the same, so as to further increase the etching uniformity of the longitudinal winding portion of the engraved edge.
- first interval between two adjacent second signal lines in the plurality of second signal lines for example, there is a first interval between the longitudinal winding portions of two adjacent second signal lines, and the first floating
- the interval between the electrode and the edge longitudinal winding part is substantially equal to the first interval, so as to further increase the etching uniformity of the edge longitudinal winding part.
- the first portion 41 of the first floating electrode and the second portion 42 of the first floating electrode are spaced apart from each other.
- the first part 41 of the first floating electrode and the second part of the first floating electrode are integrally formed.
- the overall planar shape formed by the first part 41 of the first floating electrode and the second part 42 of the first floating electrode is an unclosed ring surrounding the first opening 201A.
- the opening in the ring can better release the accumulated charges and avoid signal interference to the surrounding signal lines.
- the overall planar shape formed by the first part 41 of the first floating electrode and the second part 42 of the first floating electrode may also be a closed ring.
- the display substrate further includes a second floating electrode.
- the lateral winding portion closest to the first opening 201A is the edge lateral winding portion, and the second floating electrode is transverse to the edge.
- the winding part is arranged in the same layer and is arranged in a different layer from the first floating electrode.
- the second floating electrode is located on the side of the edge transverse winding part close to the first opening.
- the second floating electrode is located on the base substrate 210.
- the projection and the orthographic projection of the first floating electrode on the base substrate 210 have an overlapping area, thereby avoiding the difference in the etching properties of the lateral winding portion of the edge and increasing the etching uniformity.
- the line width and extension direction of the second floating electrode and the lateral winding portion of the edge are basically the same, so as to further increase the etching uniformity of the lateral winding portion of the edge.
- the interval between the electrode and the edge lateral winding part is substantially equal to the second interval, so as to further increase the etching uniformity of the edge lateral winding part.
- the first signal line includes a plurality of gate scan signal lines and a plurality of reset signal lines.
- the gate scan signal line 2303A (in this case, the part is the first part 2303A of the gate scan signal line) and the reset signal line 2301A (in this case, the part is the first part 2301A of the gate scan signal line)
- the lateral winding portions 2303A-1 of the gate scanning signal line 2303A and the lateral winding portions 2301A-1 of the reset signal line 2301A are alternately arranged in the second direction.
- the gate scan signal line 2303A of the plurality of gate scan signal lines 2303A closest to the first opening 201A is the edge gate scan signal line 2303A-0
- the reset signal line of the plurality of reset signal lines 2301A closest to the first opening 201A is the edge reset Signal line 2301A-0.
- the second floating electrode includes: a first sub floating electrode 511 and a second sub floating electrode 512.
- the first sub-floating electrode 511 is arranged in the same layer as the gate scanning signal line and is located on the side of the edge gate scanning signal line 2303A close to the first opening 201A; the second sub-floating electrode 512 is arranged in the same layer as the reset signal line 2301A-0 And located on the side of the edge reset signal line 2301A-0 close to the first opening 201A; the edge gate scanning signal line 2303A-0 is farther from the first opening 201A than the edge reset signal line 2301A-0, and the first sub floating electrode 511 is larger than the first opening 201A.
- the two sub-floating electrodes 512 are far away from the first opening 201A, and the orthographic projection of the first floating electrode on the base substrate at least overlaps with the first sub-floating electrode, which can solve the problem of the edge reset signal line 2301A-0 and the edge
- the etching uniformity of the reset signal line 2301A-0 is problematic.
- the edge reset signal line 2301A-0 is farther from the first opening 201A than the edge gate scan signal line 2303A-0
- the second sub floating electrode 512 is farther from the first opening 201A than the first sub floating electrode 511
- the first floating electrode The orthographic projection on the base substrate at least has an overlap area with the second sub-floating electrode, which can also solve the problem of the etching uniformity of the edge reset signal line 2301A-0 and the edge reset signal line 2301A-0.
- the part of the plurality of second signal lines includes a first part of the second signal line 2410 and a second part of the second signal line 2412, and the first part of the second signal line 2410 is connected to the
- the second part of the second signal lines 2412 are arranged in different layers and alternately arranged in the first direction. Please refer to the previous description for the layer on which they are located.
- the second signal line closest to the first opening in the first part of the second signal line 2410 is the edge first sub-data signal line
- the second signal line closest to the first opening in the second part of the second signal line 2412 is the edge
- the orthographic projection on the substrate has an overlapping area, and the orthographic projection of the longitudinal winding portion of each second signal line in the second part of the second signal line on the base substrate is the same as the lateral winding of each reset signal line.
- the orthographic projection of the line portion on the base substrate has an overlapping area;
- the first floating electrode includes: a third sub-floating electrode 411 and a fourth sub-floating electrode 412.
- the third sub-floating electrode 411 is arranged in the same layer as the first part of the second signal line 2410 and is located on the edge of the first sub-data signal line on the side close to the first opening;
- the fourth sub-floating electrode 412 is the same as the second part of the second signal line
- the line 2412 is arranged in the same layer and is located on the side of the second sub-data signal line of the edge close to the first opening 201A;
- the orthographic projection of the third sub-floating electrode 411 on the base substrate has an overlapping area with the first sub-floating electrode 511 ,
- the orthographic projection of the fourth sub-floating electrode 412 on the base substrate and the second sub-floating electrode 512 have an overlapping area.
- the first part of the second signal line 2410 (here, the longitudinal winding part) is arranged on the same layer as the source and drain 122/123, and the second part of the second signal line 2412 (here, the longitudinal winding part) is located at
- the first part of the second signal line 2410 is on the side away from the base substrate; multiple gate scan signal lines are arranged on the same layer as the second plate of the storage capacitor, and multiple reset signal lines are connected to the first electrode of the storage capacitor CST.
- the plate CE1 is arranged in the same layer; or, the multiple gate scan signal lines are arranged in the same layer as the first plate CE1 of the storage capacitor CST, and the multiple reset signal lines are arranged on the same layer as the second plate CE1 of the storage capacitor CST.
- CE2 is set at the same layer.
- the gate scan signal line and the reset signal line are both wound at the first opening, instead of being disconnected at the first opening.
- the plurality of first signal lines include a plurality of gate scan signal lines and a plurality of reset signal lines, and the gate scan signal lines and the reset signal lines are arranged in different layers; each The gate scan signal line sequentially passes through the first display area, the first opening peripheral area, and the second display area along the first direction, and includes a first lead portion located in the first opening peripheral area And a lateral winding part, wherein the lateral winding part is partially arranged around the first opening, and the first lead part is connected to the lateral winding part; each of the reset signal lines includes: a first part And the second part.
- the first part passes through the first display area in the first direction; the second part passes through the second display area in the first direction, and is separated from the first part by the first opening area. That is, the gate scan signal line is wound at the first opening, and the reset signal line is disconnected at the first opening.
- the plurality of first signal lines include a plurality of gate scan signal lines and a plurality of reset signal lines, and the gate scan signal lines and the reset signal lines are arranged in different layers; each The reset signal line sequentially passes through the first display area, the first opening peripheral area, and the second display area along the first direction, and includes a first lead part and a first lead located in the first opening peripheral area.
- the lateral winding part wherein the lateral winding part is partially arranged around the first opening, and the first lead part is connected to the lateral winding part; each of the gate scan signal lines includes: a first part And the second part.
- the first portion passes through the first display area along the first direction; the second portion passes through the second display area along the first direction, and is separated from the first portion by the first opening area . That is, the reset signal line is wound at the first opening, and the gate scan signal line is disconnected at the first opening.
- the plurality of first signal lines include a plurality of gate scan signal lines and a plurality of reset signal lines, and the gate scan signal lines and the reset signal lines are arranged in different layers; each The gate scan signal line includes: a first part and a second part. The first portion passes through the first display area along the first direction; the second portion passes through the second display area along the first direction, and is separated from the first portion by the first opening area And, each of the reset signal lines includes: a first part and a second part, the first part passes through the first display area in the first direction; the second part passes through the first display area in the first direction The second display area is separated from the first portion by the first opening area. That is, the gate scan signal line and the reset signal line are both disconnected at the first opening.
- a bilateral drive method can be adopted to load the disconnected signal lines with drive signals from both sides of the substrate in the first direction.
- a bilateral drive method can be adopted to load the disconnected signal lines with drive signals from both sides of the substrate in the first direction.
- the display substrate may further include outer floating electrodes.
- the longitudinal winding part farthest from the first opening among the longitudinal winding parts of the portion of the plurality of second signal lines is an outer edge longitudinal winding part, and the outer floating electrode is longitudinally connected to the outer edge.
- the winding part is arranged in the same layer and is located on a side of the outer edge longitudinal winding part away from the first opening, so as to increase the etching uniformity of the outer longitudinal winding part.
- each of the portions of the plurality of second signal lines further includes a second lead part.
- the second lead part extends along the second direction and is connected to the longitudinal winding part.
- the arrangement density of the second lead part is greater than the arrangement density of the longitudinal winding part.
- the line width of the second lead part is substantially equal to the line width of the longitudinal winding part. Due to the difference in arrangement density and the limitation of the etching process, the design line width of the second lead part is made smaller than the longitudinal direction in the manufacturing process.
- the design line width of the winding part can make the final line width of the two formed basically equal. Or, if the difference in the design line width is not made, the line width of the second lead part is smaller than the line width of the longitudinal winding part.
- At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
- the display device may be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other devices with display functions or other types of devices, which are not limited in the embodiments of the present disclosure.
- the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
- a display function such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
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Abstract
Description
图4J是显示基板的局部图;
图12是图11中的局部G的放大示意图;
图16A为本公开一实施例提供的一种显示基板中的一个第二虚拟子像素中的第二虚拟像素电路的平面布局示意图;
图16B为沿图16A中的A3-B3线的截面示意图;
图16C-图16F为本公开一实施例提供的一种显示基板的第二虚拟像素电路的各层的示意图;
Claims (17)
- 一种显示基板,包括:衬底基板,包括:第一开口区域,包括第一开口和围绕所述第一开口的第一开口周边区域;显示区域,至少部分围绕所述第一开口区域,包括:第一显示区域,位于所述第一开口区域的第一侧;以及第二显示区域,位于所述第一开口区域的第二侧,其中,所述第一侧与所述第二侧在第一方向上彼此相对,所述第一显示区域和所述第二显示区域包括多个像素;多条第一信号线,配置为给所述多个像素提供第一显示信号,沿所述第一方向延伸且穿过所述第一显示区域和所述第二显示区域;多条第二信号线,配置为给所述多个像素提供第二显示信号,沿与所述第一方向相交的第二方向延伸,所述多条第二信号线的部分沿所述第二方向穿过所述第一开口周边区域,所述多条第二信号线的所述部分中的每条第二信号线包括位于所述第一开口周边区域的纵向绕线部,其中,所述纵向绕线部部分地围绕所述第一开口设置;以及第一浮置电极,其中,所述多条第二信号线的纵向绕线部中最靠近所述第一开口的纵向绕线部为边缘纵向绕线部,所述第一浮置电极与所述边缘纵向绕线部同层设置且位于所述边缘纵向绕线部的靠近所述第一开口的一侧。
- 根据权利要求1所述的显示基板,其中,所述第一浮置电极与所述边缘纵向绕线部的线宽和延伸方向基本相同。
- 根据权利要求1所述的显示基板,其中,所述多条第二信号线中相邻两条第二信号线之间具有第一间隔,所述第一浮置电极与所述边缘纵向绕线部之间的间隔与所述第一间隔基本相等。
- 根据权利要求1-3任一所述的显示基板,其中,所述多个像素包括分别沿所述第二方向延伸的第一像素列和第二像素列;所述第一开口具有在所述第一方向上彼此相对的第一侧和第二侧,以及在所述第二方向上彼此相对的第三侧和第四侧;所述显示基板包括与所述第一开口对应设置的两条所述边缘纵向绕线部,所述两条边缘纵向绕线部包括:配置为给所述第一像素列提供所述第二显示信号的所述边缘纵向绕线部,其中,给所述第一像素列提供所述第二显示信号的所述边缘纵向绕线部在所述第一开口的第一侧部分地围绕所述第一开口;以及配置为给所述第二像素列提供所述第二显示信号的所述边缘纵向绕线部,其中,给所述第二像素列提供所述第二显示信号的所述边缘纵向绕线部在所述第一开口的第二侧部分地围绕所述第一开口;所述第一浮置电极包括:第一部分,位于给所述第一像素列提供所述第二显示信号的所述边缘纵向绕线部的靠近所述第一开口的一侧;第二部分,位于给所述第二像素列提供所述第二显示信号的所述边缘纵向绕线部的靠近所述第一开口的一侧。
- 根据权利要求4所述的显示基板,其中,所述第一浮置电极的第一部分与述第一浮置电极的第二部分彼此间隔开。
- 根据权利要求4所述的显示基板,其中,所述第一浮置电极的第一部分与述第一浮置电极的第二部分一体成型。
- 根据权利要求6所述的显示基板,其中,所述第一浮置电极的第一部分与所述第一浮置电极的第二部分构成的整体的平面形状为围绕所述第一开口的不封闭的环形或者封闭的环形。
- 根据权利要求1-7任一所述的显示基板,其中,所述多条第一信号线中的每条沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域和所述第二显示区域,且包括位于所述第一开口周边区域的第一引线部和横向绕线部,其中,所述横向绕线部部分围绕所述第一开口设置,所述第一引线部与所述横向绕线部连接;所述多条第一信号线的横向绕线部在所述衬底基板上的正投影分别与所述多条第二信号线的所述部分的纵向绕线部在所述衬底基板上的正投影具有重叠区;所述显示基板还包括:第二浮置电极,所述多条第一信号线的横向绕线部中最靠近所述第一开口的横向绕线部为边缘横向绕线部,所述第二浮置电极与所述边缘横向绕线部同层设置且与所述第一浮置电极异层设置,其中,所述第二浮置电极位于 所述边缘横向绕线部的靠近所述第一开口的一侧,所述第二浮置电极在所述衬底基板上的正投影与所述第一浮置电极在所述衬底基板上的正投影具有重叠区。
- 根据权利要求8所述的显示基板,其中,所述第一信号线包括多条栅扫描信号线和多条复位信号线,所述栅扫描信号线与所述复位信号线异层设置,并且,所述栅扫描信号线的横向绕线部与所述复位信号线的横向绕线部在所述第二方向上交替排布;所述多条栅扫描信号线中最靠近所述第一开口的栅扫描信号线为边缘栅扫描信号线,所述多条复位信号线中最靠近所述第一开口的复位信号线为边缘复位信号线;所述第二浮置电极包括:第一子浮置电极,与所述栅扫描信号线同层设置且位于所述边缘栅扫描信号线的靠近所述第一开口的一侧;以及第二子浮置电极,与所述复位信号线同层设置且位于所述边缘复位信号线的靠近所述第一开口的一侧;所述边缘栅扫描信号线比所述边缘复位信号线远离所述第一开口,所述第一子浮置电极比所述第二子浮置电极远离所述第一开口,所述第一浮置电极在所述衬底基板上的正投影至少与所述第一子浮置电极具有重叠区;或者,所述边缘复位信号线比所述边缘栅扫描信号线远离所述第一开口,所述第二子浮置电极比所述第一子浮置电极远离所述第一开口,所述第一浮置电极在所述衬底基板上的正投影至少与所述第二子浮置电极具有重叠区。
- 根据权利要求9所述的显示基板,其中,所述多条第二信号线的所述部分包括第一部分第二信号线和第二部分第二信号线,所述第一部分第二信号线与所述第二部分第二信号线异层设置且在所述第一方向上交替排布;所述第一部分第二信号线中最靠近所述第一开口的第二信号线为边缘第一子数据信号线,所述第二部分第二信号线中最靠近所述第一开口的第二信号线为边缘第二子数据信号线;所述第一部分第二信号线中的每条第二信号线的纵向绕线部在所述衬底基板上的正投影与一条所述栅驱动扫描信号线的横向绕线部在所述衬底基板上的正投影具有重叠区,所述第二部分第二信号线中的每条第二信号线的纵 向绕线部在所述衬底基板上的正投影与每条所述复位信号线的横向绕线部在所述衬底基板上的正投影具有重叠区;所述第一浮置电极包括:第三子浮置电极,与所述第一部分第二信号线同层设置且位于所述边缘第一子数据信号线的靠近所述第一开口的一侧;以及第四子浮置电极,与所述第二部分第二信号线同层设置且位于所述边缘第二子数据信号线的靠近所述第一开口的一侧;所述第三子浮置电极在所述衬底基板上的正投影与所述第一子浮置电极具有重叠区,所述第四子浮置电极在所述衬底基板上的正投影与所述第二子浮置电极具有重叠区。
- 根据权利要求10所述的显示基板,其中,每个所述像素包括多个子像素,每个所述子像素包括像素电路,所述像素电路包括:晶体管,包括有源层、栅极和源漏极;发光元件,与所述晶体管的源漏极之一连接;以及存储电容,包括第一极板和第二极板,其中,所述第一部分第二信号线与所述源漏极同层设置,所述第二部分第二信号线位于所述第一部分第二信号线的远离所述衬底基板的一侧;所述多条栅扫描信号线与所述存储电容的第二极板同层设置,所述多条复位信号线与所述存储电容的第一极板同层设置;或者,所述多条栅扫描信号线与所述存储电容的第一极板同层设置,所述多条复位信号线与所述存储电容的第二极板同层设置。
- 根据权利要求1-7任一所述的显示基板,其中,所述多条第一信号线包括多条栅扫描信号线和多条复位信号线,所述栅扫描信号线与所述复位信号线异层设置;每条所述栅扫描信号线沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域和所述第二显示区域,且包括位于所述第一开口周边区域的第一引线部和横向绕线部,其中,所述横向绕线部部分地围绕所述第一开口设置,所述第一引线部与所述横向绕线部连接;每条所述复位信号线包括:第一部分,沿所述第一方向穿过所述第一显示区域;第二部分,沿所述第一方向穿过所述第二显示区域,与所述第一部分被所述第一开口区域间隔。
- 根据权利要求1-7任一所述的显示基板,其中,所述多条第一信号线包括多条栅扫描信号线和多条复位信号线,所述栅扫描信号线与所述复位信号线异层设置;每条所述复位信号线沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域和所述第二显示区域,且包括位于所述第一开口周边区域的第一引线部和横向绕线部,其中,所述横向绕线部部分地围绕所述第一开口设置,所述第一引线部与所述横向绕线部连接;每条所述栅扫描信号线包括:第一部分,沿所述第一方向穿过所述第一显示区域;第二部分,沿所述第一方向穿过所述第二显示区域,与所述第一部分被所述第一开口区域间隔。
- 根据权利要求1-7任一所述的显示基板,其中,所述多条第一信号线包括多条栅扫描信号线和多条复位信号线,所述栅扫描信号线与所述复位信号线异层设置;每条所述栅扫描信号线包括:第一部分,沿所述第一方向穿过所述第一显示区域;以及第二部分,沿所述第一方向穿过所述第二显示区域,与所述第一部分被所述第一开口区域间隔;并且,每条所述复位信号线包括:第一部分,沿所述第一方向穿过所述第一显示区域;第二部分,沿所述第一方向穿过所述第二显示区域,与所述第一部分被所述第一开口区域间隔。
- 根据权利要求1-14任一所述的显示基板,还包括:外侧浮置电极,其中,所述多条第二信号线的所述部分的纵向绕线部中最远离所述第一开口的纵向绕线部为外边缘纵向绕线部,所述外侧浮置电极与所述外边缘纵向绕线部同层设置且位于所述外边缘纵向绕线部的远离所述第一开口的一侧。
- 根据权利要求1-15任一所述的显示基板,其中,所述多条第二信号 线的所述部分的每条所述第二信号线还包括:第二引线部,沿所述第二方向延伸且与所述纵向绕线部连接,其中,所述第二引线部的排布密度大于所述纵向绕线部的排布密度;所述第二引线部的线宽与所述纵向绕线部的线宽基本相等,或者,所述第二引线部的线宽小于所述纵向绕线部的线宽。
- 一种显示装置,包括根据权利要求1-16任一所述的显示基板。
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WO2021243879A1 (zh) | 2021-12-09 |
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