WO2023124578A1 - 电路板集成电感、其制备方法及电子设备 - Google Patents

电路板集成电感、其制备方法及电子设备 Download PDF

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Publication number
WO2023124578A1
WO2023124578A1 PCT/CN2022/131429 CN2022131429W WO2023124578A1 WO 2023124578 A1 WO2023124578 A1 WO 2023124578A1 CN 2022131429 W CN2022131429 W CN 2022131429W WO 2023124578 A1 WO2023124578 A1 WO 2023124578A1
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Prior art keywords
layer
circuit board
magnetic
alloys
magnetic film
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PCT/CN2022/131429
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English (en)
French (fr)
Inventor
陈奕君
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Oppo广东移动通信有限公司
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Publication of WO2023124578A1 publication Critical patent/WO2023124578A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding

Definitions

  • the present application relates to the field of electronics, in particular to a circuit board integrated inductor, its preparation method and electronic equipment.
  • Inductance is an indispensable component of electronic equipment. Most of the current inductors are prepared as inductors and then mounted on the circuit board. This not only occupies the area of the circuit board, but also requires discrete mounting, which reduces packaging efficiency.
  • circuit board integrated inductor which includes:
  • a magnetic film layer is arranged on at least one of the opposite sides of the circuit board, and at least partially overlaps the coil, and the magnetic film layer includes at least two magnetic film sub-layers and at least one insulating sublayer, the magnetic film sublayers and the insulating sublayers are stacked alternately in sequence.
  • the embodiment of the second aspect of the present application provides a method for preparing a circuit board integrated inductor, which includes:
  • At least one of the opposite sides of the circuit board is alternately deposited with magnetic film sublayers and insulating sublayers to form a magnetic film layer on at least one of the two opposite sides of the circuit board, wherein, The magnetic film layer at least partially overlaps the coil, and the magnetic film layer includes at least two magnetic film sublayers and at least one insulating sublayer.
  • the embodiment of the third aspect of the present application provides an electronic device, and the electronic device includes the circuit board integrated inductor described in the embodiment of the present application.
  • FIG. 1 is a schematic perspective view of a circuit board integrated inductor according to an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structural diagram of a circuit board integrated inductor along the direction A-A in FIG. 1 according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a circuit board according to an embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional structure diagram of a circuit board along the direction A-A in FIG. 1 according to another embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a circuit board according to another embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional structure diagram of a circuit board along the direction A-A in FIG. 1 according to another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a circuit board according to another embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of a coil according to another embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a circuit board according to another embodiment of the present application.
  • FIG. 10 is a block diagram of a circuit structure of a circuit board integrated inductor according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a magnetic film layer according to an embodiment of the present application.
  • FIG. 12 is a schematic cross-sectional structure diagram of a circuit board integrated inductor according to another embodiment of the present application along the direction A-A in FIG. 1 .
  • FIG. 13 is a schematic flowchart of a method for manufacturing a circuit board integrated inductor according to an embodiment of the present application.
  • FIG. 14 is a schematic flowchart of a method for preparing a circuit board according to an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a first substrate according to an embodiment of the present application.
  • FIG. 16 is a schematic flowchart of a method for preparing a circuit board according to another embodiment of the present application.
  • FIG. 17 is a schematic flowchart of a method for preparing a circuit board according to another embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a second substrate according to an embodiment of the present application.
  • FIG. 19 is a schematic flowchart of a method for manufacturing a circuit board integrated inductor according to an embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • FIG. 21 is a schematic diagram of a partial exploded structure of an electronic device according to an embodiment of the present application.
  • FIG. 22 is a circuit block diagram of an electronic device according to an embodiment of the present application.
  • the present application provides a circuit board integrated inductor, which includes:
  • a magnetic film layer is arranged on at least one of the opposite sides of the circuit board, and at least partially overlaps the coil, and the magnetic film layer includes at least two magnetic film sub-layers and at least one insulating sublayer, the magnetic film sublayers and the insulating sublayers are stacked alternately in sequence.
  • the circuit board includes at least one supporting insulating layer and at least one conductive layer; the supporting insulating layer and the conductive layer are stacked alternately in sequence, and the conductive layer includes a wire; when the conductive layer is a layer When the conductive layer is single-layer, the wires form the coil; when the conductive layer is multi-layered, the wires of any two adjacent conductive layers are electrically connected to form the coil.
  • the magnetic film sublayer includes at least one of magnetic metals and magnetic alloys;
  • the magnetic metals include at least one of iron, cobalt, and nickel;
  • the magnetic alloys include iron-based crystalline alloys, iron-based non- At least one of crystalline alloys and cobalt-based amorphous alloys;
  • the iron-based crystalline alloys include at least one of FeNi alloys, FeCo alloys, FeAl alloys, FeSiAl alloys, FeNiMo alloys, and FeC alloys;
  • the crystalline alloy includes at least one of FeSiB alloy, FeB alloy, FeNiPB alloy, and FeNiMoB alloy;
  • the cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, CoFeCrSiB alloy, and CoNiFeSiB alloy.
  • the thickness h1 of each magnetic film sublayer is in the range of 0.5 ⁇ m ⁇ h1 ⁇ 30 ⁇ m, and the total thickness of the at least one magnetic film sublayer is The range of h is 0.5 ⁇ m ⁇ h ⁇ 200 ⁇ m.
  • the circuit board integrated inductor further includes a dielectric layer, and the dielectric layer is located between the coil and the magnetic film layer.
  • the medium layer is a magnetic glue layer
  • the magnetic glue layer includes resin and magnetic particles, and the magnetic particles are dispersed in the resin.
  • the weight fraction of the magnetic particles ranges from 30% to 90%.
  • the range of the average particle diameter D of the magnetic particles is 5 ⁇ m ⁇ D ⁇ 50 ⁇ m.
  • the resin includes at least one of epoxy resin, polyurethane and acrylate.
  • the magnetic particles include at least one of ferrite particles, magnetic metal particles, and magnetic alloy particles; the ferrite includes at least one of MnZn ferrite and NiZn ferrite; the magnetic metal The particles include at least one of iron, cobalt, and nickel; the magnetic alloy particles include at least one of iron-based crystalline alloys, iron-based amorphous alloys, and cobalt-based amorphous alloys; the iron-based crystalline alloys include At least one of FeNi alloy, FeCo alloy, FeAl alloy, FeSiAl alloy, FeNiMo alloy, and FeC alloy; the iron-based amorphous alloy includes at least one of FeSiB alloy, FeB alloy, FeNiPB alloy, and FeNiMoB alloy; the The cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, CoFeCrSiB alloy and CoNiFeSiB alloy.
  • the medium layer is at least one of glass fiber/epoxy resin composite board, polyimide, polypropylene, and polytetrafluoroethylene.
  • the thickness h2 of the dielectric layer is in the range of 5 ⁇ m ⁇ h2 ⁇ 200 ⁇ m.
  • the insulator layer includes at least one of a ceramic insulating layer and an organic insulating layer; the ceramic insulating layer includes at least one of alumina and silicon dioxide; the organic insulating layer includes polypropylene, polytetrafluoroethylene At least one of vinyl and polyimide.
  • the thickness h3 of the insulator layer is in the range of 50nm ⁇ h3 ⁇ 500nm.
  • the circuit board further includes a substrate and a functional circuit, the functional circuit is carried on the substrate and electrically connected to the coil.
  • the present application provides a method for preparing a circuit board integrated inductor, which includes:
  • At least one of the opposite sides of the circuit board is alternately deposited with magnetic film sublayers and insulating sublayers to form a magnetic film layer on at least one of the two opposite sides of the circuit board, wherein, The magnetic film layer at least partially overlaps the coil, and the magnetic film layer includes at least two magnetic film sublayers and at least one insulating sublayer.
  • circuit board includes:
  • the first substrate comprising a supporting insulating layer and a conductor layer disposed on at least one of two surfaces opposite to the supporting insulating layer;
  • said providing circuit board also includes:
  • the second substrate comprising a supporting insulating layer and a conductor layer disposed on a surface of the supporting insulating layer;
  • the circuit board includes at least one supporting insulating layer and at least one conductive layer; the supporting insulating layer and the conductive layer
  • the coils are stacked alternately in sequence; wherein, each conductive layer includes wires; the wires of any two adjacent conductive layers are electrically connected to form the coil.
  • the method further includes:
  • a dielectric layer is formed on at least one of the two opposite surfaces of the circuit board, and the dielectric layer at least covers the coil.
  • the present application provides an electronic device, which includes the circuit board integrated inductor described in the first aspect or any one of the first aspect.
  • the inductor is composed of a coil and a magnetic part. When an alternating current passes through the coil, an alternating magnetic flux is generated inside and around the coil, which has the function of storing and releasing energy.
  • the inductance acts on the AC finite current, and it can form a high-pass filter or a low-pass filter, a phase-shifting circuit and a resonant circuit with a resistor or a capacitor, so it is widely used in various instruments and equipment.
  • the inductance device occupies a large area on the circuit board.
  • the inductance device occupies more than 40% of the surface area of the power board, which is not conducive to the miniaturization and high density of the product; and most inductance devices Both require discrete mounting, which reduces packaging efficiency.
  • Inductors are usually directly deposited on the surface with a single-layer magnetic film on the opposite sides of the coil. The thickness is generally tens of microns to one or two hundred microns, and the thickness is relatively large. The eddy current effect is easily generated in the thickness direction of the film, which increases the eddy current loss, reduces the efficiency of the inductor, and tends to aggravate the heating of the inductor.
  • the circuit board integrated inductor 100 of this embodiment includes a circuit board 10 and a magnetic film layer 30, the circuit board 10 is embedded with a coil 11; the magnetic film layer 30 is arranged on at least one of the opposite sides of the circuit board 10, and At least partially overlapping with the coil 11 , the magnetic film layer 30 includes at least two magnetic film sublayers 31 and at least one insulating sublayer 33 , and the magnetic film sublayers 31 and the insulating sublayers 33 are alternately stacked in sequence.
  • At least one means more than one, in other words, greater than or equal to one.
  • At least one layer means more than one layer, in other words, greater than or equal to one layer.
  • At least two layers means more than two layers, in other words, greater than or equal to two layers.
  • the circuit board 10 may be a flexible circuit board (FPC), or a printed circuit board (PCB), which is not specifically limited in this application.
  • FPC flexible circuit board
  • PCB printed circuit board
  • the number of coils 11 on the circuit board 10 can be one or multiple, for example, but not limited to 1, 2, 3, etc.
  • the specific number of coils 11 can be set according to actual application requirements , this application does not specifically limit. Multiple refers to two or more or greater than or equal to two. It can be understood that each coil 11 can be, but not limited to, a part of a one-turn coil 11 (such as a half-turn coil 11, a 0.3-turn coil 11, etc.), a one-turn coil 11, a two-turn coil 11, a three-turn coil 11, and a four-turn coil. Turn coil 11, five-turn coil 11, etc. The more turns of the coil 11, the greater the inductance when other conditions remain unchanged. Therefore, the number of turns of the coil 11 can be designed according to the application scene, the required inductance, etc., and this application does not make specific limitations. .
  • the circuit board 10 is embedded with the coil 11 , in other words, the coil 11 is embedded in the circuit board 10 .
  • the coil 11 is embedded in the circuit board 10, and the coil 11 can be at least partially wrapped by the circuit board 10; it can also be an integrated structure of the coil 11 and the circuit board 10, and the coil 11 is directly composed of the wires in the circuit board 10, and the circuit board 10 During the preparation process, the coil 11 is formed together; the coil 11 can also be pierced through the circuit board 10 , in other words, the coil 11 partially passes through the circuit board 10 and partially exposes the circuit board 10 .
  • the magnetic film layer 30 refers to a film layer that includes continuous magnetic materials without interruptions in the middle.
  • the magnetic film sub-layer 31 refers to a film layer that is a continuous magnetic material with no breaks in the middle.
  • the magnetic film layer 30 is arranged on at least one side in the opposite sides of the circuit board 10, and the magnetic film layer 30 can be arranged on one side of the circuit board 10, such as being arranged on the surface of the circuit board 10, or the circuit board 10
  • the surface of the surface is provided with film layers such as dielectric layer 50, and magnetic film layer 30 is arranged on the surface of film layer such as dielectric layer 50; It can also be that magnetic film layer 30 is arranged on opposite sides of circuit board 10, in other words, circuit board 10 opposite sides are provided with a magnetic film layer 30, such as the two opposite surfaces of the circuit board 10 are provided with a magnetic film layer 30, or the two opposite surfaces of the circuit board 10 are provided with a dielectric layer 50, the magnetic The film layer 30 is disposed on the surface of the dielectric layer 50 .
  • At least partially overlapping refers to at least partially overlapping the orthographic projection of the magnetic film layer 30 and the coil 11 on the surface of the circuit board 10 .
  • the magnetic film layer 30 and the coil 11 overlap at least partially, and the magnetic film layer 30 and the coil 11 can be partially overlapped; the magnetic film layer 30 can also cover the surface of the entire coil 11; the magnetic film layer 30 can also cover part of the coil 11 , located within the coil 11, etc.
  • the magnetic film layer 30 includes at least two magnetic film sub-layers 31 and at least one insulating sub-layer 33.
  • the magnetic film sub-layers 31 and the insulating sub-layers 33 are stacked alternately in sequence. It may be, but not limited to, that the magnetic film layer 30 includes two magnetic film layers.
  • Sub-layer 31 and one layer of insulating sub-layer 33 two layers of magnetic sub-layers are arranged opposite to each other at intervals, and insulating sub-layer 33 is arranged between two layers of magnetic sub-layers; or, magnetic film layer 30 includes three layers of magnetic film sub-layers 31 and two layers The insulating sublayer 33, the magnetic film sublayer 31 and the insulating sublayer 33 are stacked alternately in sequence; or, the magnetic film layer 30 includes four magnetic film sublayers 31 and three insulating sublayers 33, and the magnetic film sublayer 31 and the insulating sublayer 33 are alternately arranged successively. Cascading settings. Alternatively, the magnetic film layer 30 includes five magnetic film sub-layers 31 and four insulating sub-layers 33 , the magnetic film sub-layers 31 and the insulating sub-layers 33 are stacked alternately in sequence, and so on.
  • the circuit board integrated inductor 100 of this embodiment integrates the inductor on the circuit board 10, and when applied to electronic equipment, it can make the electronic equipment more miniaturized and ultra-thin, and the inductor is prepared together with the circuit board 10 without the need for a separate paste. package, improving packaging efficiency.
  • the inductor is integrated in the circuit board 10, and the position corresponding to the inductor on the circuit board 10 can be saved for mounting other components, saving the area on the circuit board 10, and enhancing the wiring and layout capabilities of the circuit board 10 .
  • the thickness of the magnetic layer is too thick, a large eddy current effect will be generated in the thickness direction of the magnetic layer.
  • the magnetic film layer 30 of the circuit board integrated inductor 100 of the present application includes at least two magnetic film sub-layers 31 and At least one insulating sublayer 33, the magnetic film sublayer 31 and the insulating sublayer 33 are stacked alternately in sequence, compared with the scheme in which the magnetic film layer 30 is a single magnetic layer, the magnetic layer in the magnetic film layer 30 is divided into at least two layers Magnetic film sub-layer 31, is provided with insulating sub-layer 33 between two adjacent magnetic film sub-layers 31, and insulating sub-layer 33 can stop the conduction of the eddy current in the magnetic film in the thickness direction, thereby reduces the whole magnetic film layer 30 in the thickness direction. On the eddy current loss, thereby reducing the eddy current loss of the entire inductor.
  • the circuit board 10 includes at least one supporting insulating layer 12 and at least one conductive layer 14; the supporting insulating layer 12 and the conductive layer 14 are stacked alternately in sequence, and the conductive layer 14 includes Wire 14a; when conductive layer 14 is one layer, the wire 14a of single-layer conductive layer 14 forms coil 11; When conductive layer 14 is multilayer, the wire 14a of any adjacent two layers of conductive layer 14 is electrically connected, forms coil 11.
  • the coil 11 of the inductor is integrated into the circuit board 10 , which simplifies the manufacturing process, and the obtained circuit board integrated inductor 100 is more ultra-thin and miniaturized.
  • the circuit board 10 includes at least one supporting insulating layer 12 and at least one conductive layer 14 ; the supporting insulating layer 12 and the conductive layer 14 are stacked alternately in sequence.
  • the circuit board 10 includes a layer of supporting insulating layer 12 and a layer of conductive layer 14 that are stacked, and the conductive layer 14 includes wires 14a, such as one, two, three, four etc., the wire 14a forms the coil 11 (or in other words, one wire 14a forms one coil 11).
  • wires 14a such as one, two, three, four etc.
  • the circuit board 10 includes a layer of supporting insulating layer 12 and two layers of conductive layers 14 that are stacked, and the two layers of conductive layers 14 are respectively arranged on the supporting insulating layer 12 opposite to each other.
  • the two conductive layers 14 include wires 14 a on both surfaces of the two conductive layers 14 , and the wires 14 a of the two conductive layers 14 are electrically connected to form the coil 11 . As shown in FIG.
  • the circuit board 10 includes two layers of supporting insulating layers 12 and three layers of conductive layers 14 stacked, the supporting insulating layers 12 and the conductive layers 14 are alternately stacked in sequence, and the three layers of conductive layers 14 each includes a wire 14a, and the wires 14a of any two adjacent conductive layers 14 are electrically connected to form the coil 11 .
  • the present application does not specifically limit the number of supporting insulating layers 12 and conductive layers 14 in the circuit board 10, as long as a structure in which supporting insulating layers 12 and conductive layers 14 are alternately stacked in sequence can be formed, which can be designed according to actual needs.
  • the circuit board 10 includes a layer of supporting insulating layer 12 and a layer of conductive layer 14 which are laminated.
  • the conductive layer 14 includes a wire 14a, and the wire 14a forms a coil 11, as shown in FIG. 5 .
  • the circuit board 10 includes a layer of supporting insulating layer 12 and two layers of conductive layers 14 that are stacked.
  • the conductive layers 14 each include a wire 14 a, and the wires 14 a of the two conductive layers 14 are electrically connected to form a coil 11 , as shown in FIG. 3 .
  • the circuit board 10 includes a layer of supporting insulating layer 12 and two layers of conductive layers 14 that are stacked.
  • the conductive layers 14 each include two wires 14a, wherein one wire 14a of the two layers of conductive layers 14 is electrically connected to form a coil 11, and the other wire 14a of the two layers of conductive layers 14 is electrically connected to form another coil 11, in other words, formed Two coils 11 are shown in FIG. 7 .
  • the supporting insulating layer 12 may include, but is not limited to, at least one of polyimide (PI), glass fiber/epoxy composite board (Prepreg), and the like.
  • the wire 14a may include, but is not limited to, at least one of copper, silver conductive metal, or an alloy.
  • polyimide can be used as the supporting insulating layer 12
  • PCB board printed circuit board
  • the glass fiber/epoxy resin composite board can be used as the support insulating layer 12.
  • the supporting insulating layer 12 is polyimide
  • the wire 14a is copper wire.
  • each supporting insulating layer 12 is 10 ⁇ m to 50 ⁇ m; specifically, it can be but not limited to 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, 45 ⁇ m, 50 ⁇ m, etc.
  • the thickness of the supporting insulating layer 12 is too small, such as when less than 10 ⁇ m, the mechanical properties of the supporting insulating layer 12 are limited, and it is difficult to effectively support the conductive layer 14; because the magnetic permeability of the supporting insulating layer 12 is very low, the supporting insulating layer 12 If the thickness is too large, such as greater than 50 ⁇ m, the length of the magnetic circuit will be increased, which will increase the reluctance, which is not conducive to the performance of the obtained inductor.
  • the thickness of the wire 14 a is 50 ⁇ m to 150 ⁇ m, and the thickness of the wire 14 a can be any value between 50 ⁇ m and 150 ⁇ m, including the endpoint 50 ⁇ m and the endpoint 150 ⁇ m.
  • the thickness d1 of the wire 14a ranges from 50 ⁇ m to 150 ⁇ m, specifically, but not limited to 50 ⁇ m, 60 ⁇ m, 70 ⁇ m, 80 ⁇ m, 90 ⁇ m, 100 ⁇ m, 110 ⁇ m, 120 ⁇ m, 130 ⁇ m, 140 ⁇ m, 150 ⁇ m, etc.
  • the width d2 of the wire 14a (that is, the width parallel to the extending direction of the supporting insulating layer 12) ranges from 100 ⁇ m to 300 ⁇ m; 180 ⁇ m, 200 ⁇ m, 220 ⁇ m, 240 ⁇ m, 280 ⁇ m, 300 ⁇ m, etc.
  • the line distance d3 of the two oppositely arranged wires 14a ranges from 100 ⁇ m to 200 ⁇ m; specifically, it can be but not limited to 100 ⁇ m, 110 ⁇ m, 120 ⁇ m, 130 ⁇ m, 140 ⁇ m, 150 ⁇ m, 180 ⁇ m , 200 ⁇ m.
  • the thickness of the wire 14 a is 100 ⁇ m
  • the width of the wire 14 a is 200 ⁇ m
  • the pitch of the wire 14 a is 150 ⁇ m.
  • the circuit board 10 further includes a substrate 10 a and a functional circuit 10 b , the functional circuit 10 b is carried on the substrate 10 a and is electrically connected to the coil 11 .
  • the substrate 10 a and the supporting insulating layer 12 are integrally structured.
  • the functional circuit 10b includes a processor 11b and a memory 13b, both of which are disposed on the surface of the substrate 10a, and the processor 11b is electrically connected to the memory 13b and the coil 11 respectively.
  • the processor 11b is used for controlling the magnitude and direction of the current of the coil 11 and the like.
  • the memory 13b is used to store program codes required for the operation of the processor 11b.
  • the processor 11b includes one or more general-purpose processors 11b, wherein the general-purpose processor can be any type of device capable of processing electronic instructions, including a central processing unit (Central Processing Unit, CPU), a microprocessor, Microcontrollers, main processors, controllers, ASICs, and more.
  • the processor 11b is used to execute various types of digitally stored instructions, such as software or firmware programs stored in memory, which enable the computing device to provide a wide variety of services.
  • the memory 13b can include a volatile memory (Volatile Memory), such as a Random Access Memory (Random Access Memory, RAM); the memory 13b can also include a non-volatile memory (Non-Volatile Memory, NVM), such as Read-only memory (Read-Only Memory, ROM), flash memory (Flash Memory, FM), hard disk (Hard Disk Drive, HDD) or solid-state drive (Solid-State Drive, SSD).
  • NVM non-volatile Memory
  • ROM Read-only memory
  • flash memory Flash Memory
  • HDD Hard Disk Drive
  • SSD solid-state drive
  • the memory 13b may also include a combination of the above-mentioned kinds of memories.
  • the magnetic film sublayer 31 is a magnetic layer. Further, the magnetic film sublayer 31 is a soft magnetic layer. Soft magnetism has high permeability, low remanence, low coercivity, low reluctance, low hysteresis loss, and is easy to be magnetized.
  • the magnetic film sub-layer 31 may be, but not limited to, at least one of magnetic metal, magnetic alloy and the like.
  • the magnetic metal includes at least one of iron, cobalt, nickel and the like.
  • the magnetic alloy may include, but is not limited to, at least one of an iron-based crystalline alloy, an iron-based amorphous alloy, a cobalt-based amorphous alloy, and the like.
  • the iron-based crystalline alloy includes at least one of FeNi alloy, FeCo alloy, FeAl alloy, FeSiAl alloy, FeNiMo alloy, FeC alloy and the like.
  • the iron-based amorphous alloy includes at least one of FeSiB alloy, FeB alloy, FeNiPB alloy, FeNiMoB alloy and the like.
  • the cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, CoFeCrSiB alloy, CoNiFeSiB alloy and the like.
  • the magnetic film sublayer 31 can be At least one of cobalt-based amorphous alloys is used. Compared with cobalt-based amorphous alloys, iron-based crystalline alloys and iron-based amorphous alloys have higher saturation magnetic properties. When the magnetic film layer 30 requires higher saturation magnetic properties, the magnetic film sublayer 31 can use iron At least one of base crystalline alloys and iron-based amorphous alloys.
  • the magnetic film sublayer 31 can be made of iron. base amorphous alloy and cobalt base amorphous alloy.
  • Coercive force means that after the magnetic material is saturated and magnetized, its magnetic induction intensity B does not return to zero when the external magnetic field returns to zero. Only by adding a certain size of magnetic field in the opposite direction of the original magnetization field can the magnetic induction intensity return. To zero, the magnetic field is called coercive magnetic field, also known as coercive force.
  • the thickness h1 of each magnetic film sub-layer 31 ranges from 0.5 ⁇ m ⁇ h1 ⁇ 30 ⁇ m; specifically, each layer The thickness h1 of the magnetic film sublayer 31 may be, but not limited to, 0.5 ⁇ m, 1 ⁇ m, 2 ⁇ m, 4 ⁇ m, 6 ⁇ m, 8 ⁇ m, 10 ⁇ m, 13 ⁇ m, 15 ⁇ m, 18 ⁇ m, 20 ⁇ m, 23 ⁇ m, 25 ⁇ m, 28 ⁇ m, 30 ⁇ m, etc.
  • the ratio of the thickness of the magnetic film sublayer 31 to the supporting insulating layer 12 is relatively small, which affects the effective permeability of the magnetic film layer 30 and the inductance of the circuit board integrated inductor 100.
  • more layers are required, which increases the complexity of the process and the production cost.
  • the thickness h1 of the magnetic film sub-layer 31 is greater than 30 ⁇ m, this increases the eddy current loss in the single-layer magnetic film sub-layer 31 and increases the difficulty of depositing the magnetic film sub-layer 31 .
  • the total thickness h of at least one magnetic film sublayer 31 is in the range of 0.5 ⁇ m ⁇ h ⁇ 200 ⁇ m; specifically, at least one magnetic film
  • the total thickness h of the sublayer 31 may be, but not limited to, 0.5 ⁇ m, 5 ⁇ m, 10 ⁇ m, 20 ⁇ m, 40 ⁇ m, 60 ⁇ m, 80 ⁇ m, 100 ⁇ m, 120 ⁇ m, 180 ⁇ m, 200 ⁇ m, etc.
  • the insulator layer 33 includes at least one of a ceramic insulating layer and an organic insulating layer; the ceramic insulating layer includes at least one of alumina and silicon dioxide; the organic insulating layer includes polypropylene, polytetrafluoroethylene , at least one of polyimide. Compared with the organic insulating layer, the ceramic insulating layer has better insulating performance and mechanical strength, but the organic insulating layer has lower preparation cost.
  • the material of the insulator layer 33 can be selected according to actual application requirements.
  • the thickness h3 of the insulator layer 33 is 50nm ⁇ h3 ⁇ 500nm; specifically, it may be, but not limited to, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, etc.
  • the thickness of the insulator layer 33 is less than 50nm, this makes the impact of defects such as holes in the insulator layer 33 larger, affecting the insulation performance of the insulator layer 33, in other words, reducing the insulation performance of the insulator layer 33; when the thickness of the insulator layer 33 is greater than 500nm, making The ratio of the thicknesses of the magnetic film sub-layer 31 and the insulating sub-layer 33 is small, which affects the effective permeability of the magnetic film layer 30 and the inductance of the circuit board integrated inductor 100 .
  • the circuit board integrated inductor 100 of the embodiment of the present application further includes a dielectric layer 50, and the dielectric layer 50 is located between the coil 11 and the magnetic film layer 30 for making the coil 11 and the magnetic film layer 30 insulation settings. While ensuring the insulation performance, the higher the magnetic permeability of the dielectric layer 50, the better. The higher the magnetic permeability of the dielectric layer 50, the higher the inductance of the circuit board integrated inductor 100 produced.
  • the dielectric layer 50 is at least one of glass fiber/epoxy resin composite board, polyimide, polypropylene, polytetrafluoroethylene and the like.
  • the dielectric layer 50 can be formed on the surface of the coil 11 when the circuit board 10 and the coil 11 are prepared, so as to simplify the manufacturing process of the circuit board integrated inductor 100 .
  • the medium layer 50 is a magnetic glue layer
  • the magnetic glue layer includes resin and magnetic particles
  • the magnetic particles are dispersed in the resin.
  • the magnetic glue layer can be formed by dispersing magnetic particles in a liquid resin to form a magnetic slurry, and then coating or printing it on the surface of the circuit board 10 and curing (for example, UV curing).
  • the magnetic glue layer refers to a film layer in which magnetic materials are discontinuously distributed and the magnetic materials are disconnected.
  • the weight fraction of the magnetic particles ranges from 30% to 90%; specifically, it can be but not limited to 30%, 35%, 40%, 45%, 50%, 55% , 60%, 65%, 70%, 75%, 80%, 85%, 90%, etc.
  • the weight fraction of the magnetic particles in the magnetic glue layer is less than 30%, it is difficult to achieve the effect of improving the magnetic permeability of the circuit board integrated inductor 100, and the cost of the circuit board integrated inductor 100 will be increased; when the weight of the magnetic particles in the magnetic glue layer When the fraction is greater than 90%, the dispersion of magnetic particles in the magnetic slurry is difficult and the fluidity is insufficient.
  • coating or printing it is difficult to fill the gap between the coil 11 on the surface of the circuit board 10, so that the air gap between the magnetic glue layer and the coil 11 is too large. More, the reluctance becomes larger, thereby reducing the magnetic permeability.
  • the range of the average particle diameter D of the magnetic particles is 5 ⁇ m ⁇ D ⁇ 50 ⁇ m; specifically, it may be, but not limited to, 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, 45 ⁇ m, 50 ⁇ m, etc.
  • the magnetic particles are small, the eddy current is limited to a small range. With the increase of the magnetic particles, the area where the current can flow becomes larger, thus increasing the eddy current loss.
  • the average particle size of the magnetic particles is less than 5 ⁇ m, not only the cost of the magnetic particles will be increased, but also the magnetic permeability of the magnetic glue layer will be reduced, and the meaning of increasing the magnetic permeability through the magnetic glue layer will be lost.
  • the average particle size of the magnetic particles is greater than 50 ⁇ m, the eddy current loss is too large, which is also not conducive to the performance of the circuit board integrated inductor 100 .
  • the magnetic particles are soft magnetic particles.
  • Soft magnetism has high permeability, low remanence, low coercivity, low reluctance, low hysteresis loss, and is easy to be magnetized.
  • the magnetic particles include at least one of ferrite particles, magnetic metal particles, and magnetic alloy particles. Ferrite particles have better electrical insulation and lower loss, and magnetic metal particles or magnetic alloy particles have higher magnetic permeability and magnetic saturation induction. Therefore, when the magnetic glue layer is required to have better electrical insulation and lower loss, ferrite particles can be selected as magnetic particles. When the magnetic glue layer is required to have higher magnetic permeability and magnetic saturation induction, Magnetic metal particles or magnetic alloy particles can be selected as the magnetic particles.
  • the ferrite particles include at least one of MnZn ferrite, NiZn ferrite and the like.
  • the magnetic metal particles include at least one of iron, cobalt, nickel and the like.
  • the magnetic alloy particles include at least one of an iron-based crystalline alloy, an iron-based amorphous alloy, a cobalt-based amorphous alloy, and the like.
  • the iron-based crystalline alloy includes at least one of FeNi alloy, FeCo alloy, FeAl alloy, FeSiAl alloy, FeNiMo alloy, FeC alloy and the like.
  • the iron-based amorphous alloy includes at least one of FeSiB alloy, FeB alloy, FeNiPB alloy, FeNiMoB alloy and the like.
  • the cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, CoFeCrSiB alloy, CoNiFeSiB alloy and the like.
  • cobalt-based amorphous alloys have higher magnetic permeability. Therefore, when the magnetic layer requires higher magnetic permeability, the magnetic particles can use cobalt-based amorphous alloys. At least one of crystal alloys. Compared with cobalt-based amorphous alloys, iron-based crystalline alloys and iron-based amorphous alloys have higher saturation magnetic properties. When the magnetic layer requires higher saturation magnetic properties, magnetic particles can be selected from iron-based crystalline alloys. And at least one of iron-based amorphous alloys and the like.
  • iron-based amorphous alloys and cobalt-based amorphous alloys have lower coercive forces.
  • magnetic particles can be selected from iron-based amorphous alloys. and cobalt-based amorphous alloys.
  • the surface of the magnetic alloy particles has a passivation layer, and the passivation layer is an insulating layer, in other words, the passivation layer is insulating.
  • a layer of organic resin can be coated on the surface of the magnetic alloy particles to make the magnetic alloy particles insulative.
  • the magnetic alloy particles may be passivated with phosphoric acid to form a non-conductive passivation layer on the surface of the magnetic alloy particles.
  • the resin includes at least one of epoxy resin, polyurethane and acrylate.
  • the resin of the magnetic adhesive layer can be epoxy resin, which can make the magnetic adhesive layer and the circuit board 10 have a closer Good bonding performance can be better attached to the circuit board 10 .
  • the thickness h2 of the dielectric layer 50 ranges from 5 ⁇ m ⁇ h2 ⁇ 200 ⁇ m; specifically, it can be but not limited to 5 ⁇ m, 10 ⁇ m, 30 ⁇ m , 50 ⁇ m, 80 ⁇ m, 100 ⁇ m, 120 ⁇ m, 140 ⁇ m, 160 ⁇ m, 180 ⁇ m, 200 ⁇ m, etc.
  • the dielectric layer 50 is at least one of glass fiber/epoxy resin composite board, polyimide, polypropylene, polytetrafluoroethylene, etc.
  • the ready-made film layer is usually laminated to the surface of the circuit board 10 during preparation.
  • the dielectric layer 50 is a magnetic glue layer and h2 is less than 5 ⁇ m, it may be difficult for the dielectric layer 50 to completely cover the coil 11 exposed on the surface of the circuit board 10, resulting in steps on the surface of the dielectric layer 50, which is not conducive to the deposition of the magnetic film sub-layer 31.
  • the thickness of the dielectric layer 50 is greater than 200 ⁇ m, the magnetoresistance of the dielectric layer 50 is too large, which reduces the inductance of the manufactured circuit board integrated inductor 100 .
  • the circuit board integrated inductor 100 of the embodiment of the present application can be prepared by the method of the following embodiments of the present application. In addition, it can also be prepared by other methods.
  • the preparation method of the embodiment of the present application is only a part of the circuit board integrated inductor 100 of the present application. Such a preparation method should not be construed as a limitation to the circuit board integrated inductor 100 provided in the embodiment of the present application.
  • the embodiment of the present application also provides a method for preparing a circuit board integrated inductor 100, which includes:
  • circuit board 10 and the coil 11 please refer to the description of the corresponding part of the above embodiment, which will not be repeated here.
  • a magnetic film sublayer 31 is first deposited on at least one of the two opposite sides of the circuit board 10 by physical vapor deposition or electrodeposition, and then a magnetic film sublayer 31 is deposited on the magnetic film by physical vapor deposition or the like.
  • a layer of insulating sublayer 33 is deposited on the surface of layer 31 away from the circuit board 10 , and then repeated alternately in sequence until the predesigned number of magnetic film sublayers 31 is obtained.
  • the magnetic film sublayer 31 made by physical vapor deposition method has a good appearance, but it is easy to fall off; the magnetic film sublayer 31 made by electrodeposition method has good peeling resistance and is difficult to fall off, but the surface appearance poor. Therefore, when the thickness of the magnetic sublayer 31 is less than 1 ⁇ m, it can be prepared by physical vapor deposition; when the thickness of the magnetic sublayer 31 is greater than or equal to 1 ⁇ m, it can be prepared by electrodeposition.
  • the magnetic film layer 30 the magnetic film sub-layer 31 and the insulating sub-layer 33 , please refer to the descriptions of the corresponding parts of the above embodiments, and details are not repeated here.
  • the circuit board integrated inductor 100 prepared by the method for preparing the circuit board integrated inductor 100 of this embodiment integrates the inductor on the circuit board 10, and when applied to electronic equipment, it can make the electronic equipment more miniaturized and ultra-thin, and the inductance It is prepared together with the circuit board 10 without independent mounting, which improves packaging efficiency.
  • the inductor is integrated in the circuit board 10, and the position corresponding to the inductor on the circuit board 10 can be saved for mounting other components, saving the area on the circuit board 10, and enhancing the wiring and layout capabilities of the circuit board 10 .
  • the thickness of the magnetic layer is too thick, a large eddy current effect will be generated in the thickness direction of the magnetic layer.
  • the magnetic film layer 30 of the circuit board integrated inductor 100 of the present application includes at least two magnetic film sub-layers 31 and At least one insulating sublayer 33, the magnetic film sublayer 31 and the insulating sublayer 33 are stacked alternately in sequence, compared with the scheme in which the magnetic film layer 30 is a single magnetic layer, the magnetic layer in the magnetic film layer 30 is divided into at least two layers Magnetic film sub-layer 31, is provided with insulating sub-layer 33 between two adjacent magnetic film sub-layers 31, and insulating sub-layer 33 can stop the conduction of the eddy current in the magnetic film in the thickness direction, thereby reduces the whole magnetic film layer 30 in the thickness direction. On the eddy current loss, thereby reducing the eddy current loss of the entire inductor.
  • the embodiment of the present application provides a method for preparing a circuit board 10, which includes:
  • S2011 providing a first substrate 10', the first substrate 10' comprising a supporting insulating layer 12 and a conductor layer 11' disposed on at least one of the two surfaces opposite to the supporting insulating layer 12;
  • the first substrate 10' includes a supporting insulating layer 12 and a conducting layer 11', and the supporting insulating layer 12 and the conducting layer 11' are laminated.
  • the first substrate 10' includes a conductive layer 11', a supporting insulating layer 12, and a conductive layer 11' that are stacked in sequence.
  • the conductor layer 11' may be, but not limited to, conductive materials including metals such as copper and silver or alloys.
  • each conductive layer 11' of the first substrate 10' etching each conductive layer 11' of the first substrate 10', so that the conductive layer 11' forms a conductive layer 14, and the conductive layer 14 includes a wire 14a; wherein, when the conductive layer 14 is one layer, a single layer The wires 14 a of the conductive layer 14 form the coil 11 ; when the conductive layer 14 has two layers, the wires 14 a of the two conductive layers 14 are electrically connected to form the coil 11 .
  • a yellow photolithography process is used to coat photoresist on the surface of the conductor layer 11', and the photoresist is successively subjected to processes such as soft baking, exposure, development, and hard baking to form a photoresist mask, and then
  • the conductive layer 11' is etched to obtain the conductive layer 14, the conductive layer 14 includes a wire 14a, when the conductive layer 14 is one layer, the wire 14a of the single-layer conductive layer 14 forms the coil 11; when the conductive layer 14 is two layers At this time, the wires 14a of the two conductive layers 14 are electrically connected to form the coil 11 .
  • the conductive layer 14 and the coil 11 please refer to the descriptions of the corresponding parts of the above embodiments, which will not be repeated here.
  • the preparation method of the circuit board 10 includes :
  • the first substrate 10' includes a supporting insulating layer 12 and two layers of conductor layers 11' disposed on the two opposite surfaces of the supporting insulating layer 12;
  • step S2011a For a detailed description of step S2011a, please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.
  • the first via hole 101 can be a through hole or a blind hole; when the first via hole 101 is a through hole, the supporting insulating layer 12 and the two conductor layers 11' are pierced; When the hole 101 is a blind hole, at least one of the supporting insulating layer 12 and the two layers of conductors is pierced.
  • the first via hole 101 may be drilled with a laser.
  • step S2013a For a detailed description of step S2013a, please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.
  • PVD physical vapor deposition
  • electrodeposition can be used to deposit conductive material in the first via hole 101 to electrically connect the wires 14 a in the two conductive layers 14 to form the coil 11 .
  • the conductive material may be, but not limited to, metals or alloys such as copper and silver.
  • the preparation method of the circuit board 10 includes:
  • the first substrate 10' includes a supporting insulating layer 12 and two layers of conductor layers 11' disposed on the two surfaces opposite to the supporting insulating layer 12;
  • steps S2011b to S2014b please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.
  • the second substrate 10 includes a supporting insulating layer 12 and a conductor layer 11' disposed on the surface of the supporting insulating layer 12;
  • the second via hole is a through hole; in other words, both the supporting insulating layer 12 and the two conductor layers 11' are pierced.
  • the second via hole may be drilled by laser.
  • each layer of conductive layer 14 includes a wire 14a; the wires 14a of any adjacent two layers of conductive layer 14 are electrically connected to form Coil 11.
  • the embodiment of the present application also provides a method for preparing a circuit board integrated inductor 100, which includes:
  • step S301 please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.
  • the dielectric layer 50 is at least one of glass fiber/epoxy resin composite board, polyimide, polypropylene, and polytetrafluoroethylene
  • the dielectric layer 50 is laminated on the opposite side of the circuit board 10. At least one of the two surfaces is pressed, so that the dielectric layer 50 is attached to the circuit board 10 and at least covers the coil 11 .
  • the dielectric layer 50 is a magnetic glue layer
  • the magnetic particles are first dispersed in the liquid resin to form a magnetic slurry, and then the magnetic slurry is formed on the surface of the circuit board 10 by coating, printing, etc.
  • the magnetic paste layer may also be cured by thermal curing, which is not specifically limited in the present application.
  • the magnetic film layer 30 on the surface of the dielectric layer 50 away from the circuit board 10, alternately deposit the magnetic film sub-layer 31 and the insulating sub-layer 33, so as to form the magnetic film layer 30 on at least one of the opposite sides of the circuit board 10, wherein the magnetic The film layer 30 at least partially overlaps the coil 11 , and the magnetic film layer 30 includes at least two magnetic film sub-layers 31 and at least one insulating sub-layer 33 .
  • step S303 please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.
  • circuit board integrated inductor 100 of the embodiment of the present application will be further described below through specific examples.
  • the circuit board integrated inductor 100 of this example includes a circuit board 10 , and the circuit board 10 includes a supporting insulating layer 12 and a coil 11 .
  • the coil 11 is embedded in the supporting insulating layer 12 .
  • the coil 11 is a copper coil 11, and the number of turns of the coil 11 is 1 turn.
  • the thickness of the supporting insulating layer 12 is 50 ⁇ m, the line width of the copper coil 11 is 200 ⁇ m, the line thickness of the copper coil 11 is 100 ⁇ m, and the line distance of the copper coil 11 is 150 ⁇ m.
  • the circuit board integrated inductor 100 further includes a dielectric layer 50 disposed on two opposite surfaces of the circuit board 10 and covering at least the coil 11 .
  • the thickness of the dielectric layer 50 is 100 ⁇ m, and the dielectric layer 50 is a glass fiber/epoxy resin composite board.
  • the circuit board integrated inductor 100 also includes a magnetic film layer 30, the magnetic film layer 30 is arranged on the surface of the dielectric layer 50 away from the circuit board 10 (in other words, a magnetic film layer 30 is provided on the opposite sides of the circuit board 10), the magnetic film layer 30, a FeNi alloy layer (magnetic film sublayer 31), an Al 2 O 3 layer (insulator sublayer 33), and a FeNi alloy layer are stacked in this order.
  • each magnetic film sublayer 31 (FeNi alloy layer) is 5 ⁇ m, the relative magnetic permeability of the magnetic film sublayer 31 is 800, and the electrical conductivity is 40KS/m.
  • the thickness of the insulating sublayer 33 is 0.2 ⁇ m.
  • the circuit board integrated inductor 100 of this comparative example includes a circuit board 10 , and the circuit board 10 includes a supporting insulating layer 12 and a coil 11 .
  • the coil 11 is embedded in the supporting insulating layer 12 .
  • the coil 11 is a copper coil 11, and the number of turns of the coil 11 is 1 turn.
  • the thickness of the supporting insulating layer 12 is 50 ⁇ m, the line width of the copper coil 11 is 200 ⁇ m, the line thickness of the copper coil 11 is 100 ⁇ m, and the line distance of the copper coil 11 is 150 ⁇ m.
  • the circuit board integrated inductor 100 further includes a dielectric layer 50 disposed on two opposite surfaces of the circuit board 10 and covering at least the coil 11 .
  • the thickness of the dielectric layer 50 is 100 ⁇ m, and the dielectric layer 50 is a glass fiber/epoxy resin composite board.
  • the circuit board integrated inductor 100 also includes a magnetic film layer 30, the magnetic film layer 30 is arranged on the surface of the dielectric layer 50 away from the circuit board 10 (in other words, a magnetic film layer 30 is provided on the opposite sides of the circuit board 10), the magnetic film layer 30 includes a FeNi alloy layer, the thickness of the FeNi alloy layer is 10 ⁇ m, the relative magnetic permeability of the FeNi alloy layer is 800, and the electrical conductivity is 40KS/m.
  • Example 1 Comparative example 1 Sensitivity (nH) 4.31 4.32 Eddy current loss ( ⁇ W) 9 16
  • the circuit board integrated inductor 100 of this example includes a circuit board 10 , and the circuit board 10 includes a supporting insulating layer 12 and a coil 11 .
  • the coil 11 is embedded in the supporting insulating layer 12 .
  • the coil 11 is a copper coil 11, and the number of turns of the coil 11 is 1 turn.
  • the thickness of the supporting insulating layer 12 is 50 ⁇ m, the line width of the copper coil 11 is 200 ⁇ m, the line thickness of the copper coil 11 is 100 ⁇ m, and the line distance of the copper coil 11 is 150 ⁇ m.
  • the circuit board integrated inductor 100 further includes a dielectric layer 50 disposed on two opposite surfaces of the circuit board 10 and covering at least the coil 11 .
  • the thickness of the dielectric layer 50 is 100 ⁇ m, and the dielectric layer 50 is a glass fiber/epoxy resin composite board.
  • the circuit board integrated inductor 100 also includes a magnetic film layer 30, the magnetic film layer 30 is arranged on the surface of the dielectric layer 50 away from the circuit board 10 (in other words, a magnetic film layer 30 is provided on the opposite sides of the circuit board 10), the magnetic film layer 30, a FeNi alloy layer (magnetic film sublayer 31), an Al 2 O 3 layer (insulator sublayer 33), and a FeNi alloy layer are stacked in this order.
  • each magnetic film sublayer 31 (FeNi alloy layer) is 15 ⁇ m, the relative magnetic permeability of the magnetic film sublayer 31 is 800, and the electrical conductivity is 40KS/m.
  • the thickness of the insulating sublayer 33 is 0.2 ⁇ m.
  • the circuit board integrated inductor 100 of this example includes a circuit board 10 , and the circuit board 10 includes a supporting insulating layer 12 and a coil 11 .
  • the coil 11 is embedded in the supporting insulating layer 12 .
  • the coil 11 is a copper coil 11, and the number of turns of the coil 11 is 1 turn.
  • the thickness of the supporting insulating layer 12 is 50 ⁇ m, the line width of the copper coil 11 is 200 ⁇ m, the line thickness of the copper coil 11 is 100 ⁇ m, and the line distance of the copper coil 11 is 150 ⁇ m.
  • the circuit board integrated inductor 100 further includes a dielectric layer 50 disposed on two opposite surfaces of the circuit board 10 and covering at least the coil 11 .
  • the thickness of the dielectric layer 50 is 100 ⁇ m, and the dielectric layer 50 is a glass fiber/epoxy resin composite board.
  • the circuit board integrated inductor 100 also includes a magnetic film layer 30, the magnetic film layer 30 is arranged on the surface of the dielectric layer 50 away from the circuit board 10 (in other words, a magnetic film layer 30 is provided on the opposite sides of the circuit board 10), the magnetic film layer 30 is sequentially provided with a FeNi alloy layer (magnetic film sublayer 31 ), an Al 2 O 3 layer (insulator layer 33 ), a FeNi alloy layer, an Al 2 O 3 layer (insulator layer 33 ), and a FeNi alloy layer.
  • each magnetic sublayer 31 (FeNi alloy layer) is 10 ⁇ m, the relative magnetic permeability of the magnetic sublayer 31 is 800, and the electrical conductivity is 40KS/m.
  • the thickness of the insulating sublayer 33 is 0.2 ⁇ m.
  • the circuit board integrated inductor 100 of this comparative example includes a circuit board 10 , and the circuit board 10 includes a supporting insulating layer 12 and a coil 11 .
  • the coil 11 is embedded in the supporting insulating layer 12 .
  • the coil 11 is a copper coil 11, and the number of turns of the coil 11 is 1 turn.
  • the thickness of the supporting insulating layer 12 is 50 ⁇ m, the line width of the copper coil 11 is 200 ⁇ m, the line thickness of the copper coil 11 is 100 ⁇ m, and the line distance of the copper coil 11 is 150 ⁇ m.
  • the circuit board integrated inductor 100 further includes a dielectric layer 50 disposed on two opposite surfaces of the circuit board 10 and covering at least the coil 11 .
  • the thickness of the dielectric layer 50 is 100 ⁇ m, and the dielectric layer 50 is a glass fiber/epoxy resin composite board.
  • the circuit board integrated inductor 100 also includes a magnetic film layer 30, the magnetic film layer 30 is arranged on the surface of the dielectric layer 50 away from the circuit board 10 (in other words, a magnetic film layer 30 is provided on the opposite sides of the circuit board 10), the magnetic film layer 30 includes a FeNi alloy layer, the thickness of the FeNi alloy layer is 30 ⁇ m, the relative magnetic permeability of the FeNi alloy layer is 800, and the electrical conductivity is 40KS/m.
  • Example 2 According to the standard GB/T 8554-1998, the inductance and eddy current loss of the circuit board integrated inductor 100 obtained in Example 2, Example 3 and Comparative Example 2 are shown in Table 2 below.
  • Example 2 Example 3 Comparative example 2 Sensitivity (nH) 4.68 4.67 4.69 Eddy current loss ( ⁇ W) 36 30 64
  • the embodiment of the present application also provides an electronic device 400 , which includes: a display component 410 , the circuit board integrated inductor 100 and the casing 430 of the embodiment of the present application.
  • the display assembly 410 is used for display; the casing 430 is arranged on one side of the display assembly 410; the circuit board integrated inductor 100 is arranged between the display assembly 410 and the casing 430, and is electrically connected with the display assembly 410, and the circuit board integrated inductor 100
  • the processor 11b is also used to control the display component 410 to display.
  • the electronic device 400 in the embodiment of the present application may be, but not limited to, portable electronic devices 400 such as mobile phones, tablet computers, notebook computers, desktop computers, smart bracelets, smart watches, e-readers, and game consoles.
  • portable electronic devices 400 such as mobile phones, tablet computers, notebook computers, desktop computers, smart bracelets, smart watches, e-readers, and game consoles.
  • a mobile phone is taken as an example in FIG. 20 , which should not be construed as a limitation to the embodiment of the present application.
  • circuit board integrated inductor 100 For a detailed description of the circuit board integrated inductor 100 , please refer to the description of the corresponding part of the above embodiment, and details will not be repeated here.
  • the casing 430 in this embodiment may be in a 2D structure, a 2.5D structure, a 3D structure, or the like.
  • the housing 430 in this embodiment can be the back cover (battery cover) of the electronic device 400, or a case in which the middle frame and the back cover are integrated.
  • the display component 410 may be, but not limited to, a liquid crystal display component, a light-emitting diode display component (LED display component), a micro light-emitting diode display component (Micro LED display component), a submillimeter light-emitting diode display component (Mini LED display component) ), organic light emitting diode display components (OLED display components) and the like.
  • LED display component light-emitting diode display component
  • Micro LED display component micro light-emitting diode display component
  • Mini LED display component submillimeter light-emitting diode display component
  • OLED display components organic light emitting diode display components
  • the housing 430 is the back cover of the electronic device 400.
  • the electronic device 400 in the embodiment of the present application also includes a middle frame 420 and a camera module 450.
  • the middle frame 420 is set on Between the display assembly 410 and the housing 430 , and the side of the middle frame 420 is exposed from the housing 430 and the display assembly 410 .
  • the middle frame 420 and the casing 430 form an accommodating space, and the accommodating space is used for accommodating the circuit board integrated inductor 100 and the camera module 450 .
  • the camera module 450 is electrically connected to the processor 11b of the circuit board integrated inductor 100 for taking pictures under the control of the processor 11b.
  • the housing 430 has a light-transmitting portion 431 through which the camera module 450 can take pictures. That is, the camera module 450 in this embodiment is a rear camera module 450 . Understandably, in other implementation manners, the light-transmitting portion 431 may be disposed on the display assembly 410 , that is, the camera module 450 is the front camera module 450 . In the schematic diagram of this embodiment, the light-transmitting portion 431 is used as an opening for illustration. In other embodiments, the light-transmitting portion 431 may not be an opening, but a light-transmitting material, such as plastic or glass.
  • the electronic equipment in this embodiment is only a form of electronic equipment applied to circuit board integrated inductors, and should not be interpreted as a limitation on the electronic equipment provided by this application, nor should it be understood as a limitation of each implementation mode of this application. Provides board-integrated inductance limits.
  • references in this application to "an embodiment” or “implementation” mean that a specific feature, structure or characteristic described in connection with an embodiment may be included in at least one embodiment of this application.
  • the appearances of phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described in this application can be combined with other embodiments.
  • the features, structures or characteristics described in the various embodiments of the present application can be combined arbitrarily without departing from the spirit and scope of the technical solution of the present application if there is no contradiction between them. an embodiment.

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Abstract

本申请提供一种电路板集成电感、其制备方法及电子设备。所述电路板集成电感包括：电路板，所述电路板嵌设有线圈；以及磁膜层，所述磁膜层设置于所述电路板相背的两侧中的至少一侧上，且与所述线圈至少部分交叠，所述磁膜层包括至少两层磁膜子层及至少一层绝缘子层，所述磁膜子层与所述绝缘子层依次交替层叠设置。本申请的电路板集成电感将电感集成于电路板中，更加超薄化，小型化，提高了封装效率，且可以更好的降低电感的涡流损耗。

Description

电路板集成电感、其制备方法及电子设备 技术领域
本申请涉及电子领域，具体涉及一种电路板集成电感、其制备方法及电子设备。
背景技术
随着电子硬件的小型化和高密度发展趋势，电路板的表面积急剧减少，但板面上要求贴装的电子元件却有增无减。电感是电子设备不可缺少的元器件，当前的电感大多先制备成电感器后，再贴装至电路板上，这不仅占用了电路板的面积，还需要分立贴装，降低封装效率。
发明内容
本申请第一方面实施例提供了一种电路板集成电感，其包括：
电路板，所述电路板嵌设有线圈；以及
磁膜层，所述磁膜层设置于所述电路板相背的两侧中的至少一侧上，且与所述线圈至少部分交叠，所述磁膜层包括至少两层磁膜子层及至少一层绝缘子层，所述磁膜子层与所述绝缘子层依次交替层叠设置。
本申请第二方面实施例提供了一种电路板集成电感的制备方法，其包括：
提供电路板，所述电路板嵌设有线圈；以及
在所述电路板相背的两侧中的至少一侧依次交替沉积磁膜子层及绝缘子层，以在所述电路板相背的两侧中的至少一侧上形成磁膜层，其中，所述磁膜层与所述线圈至少部分交叠，所述磁膜层包括至少两层所述磁膜子层及至少一层所述绝缘子层。
本申请第三方面实施例提供一种电子设备，所述电子设备包括本申请实施例所述的电路板集成电感。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例的电路板集成电感的透视结构示意图。
图2是本申请一实施例的电路板集成电感沿图1中A-A方向的剖视结构示意图。
图3是本申请一实施例的电路板的结构示意图。
图4是本申请又一实施例的电路板沿图1中A-A方向的剖视结构示意图。
图5是本申请又一实施例的电路板的结构示意图。
图6是本申请又一实施例的电路板沿图1中A-A方向的剖视结构示意图。
图7是本申请又一实施例的电路板的结构示意图。
图8是本申请又一实施例的线圈的结构示意图。
图9是本申请又一实施例的电路板的结构示意图。
图10是本申请一实施例的电路板集成电感的电路结构框图。
图11是本申请一实施例的磁膜层的结构示意图。
图12是本申请又一实施例的电路板集成电感沿图1中A-A方向的剖视结构示意图。
图13是本申请一实施例的电路板集成电感的制备方法流程示意图。
图14是本申请一实施例的电路板的制备方法流程示意图。
图15是本申请一实施例的第一基板的结构示意图。
图16是本申请又一实施例的电路板的制备方法流程示意图。
图17是本申请又一实施例的电路板的制备方法流程示意图。
图18是本申请一实施例的第二基板的结构示意图。
图19是本申请一实施例的电路板集成电感的制备方法流程示意图。
图20是本申请实施例的电子设备的结构示意图。
图21是本申请实施例的电子设备的部分***结构示意图。
图22是本申请实施例的电子设备的电路框图。
附图标记说明：
100-电路板集成电感，10-电路板，11-线圈，12-支撑绝缘层，14-导电层，14a-导线，10a-基板，10b-功能电路，11b-处理器，13b-存储器，30-磁膜层，31-磁膜子层，33-绝缘子层，50-介质层，10’-第一基板，11’-导体层，10”-第二基板，101-第一过孔，400-电子设备，410-显示组件，420-中框，430-壳体，431-透光部，450-摄像头模组。
具体实施方式
第一方面，本申请提供一种电路板集成电感，其包括：
电路板，所述电路板嵌设有线圈；以及
磁膜层，所述磁膜层设置于所述电路板相背的两侧中的至少一侧上，且与所述线圈至少部分交叠，所述磁膜层包括至少两层磁膜子层及至少一层绝缘子层，所述磁膜子层与所述绝缘子层依次交替层叠设置。
其中，所述电路板包括至少一层支撑绝缘层及至少一层导电层；所述支撑绝缘层与所述导电层依次交替层叠设置，所述导电层包括导线；当所述导电层为一层时，单层所述导电层的所述导线形成所述线圈；当所述导电层为多层时，任意相邻的两层导电层的导线电连接，形成所述线圈。
其中，所述磁膜子层包括磁性金属、磁性合金中的至少一种；所述磁性金属包括铁、钴、镍中的至少一种；所述磁性合金包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金中的至少一种；所述铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金中的至少一种。
其中，沿所述电路板及所述磁膜层的层叠方向，每层所述磁膜子层的厚度h1的范围为0.5μm≤h1≤30μm，所述至少一层磁膜子层的总厚度h的范围为0.5μm≤h≤200μm。
其中，所述电路板集成电感还包括介质层，所述介质层位于所述线圈与所述磁膜层之间。
其中，所述介质层为磁胶层，所述磁胶层包括树脂及磁性颗粒，所述磁性颗粒分散于所述树脂中。
其中，在所述磁胶层中，所述磁性颗粒的重量分数的范围为30％至90％。
其中，所述磁性颗粒的平均粒径D的范围为5μm≤D≤50μm。
其中，所述树脂包括环氧树脂、聚氨酯及丙烯酸酯中的至少一种。
其中，所述磁性颗粒包括铁氧体颗粒、磁性金属颗粒、磁性合金颗粒中的至少一种；所述铁氧体包括MnZn铁氧体、NiZn铁氧体中的至少一种；所述磁性金属颗粒包括铁、钴、镍中的至少一种；所述磁性合金颗粒包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金中的至少一种；所述铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金中的至少一种。
其中，所述介质层为玻纤/环氧树脂复合板、聚酰亚胺、聚丙烯、聚四氟乙烯中的至少一种。
其中，沿所述电路板、所述介质层及所述磁膜层的层叠方向，所述介质层的厚度h2的范围为5μm≤h2≤200μm。
其中，所述绝缘子层包括陶瓷绝缘层、有机绝缘层中的至少一种；所述陶瓷绝缘层包括氧化铝、二氧化硅中的至少一种；所述有机绝缘层包括聚丙烯、聚四氟乙烯、聚酰亚胺中的至少一种。
其中，所述绝缘子层的厚度h3的范围为50nm≤h3≤500nm。
其中，所述电路板还包括基板及功能电路，所述功能电路承载于所述基板，且与所述线圈电连接。
第二方面，本申请提供一种电路板集成电感的制备方法，其包括：
提供电路板，所述电路板嵌设有线圈；以及
在所述电路板相背的两侧中的至少一侧依次交替沉积磁膜子层及绝缘子层，以在所述电路板相背的两侧中的至少一侧上形成磁膜层，其中，所述磁膜层与所述线圈至少部分交叠，所述磁膜层包括至少两层所述磁膜子层及至少一层所述绝缘子层。
其中，所述提供电路板包括：
提供第一基板，所述第一基板包括支撑绝缘层及设置于所述支撑绝缘层相背的两个表面中的至少一个表面的导体层；以及
对所述第一基板的每层所述导体层进行刻蚀，以使所述导体层形成导电层，所述导电层包括导线；其中，当所述导电层为一层时，单层所述导电层的所述导线形成所述线圈；当所述导电层为两层时，两层所述导电层的导线电连接，形成所述线圈。
其中，所述提供电路板还包括：
提供第二基板，所述第二基板包括支撑绝缘层及设置于所述支撑绝缘层的表面的导体层；
对所述第二基板的所述导体层进行刻蚀，以得到导电层，所述导电层包括导线；以及
将所述第一基板与所述第二基板压合，以得到电路板，其中，所述电路板包括至少一层支撑绝缘层及至少一层导电层；所述支撑绝缘层与所述导电层依次交替层叠设置；其中，每层所述导电层包括导线；任意相邻的两层导电层的导线电连接，形成所述线圈。
其中，所述在所述电路板相背的两侧中的至少一侧依次交替沉积磁膜子层及绝缘子层之前，所述方法还包括：
在所述电路板相背的两个表面中的至少一个表面上形成介质层，并使所述介质层至少覆盖所述线圈。
第三方面，本申请提供一种电子设备，所述电子设备包括第一方面或第一方面任一项所述的电路板集成电感。
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何的变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、***、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。
下面将结合附图，对本申请实施例中的技术方案进行描述。需要说明的是，为便于说明，在本申请的实施例中，相同的附图标记表示相同的部件，并且为了简洁，在不同实施例中，省略对相同部件的详细说明。
电感由线圈与磁性件组成，当线圈中通过交流电流时，在线圈的内部及其周围产生交变磁通，拥有储存和释放能量的功能。在电子线路中，电感对交流有限流作用，它与电阻器或电容器能组成高通滤波器或低通滤波器、移相电路及谐振电路，因此广泛应用于各类仪器及设备中。
电感器件在电路板上占用了较大的面积，例如在电源模块中，电感器件所占用电源板表面40％以上的面积，这不仅不利于产品的小型化和高密度化；且大部分电感器件都需要分立贴装，降低封装效率。电感通常在线圈的相背两侧采用单层磁膜直接沉积在表面上，厚度一般为几十微米至一两百微米，厚度较大，当采用磁性合金等导电材料作为磁膜时，在磁膜的厚度方向上容易产生涡流效应，增大涡流损耗，降低了电感的效率，且容易使电感发热加剧。
请参见图1及图2，本申请实施例提供一种电路板集成电感100，其应用于电子设备例如手机、平板电脑等中，本申请的电子设备以手机为例进行示意，不应该理解为对本申请保护范围的限制。本实施 例的电路板集成电感100包括电路板10以及磁膜层30，电路板10嵌设有线圈11；磁膜层30设置于电路板10相背的两侧中的至少一侧上，且与线圈11至少部分交叠，磁膜层30包括至少两层磁膜子层31及至少一层绝缘子层33，磁膜子层31与绝缘子层33依次交替层叠设置。至少一个指一个以上，换言之，大于等于一个。至少一层指一层以上，换言之，大于等于一层。至少两层指两层以上，换言之，大于等于两层。
电路板10可以为柔性电路板(FPC)，也可以为印制电路板(PCB)，对此本申请不作具体限定。
电路板10上的线圈11的数量可以为一个，也可以为多个，例如，可以为但不限于为1个、2个、3个等，线圈11的具体数量可以根据实际应用需求进行设定，本申请不作具体限定。多个指两个以上或大于等于两个。可以理解，每个线圈11可以为但不限于为一匝线圈11中的一部分(例如半匝线圈11、0.3匝线圈11等)、一匝线圈11、两匝线圈11、三匝线圈11、四匝线圈11、五匝线圈11等。线圈11的匝数越多，在其他条件不变的情况下，电感量越大，因此，线圈11的匝数可以根据应用的场景、所需要达到的电感量等进行设计，本申请不作具体限定。
电路板10嵌设有线圈11，换言之，线圈11嵌设于电路板10内。线圈11嵌设于电路板10内，可以为线圈11至少部分被电路板10包裹；还可以为线圈11与电路板10集成为一体结构，线圈11直接由电路板10中的导线组成，电路板10在制备的过程中，一并形成线圈11；还可以为线圈11穿设于电路板10，换言之，线圈11部分穿过电路板10，部分露出电路板10。
磁膜层30指包括连续的磁性材料、中间没有断开的膜层。磁膜子层31指整层为连续的磁性材料、中间没有断开的膜层。磁膜层30设置于电路板10相背的两侧中的至少一侧上，可以为磁膜层30设置于电路板10的一侧，例如设置于电路板10的表面上，或者电路板10的表面设有介质层50等膜层，磁膜层30设置在介质层50等膜层的表面上；还可以为，磁膜层30设置于电路板10的相背两侧，换言之，电路板10相背的两侧均设有磁膜层30，如电路板10相背的两个表面均设有磁膜层30，或者电路板10相背的两个表面均设有介质层50，磁膜层30设置于该介质层50的表面。
至少部分交叠指磁膜层30与线圈11在电路板10表面的正投影至少部分交叠。磁膜层30与线圈11至少部分交叠，可以为磁膜层30与线圈11部分交叠；还可以为磁膜层30覆盖整个线圈11的表面；还可以为磁膜层30覆盖部分线圈11，位于线圈11之内等。
磁膜层30包括至少两层磁膜子层31及至少一层绝缘子层33，磁膜子层31与绝缘子层33依次交替层叠设置，可以为但不限于为磁膜层30包括两层磁膜子层31及一层绝缘子层33，两层磁性子层间隔相背设置，绝缘子层33设置于两层磁性子层之间；或者，磁膜层30包括三层磁膜子层31及两层绝缘子层33，磁膜子层31与绝缘子层33依次交替层叠设置；或者，磁膜层30包括四层磁膜子层31及三层绝缘子层33，磁膜子层31与绝缘子层33依次交替层叠设置。或者，磁膜层30包括五层磁膜子层31及四层绝缘子层33，磁膜子层31与绝缘子层33依次交替层叠设置等。
本实施例的电路板集成电感100，将电感集成于电路板10上，应用于电子设备时，可以使得电子设备更加小型化、超薄化，且电感与电路板10一起制备，不需要独立贴装，提高了封装效率。此外，电感集成于电路板10内，电路板10上对应电感的位置可以节省出来，用于贴装其它元器件，节省了电路板10上的面积，增强了电路板10的布线、布件能力。再者，当磁性层的厚度太厚时，在磁性层的厚度方向上会产生较大的涡流效应，本申请的电路板集成电感100的磁膜层30包括至少两层磁膜子层31及至少一层绝缘子层33，磁膜子层31与绝缘子层33依次交替层叠设置，相较于磁膜层30为一层磁性层的方案，将磁膜层30中的磁性层分为至少两层磁膜子层31，相邻的两个磁膜子层31之间设有绝缘子层33，绝缘子层33可以阻止磁膜中涡流在厚度方向上的传导，从而降低整个磁膜层30在厚度方向上的涡流损耗，进而降低整个电感的涡流损耗。
请参见图3及图4，在一些实施例中，电路板10包括至少一层支撑绝缘层12及至少一层导电层14；支撑绝缘层12与导电层14依次交替层叠设置，导电层14包括导线14a；当导电层14为一层时，单层导电层14的导线14a形成线圈11；当导电层14为多层时，任意相邻的两层导电层14的导线14a电连接，形成线圈11。通过采用电路板10原有的导电层14形成线圈11，从而将电感的线圈11集成于电路板10，使得制备工艺更加简单化，得到的电路板集成电感100更加超薄化、小型化。
请参见图3至图6，电路板10包括至少一层支撑绝缘层12及至少一层导电层14；支撑绝缘层12与导电层14依次交替层叠设置。如图5所示，在一些实施例中，电路板10包括层叠设置的一层支撑绝缘层12及一层导电层14，导电层14包括导线14a，例如一根、两根、三根、四根等，导线14a形成线圈11(或者说一根导线14a形成一个线圈11)。如图3和图4所示，在另一些实施例中，电路板10包括层叠设置的一层支撑绝缘层12及两层导电层14，两层导电层14分别设置于支撑绝缘层12相背的两个表面上，两层导电层14均包括导线14a，两层导电层14的导线14a电连接，形成线圈11。如图6所示，在另一些实施例中，电路板10包括层叠设置的两层支撑绝缘层12及三层导电层14，支撑绝缘层12与导电层14依次交替层叠设置，三层导电层14均包括导线14a，任意相邻的两层导电层14的导线14a电连接，形成线圈11。本申请对电路板10中支撑绝缘层12和导电层14的数量不作具体限定，只要能够形成支撑绝缘层12与导电层14依次交替层叠的结构即可，具体可以根据实际需求进行设计。
在一具体实施例中，电路板10包括层叠设置的一层支撑绝缘层12及一层导电层14，导电层14包括一根导线14a，该导线14a形成一个线圈11，如图5所示。在另一具体实施例中，电路板10包括层叠设置的一层支撑绝缘层12及两层导电层14，两层导电层14分别设置于支撑绝缘层12相背的两个表面上，两层导电层14均包括一根导线14a，两层导电层14的导线14a电连接形成一个线圈11，如图3所示。在另一具体实施例中，电路板10包括层叠设置的一层支撑绝缘层12及两层导电层14，两层导电层14分别设置于支撑绝缘层12相背的两个表面上，两层导电层14均包括两根导线14a，两层导电层14的其中一根导线14a电连接形成一个线圈11，两层导电层14的另一根导线14a电连接形成另一个线圈11，换言之，形成两个线圈11，如图7所示。
可选地，支撑绝缘层12可以包括但不限于包括聚酰亚胺(PI)、玻纤/环氧树脂复合板(Prepreg)等中的至少一种。导线14a可以包括但不限于包括铜、银导电金属或合金中的至少一种。当需要制备柔性电路板(FPC)10时，可以采用聚酰亚胺作为支撑绝缘层12，当需要制备印制电路板(PCB板)10时，可以采用玻纤/环氧树脂复合板作为支撑绝缘层12。在一具体实施例中，支撑绝缘层12为聚酰亚胺，导线14a为铜线。
可选地，沿支撑绝缘层12与导电层14的层叠方向上，每层支撑绝缘层12的厚度为10μm至50μm；具体地，可以为但不限于为10μm、15μm、20μm、25μm、30μm、35μm、40μm、45μm、50μm等。支撑绝缘层12的厚度太小，如小于10μm时，支撑绝缘层12的力学性能有限，难以对导电层14起到有效支撑作用；由于支撑绝缘层12的磁导率很低，支撑绝缘层12的厚度过大，例如大于50μm时，会增加磁路的长度，使得磁阻增大，不利于得到的电感的性能。
本申请实施例中，当涉及到数值范围a至b时，如未特别指明，均表示包括端点数值a，且包括端点数值b。例如，导线14a的厚度为50μm至150μm表示，导线14a的厚度可以为50μm至150μm之间的任意数值，包括端点50μm及端点150μm。
请参见图8，可选地，沿支撑绝缘层12与导电层14的层叠方向上，导线14a的厚度d1的范围为50μm至150μm，具体地，可以为但不限于为50μm、60μm、70μm、80μm、90μm、100μm、110μm、120μm、130μm、140μm、150μm等。可选地，导线14a的宽度d2(即平行于支撑绝缘层12延伸方向的宽度)的范围为100μm至300μm；具体地，可以为但不限于为100μm、110μm、120μm、130μm、140μm、150μm、180μm、200μm、220μm、240μm、280μm、300μm等。可选地，同一匝线圈11中，相对设置的两部分导线14a的线距d3的范围为100μm至200μm；具体地，可以为但不限于为100μm、110μm、120μm、130μm、140μm、150μm、180μm、200μm。在一具体实施例中，导线14a的厚度为100μm，导线14a的宽度为200μm，导线14a的线距为150μm。
请参见图9及图10，在一些实施例中，电路板10还包括基板10a及功能电路10b，功能电路10b承载于基板10a，且与线圈11电连接。可选地，基板10a与支撑绝缘层12为一体结构。请参见图10，功能电路10b包括处理器11b及存储器13b，处理器11b及存储器13b均设置于基板10a的表面，处理器11b分别与存储器13b及线圈11电连接。处理器11b用于控制线圈11电流的大小及方向等。存储器13b用于存储处理器11b运行所需的程序代码。
可选地，处理器11b包括一个或者多个通用处理器11b，其中，通用处理器可以是能够处理电子指 令的任何类型的设备，包括中央处理器(Central Processing Unit，CPU)、微处理器、微控制器、主处理器、控制器以及ASIC等等。处理器11b用于执行各种类型的数字存储指令，例如存储在存储器中的软件或者固件程序，它能使计算设备提供较宽的多种服务。
可选地，存储器13b可以包括易失性存储器(Volatile Memory)，例如随机存取存储器(Random Access Memory，RAM)；存储器13b也可以包括非易失性存储器(Non-Volatile Memory，NVM)，例如只读存储器(Read-Only Memory，ROM)、快闪存储器(Flash Memory，FM)、硬盘(Hard Disk Drive，HDD)或固态硬盘(Solid-State Drive，SSD)。存储器13b还可以包括上述种类的存储器的组合。
可选地，磁膜子层31为磁性层。进一步地，磁膜子层31为软磁层。软磁具有高磁导率、低剩磁、低矫顽力、低磁阻、磁滞损耗小、且容易被磁化。在一些实施例中，磁膜子层31可以为但不限于为磁性金属、磁性合金等中的至少一种。磁性金属包括铁、钴、镍等中的至少一种。可选地，磁性合金可以包括但不限于包括铁基晶态合金、铁基非晶合金、钴基非晶合金等中的至少一种。铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金等中的至少一种。铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金等中的至少一种。钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金等中的至少一种。
相较于铁基晶态合金及铁基非晶合金，钴基非晶合金具有更高的磁导率，因此，当磁膜层30要求较高的磁导率时，磁膜子层31可以采用钴基非晶合金中的至少一种。相较于钴基非晶合金，铁基晶态合金及铁基非晶合金具有较高的饱和磁特性，当磁膜层30要求较高的饱和磁特性时，磁膜子层31可以选用铁基晶态合金及铁基非晶合金等中的至少一种。相较于铁基晶态合金，铁基非晶合金及钴基非晶合金具有较低的矫顽力，当磁膜层30要求较低的矫顽力时，磁膜子层31可以选用铁基非晶合金及钴基非晶合金。矫顽力(coercive force)是指磁性材料在饱和磁化后，当外磁场退回到零时其磁感应强度B并不退到零，只有在原磁化场相反方向加上一定大小的磁场才能使磁感应强度退回到零，该磁场称为矫顽磁场，又称矫顽力。
请参见图11，在一些实施例中，沿电路板10及磁膜层30的层叠方向上，每层磁膜子层31的厚度h1的范围为0.5μm≤h1≤30μm；具体地，每层磁膜子层31的厚度h1可以为但不限于为0.5μm、1μm、2μm、4μm、6μm、8μm、10μm、13μm、15μm、18μm、20μm、23μm、25μm、28μm、30μm等。当磁膜子层31小于0.5μm时，磁膜子层31与支撑绝缘层12的厚度之比相对较小，影响磁膜层30的有效磁导率及电路板集成电感100的感量，此外，若要实现相同总厚度的磁性层，需要更多的层数，增加了工艺的复杂性和生产成本。当磁膜子层31的厚度h1大于30μm时，这使得单层磁膜子层31内的涡流损耗增加，且增加了磁膜子层31的沉积难度。
在一些实施例中，沿电路板10及磁膜层30的层叠方向上，至少一层磁膜子层31的总厚度h的范围为0.5μm≤h≤200μm；具体地，至少一层磁膜子层31的总厚度h可以为但不限于为0.5μm、5μm、10μm、20μm、40μm、60μm、80μm、100μm、120μm、180μm、200μm等。
在一些实施例中，绝缘子层33包括陶瓷绝缘层、有机绝缘层中的至少一种；陶瓷绝缘层包括氧化铝、二氧化硅中的至少一种；有机绝缘层包括聚丙烯、聚四氟乙烯、聚酰亚胺中的至少一种。相较于有机绝缘层，陶瓷绝缘层具有更好的绝缘性能和机械强度，但是，有机绝缘层具有更低的制备成本。绝缘子层33材料的选择，可以根据实际应用需求进行选择。
可选地，绝缘子层33的厚度h3为50nm≤h3≤500nm；具体地，可以为但不限于为50nm、100nm、150nm、200nm、250nm、300nm、350nm、400nm、450nm、500nm等。绝缘子层33的厚度小于50nm时，这使得绝缘子层33内孔洞等缺陷影响变大，影响绝缘子层33的绝缘性能，换言之，降低绝缘子层33的绝缘性能；绝缘子层33的厚度大于500nm时，使得磁膜子层31与绝缘子层33的厚度之比较小，影响磁膜层30的有效磁导率及电路板集成电感100的感量。
请参见图12，在一些实施例中，本申请实施例的电路板集成电感100还包括介质层50，介质层50位于线圈11与磁膜层30之间，用于使线圈11与磁膜层30绝缘设置。在保证绝缘性能的同时，介质层50的磁导率越高越好，介质层50的磁导率越高，制得的电路板集成电感100具有越高的电感量。
在一些实施例中，介质层50为玻纤/环氧树脂复合板、聚酰亚胺、聚丙烯、聚四氟乙烯等中的至 少一种。当介质层50的材料与支撑绝缘层12的材料相同时，可以在制备电路板10及线圈11时，在线圈11的表面形成介质层50，以简化电路板集成电感100的制备工艺。
在另一些实施例中，介质层50为磁胶层，磁胶层包括树脂及磁性颗粒，磁性颗粒分散于树脂中。采用磁胶层作为介质层50，可以提高电路板集成电感100中电感的磁导率及电感量。磁胶层可以通过将磁性颗粒分散于液体树脂中形成磁性浆料，再将其涂覆或印刷于电路板10的表面，经过固化(例如紫外光光固化)形成。磁胶层指包括磁性材料在其中不连续分布、磁性材料之间断开的膜层。
可选地，在磁胶层中，磁性颗粒的重量分数的范围为30％至90％；具体地，可以为但不限于为30％、35％、40％、45％、50％、55％、60％、65％、70％、75％、80％、85％、90％等。磁胶层中磁性颗粒的重量分数小于30％时，难以达到提高电路板集成电感100中电感磁导率的效果，且会增加电路板集成电感100的成本；当磁胶层中磁性颗粒的重量分数大于90％时，磁性浆料中磁性颗粒分散困难、流动性不足，进行涂覆或印刷时，难以填满电路板10表面线圈11的间隙，使得磁胶层与线圈11之间空气间隙过多，磁阻变大，从而降低磁导率。
可选地，磁性颗粒的平均粒径D的范围为5μm≤D≤50μm；具体地，可以为但不限于为5μm、10μm、15μm、20μm、25μm、30μm、35μm、40μm、45μm、50μm等。磁性颗粒较小时，涡流被限制在很小的范围内，随着磁性颗粒的增加，可以供电流流过的区域变大，从而增加了涡流损耗。当磁性颗粒的平均粒径小于5μm时，不仅增加了磁性颗粒的成本，且会降低磁胶层的磁导率，失去了通过磁胶层提高磁导率的意义。当磁性颗粒的平均粒径大于50μm时，涡流损耗过大，也不利于电路板集成电感100的性能。
可选地，磁性颗粒为软磁颗粒。软磁具有高磁导率、低剩磁、低矫顽力、低磁阻、磁滞损耗小、且容易被磁化。可选地，磁性颗粒包括铁氧体颗粒、磁性金属颗粒、磁性合金颗粒中的至少一种。铁氧体颗粒具有更好的电绝缘性及更低的损耗，磁性金属颗粒或磁性合金颗粒具有更高的磁导率和磁饱和感应强度。因此，当要求磁胶层具有更好的电绝缘性和更低的损耗时，可以选择铁氧体颗粒作为磁性颗粒，当要求磁胶层具有更高的磁导率和磁饱和感应强度时，可以选择磁性金属颗粒或磁性合金颗粒作为磁性颗粒。可选地，铁氧体颗粒包括MnZn铁氧体、NiZn铁氧体等中的至少一种。可选地，磁性金属颗粒包括铁、钴、镍中等的至少一种。可选地，磁性合金颗粒包括铁基晶态合金、铁基非晶合金、钴基非晶合金等中的至少一种。铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金等中的至少一种。铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金等中的至少一种。钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金等中的至少一种。
相较于铁基晶态合金及铁基非晶合金，钴基非晶合金具有更高的磁导率，因此，当磁胶层要求较高的磁导率时，磁性颗粒可以采用钴基非晶合金中的至少一种。相较于钴基非晶合金，铁基晶态合金及铁基非晶合金具有较高的饱和磁特性，当磁胶层要求较高的饱和磁特性时，磁性颗粒可以选用铁基晶态合金及铁基非晶合金等中的至少一种。相较于铁基晶态合金，铁基非晶合金及钴基非晶合金具有较低的矫顽力，当磁胶层要求较低的矫顽力时，磁性颗粒可以选用铁基非晶合金及钴基非晶合金。
当磁性颗粒为磁性合金颗粒时，磁性合金颗粒的表面具有钝化层，钝化层为绝缘层，换言之，钝化层是绝缘的。在一些实施例中，可以在磁性合金颗粒的表面包裹一层有机树脂，以使磁性合金颗粒具有绝缘性。在另一些实施例中，可以将磁性合金颗粒采用磷酸进行钝化，以在磁性合金颗粒的表面形成一层不导电的钝化层。
可选地，树脂包括环氧树脂、聚氨酯及丙烯酸酯等中的至少一种。在一具体实施例中，当电路板10的支撑绝缘层12为玻纤/环氧树脂复合板时，磁胶层的树脂可以为环氧树脂，这样可以使得磁胶层与电路板10具有更好的结合性能，可以更好的附着于电路板10上。
可选地，沿电路板10、介质层50及磁膜层30层叠方向上，介质层50的厚度h2的范围为5μm≤h2≤200μm；具体地，可以为但不限于为5μm、10μm、30μm、50μm、80μm、100μm、120μm、140μm、160μm、180μm、200μm等。当介质层50为玻纤/环氧树脂复合板、聚酰亚胺、聚丙烯、聚四氟乙烯等中的至少一种时，制备时通常将现成的膜层压合至电路板10的表面，目前低于5μm的 介质层50很少，且价格高。当介质层50为磁胶层且h2小于5μm时，介质层50可能难以完全覆盖裸露在电路板10表面的线圈11，导致介质层50的表面有台阶，不利于磁膜子层31的沉积。当介质层50的厚度大于200μm时，介质层50的磁阻过大，使得制得的电路板集成电感100的感量降低。
本申请实施例的电路板集成电感100可以通过本申请下列实施例的方法进行制备，此外，还可以通过其它方法进行制备，本申请实施例的制备方法仅仅是本申请电路板集成电感100的一种制备方法，不应理解为对本申请实施例提供的电路板集成电感100的限定。
请参见图13，本申请实施例还提供了一种电路板集成电感100的制备方法，其包括：
S201，提供电路板10，电路板10嵌设有线圈11；
关于电路板10及线圈11的详细描述请参见上述实施例对应部分的描述，在此不再赘述。
S202，在电路板10相背的两侧中的至少一侧依次交替沉积磁膜子层31及绝缘子层33，以在电路板10相背的两侧中的至少一侧上形成磁膜层30，其中，磁膜层30与线圈11至少部分交叠，磁膜层30包括至少两层磁膜子层31及至少一层绝缘子层33。
可选地，采用物理气相沉积法、或电沉积法等在电路板10相背的两侧中的至少一侧先沉积一层磁膜子层31，接着采用物理气相沉积法等在磁膜子层31背离电路板10的表面沉积一层绝缘子层33，接着依次交替重复，直到得到预先设计的磁膜子层31的层数。采用物理气相沉积方法制得的磁膜子层31的外观形貌好，但是容易产生脱落；采用电沉积方法制得的磁膜子层31具有良好的耐剥离性能，不易脱落，但是表面形貌较差。因此当磁膜子层31的厚度小于1μm时，可以采用物理气相沉积方法制备；当磁膜子层31的厚度大于或等于1μm时，可以采用电沉积方法制备。
关于磁膜层30、磁膜子层31及绝缘子层33的详细描述请参见上述实施例对应部分的描述，在此不再赘述。
本实施例的电路板集成电感100的制备方法制得的电路板集成电感100，将电感集成于电路板10上，应用于电子设备时，可以使得电子设备更加小型化、超薄化，且电感与电路板10一起制备，不需要独立贴装，提高了封装效率。此外，电感集成于电路板10内，电路板10上对应电感的位置可以节省出来，用于贴装其它元器件，节省了电路板10上的面积，增强了电路板10的布线、布件能力。再者，当磁性层的厚度太厚时，在磁性层的厚度方向上会产生较大的涡流效应，本申请的电路板集成电感100的磁膜层30包括至少两层磁膜子层31及至少一层绝缘子层33，磁膜子层31与绝缘子层33依次交替层叠设置，相较于磁膜层30为一层磁性层的方案，将磁膜层30中的磁性层分为至少两层磁膜子层31，相邻的两个磁膜子层31之间设有绝缘子层33，绝缘子层33可以阻止磁膜中涡流在厚度方向上的传导，从而降低整个磁膜层30在厚度方向上的涡流损耗，进而降低整个电感的涡流损耗。
请参见图14及图15，在一些实施例中，本申请实施例提供了一种电路板10的制备方法，其包括：
S2011，提供第一基板10’，第一基板10’包括支撑绝缘层12及设置于支撑绝缘层12相背的两个表面中的至少一个表面的导体层11’；
在一具体实施例中，第一基板10’包括一层支撑绝缘层12及一层导体层11’，支撑绝缘层12与导体层11’层叠设置。在另一具体实施例中，第一基板10’包括依次层叠设置的导体层11’、支撑绝缘层12、导体层11’。可选地，导体层11’可以为但不限于为包括铜、银等金属或合金等导电材料。关于支撑绝缘层12的详细描述请参见上述实施例对应部分的描述，在此不再赘述。
S2012，对第一基板10’的每层导体层11’进行刻蚀，以使导体层11’形成导电层14，导电层14包括导线14a；其中，当导电层14为一层时，单层导电层14的导线14a形成线圈11；当导电层14为两层时，两层导电层14的导线14a电连接，形成线圈11。
可选地，采用黄光刻蚀工艺，在导体层11’的表面涂覆光刻胶，对光刻胶先后进行软烤、曝光、显影、硬烤等工艺形成光刻胶掩膜板，接着对导体层11’进行刻蚀，以得到导电层14，导电层14包括导线14a，当导电层14为一层时，单层导电层14的导线14a形成线圈11；当导电层14为两层时，两层导电层14的导线14a电连接，形成线圈11。关于导电层14、线圈11的详细描述请参见上述实施例对应部分的描述，在此不再赘述。
请参见图16，在一些实施例中，当第一基板10’包括两层导体层11’且线圈11由两层导体层11’刻 蚀形成的导线14a形成时，电路板10的制备方法包括：
S2011a，提供第一基板10’，第一基板10’包括支撑绝缘层12及设置于支撑绝缘层12相背的两个表面的两层导体层11’；
关于步骤S2011a的详细描述请参见上述实施例对应部分的描述，在此不再赘述。
S2012a，在第一基板10’的支撑绝缘层12及两层导体层11’中的至少一层的预设位置形成第一过孔101(如图3所示)；
可选地，第一过孔101可以为通孔、也可以为盲孔；当第一过孔101为通孔时支撑绝缘层12及两层导体层11’均被打穿；当第一过孔101为盲孔时，支撑绝缘层12与两层导体中的至少一层被打穿。第一过孔101可以采用激光进行打孔。
S2013a，对第一基板10’的两层导体层11’进行刻蚀，以使导体层11’形成导电层14，导电层14包括导线14a；以及
关于步骤S2013a的详细描述请参见上述实施例对应部分的描述，在此不再赘述。
S2014a，在第一过孔101中沉积导电材料，以将两层导电层14中的导线14a电连接形成线圈11。
具体地，可以采用物理气相沉积法(简称PVD)或电沉积法等方法在第一过孔101中沉积导电材料，以将两层导电层14中的导线14a电连接形成线圈11。导电材料可以为但不限于为铜、银等金属或合金。本实施例与上述实施例相同特征部分的详细描述请参见上述实施例，在此不再赘述。
请参见图17及图18，在一些实施例中，当电路板10包括至少三层导电层14时，电路板10的制备方法包括：
S2011b，提供第一基板10’，第一基板10’包括支撑绝缘层12及设置于支撑绝缘层12相背的两个表面的两层导体层11’；
S2012b，在第一基板10’的支撑绝缘层12及两层导体层11’中的至少一层的预设位置形成第一过孔101；
S2013b，对第一基板10’的两层导体层11’进行刻蚀，以使导体层11’形成导电层14，导电层14包括导线14a；
S2014b，在第一过孔101中沉积导电材料，以将第一基板10’的两层导电层14中的导线14a电连接；
关于步骤S2011b至S2014b的详细描述请参见上述实施例对应部分的描述，在此不再赘述。
S2015b，提供第二基板10”，第二基板10”包括支撑绝缘层12及设置于支撑绝缘层12表面的导体层11’；
关于支撑绝缘层12与导体层11’的详细描述请参见上述实施例对应部分的描述，在此不再赘述。
S2016b，在第二基板10”的支撑绝缘层12及导体层11’的预设位置形成第二过孔；
可选地，第二过孔为通孔；换言之，支撑绝缘层12及两层导体层11’均被打穿。第二过孔可以采用激光进行打孔。
S2017b，对第二基板10”的导体层11’进行刻蚀，以得到导线14a；
S2018b，将第一基板10’与第二基板10”压合；可选地，将第一基板10’与至少一个第二基板10”叠合，叠合第一基板10’的导电层14面向第二基板10”的支撑绝缘层12叠合，以使得导电层14与支撑绝缘层12可以形成依次交替层叠的结构，叠合后通过热压等方式将第一基板10’与第二基板10”粘合到一起，形成一体结构。
S2019b，在第二过孔中沉积导电材料，以将第一基板10’的导线14a与第二基板10”的导线14a电连接，得到电路板10，其中，电路板10包括至少一层支撑绝缘层12及至少一层导电层14；支撑绝缘层12与导电层14依次交替层叠设置；其中，每层导电层14包括导线14a；任意相邻的两层导电层14的导线14a电连接，形成线圈11。
本实施例与上述实施例相同特征部分的详细描述请参见上述实施例，在此不再赘述。
请参见图19，本申请实施例还提供了一种电路板集成电感100的制备方法，其包括：
S301，提供电路板10，电路板10嵌设有线圈11；
关于步骤S301的详细描述请参见上述实施例对应部分的描述，在此不再赘述。
S302，在电路板10相背的两个表面中的至少一个表面上形成介质层50，并使介质层50至少覆盖线圈11；
可选地，当介质层50为玻纤/环氧树脂复合板、聚酰亚胺、聚丙烯、聚四氟乙烯中的至少一种时，将介质层50叠合于电路板10相背的两个表面中的至少一个表面上，并进行压合，以使使介质层50贴合与电路板10，并至少覆盖线圈11。当介质层50为磁胶层时，先将磁性颗粒分散于液体树脂中形成磁性浆料，再将磁性浆料采用涂覆、印刷等方式在电路板10表面形成磁性浆料层，接着置于LED灯或汞灯等等紫外光下以使液体树脂发生光固化形成固态树脂，得到磁胶层。在其它实施例中，磁性浆料层也可以采用热固化进行固化，本申请对此不作具体限定。
S303，在介质层50背离电路板10的表面依次交替沉积磁膜子层31及绝缘子层33，以在电路板10相背的两侧中的至少一侧上形成磁膜层30，其中，磁膜层30与线圈11至少部分交叠，磁膜层30包括至少两层磁膜子层31及至少一层绝缘子层33。
关于步骤S303的详细描述请参见上述实施例对应部分的描述，在此不再赘述。
本实施例与上述实施例相同特征部分的详细描述请参见上述实施例，在此不再赘述。
以下通过具体示例对本申请实施例的电路板集成电感100做进一步说明。
示例1
本示例的电路板集成电感100包括电路板10，电路板10包括支撑绝缘层12及线圈11。线圈11嵌设于支撑绝缘层12中。线圈11为铜线圈11，线圈11的匝数为1匝。支撑绝缘层12的厚度为50μm，铜线圈11的线宽为200μm，铜线圈11的线厚为100μm，铜线圈11的线距为150μm。电路板集成电感100还包括介质层50，介质层50设置于电路板10相背的两个表面，且至少覆盖线圈11。介质层50的厚度为100μm，介质层50为玻纤/环氧树脂复合板。电路板集成电感100还包括磁膜层30，磁膜层30设置于介质层50背离电路板10的表面(换言之，电路板10的相对两侧均设有一个磁膜层30)，磁膜层30依次层叠设置有FeNi合金层(磁膜子层31)、Al 2O 3层(绝缘子层33)以及FeNi合金层。每层磁膜子层31(FeNi合金层)的厚度为5μm，磁膜子层31的相对磁导率为800，电导率为40KS/m。绝缘子层33的厚度为0.2μm。
对比例1
本对比例的电路板集成电感100包括电路板10，电路板10包括支撑绝缘层12及线圈11。线圈11嵌设于支撑绝缘层12中。线圈11为铜线圈11，线圈11的匝数为1匝。支撑绝缘层12的厚度为50μm，铜线圈11的线宽为200μm，铜线圈11的线厚为100μm，铜线圈11的线距为150μm。电路板集成电感100还包括介质层50，介质层50设置于电路板10相背的两个表面，且至少覆盖线圈11。介质层50的厚度为100μm，介质层50为玻纤/环氧树脂复合板。电路板集成电感100还包括磁膜层30，磁膜层30设置于介质层50背离电路板10的表面(换言之，电路板10的相对两侧均设有一个磁膜层30)，磁膜层30包括一层FeNi合金层，FeNi合金层的厚度为10μm，FeNi合金层的相对磁导率为800，电导率为40KS/m。
根据标准GB/T 8554-1998进行模拟计算，得到示例1及对比例1得到的电路板集成电感100的感量及涡流损耗如下表1所示。
表1 示例1及对比例1的电路板集成电感100的模拟测试数据
示例 示例1 对比例1
感量(nH) 4.31 4.32
涡流损耗(μW) 9 16
由表1的模拟计算结果可知，当在FeNi合金层的总厚度一定的情况下，FeNi合金层分成两个膜层的电感与一个膜层的感量相当，但是FeNi合金层分成两个膜层的涡流损耗比一个膜层的涡流损耗会小很多。
示例2
本示例的电路板集成电感100包括电路板10，电路板10包括支撑绝缘层12及线圈11。线圈11 嵌设于支撑绝缘层12中。线圈11为铜线圈11，线圈11的匝数为1匝。支撑绝缘层12的厚度为50μm，铜线圈11的线宽为200μm，铜线圈11的线厚为100μm，铜线圈11的线距为150μm。电路板集成电感100还包括介质层50，介质层50设置于电路板10相背的两个表面，且至少覆盖线圈11。介质层50的厚度为100μm，介质层50为玻纤/环氧树脂复合板。电路板集成电感100还包括磁膜层30，磁膜层30设置于介质层50背离电路板10的表面(换言之，电路板10的相对两侧均设有一个磁膜层30)，磁膜层30依次层叠设置有FeNi合金层(磁膜子层31)、Al 2O 3层(绝缘子层33)以及FeNi合金层。每层磁膜子层31(FeNi合金层)的厚度为15μm，磁膜子层31的相对磁导率为800，电导率为40KS/m。绝缘子层33的厚度为0.2μm。
示例3
本示例的电路板集成电感100包括电路板10，电路板10包括支撑绝缘层12及线圈11。线圈11嵌设于支撑绝缘层12中。线圈11为铜线圈11，线圈11的匝数为1匝。支撑绝缘层12的厚度为50μm，铜线圈11的线宽为200μm，铜线圈11的线厚为100μm，铜线圈11的线距为150μm。电路板集成电感100还包括介质层50，介质层50设置于电路板10相背的两个表面，且至少覆盖线圈11。介质层50的厚度为100μm，介质层50为玻纤/环氧树脂复合板。电路板集成电感100还包括磁膜层30，磁膜层30设置于介质层50背离电路板10的表面(换言之，电路板10的相对两侧均设有一个磁膜层30)，磁膜层30依次层叠设置有FeNi合金层(磁膜子层31)、Al 2O 3层(绝缘子层33)、FeNi合金层、Al 2O 3层(绝缘子层33)以及FeNi合金层。每层磁膜子层31(FeNi合金层)的厚度为10μm，磁膜子层31的相对磁导率为800，电导率为40KS/m。绝缘子层33的厚度为0.2μm。
对比例2
本对比例的电路板集成电感100包括电路板10，电路板10包括支撑绝缘层12及线圈11。线圈11嵌设于支撑绝缘层12中。线圈11为铜线圈11，线圈11的匝数为1匝。支撑绝缘层12的厚度为50μm，铜线圈11的线宽为200μm，铜线圈11的线厚为100μm，铜线圈11的线距为150μm。电路板集成电感100还包括介质层50，介质层50设置于电路板10相背的两个表面，且至少覆盖线圈11。介质层50的厚度为100μm，介质层50为玻纤/环氧树脂复合板。电路板集成电感100还包括磁膜层30，磁膜层30设置于介质层50背离电路板10的表面(换言之，电路板10的相对两侧均设有一个磁膜层30)，磁膜层30包括一层FeNi合金层，FeNi合金层的厚度为30μm，FeNi合金层的相对磁导率为800，电导率为40KS/m。
根据标准GB/T 8554-1998进行模拟计算，得到示例2、示例3及对比例2得到的电路板集成电感100的感量及涡流损耗如下表2所示。
表2 示例2、示例3及对比例2的电路板集成电感100的模拟测试数据
示例 示例2 示例3 对比例2
感量(nH) 4.68 4.67 4.69
涡流损耗(μW) 36 30 64
由表2的模拟计算结果可知，当在FeNi合金层的总厚度一定的情况下，FeNi合金层分成两个膜层、或三个膜层后的感量与一个膜层的感量相当，但是，FeNi合金层分成多个膜层的涡流损耗比一个膜层的涡流损耗会小很多，且FeNi合金层的层数越多，涡流损耗越小。
请参见图20、图21及图22，本申请实施例还提供一种电子设备400，电子设备400包括：显示组件410、本申请实施例的电路板集成电感100及壳体430。显示组件410用于显示；壳体430设置于显示组件410的一侧；电路板集成电感100设置于显示组件410与壳体430之间，且与显示组件410电连接，电路板集成电感100的处理器11b还用于控制显示组件410进行显示。
本申请实施例的电子设备400可以为但不限于为手机、平板电脑、笔记本电脑、台式电脑、智能手环、智能手表、电子阅读器、游戏机等便携式电子设备400。本实施例中图20中以手机的为例进行示意，不应理解为对本申请实施例的限制。
关于电路板集成电感100的详细描述，请参见上述实施例对应部分的描述，在此不再赘述。
本实施例的壳体430可以为2D结构、2.5D结构、3D结构等。本实施例的壳体430可以为电子设 备400的后盖(电池盖)、或中框及后盖一体化的外壳。
可选地，显示组件410可以为但不限于为液晶显示组件、发光二极管显示组件(LED显示组件)、微发光二极管显示组件(Micro LED显示组件)、次毫米发光二极管显示组件(Mini LED显示组件)、有机发光二极管显示组件(OLED显示组件)等中的一种或多种。
请再次参见图21及图22，在一些实施例中，壳体430为电子设备400的后盖，本申请实施例的电子设备400还包括中框420及摄像头模组450，中框420设置于显示组件410与壳体430之间，且中框420的侧面显露于壳体430与显示组件410。中框420与壳体430围合成容置空间，容置空间用于容置电路板集成电感100与摄像头模组450。摄像头模组450与电路板集成电感100的处理器11b电连接，用于在处理器11b的控制下进行拍摄。
可选地，壳体430上具有透光部431，摄像头模组450可通过壳体430上的透光部431拍摄，即，本实施方式中的摄像头模组450为后置摄像头模组450。可以理解地，在其他实施方式中，透光部431可设置在显示组件410上，即，摄像头模组450为前置摄像头模组450。在本实施方式的示意图中，以透光部431为开口进行示意，在其他实施方式中，透光部431可以不为开口，而是为透光的材质，比如塑料、玻璃等。
可以理解地，本实施方式中的电子设备仅仅为电路板集成电感所应用的电子设备的一种形态，不应当理解为对本申请提供的电子设备的限定，也不应当理解为对本申请各个实施方式提供的电路板集成电感的限定。
在本申请中提及“实施例”、“实施方式”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现的短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本申请所描述的实施例可以与其它实施例相结合。此外，还应该理解的是，本申请各实施例所描述的特征、结构或特性，在相互之间不存在矛盾的情况下，可以任意组合，形成未脱离本申请技术方案的精神和范围的又一实施例。
最后应说明的是，以上实施方式仅用以说明本申请的技术方案而非限制，尽管参照以上较佳实施方式对本申请进行了详细说明，本领域的普通技术人员应当理解，可以对本申请的技术方案进行修改或等同替换都不应脱离本申请技术方案的精神和范围。

Claims (20)

  1. 一种电路板集成电感，其特征在于，包括：
    电路板，所述电路板嵌设有线圈；以及
    磁膜层，所述磁膜层设置于所述电路板相背的两侧中的至少一侧上，且与所述线圈至少部分交叠，所述磁膜层包括至少两层磁膜子层及至少一层绝缘子层，所述磁膜子层与所述绝缘子层依次交替层叠设置。
  2. 根据权利要求1所述的电路板集成电感，其特征在于，所述电路板包括至少一层支撑绝缘层及至少一层导电层；所述支撑绝缘层与所述导电层依次交替层叠设置，所述导电层包括导线；当所述导电层为一层时，单层所述导电层的所述导线形成所述线圈；当所述导电层为多层时，任意相邻的两层导电层的导线电连接，形成所述线圈。
  3. 根据权利要求1所述的电路板集成电感，其特征在于，所述磁膜子层包括磁性金属、磁性合金中的至少一种；所述磁性金属包括铁、钴、镍中的至少一种；所述磁性合金包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金中的至少一种；所述铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金中的至少一种。
  4. 根据权利要求1所述的电路板集成电感，其特征在于，沿所述电路板及所述磁膜层的层叠方向，每层所述磁膜子层的厚度h1的范围为0.5μm≤h1≤30μm，所述至少一层磁膜子层的总厚度h的范围为0.5μm≤h≤200μm。
  5. 根据权利要求1所述的电路板集成电感，其特征在于，所述电路板集成电感还包括介质层，所述介质层位于所述线圈与所述磁膜层之间。
  6. 根据权利要求5所述的电路板集成电感，其特征在于，所述介质层为磁胶层，所述磁胶层包括树脂及磁性颗粒，所述磁性颗粒分散于所述树脂中。
  7. 根据权利要求6所述的电路板集成电感，其特征在于，在所述磁胶层中，所述磁性颗粒的重量分数的范围为30％至90％。
  8. 根据权利要求6所述的电路板集成电感，其特征在于，所述磁性颗粒的平均粒径D的范围为5μm≤D≤50μm。
  9. 根据权利要求6所述的电路板集成电感，其特征在于，所述树脂包括环氧树脂、聚氨酯及丙烯酸酯中的至少一种。
  10. 根据权利要求6所述的电路板集成电感，其特征在于，所述磁性颗粒包括铁氧体颗粒、磁性金属颗粒、磁性合金颗粒中的至少一种；所述铁氧体包括MnZn铁氧体、NiZn铁氧体中的至少一种；所述磁性金属颗粒包括铁、钴、镍中的至少一种；所述磁性合金颗粒包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金中的至少一种；所述铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金中的至少一种。
  11. 根据权利要求5所述的电路板集成电感，其特征在于，所述介质层为玻纤/环氧树脂复合板、聚酰亚胺、聚丙烯、聚四氟乙烯中的至少一种。
  12. 根据权利要求5-11任一项所述的电路板集成电感，其特征在于，沿所述电路板、所述介质层及所述磁膜层的层叠方向，所述介质层的厚度h2的范围为5μm≤h2≤200μm。
  13. 根据权利要求1所述的电路板集成电感，其特征在于，所述绝缘子层包括陶瓷绝缘层、有机绝缘层中的至少一种；所述陶瓷绝缘层包括氧化铝、二氧化硅中的至少一种；所述有机绝缘层包括聚丙烯、聚四氟乙烯、聚酰亚胺中的至少一种。
  14. 根据权利要求1所述的电路板集成电感，其特征在于，所述绝缘子层的厚度h3的范围为50nm ≤h3≤500nm。
  15. 根据权利要求2-10任一项所述的电路板集成电感，其特征在于，所述电路板还包括基板及功能电路，所述功能电路承载于所述基板，且与所述线圈电连接。
  16. 一种电路板集成电感的制备方法，其特征在于，包括：
    提供电路板，所述电路板嵌设有线圈；以及
    在所述电路板相背的两侧中的至少一侧依次交替沉积磁膜子层及绝缘子层，以在所述电路板相背的两侧中的至少一侧上形成磁膜层，其中，所述磁膜层与所述线圈至少部分交叠，所述磁膜层包括至少两层所述磁膜子层及至少一层所述绝缘子层。
  17. 根据权利要求16所述的电路板集成电感的制备方法，其特征在于，所述提供电路板包括：
    提供第一基板，所述第一基板包括支撑绝缘层及设置于所述支撑绝缘层相背的两个表面中的至少一个表面的导体层；以及
    对所述第一基板的每层所述导体层进行刻蚀，以使所述导体层形成导电层，所述导电层包括导线；其中，当所述导电层为一层时，单层所述导电层的所述导线形成所述线圈；当所述导电层为两层时，两层所述导电层的导线电连接，形成所述线圈。
  18. 根据权利要求17所述的电路板集成电感的制备方法，其特征在于，所述提供电路板还包括：
    提供第二基板，所述第二基板包括支撑绝缘层及设置于所述支撑绝缘层的表面的导体层；
    对所述第二基板的所述导体层进行刻蚀，以得到导电层，所述导电层包括导线；以及
    将所述第一基板与所述第二基板压合，以得到电路板，其中，所述电路板包括至少一层支撑绝缘层及至少一层导电层；所述支撑绝缘层与所述导电层依次交替层叠设置；其中，每层所述导电层包括导线；任意相邻的两层导电层的导线电连接，形成所述线圈。
  19. 根据权利要求16-18任一项所述的电路板集成电感的制备方法，其特征在于，所述在所述电路板相背的两侧中的至少一侧依次交替沉积磁膜子层及绝缘子层之前，所述方法还包括：
    在所述电路板相背的两个表面中的至少一个表面上形成介质层，并使所述介质层至少覆盖所述线圈。
  20. 一种电子设备，其特征在于，所述电子设备包括权利要求1-15任一项所述的电路板集成电感。
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