WO2023124021A1 - 半导体二极管 - Google Patents

半导体二极管 Download PDF

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WO2023124021A1
WO2023124021A1 PCT/CN2022/106457 CN2022106457W WO2023124021A1 WO 2023124021 A1 WO2023124021 A1 WO 2023124021A1 CN 2022106457 W CN2022106457 W CN 2022106457W WO 2023124021 A1 WO2023124021 A1 WO 2023124021A1
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type
region
semiconductor
carrier
carrier region
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PCT/CN2022/106457
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English (en)
French (fr)
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刘磊
刘伟
袁愿林
王睿
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苏州东微半导体股份有限公司
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Publication of WO2023124021A1 publication Critical patent/WO2023124021A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring

Definitions

  • the present application belongs to the technical field of semiconductor power devices, for example, it relates to a semiconductor diode.
  • the present application provides a semiconductor diode to reduce the sudden change in voltage of a semiconductor diode with a super junction structure caused by a two-dimensional depletion effect.
  • the application provides a semiconductor diode, comprising:
  • a low-carrier region the p-type body region and the anode metal layer in the low-carrier region form a p-type Schottky diode;
  • a p-type contact region is provided in the p-type body region in the high-carrier region, and the p-type contact region forms an ohmic contact with the anode metal layer.
  • FIG. 1 is a schematic cross-sectional structure diagram of the first embodiment of the semiconductor diode provided by the present application.
  • Fig. 1 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor diode provided by the present application.
  • the semiconductor diode of the present application includes an n-type semiconductor layer 20, and the n-type semiconductor layer 20 is usually formed on an n-type substrate 10 or more.
  • a plurality of n-type pillars 22 and p-type pillars 21 are alternately arranged in the n-type semiconductor layer 20 , and a charge-balanced superjunction structure is formed between the n-type pillars 22 and the p-type pillars 21 .
  • the p-type body region 23 located on the top of the p-type pillar 21 optionally, the width of the p-type body region 23 is greater than the width of the p-type pillar 21 .
  • the anode metal layer 25 on the n-type semiconductor layer 20 and the insulating layer 26 on the n-type semiconductor layer 20 function as electrical insulation.
  • the semiconductor diode of the present application includes a low-carrier region 31 and a high-carrier region 32.
  • the low-carrier region 31 the p-type body region 23 is in contact with the anode metal layer 25 to form a p-type Schottky diode Structure
  • a p-type contact region 24 is provided in the p-type body region 23, and the p-type contact region 24 is in contact with the anode metal layer 25 to form an ohmic contact structure.
  • the low carrier region 31 is located at the edge region of the active region of the semiconductor diode
  • the high carrier region 32 is located at the middle region of the active region of the semiconductor diode.
  • the low-carrier region 31 may be located in a part of the edge region of the active region, or the entire edge region may be the low-carrier region 31, for example, the low-carrier region 31 may be located in the high-carrier region 32 One side or two sides of , or the low-carrier region 31 surrounds the high-carrier region 32 .
  • the active area refers to the area where active devices are arranged in the semiconductor diode chip, which is a term in the technical field of semiconductor power devices. All the structures in FIG. 1 are arranged in the active area. Exemplarily, FIG. 1 only shows the structure at the adjacent positions of the low-carrier region 31 and the high-carrier region 32, but does not show the structure of the low-carrier region 31 and the high-carrier region 32 globally. structure.
  • the carriers in the low-carrier region will be extracted first, and then the carriers in the high-carrier region will be extracted, which can gradually increase the reverse withstand voltage. Voltage mutations due to two-dimensional depletion effects are avoided.
  • the n-type column 22 in the high-carrier region 32, can also be contacted with the anode metal layer 25 to form an n-type Schottky diode, which can inject many carriers into the semiconductor diode and reduce the ohmic contact area.
  • the number of minority carriers stored in the pn junction below reduces the reverse recovery peak current.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本申请属于半导体功率器件技术领域，具体公开了一种半导体二极管，包括n型半导体层(20)；位于所述n型半导体层(20)之上的阳极金属层(25)；位于所述n型半导体层(20)内的多个交替间隔设置的n型柱(22)和p型柱(21)；位于所述p型柱(21)顶部的p型体区(23)；低载流子区(31)，所述低载流子区(31)内的所述p型体区(23)与所述阳极金属层(25)形成p型肖特基二极管；高载流子区(32)，所述高载流子区(32)内的所述p型体区(23)内设有p型接触区(24)，所述p型接触区(24)与所述阳极金属层(25)形成欧姆接触。

Description

半导体二极管
本申请要求在2021年12月27日提交中国专利局、申请号为202111611956.1的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于半导体功率器件技术领域，例如涉及一种半导体二极管。
背景技术
传统的半导体二极管的芯片面积较大、电流密度偏低，目前通常在半导体二极管中增加超结结构来增加芯片电流密度、降低芯片面积，但是常规超结结构的半导体二极管的单位面积内存储的少子过多，并且由于二维耗尽效应造成电压突变，同时反向恢复软度过低，导致反向恢复过程中的过冲电压太大。
发明内容
本申请提供一种半导体二极管，以降低超结结构的半导体二极管由于二维耗尽效应造成的电压突变。
本申请提供了一种半导体二极管，包括：
n型半导体层；
位于所述n型半导体层之上的阳极金属层；
位于所述n型半导体层内的多个交替间隔设置的n型柱和p型柱；
位于所述p型柱顶部的p型体区；
低载流子区，所述低载流子区内的所述p型体区与所述阳极金属层形成p型肖特基二极管；
高载流子区，所述高载流子区内的所述p型体区内设有p型接触区，所述p型接触区与所述阳极金属层形成欧姆接触。
附图说明
图1是本申请提供的半导体二极管的第一个实施例的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过具体方式，完整地描述本申请的技术方案。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图1是本申请提供的半导体二极管的第一个实施例的剖面结构示意图，如图1所示，本申请的半导体二极管包括n型半导体层20，n型半导体层20通常形成于n型衬底10之上。
位于n型半导体层20内的多个交替间隔设置的n型柱22和p型柱21，n型柱22与p型柱21之间形成电荷平衡的超结结构。位于p型柱21顶部的p型体区23，可选的，p型体区23的宽度大于p型柱21的宽度。
位于n型半导体层20之上的阳极金属层25，位于n型半导体层20上的绝缘层26起到电性绝缘的作用。
本申请的半导体二极管包括低载流子区31和高载流子区32两部分区域，在低载流子区31内：p型体区23与阳极金属层25接触形成p型肖特基二极管结构；在高载流子区32内：p型体区23内设有p型接触区24，p型接触区24与阳极金属层25接触形成欧姆接触结构。可选的，低载流子区31位于半导体二极管的有源区的边缘区域，高载流子区32位于半导体二极管的有源区的中间区域。其中，低载流子区31可以位于有源区的边缘区域的部分区域，也可以整个边缘区域均为低载流子区31，例如，低载流子区31可以位于高载流子区32的一侧或两侧，或者低载流子区31环绕高载流子区32。其中，有源区是指半导体二极管芯片里设置有源器件的区域，是半导体功率器件技术领域的术语， 图1中的所有结构都设置在有源区中。示例性的，图1中仅展示了低载流子区31和高载流子区32相邻位置处的结构，而未从全局上展示低载流子区31和高载流子区32的结构。
本申请的半导体二极管，在反向恢复过程中，会先抽取完低载流子区的载流子，再抽取完高载流子区的载流子，这可以使反向耐压逐步上升，避免了由于二维耗尽效应造成的电压突变。
本申请的半导体二极管，在高载流子区32内，还可以使n型柱22与阳极金属层25接触形成n型肖特基二极管，这可以向半导体二极管内部注入多子，降低欧姆接触区域下方的pn结的少子存储数量，减小反向恢复峰值电流。

Claims (4)

  1. 半导体二极管，包括：
    n型半导体层(20)；
    位于所述n型半导体层(20)之上的阳极金属层(25)；
    位于所述n型半导体层(20)内的多个交替间隔设置的n型柱(22)和p型柱(21)；
    位于每个所述p型柱(21)顶部的p型体区(23)；
    低载流子区(31)，所述低载流子区(31)内的所述p型体区(23)与所述阳极金属层(25)形成p型肖特基二极管；
    高载流子区(32)，所述高载流子区(32)内的所述p型体区(23)内设有p型接触区(24)，所述p型接触区(24)与所述阳极金属层(25)形成欧姆接触。
  2. 如权利要求1所述的半导体二极管，其中，所述高载流子区(32)内的所述n型柱(22)与所述阳极金属层(25)形成n型肖特基二极管。
  3. 如权利要求1所述的半导体二极管，其中，所述低载流子区(31)位于半导体二极管的有源区的边缘区域，所述高载流子区(32)位于半导体二极管的有源区的中间区域。
  4. 如权利要求1所述的半导体二极管，其中，所述p型体区(23)的宽度大于所述p型柱(21)的宽度。
PCT/CN2022/106457 2021-12-27 2022-07-19 半导体二极管 WO2023124021A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103718297A (zh) * 2011-08-02 2014-04-09 罗伯特·博世有限公司 超结肖特基pin二极管
JP2014236171A (ja) * 2013-06-05 2014-12-15 ローム株式会社 半導体装置およびその製造方法
CN110416319A (zh) * 2019-08-21 2019-11-05 江苏中科君芯科技有限公司 双面肖特基控制的快恢复二极管器件及制备方法
CN110610981A (zh) * 2018-06-15 2019-12-24 半导体组件工业公司 功率半导体器件及其形成方法
CN113555286A (zh) * 2021-07-05 2021-10-26 浙江芯国半导体有限公司 一种氧化镓超级结肖特基二极管及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103718297A (zh) * 2011-08-02 2014-04-09 罗伯特·博世有限公司 超结肖特基pin二极管
JP2014236171A (ja) * 2013-06-05 2014-12-15 ローム株式会社 半導体装置およびその製造方法
CN110610981A (zh) * 2018-06-15 2019-12-24 半导体组件工业公司 功率半导体器件及其形成方法
CN110416319A (zh) * 2019-08-21 2019-11-05 江苏中科君芯科技有限公司 双面肖特基控制的快恢复二极管器件及制备方法
CN113555286A (zh) * 2021-07-05 2021-10-26 浙江芯国半导体有限公司 一种氧化镓超级结肖特基二极管及其制备方法

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