CN110610981A - 功率半导体器件及其形成方法 - Google Patents

功率半导体器件及其形成方法 Download PDF

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Publication number
CN110610981A
CN110610981A CN201910512107.7A CN201910512107A CN110610981A CN 110610981 A CN110610981 A CN 110610981A CN 201910512107 A CN201910512107 A CN 201910512107A CN 110610981 A CN110610981 A CN 110610981A
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trench
layer
pillar
sidewalls
well
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李元华
G·H·勒歇尔特
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Semiconductor Module Industry Corp
Semiconductor Components Industries LLC
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Semiconductor Module Industry Corp
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Abstract

本申请涉及一种功率半导体器件及其形成方法。所述功率半导体器件包括具有第一导电类型的半导体层。沟槽限定在所述半导体层内，所述沟槽具有开口、侧壁和基部。柱设在所述沟槽下方，并且具有与所述第一导电类型不同的第二导电类型。金属层设在所述沟槽的所述侧壁上方，所述金属层在所述沟槽的所述侧壁处接触所述半导体层以形成肖特基二极管的肖特基界面。第一电极设在所述半导体层的第一侧上方。第二电极设在所述半导体层的第二侧上方。

Description

功率半导体器件及其形成方法
相关申请的交叉引用
本公开要求于2018年6月15日提交的美国非临时申请No.16/009,484的优先权，该申请以引用方式并入本文以用于所有目的。
技术领域
本公开涉及功率半导体器件，具体地讲是具有超级结结构和肖特基二极管的功率器件。
背景技术
功率半导体器件用于许多不同的行业。这些行业中的一些行业，诸如电信、计算和收费***，正在迅速地发展。这些行业将受益于改进的半导体器件特性，包括可靠性、开关速度和小型化。
最近在改进功率半导体器件特性方面的努力包括产生与晶体管区分开的肖特基势垒区。单独的肖特基势垒区可以减少泄漏电流并改进反向恢复特性。然而，功率半导体器件的结构仍有改进空间，以通过更低的正向电压(VF)、更快的反向恢复性能和更好的新兴技术可靠性来满足对更高的***效率的需求。
发明内容
本申请的实施方案涉及具有超级结和肖特基二极管的功率半导体器件，其中肖特基二极管集成到功率器件的单位单元中。该器件与常规的功率器件相比具有较低的正向电压(VF)和减少的反向恢复时间。
在一个实施方案中，功率半导体器件包括半导体层，该半导体层具有第一导电类型。沟槽限定在半导体层内，沟槽具有开口、侧壁和基部。柱设在沟槽下方，并且具有与第一导电类型不同的第二导电类型。金属层设在沟槽的侧壁上方，金属层在沟槽的侧壁处接触半导体层以形成肖特基二极管的肖特基界面。第一电极设在半导体层的第一侧上方。第二电极设在半导体层的第二侧上方。
在上述器件的一个实施方案中，该功率半导体器件还包括：栅极电极，该栅极电极设在半导体层上方；阱，该阱具有第二导电类型，并且设在柱上方并与柱间隔开；和间隙，该间隙限定阱与柱之间的距离，该间隙对应于肖特基界面。第一电极设在栅极附近，栅极延伸到沟槽中并电耦接到金属层，并且第二电极设在柱下方。半导体层在第一电极与第二电极之间提供竖直电流路径，并且第一导电性是N型导电性且第二导电性是P型导电性。
在上述器件的一个实施方案中，该功率半导体器件还包括增强区，该增强区在半导体层内并在阱与柱之间。增强区具有第一导电类型和大于半导体层的掺杂浓度的掺杂浓度。
在上述器件的一个实施方案中，沟槽延伸到柱的上部部分中，使得沟槽的基部设在柱内部。功率半导体器件还包括欧姆接触区，该欧姆接触区设在沟槽的基部下方和柱内。
在上述器件的一个实施方案中，该功率半导体器件还包括：阱，该阱具有第二导电类型，并且设在柱上方并与柱间隔开；和间隙，该间隙限定阱与柱之间的距离，该间隙对应于肖特基界面。
在一个实施方案中，功率半导体器件包括衬底，该衬底具有上侧和下侧。第一电极设置在衬底的上侧上方。第二电极设置在衬底的下侧下方。外延层形成在衬底上方和第一电极与第二电极之间，该外延层具有柱和阱，柱和阱限定间隙。沟槽设置在柱上方，具有侧壁和基部，该沟槽的基部凹入柱中。金属接触层设置在沟槽的基部和侧壁上方，该金属接触层在由阱和柱限定的间隙处接触外延层，从而在间隙处限定肖特基界面。
在上述器件的一个实施方案中，该功率半导体器件还包括增强区，该增强区设在阱与柱之间并靠近肖特基界面。该功率半导体器件还包括欧姆接触区，该欧姆接触区设在沟槽下方，使得金属接触层与欧姆接触区形成欧姆接触。
在一个实施方案中，形成功率半导体器件的方法包括：在衬底上方提供外延层；在外延层的上部部分处形成阱；在阱下方形成柱并使其与阱间隔开以限定肖特基接触区；将沟槽蚀刻到外延层中，沟槽具有侧壁和基部，沟槽的侧壁的一部分对应于肖特基接触区；在沟槽的侧壁和基部上方形成金属接触层，金属接触层在肖特基接触区处与外延层形成肖特基界面；以及形成栅极电极和第一电极和第二电极。
在上述方法的一个实施方案中，该方法还包括在沟槽上方形成绝缘层，绝缘层覆盖沟槽的侧壁和基部；蚀刻绝缘层以去除绝缘层的覆盖沟槽的基部的一部分，而留下绝缘层的覆盖沟槽的侧壁的一部分，从而暴露柱的一部分；并且将离子注入到柱的暴露部分以形成欧姆接触区。金属接触层与欧姆接触区形成欧姆接触，并且绝缘层的保留在沟槽的侧壁上的部分用于在注入步骤期间保护沟槽的侧壁免于散射离子。
在上述方法的一个实施方案中，该方法还包括在阱与柱之间并邻近沟槽的侧壁形成增强区。
附图说明
图1A至图1C示出了根据一个实施方案的具有超级结结构和肖特基二极管的功率半导体器件。
图2示出了根据一个实施方案的常规的功率器件与功率器件之间的导通损耗的比较。
图3示出了根据一个实施方案的常规的超级结功率器件与功率器件的体二极管反向恢复电流的比较。
图4A至图4S示出了根据一个实施方案的形成功率半导体器件的方法。
具体实施方式
本申请的实施方案涉及具有超级结和肖特基二极管的功率半导体器件。肖特基二极管集成在功率器件的单位单元中，使得肖特基二极管不会占据比功率器件的单位单元更多的面积。肖特基二极管还在超级结柱与功率器件的源极/发射极之间提供良好的电流路径，以最小化在高电流雪崩下的动态切换问题和重大失效。肖特基二极管还可以被提供有足够的屏蔽，例如，与肖特基接触区(或肖特基界面)相邻的高掺杂区，以减少在反向偏压下的电流泄漏。在一个实施方案中，功率器件被配置为具有低外延电阻率并处理高击穿电压，例如，大于300电压、或大于500电压、或大于700电压。
下面结合附图提供实施方案的详细描述。本公开的范围仅由权利要求书限制并涵盖许多替代、修改和等同物。尽管以给定顺序呈现各种方法的步骤，但是实施方案不必限于以所列顺序执行。在一些实施方案中，某些操作可以以不同于所描述的顺序的顺序同时执行，或根本不执行。
在以下描述中阐述了许多具体细节。提供这些细节是为了通过特定示例促进对本公开的范围的透彻理解，并且可以在没有这些特定细节中的一些的情况下根据权利要求来实践实施方案。因此，本公开的特定实施方案是说明性的，而不旨在是排他性的或限制性的。出于清楚目的，没有详细地描述与本公开相关的技术领域中已知的技术材料，使得不会不必要地模糊本公开。
图1示出了根据本公开的一个实施方案的功率半导体器件100。在本实施方案中，功率器件100是具有超级结结构(或柱)的功率金属氧化物半导体场效应晶体管(MOSFET)器件。在其它实施方案中，功率器件100可以是其它功率器件，诸如绝缘栅双极晶体管(IGBT)器件。如果功率器件100是IGBT，那么它将具有附加的P+衬底或层，如本领域的技术人员将理解。
功率器件100包括半导体衬底102，例如硅衬底。外延层104(或外延层)设在衬底102的第一侧上，并且第一电极106设在衬底102的第二侧上或上方。在一个实施方案中，外延层104具有N型导电性。第二电极108设在外延层104上方。多个栅极结构110设在外延层104上方并靠近第二电极108。当栅极结构110导通时，外延层104为第一电极106和第二电极108提供电流路径。在本实施方案中，功率器件100是功率MOSFET，并且第一电极106和第二电极108分别是漏极电极和源极电极。在另一个实施方案中，功率器件可以是IGBT，并且第一电极106和第二电极108可以分别是集电极电极和发射极电极。
栅极结构110中的每个包括栅极电极112、栅极氧化物114和栅极间隔件116。在外延层中，在栅极结构110之间设有多个阱118。阱118的深度可取决于功率器件100的特性。在一个实施方案中，阱的深度范围在约1微米至约2微米之间，或可以至多5微米。在一个实施方案中，阱118具有P导电性并与外延层104形成体二极管。P阱118的掺杂剂浓度为约1.2×1016个原子/cm3至8.0×1017个原子/cm3。多个N+区120设在P阱118内并靠近栅极电极112。在一个实施方案中，N+区120是源极区。
多个柱122(或超级结结构)设置在外延层104中。每个柱与P阱118间隔开，以限定根据实施方式的1微米至5微米或2微米至3微米的间隙123。该竖直间隙123限定肖特基二极管区，并且其大小可以根据实施方式而变化。在一个实施方案中，柱122具有P型导电性，并且具有约1016个原子/cm3的掺杂剂浓度。在一个实施方案中，柱122具有至少20微米或至少25微米的竖直尺寸。在另一个实施方案中，根据实施方式，柱122可以具有约30微米至约60微米的竖直尺寸。例如，对于600V至650V器件，在实施方式中，柱具有的竖直尺寸为约45微米至50微米。
在一个实施方案中，在由P阱和柱限定的间隙123中设有多个N+增强区124。N+增强区124提供用于减小体二极管的正向电压降并减小在反向偏压下的电流泄漏。在一个实施方案中，N+增强区124以交替图案提供，如图1B所示，其示出了N+增强区124和P阱118的顶视图。在另一个实施方案中，间隙123可以仅存在于存在对应的N+增强区124的地方，而在其它地方不存在，如图1C所示。在该实施方案中，P阱118和P柱122在不存在N+增强区124的区中重叠。在又一个实施方案中，未提供N+增强区124。
多个沟槽126从外延层104的上表面延伸并进入P柱122的上部部分。沟槽126延伸穿过N+源极区120并部分地延伸到P阱118中，使得沟槽的基部或底部位于P柱122中。在一个实施方案中，沟槽126向P柱中延伸约1微米至约8微米。
多个欧姆接触区128设在沟槽126的基部下方。在一个实施方案中，通过向P柱122的上部部分提供附加的P型杂质(例如硼)来形成欧姆接触区128。在一个实施方案中，欧姆接触区128具有比P柱122的掺杂剂浓度显著更高的掺杂剂浓度。例如，P柱具有约1016个原子/cm3的掺杂剂浓度，并且欧姆接触区128具有约1019个原子/cm3的掺杂剂浓度，它的量值是P柱122的掺杂剂浓度的3倍。
肖特基接触层130设在沟槽126的表面上方。肖特基接触层130包括上部部分130a、侧部部分130b和底部部分(或基部)130c。肖特基接触层130的上部部分130a延伸超过沟槽并邻接栅极结构110的侧面。肖特基接触层130的侧部部分130b接触由P阱118和P柱122限定的间隙123，从而限定肖特基接触(肖特基界面)。这些肖特基接触限定肖特基二极管，其中阳极连接到(或对应于)源极电极108，而阴极连接到(或对应于)漏极电极106。肖特基二极管减小功率器件100的正向电压(VF)和反向恢复时间。由于肖特基接触形成在P阱118与P柱122之间，因此肖特基二极管集成到功率器件100的单位单元中。因此，肖特基二极管不占据比功率器件100的单位单元更多的面积。
另外，肖特基接触层130的底部部分130c与欧姆接触区128形成欧姆接触。欧姆接触造成柱122与第二电极108(例如，源极电极)之间的良好的电流路径，这减小了在高电流雪崩条件下的动态切换问题和重大失效的可能性。
形成肖特基二极管的肖特基接触层130可以包括金属材料，例如钼(Mo)、铂(Pt)、钒(V)、钛(Ti)、钯(Pd)等。在另一个实施方案中，肖特基接触层130是硅化物材料，诸如硅化铂或硅化钯。
如上所述，具有肖特基二极管的功率器件100具有某些优点。图2示出了随源极-漏极电压VSD而变的流过两个功率器件的电流的波形：“SJ MOS”表示常规的超级结MOSFET器件，而“具有肖特基二极管的SJ”表示功率器件100。在实验中，已经发现，具有肖特基二极管(或功率器件100)的SJ的源极-漏极电压VSD低于常规的超级结MOSFET的源极-漏极电压VSD，尤其是在低于15A的电流电平下如此。例如，虽然常规的超级结MOSFET在1A处具有0.68V的源极-漏极电压VSD，但是功率器件100的源极-漏极电压VSD在1A处为0.46V，它比常规的超级结MOSFET低约30％。据信，肖特基二极管减小功率器件100的源极-漏极电压VSD，因为肖特基二极管具有比PN二极管更低的正向电压。
类似地，虽然常规的超级结MOSFET在5A处具有0.74V的源极-漏极电压VSD，但是具有竖直肖特基二极管(或功率器件100)的超级结MOSFET在5A处为0.66V，这比常规的超级结MOSFET器件低约11％。功率器件100具有比常规的MOSFET更低的源极-漏极电压VSD，因为功率器件100中的肖特基二极管具有比常规的超级结MOSFET中的PN结二极管更低的正向电压降(例如，0.2V至0.5V对比0.7V)。因此，具有肖特基二极管的功率器件100具有比常规的超级结MOSFET更小的体二极管导通损耗，从而在包括逆变器和DC-DC功率转换的应用中提高功率效率。
图3示出了常规的超级结MOSFET器件中的PN结二极管和超级结MOSFET器件(例如，功率器件100)中的竖直肖特基二极管的体二极管反向恢复电流的波形。竖直肖特基二极管的反向恢复电流显著小于常规的超级结MOSFET器件中的PN结二极管的反向恢复电流。例如，当仅竖直肖特基二极管导通时，功率器件100的竖直肖特基二极管的反向恢复电流在漏极电流值小于6A时可以低至零。因为反向恢复电流在具有感应负载的桥式电路中的MOSFET开关中引起额外损耗，所以当在这种桥式电路中使用具有竖直肖特基二极管的功率器件100时，功率器件100的导通损耗将比常规的超级结MOSFET开关少。另外，可以减少桥式电路中的栅极-源极电压振荡并防止MOSFET发生故障。
图4A至图4S示出了根据本公开的一个实施方案的形成半导体功率器件200的方法的各方面。
在图4A中，在半导体衬底202上方形成半导体层204。可以通过外延生长方法形成层204。在一个实施方案中，衬底202是硅，并且每个外延生长步骤形成具有约2.5微米至3.2微米的外延层。在其它实施方案中，衬底202可以是其它半导体材料，诸如IV族半导体衬底、III-V族化合物半导体衬底或II-VI族氧化物半导体衬底。例如，IV族半导体衬底可以包括硅衬底、锗衬底或硅锗衬底。
衬底202可以包括外延层。在一个实施方案中，衬底202可以是N+掺杂层，其中功率器件是MOSFET。在另一个实施方案中，衬底202可以是P+层，其中功率器件是IGBT。向层204中注入N型杂质(图4B)，以将层204转换成N型导电性。可以执行退火以促进杂质扩散。在一个实施方案中，层204可以形成有N型杂质，使得可以跳过注入步骤。
在层204上方形成半导体层206(图4C)。向层206中注入N型杂质，以得到具有两个N层的结构。接着，在层206上方形成图案化光致抗蚀剂207(图4D)，以暴露层206的选定部分。将P型杂质(或离子)选择性地注入到层206的暴露部分中。层206的这些暴露部分将用于形成柱(参见图1A中的标号122)。P型杂质具有足够的浓度以将暴露部分转换成多个P区208。去除光致抗蚀剂207(图4E)。重复上述步骤(例如，13次至20次)以获得具有多个柱208'的层206'(图4F)。层206'包括多个外延层。在一个实施方案中，柱208'从顶部到基部的总深度(或竖直尺寸)大于20微米，例如，在约30微米至60微米的范围内。可以在将离子注入每个外延层之后执行退火工艺以促进掺杂剂扩散。
接着，在整个结构上方形成半导体层210并使其掺杂有N杂质(图4G)。根据实施方式，层210可以是单个外延层或多个外延层。层210形成为具有2微米至4微米的深度。层210具有足够的深度以形成间隙，在该间隙上随后形成肖特基接触。层210掺杂有N型杂质。形成图案化光致抗蚀剂212以暴露层210的部分。
在一个实施方案中，执行附加的N掺杂以在层210的选定部分处提供更高的N型浓度，从而形成多个N+增强区214(图4H)。N+增强区214对应于图1中的N+增强区124。N+增强区214中的掺杂浓度可以是例如约1.2×1016至5×1017。除其它原因外，形成N+增强区214还为了减少在反向偏压下的电流泄漏。在不存在N+增强区214的情况下不存在P柱208'与随后形成的P阱之间的间隙的情况下(图1C)，P柱208'和随后形成的P阱的重叠可以通过附加的光掩模和注入步骤实现，其中桥接的注入区仅形成在N+增强区214外的区域中。或者，桥接的注入区可以形成在存在N+增强区214的位置处，并且允许N+增强区214对P柱208'进行反掺杂以形成肖特基二极管的所期望的间隙。根据实施方式，可以形成或不形成N+增强区214。
图4I示出了根据一个实施方案的N+增强区214和柱208'的俯视图。N+增强区214的图案可以被描述为在柱208'上方的棋盘图案。换句话说，器件的每个连续的柱208'可以沿其长度具有N+增强区214和N体掺杂区的交替图案，而N+增强区214的图案相对于每个相邻的柱208'偏移。N+增强区214和N体掺杂区的宽度可以相同或类似，使得N+增强区214和N体掺杂区以交替矩阵或棋盘图案设置在柱208'上方。尽管图4I中的N+增强区214的形状是矩形，但是实施方案不限于该特定形状。例如，N+增强区214的形状可以是圆形、六边形或其它形状。
在一个实施方案中，设置在相邻的柱208'上方的N+增强区214相对于图的栅极轴线方向或从上到下方向彼此不重叠(参见图4I)。在其它实施方案中，相邻的柱208'的N+增强区214相对于栅极轴线方向彼此重叠。在又一个实施方案中，N+增强区214中的一个或多个可以在整个P柱210上方延伸。
参见图4J，通过使用上述步骤执行一个或多个外延生长步骤，在N+增强区214上方形成另一个层216。取决于实施方式，层216具有约1微米至3微米的深度，或随具有足够的厚度以随后在其中形成P阱。在层216上方形成栅极氧化物层218。在栅极氧化物层218上方形成栅极电极层220。在一个实施方案中，栅极电极层是N掺杂的多晶硅，但是根据实施方式也可以是其它导电材料。
使用本领域公知的光刻法蚀刻栅极电极层220以形成多个栅极电极220'(图4K)。尽管图4K示出了在相邻的栅极电极220'之间的空间中的完整栅极氧化物层218，但是一些实施方案可以包括去除在栅极电极220'之间提供的栅极氧化物材料。使用栅极电极220'作为掩模将P型掺杂剂注入层216中，以形成多个P阱222。可以执行退火以促进掺杂剂扩散。P阱222形成为与柱208'间隔开，从而提供间隙223。也就是说，在一个实施方案中，P阱222的底部和柱208'的顶部限定间隙223以具有至少1微米的竖直尺寸。在另一个实施方案中，间隙223为2微米至4微米，或2微米至3微米。间隙的大小限定肖特基二极管的肖特基接触(或肖特基截面)，因此其大小可以根据实施方式而变化。
使用栅极电极220'作为掩模将N型杂质选择性地注入P阱222的顶部中(图4L)。或者，可以使用光致抗蚀剂掩模来图案化注入物。控制N掺杂以产生多个N+区224。在一个实施方案中，N+区是源极区。
参见图4M，在栅极电极220'和N+源极区224上方形成栅极介电层(未示出)。可以通过在器件的上表面上方沉积一个或多个介电层来形成栅极介电层。介电层可以包括氮化物层、氧化物层或其它介电材料。在一个实施方案中，介电层是氮化物层。选择性地蚀刻介电层以去除介电材料的设置在栅极电极220'之间部分，从而产生多个栅极间隔件226。栅极间隔件226限定多个栅极结构228。栅极结构228包括栅极氧化物218'、栅极电极220'和栅极间隔件226。
多个沟槽230形成在柱208'上方并延伸穿过P阱222(图4N)。使用已知的光刻和各向异性蚀刻工艺形成沟槽。在一个实施方案中，沟槽230向柱208'中延伸1微米至8微米。
在沟槽230上方形成氧化物层232(图4O)。氧化物层232可以使用沉积工艺或热氧化工艺形成，并且可以具有50埃至600埃的厚度。在一个实施方案中，氧化物层232整体地形成在整个结构上方，包括在栅极结构228上方。在氧化物层232上方形成氮化物层234。在一个实施方案中，氮化物层234具有的厚度为1000埃至2500埃。
执行各向异性蚀刻以暴露柱208'(图4P)。蚀刻去除氮化物层234和氧化物层232的水平暴露部分，包括设置在沟槽230的底表面上方的氮化物层234和氧化物层232的底部部分。然而，氮化物层234和氧化物层232保留在沟槽230的侧壁和栅极结构228上。在一些实施方案中，氧化物层232的薄的部分可以保留在沟槽230的底表面处。剩余的氮化物层和氧化物层用作侧壁间隔件236，其保护沟槽的侧壁免受随后的注入步骤，这将在下面说明。在一个实施方案中，在各向异性蚀刻之前在栅极结构228上方形成光致抗蚀剂掩膜以保护栅极结构。
执行离子注入步骤以在沟槽230的底部形成欧姆接触区238(图4Q)，其中通过上述各向异性蚀刻暴露柱208'的部分。在一个实施方案中，欧姆接触区掺杂有P型掺杂剂达至少1019个原子/cm3的浓度。欧姆接触区238具有比柱208'体高得多的导电率，柱208'具有约1016个原子/cm3的浓度。
侧壁间隔件236保护沟槽230的侧壁免受在注入步骤期间可能散射的离子(或掺杂剂)。在一个实施方案中，相对低的注入能量，诸如3keV至25keV，可以用于注入步骤，使得散射离子将不具有足够的能量来穿透间隔件236并注入沟槽230的侧壁中。此外，如果需要，可以使用较重的注入物质诸如BF2代替硼以减小注入的预计范围。另选地，可以增加间隔件236的厚度以防止散射离子穿透沟槽230的侧壁。或者，可以调整注入能量和间隔件236的厚度两者以防止散射离子渗透到沟槽230的侧壁中。如果将P型掺杂剂注入沟槽的侧壁中，那么这些掺杂剂可以稀释随后将进行肖特基接触的侧壁的N型导电性，这将降低肖特基二极管的性能。
在离子注入步骤之后，去除保留在栅极结构228和沟槽230上的氮化物层234和氧化物层232(图4R)。在一个实施方案中，使用湿法蚀刻步骤去除氮化物层234和氧化物层232。选择湿法蚀刻以溶解在氮化物层下面的氧化物层232。因此，将氮化物层从结构抬离。在这样的实施方案中，使用氮化物层形成栅极间隔件226以保护栅极结构。
肖特基接触层240形成在沟槽230的暴露表面上方(图4R)。肖特基接触层240可以通过掩蔽和选择性地形成诸如钼(Mo)、铂(Pt)、钒(V)、钛(Ti)、钯(Pd)等的肖特基金属材料来形成。在一个实施方案中，通过形成硅化物材料诸如硅化铂或硅化钯来形成肖特基接触层。肖特基接触层240也可以是金属材料和硅化物材料的组合。在一个实施方案中，肖特基接触层240共形地形成在沟槽230的表面上。在一个实施方案中，尽管未示出，但是可以在肖特基材料层的表面上方形成诸如氮化钛的阻挡金属材料。肖特基接触层240在由P阱222和P柱208'限定的间隙223处形成肖特基接触，以形成肖特基二极管。肖特基接触层240的底部部分与欧姆接触区238形成欧姆接触。该欧姆接触有助于电流从中流过。
通过在衬底202上方沉积诸如铝的导电材料来形成第一电极242。在一个实施方案中，第一电极242是漏极电极(图4S)。通过在栅极结构228上方沉积诸如铝的导电材料并将其沉积到沟槽230中来形成第二电极244。在一个实施方案中，第二电极是源极电极。所得到的器件是功率半导体器件200，其对应于图1中的功率器件100。根据实施方式，功率器件200可以是功率MOSFET、IGBT等。
A1。本公开的实施方案包括功率半导体器件，包括：
半导体层，该半导体层具有第一导电类型；
沟槽，该沟槽限定在半导体层内，该沟槽具有开口、侧壁和基部；
柱，该柱设在沟槽下方，并且具有与第一导电类型不同的第二导电类型；
金属层，该金属层设在沟槽的侧壁上方，该金属层在沟槽的侧壁处接触半导体层以形成肖特基二极管的肖特基界面；
第一电极，该第一电极设在半导体层的第一侧上方；和
第二电极，该第二电极设在半导体层的第二侧上方。
A2。A1的器件，其中半导体层在第一电极与第二电极之间提供竖直电流路径，并且第一电极用作肖特基二极管的阳极，而第二电极用作肖特基二极管的阴极，并且
其中半导体层是形成在衬底上方的外延层。
A3。A2的器件，其中衬底包括外延层。
A4。A3的器件，其中功率器件是MOSFET，并且第一电极和第二电极分别是源极电极和漏极电极，并且柱是具有的深度为至少25微米的超级结柱。
A5。A4的器件，其中沟槽延伸到柱的上部部分中，使得沟槽的基部设在柱内部。
A6。本公开的实施方案包括功率半导体器件，包括：
衬底，该衬底具有上侧和下侧；
第一电极，该第一电极设置在衬底的上侧上方；
第二电极，该第二电极设置在衬底的下侧下方；
外延层，该外延层形成在衬底上方和第一电极与第二电极之间，该外延层具有柱和阱，柱和阱限定间隙；
沟槽，该沟槽设置在柱上方，具有侧壁和基部，该沟槽的基部凹入柱中；和
金属接触层，金属接触层设置在沟槽的基部和侧壁上方，金属接触层在由柱和阱限定的间隙处接触外延层，从而在间隙处限定肖特基界面。
A7。A6的器件，还包括：
欧姆接触区，该欧姆接触区设在沟槽下方，使得金属接触层与欧姆接触区形成欧姆接触，
其中肖特基二极管由外延层和金属接触层限定，并且
其中第一电极对应于肖特基二极管的阳极，并且第二电极对应于肖特基二极管的阴极。
A8。A6的器件，其中功率半导体器件是MOSFET。
A9。A6的器件，其中功率半导体器件是IGBT。
A10。本公开的实施方案包括用于形成功率半导体器件的方法，该方法包括：
在衬底上方提供外延层；
在外延层的上部部分处形成阱；
在阱下方形成柱并使其与阱间隔开以限定肖特基接触区；
将沟槽蚀刻到外延层中，该沟槽具有侧壁和基部，该沟槽的侧壁的一部分对应于肖特基接触区；
在沟槽的侧壁和基部上方形成金属接触层，该金属接触层在肖特基接触区处与外延层形成肖特基界面；以及
形成栅极电极和第一电极和第二电极。
A11。A10的方法，还包括：
在沟槽上方形成绝缘层，绝缘层覆盖沟槽的侧壁和基部；
蚀刻绝缘层以去除绝缘层的覆盖沟槽的基部的一部分，而留下绝缘层的覆盖沟槽的侧壁的一部分，从而暴露柱的一部分；并且
将离子注入到柱的暴露部分以形成欧姆接触区，
其中金属接触层与欧姆接触区形成欧姆接触，并且绝缘层的保留在沟槽的侧壁上的部分用于在注入步骤期间保护沟槽的侧壁免于散射离子。
A12。A11的方法，还包括：
在阱与柱之间并邻近沟槽的侧壁形成增强区。
A13。A12的方法，其中功率半导体器件是MOSEFT，并且柱是超级结柱。
A14。A11的方法，其中离子以不足以穿透保留在沟槽的侧壁上的绝缘层的能级注入。
已经与作为示例提出的具体实施方案一起描述了本公开的各方面。在不脱离下文所述的权利要求的范围的情况下，可以对本文所述的实施方案进行多种替换、修改和变化。例如，在另一个实施方案中，P柱可以通过如下方法形成：包括形成交替的外延半导体层和阻挡层，将杂质注入阻挡层中，并且将杂质从阻挡层扩散到外延半导体层中，如美国申请No.15/454,861所述，该申请以引用方式并入。或者，P柱可以通过完全不同的方法形成，诸如蚀刻深沟槽，在沟槽中掺入P型掺杂剂，并且用诸如单晶硅的一些材料填充沟槽。此外，掺入P型掺杂剂的方法可以包括掺杂的外延硅在深沟槽内的生长、成角度的离子注入、等离子体离子掺杂、从固体源的扩散、原子层沉积或一些其它掺杂技术。类似地，尽管在前面的实施方案中使用平面栅极结构，但是其它类型的栅极结构也是可能的。具体地，可以使用沟槽栅极结构代替平面栅极结构。因此，本文所述的实施方案旨在是说明性的而非限制性的。

Claims (10)

1.一种功率半导体器件，包括：
半导体层，所述半导体层具有第一导电类型；
沟槽，所述沟槽限定在所述半导体层内，所述沟槽具有开口、侧壁和基部；
柱，所述柱设在所述沟槽下方，并且具有与所述第一导电类型不同的第二导电类型；
金属层，所述金属层设在所述沟槽的所述侧壁上方，所述金属层在所述沟槽的所述侧壁处接触所述半导体层以形成肖特基二极管的肖特基界面；
第一电极，所述第一电极设在所述半导体层的第一侧上方；和
第二电极，所述第二电极设在所述半导体层的第二侧上方。
2.根据权利要求1所述的功率半导体器件，还包括：
栅极电极，所述栅极电极设在所述半导体层上方；
阱，所述阱具有所述第二导电类型，并且设在所述柱上方并与所述柱间隔开；和
间隙，所述间隙限定所述阱与所述柱之间的距离，所述间隙对应于所述肖特基界面，
其中所述第一电极设在所述栅极附近，所述栅极延伸到所述沟槽中并电耦接到所述金属层，并且所述第二电极设在所述柱下方，并且
其中所述半导体层在所述第一电极与所述第二电极之间提供竖直电流路径，并且第一导电性是N型导电性且第二导电性是P型导电性。
3.根据权利要求2所述的功率半导体器件，还包括：
增强区，所述增强区在所述半导体层内并在所述阱与所述柱之间，所述增强区具有所述第一导电类型和大于所述半导体层的掺杂浓度的掺杂浓度。
4.根据权利要求2所述的功率半导体器件，其中所述沟槽延伸到所述柱的上部部分中，使得所述沟槽的所述基部设在所述柱内部，其中所述功率半导体器件还包括：
欧姆接触区，所述欧姆接触区设在所述沟槽的所述基部下方和所述柱内。
5.根据权利要求1所述的功率半导体器件，还包括：
阱，所述阱具有第二导电类型，并且设在所述柱上方并与所述柱间隔开；和
间隙，所述间隙限定所述阱与所述柱之间的距离，所述间隙对应于所述肖特基界面。
6.一种功率半导体器件，包括：
衬底，所述衬底具有上侧和下侧；
第一电极，所述第一电极设置在所述衬底的所述上侧上方；
第二电极，所述第二电极设置在所述衬底的所述下侧下方；
外延层，所述外延层形成在所述衬底上方以及所述第一电极与所述第二电极之间，所述外延层具有柱和阱，所述柱和所述阱限定间隙；
沟槽，所述沟槽设置在所述柱上方，具有侧壁和基部，所述沟槽的所述基部凹入所述柱中；和
金属接触层，所述金属接触层设置在所述沟槽的所述基部和所述侧壁上方，所述金属接触层在由所述柱和所述阱限定的所述间隙处接触所述外延层，从而在所述间隙处限定肖特基界面。
7.根据权利要求6所述的功率半导体器件，还包括：
增强区，所述增强区设在所述阱与所述柱之间并靠近所述肖特基界面；和
欧姆接触区，所述欧姆接触区设在所述沟槽下方，使得所述金属接触层与所述欧姆接触区形成欧姆接触。
8.一种形成功率半导体器件的方法，所述方法包括：
在衬底上方提供外延层；
在所述外延层的上部部分处形成阱；
在所述阱下方形成柱并使其与所述阱间隔开以限定肖特基接触区；
将沟槽蚀刻到所述外延层中，所述沟槽具有侧壁和基部，所述沟槽的所述侧壁的一部分对应于所述肖特基接触区；
在所述沟槽的所述侧壁和所述基部上方形成金属接触层，所述金属接触层在所述肖特基接触区处与所述外延层形成肖特基界面；以及
形成栅极电极和第一电极和第二电极。
9.根据权利要求8所述的方法，还包括：
在所述沟槽上方形成绝缘层，所述绝缘层覆盖所述沟槽的所述侧壁和所述基部；
蚀刻所述绝缘层以去除所述绝缘层的覆盖所述沟槽的所述基部的一部分，而留下所述绝缘层的覆盖所述沟槽的所述侧壁的一部分，从而暴露所述柱的一部分；并且
将离子注入到所述柱的所述暴露部分以形成欧姆接触区，
其中所述金属接触层与所述欧姆接触区形成欧姆接触，并且所述绝缘层的保留在所述沟槽的所述侧壁上的所述部分用于在所述注入步骤期间保护所述沟槽的所述侧壁免于散射离子。
10.根据权利要求9所述的方法，还包括：
在所述阱与所述柱之间并邻近所述沟槽的所述侧壁形成增强区。
CN201910512107.7A 2018-06-15 2019-06-13 功率半导体器件及其形成方法 Pending CN110610981A (zh)

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