WO2023097857A1 - 带隙基准电压电路及带隙基准电压的补偿方法 - Google Patents

带隙基准电压电路及带隙基准电压的补偿方法 Download PDF

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WO2023097857A1
WO2023097857A1 PCT/CN2021/143487 CN2021143487W WO2023097857A1 WO 2023097857 A1 WO2023097857 A1 WO 2023097857A1 CN 2021143487 W CN2021143487 W CN 2021143487W WO 2023097857 A1 WO2023097857 A1 WO 2023097857A1
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transistor
npn bipolar
bipolar transistor
drain
current
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PCT/CN2021/143487
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English (en)
French (fr)
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胡蓉彬
朱璨
王健安
陈光炳
付东兵
张正平
俞宙
杨治美
龚敏
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重庆吉芯科技有限公司
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Publication of WO2023097857A1 publication Critical patent/WO2023097857A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Definitions

  • the invention relates to the technical field of integrated circuits, in particular to a bandgap reference voltage circuit and a compensation method for the bandgap reference voltage.
  • the reference voltage source is a high-precision, high-stability voltage source, which is widely used in various analog and digital-analog hybrid integrated circuits.
  • the reference voltage source is mainly generated by a reference voltage generating circuit.
  • the existing temperature-independent common reference voltage generating circuits include: one is to form a temperature-stable reference voltage based on the difference between the turn-on voltages of the enhancement-mode NMOS and the depletion-mode NMOS.
  • the second is based on the breakdown voltage of the Zener diode made of NPN reverse breakdown BE structure, this method is not suitable for low power supply voltage applications due to the high breakdown voltage;
  • the third is based on The first-order bandgap reference circuit in which the positive temperature coefficient of the equivalent thermal voltage and the negative temperature coefficient of the BE junction voltage of the bipolar transistor compensate each other. This circuit can better solve the problems existing in the first two reference voltage generation circuits, but this The temperature coefficient of the first-order bandgap reference circuit is still high after the first-order compensation, and is not suitable for occasions with large temperature changes.
  • a high-precision A/D converter requires a high-precision reference voltage, and often the bandgap reference voltage of the first-order temperature compensation cannot meet the requirements, and curvature (second-order) compensation is required.
  • curvature (second-order) compensation is required.
  • most of the existing curvature compensation technologies remain at the theoretical or model stage, and few are practical.
  • the purpose of the present invention is to provide a technical solution for second-order temperature compensation of the bandgap reference voltage, so as to quickly and effectively realize the second-order temperature compensation of the bandgap reference voltage.
  • a bandgap reference voltage circuit comprising:
  • a first-order temperature compensated bandgap reference unit which outputs a bandgap reference voltage with first-order temperature compensation
  • the second-order temperature compensation unit is connected to the first-order temperature-compensated bandgap reference unit, and outputs a compensation current with a second-order positive temperature coefficient to the first-order temperature-compensated bandgap reference unit, and performs a second-order correction on the bandgap reference voltage. Temperature compensation.
  • the first-order temperature compensation bandgap reference unit includes a first NPN bipolar transistor, a second NPN bipolar transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and an operational amplifier
  • the output terminal of the operational amplifier is connected to the collector of the first NPN bipolar transistor after the first resistor connected in series
  • the collector of the first NPN bipolar transistor is connected to the base of the first NPN bipolar transistor
  • the emitter of the first NPN bipolar transistor is grounded after the second resistor connected in series
  • the output terminal of the operational amplifier is also connected to the second NPN bipolar transistor through the third resistor connected in series collector
  • the collector of the second NPN bipolar transistor is connected to the base of the second NPN bipolar transistor
  • the emitter of the second NPN bipolar transistor is connected to the fourth resistor connected in series
  • the emitter of the first NPN bipolar transistor, the collector of the first NPN bipolar transistor is connected to the non-inverting input terminal of the operational amplifier
  • the second-order temperature compensation unit includes a first current generation module, a second current generation module, a third current generation module, a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, and The fifth current mirror, the output end of the first current generation module is connected to the input end of the first current mirror, the output end of the first current mirror is connected to the bias input end of the second current generation module,
  • the output terminal of the second current generating module is connected to the input terminal of the second current mirror, the output terminal of the second current mirror is connected to the input terminal of the third current mirror, and the output terminal of the third current mirror connected to the first input terminal of the third current generation module, the input terminal of the fourth current mirror is connected to the output terminal of the first current generation module, and the output terminal of the fourth current mirror is connected to the third current mirror
  • the second input terminal of the generating module, the third input terminal of the third current generating module is connected to the working voltage, the output terminal of the third current generating module is connected to the input terminal of the fifth
  • the first current generating module is a positive temperature coefficient current generating module, which includes a third NPN bipolar transistor, a fourth NPN bipolar transistor, a fifth NPN bipolar transistor, a sixth NPN bipolar transistor, a sixth NPN bipolar transistor, Five resistors and a sixth resistor, the working voltage is connected to the collector of the third NPN bipolar transistor after the fifth resistor connected in series, and the collector of the third NPN bipolar transistor is connected to the third NPN bipolar transistor The base of the NPN bipolar transistor, the emitter of the third NPN bipolar transistor is connected to the collector of the fourth NPN bipolar transistor, the emitter of the fourth NPN bipolar transistor is grounded, and the fifth NPN The base of the bipolar transistor is connected to the base of the third NPN bipolar transistor, the emitter of the fifth NPN bipolar transistor is connected to the collector of the sixth NPN bipolar transistor, and the fifth NPN bipolar transistor The emitter of the transistor is also connected to the base of the fourth NPN bipolar transistor, the base, the
  • the first current mirror includes a first PMOS transistor and a second PMOS transistor, the source of the first PMOS transistor is connected to the operating voltage, and the gate of the first PMOS transistor is connected to the first PMOS transistor.
  • the drain of the PMOS transistor, the drain of the first PMOS transistor is connected to the collector of the fifth NPN bipolar transistor, the source of the second PMOS transistor is connected to the operating voltage, and the drain of the second PMOS transistor is connected to the collector of the fifth NPN bipolar transistor.
  • the gate is connected to the gate of the first PMOS transistor, wherein the drain of the first PMOS transistor is the input terminal of the first current mirror, and the drain of the second PMOS transistor is the input terminal of the first current mirror. output.
  • the second current generation module is a negative temperature coefficient current generation module, which includes a seventh NPN bipolar transistor, a first NMOS transistor, and a seventh resistor, and the collector of the seventh NPN bipolar transistor is connected to the The drain of the second PMOS transistor, the emitter of the seventh NPN bipolar transistor is grounded, the gate of the first NMOS transistor is connected to the drain of the second PMOS transistor, and the source of the first NMOS transistor The pole is grounded after the seventh resistor connected in series, and the source of the first NMOS transistor is also connected to the base of the seventh NPN bipolar transistor, wherein the gate of the first NMOS transistor is the first The bias input end of the second current generation module, the drain of the first NMOS transistor is the output end of the second current generation module.
  • the second current mirror includes a third PMOS transistor and a fourth PMOS transistor, the source of the third PMOS transistor is connected to the operating voltage, and the gate of the third PMOS transistor is connected to the third PMOS transistor.
  • the drain of the PMOS transistor, the drain of the third PMOS transistor is connected to the drain of the first NMOS transistor, the source of the fourth PMOS transistor is connected to the operating voltage, and the gate of the fourth PMOS transistor connected to the gate of the third PMOS transistor, wherein the drain of the third PMOS transistor is the input end of the second current mirror, and the drain of the fourth PMOS transistor is the output end of the second current mirror .
  • the third current mirror includes a second NMOS transistor and a third NMOS transistor, the drain of the second NMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the second NMOS transistor connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is grounded, the gate of the third NMOS transistor is connected to the gate of the second NMOS transistor, and the source of the third NMOS transistor
  • the drain of the second NMOS transistor is the input end of the third current mirror, and the drain of the third NMOS transistor is the output end of the third current mirror.
  • the third current generating module includes a fourth NMOS transistor, a fifth NMOS transistor, an eighth NPN bipolar transistor, a ninth NPN bipolar transistor, and a tenth NPN bipolar transistor, and the fourth NMOS transistor
  • the drain is connected to the operating voltage
  • the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor
  • the source of the fourth NMOS transistor is connected to the collector of the eighth NPN bipolar transistor
  • the emitter of the eighth NPN bipolar transistor is grounded
  • the drain of the fifth NMOS transistor is connected to the gate of the fifth NMOS transistor
  • the gate of the fifth NMOS transistor is also connected to the fourth NMOS transistor
  • the gate of the transistor, the source of the fifth NMOS transistor is connected to the collector of the ninth NPN bipolar transistor, and the collector of the ninth NPN bipolar transistor is connected to the base of the ninth NPN bipolar transistor
  • the base of the ninth NPN bipolar transistor is also connected to the base of the eighth NPN bi
  • the fourth current mirror includes the first PMOS transistor and a fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the operating voltage, and the gate of the fifth PMOS transistor is connected to the The gate of the first PMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, wherein the drain of the first PMOS transistor is the input terminal of the fourth current mirror, so The drain of the fifth PMOS transistor is the output terminal of the fourth current mirror.
  • the fifth current mirror includes a sixth PMOS transistor and a seventh PMOS transistor, the source of the sixth PMOS transistor is connected to the operating voltage, and the gate of the sixth PMOS transistor is connected to the sixth PMOS transistor.
  • the drain of the PMOS transistor, the drain of the sixth PMOS transistor is connected to the collector of the tenth NPN bipolar transistor, the source of the seventh PMOS transistor is connected to the operating voltage, and the drain of the seventh PMOS transistor is connected to the collector of the tenth NPN bipolar transistor.
  • the gate is connected to the gate of the sixth PMOS transistor, wherein the drain of the sixth PMOS transistor is the input terminal of the fifth current mirror, and the drain of the seventh PMOS transistor is the input terminal of the fifth current mirror. output.
  • the third resistor includes a digitally adjustable resistor
  • the seventh PMOS transistor includes a digitally adjustable PMOS transistor.
  • a compensation method for a bandgap reference voltage comprising the steps of:
  • a compensation current with a second-order positive temperature coefficient is generated by using a positive temperature coefficient current and a negative temperature coefficient current;
  • second-order temperature compensation is performed on the bandgap reference voltage.
  • the bandgap reference voltage circuit and the compensation method of the bandgap reference voltage of the present invention have at least the following beneficial effects:
  • the bandgap reference voltage with first-order temperature compensation is generated through the first-order temperature compensation bandgap reference unit, and the compensation current with second-order positive temperature coefficient is generated through the second-order temperature compensation unit, and then the compensation current with second-order positive temperature coefficient is applied To the bandgap reference voltage, the second-order temperature compensation of the output bandgap reference voltage is effectively realized.
  • FIG. 1 is a schematic structural diagram of a bandgap reference voltage circuit in Embodiment 1 of the present invention.
  • Figure 2 shows the temperature curve of the bandgap reference voltage after the first-order temperature compensation in Figure 1 .
  • FIG. 3 is a circuit diagram of the second-order temperature compensation unit 2 in FIG. 1 .
  • Figure 4 shows the temperature curve of the bandgap reference voltage after the second-order temperature compensation in Figure 1 .
  • FIG. 5 is a schematic structural diagram of a bandgap reference voltage circuit in Embodiment 2 of the present invention.
  • FIG. 6 is a circuit diagram of the second-order temperature compensation unit 2 in FIG. 5 .
  • the bandgap reference voltage of the first-order temperature compensation cannot meet the requirements more and more, and there is an urgent need to use the bandgap reference voltage of the second-order temperature compensation Reference voltage; while most of the existing second-order compensation technologies stay at the theoretical or model stage, and few are practical.
  • the present invention proposes a second-order temperature compensation technical solution for the bandgap reference voltage: on the basis of generating a bandgap reference voltage with first-order temperature compensation, a current with a positive temperature coefficient and a current with a negative temperature coefficient are used to generate The second-order positive temperature coefficient compensation current is used to perform second-order temperature compensation on the bandgap reference voltage.
  • an embodiment of the present invention provides a bandgap reference voltage circuit, which includes:
  • a first-order temperature compensated bandgap reference unit 1 which outputs a bandgap reference voltage V ref with first-order temperature compensation
  • the second-order temperature compensation unit 2 is connected to the first-order temperature-compensated bandgap reference unit 1, and outputs a compensation current I 3 with a second-order positive temperature coefficient to the first-order temperature-compensated bandgap reference unit 1, and conducts secondary calculation of the bandgap reference voltage V ref stage temperature compensation.
  • the first-order temperature-compensated bandgap reference unit 1 includes a first NPN bipolar transistor Q 1 , a second NPN bipolar transistor Q 2 , a first resistor R 1 , a second resistor R 2 , a first Three resistors R 3 , the fourth resistor R 4 and operational amplifier A, the output terminal of operational amplifier A is connected to the collector of the first NPN bipolar transistor Q 1 after the first resistor R 1 connected in series, and the collector of the first NPN bipolar transistor The collector of Q 1 is connected to the base of the first NPN bipolar transistor Q 1 , the emitter of the first NPN bipolar transistor Q 1 is connected to the ground through the second resistor R 2 in series, and the output terminal of the operational amplifier A is also connected to the second resistor R 2 in series.
  • the three resistors R3 are connected to the collector of the second NPN bipolar transistor Q2 , the collector of the second NPN bipolar transistor Q2 is connected to the base of the second NPN bipolar transistor Q2 , and the second NPN bipolar transistor Q2
  • the emitter of the first NPN bipolar transistor Q1 is connected to the emitter of the first NPN bipolar transistor Q1 through the fourth resistor R4 connected in series, the collector of the first NPN bipolar transistor Q1 is connected to the non-inverting input terminal of the operational amplifier A, and the second NPN bipolar transistor Q1
  • the collector of the transistor Q 2 is connected to the inverting input terminal of the operational amplifier A, and the output terminal of the operational amplifier A outputs the bandgap reference voltage V ref .
  • the ratio of the emitter junction area of the first NPN bipolar transistor Q 1 to the second NPN bipolar transistor Q 2 is 1:n 1 , and the first NPN bipolar transistor Q 1 and the second NPN bipolar transistor Q 1
  • the NPN bipolar transistor Q 2 is a diode connection mode, and the operational amplifier A makes the voltage drop on the first resistor R 1 and the third resistor R 3 equal, so the current I 1 flowing through the first resistor R 1 is the same as the current I 1 flowing through the second resistor R 1
  • the current I 2 of the three resistors R 3 has the following relationship:
  • V be1 V be2 +I 2 R 4 (2)
  • V be1 and V be2 are the base-emitter junction voltage drops of the first NPN bipolar transistor Q1 and the second NPN bipolar transistor Q2 respectively. According to the bipolar transistor current-voltage relationship and formula (2):
  • k is the Boltzmann constant
  • T is the absolute temperature
  • q is the electronic charge
  • I s1 and I s2 are the reverse saturation currents of the first NPN bipolar transistor Q1 and the second NPN bipolar transistor Q2 , respectively ;
  • the reverse saturation current is proportional to the emitter junction area of the bipolar transistor, and the ratio of the emitter junction area of the first NPN bipolar transistor Q1 to the second NPN bipolar transistor Q2 is 1: n1 , combined with formula (1), we can get from formula (4)
  • V ref V be1 +I 1 R 1 +(I 1 +I 2 )R 2 +I 3 R 2 (6)
  • V be10 is the base-emitter junction voltage of the first NPN bipolar transistor Q1 at room temperature
  • T 0 is the absolute temperature at room temperature
  • b is the first-order temperature coefficient of V be10
  • a is the second-order temperature coefficient of V be10 .
  • the first term, the third term, the fourth term and the fifth term on the right side of the formula (11) are all temperature-independent constants, which can be adjusted by adjusting the first resistance R 1 , the third resistance R 3 and the fourth resistance R 4 of the circuit
  • the resistance value is used to realize the mutual cancellation of the first item, the third item, the fourth item and the fifth item, so as to realize the first-order compensation of the reference temperature curve.
  • the temperature curve of the bandgap reference voltage after the first-order temperature compensation is shown in Figure 2 Show.
  • the first term on the right side of (12) is the second-order temperature coefficient of V be10 , which determines the curvature of the parabola in Figure 2, and ultimately determines the temperature performance of the bandgap reference voltage after first-order temperature compensation.
  • first-order temperature compensation is often not sufficient. Therefore, we use the last two terms on the right side of (12) to partially compensate the first term to improve the temperature performance of the bandgap reference voltage after the first-order temperature compensation.
  • the compensation current I 3 of the last item on the right side of the formula (12) is generated by the second-order temperature compensation unit 2 shown in FIG. 3 .
  • the second-order temperature compensation unit 2 includes a first current generating module, a second current generating module, a third current generating module, a first current mirror, a second current mirror, a third current mirror, a Four current mirrors and the fifth current mirror, the output end of the first current generation module is connected to the input end of the first current mirror, the output end of the first current mirror is connected to the bias input end of the second current generation module, and the second current generation module
  • the output terminal of the module is connected to the input terminal of the second current mirror, the output terminal of the second current mirror is connected to the input terminal of the third current mirror, the output terminal of the third current mirror is connected to the first input terminal of the third current generation module, and the fourth The input terminal of the current mirror is connected to the output terminal of the first current generating module, the output terminal of the fourth current mirror is connected to the second input terminal of the third current generating module, and the third input terminal of the third current generating module is connected to the working voltage V CC ,
  • the first current generating module is a positive temperature coefficient current generating module, which includes a third NPN bipolar transistor Q 3 , a fourth NPN bipolar transistor Q 4 , a fifth NPN bipolar transistor Q 5.
  • the sixth NPN bipolar transistor Q 6 , the fifth resistor R 5 and the sixth resistor R 6 , the operating voltage V CC is connected to the collector of the third NPN bipolar transistor Q 3 after being connected in series with the fifth resistor R 5 ,
  • the collector of the third NPN bipolar transistor Q3 is connected to the base of the third NPN bipolar transistor Q3
  • the emitter of the third NPN bipolar transistor Q3 is connected to the collector of the fourth NPN bipolar transistor Q4 .
  • the emitter of the NPN bipolar transistor Q4 is grounded, the base of the fifth NPN bipolar transistor Q5 is connected to the base of the third NPN bipolar transistor Q3 , and the emitter of the fifth NPN bipolar transistor Q3 is connected to the sixth NPN
  • the collector of the bipolar transistor Q6 , the emitter of the fifth NPN bipolar transistor Q5 is also connected to the base of the fourth NPN bipolar transistor Q4 , the base of the sixth NPN bipolar transistor Q6 is connected to the third NPN bipolar transistor
  • the emitter of the polar transistor Q3 , the emitter of the sixth NPN bipolar transistor Q6 is grounded after the sixth resistor R6 connected in series, wherein the collector of the fifth NPN bipolar transistor Q5 is the first current generating module output terminal.
  • the first current mirror includes a first PMOS transistor P 1 and a second PMOS transistor P 2 , the source of the first PMOS transistor P 1 is connected to the working voltage V CC , and the first PMOS transistor P 1
  • the gate of the first PMOS transistor P1 is connected to the drain of the first PMOS transistor P1
  • the drain of the first PMOS transistor P1 is connected to the collector of the fifth NPN bipolar transistor Q5
  • the source of the second PMOS transistor P2 is connected to the operating voltage V CC
  • the gate of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1
  • the drain of the first PMOS transistor P1 is the input terminal of the first current mirror
  • the drain of the second PMOS transistor P2 is the first current mirror. output terminal of a current mirror.
  • the second current generating module is a negative temperature coefficient current generating module, which includes a seventh NPN bipolar transistor Q 7 , a first NMOS transistor N 1 and a seventh resistor R 7 , and the seventh NPN
  • the collector of the bipolar transistor Q7 is connected to the drain of the second PMOS transistor P2
  • the emitter of the seventh NPN bipolar transistor Q7 is connected to the ground
  • the gate of the first NMOS transistor N1 is connected to the drain of the second PMOS transistor P2 pole
  • the source of the first NMOS transistor N1 is grounded through the seventh resistor R7 connected in series
  • the source of the first NMOS transistor N1 is also connected to the base of the seventh NPN bipolar transistor Q7 , wherein the first The gate of the NMOS transistor N1 is the bias input terminal of the second current generating module, and the drain of the first NMOS transistor N1 is the output terminal of the second current generating module.
  • the second current mirror includes a third PMOS transistor P 3 and a fourth PMOS transistor P 4 , the source of the third PMOS transistor P 3 is connected to the working voltage V CC , and the third PMOS transistor P 3
  • the gate of the third PMOS transistor P3 is connected to the drain of the third PMOS transistor P3
  • the drain of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1
  • the source of the fourth PMOS transistor P4 is connected to the working voltage V CC
  • the drain of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1.
  • the gates of the four PMOS transistors P4 are connected to the gates of the third PMOS transistor P3 , wherein the drain of the third PMOS transistor P3 is the input terminal of the second current mirror, and the drain of the fourth PMOS transistor P4 is the second current mirror. mirror output.
  • the third current mirror includes a second NMOS transistor N2 and a third NMOS transistor N3 .
  • the drain of the second NMOS transistor N2 is connected to the drain of the fourth PMOS transistor P4 .
  • the gate of the second NMOS transistor N2 is connected to the drain of the second NMOS transistor N2
  • the source of the second NMOS transistor N2 is grounded
  • the gate of the third NMOS transistor N3 is connected to the gate of the second NMOS transistor N2
  • the source of the third NMOS transistor N3 is grounded, wherein the drain of the second NMOS transistor N2 is the input end of the third current mirror, and the drain of the third NMOS transistor N3 is the output end of the third current mirror.
  • the third current generating module includes a fourth NMOS transistor N 4 , a fifth NMOS transistor N 5 , an eighth NPN bipolar transistor Q 8 , a ninth NPN bipolar transistor Q 9 and a tenth NPN transistor.
  • the drain of the fourth NMOS transistor N 4 is connected to the working voltage V CC
  • the source of the fourth NMOS transistor N 4 is connected to the drain of the third NMOS transistor N 3
  • the source of the fourth NMOS transistor N 4 is pole is also connected to the collector of the eighth NPN bipolar transistor Q8
  • the emitter of the eighth NPN bipolar transistor Q8 is grounded
  • the drain of the fifth NMOS transistor N5 is connected to the gate of the fifth NMOS transistor N5
  • the fifth NMOS transistor N5 is connected to the drain of the fifth NMOS transistor N5.
  • the gate of the NMOS transistor N5 is also connected to the gate of the fourth NMOS transistor N4 , the source of the fifth NMOS transistor N5 is connected to the collector of the ninth NPN bipolar transistor Q9 , and the gate of the ninth NPN bipolar transistor Q9
  • the collector is connected to the base of the ninth NPN bipolar transistor Q9
  • the base of the ninth NPN bipolar transistor Q9 is also connected to the base of the eighth NPN bipolar transistor Q8
  • the emitter of the ninth NPN bipolar transistor Q9 ground
  • the base of the tenth NPN bipolar transistor Q10 is connected to the source of the fourth NMOS transistor N4
  • the emitter of the tenth NPN bipolar transistor Q10 is grounded
  • the source of the fourth NMOS transistor N4 is the first The first input end of the three current generation modules
  • the drain of the fifth NMOS transistor N5 is the second input end of the third current generation module
  • the drain of the fourth NMOS transistor N4 is the third input end of the third current
  • the fourth current mirror includes a first PMOS transistor P 1 and a fifth PMOS transistor P 5 , the source of the fifth PMOS transistor P 5 is connected to the working voltage V CC , and the fifth PMOS transistor P 5
  • the gate of the first PMOS transistor P1 is connected to the gate of the first PMOS transistor P1
  • the drain of the fifth PMOS transistor P5 is connected to the drain of the fifth NMOS transistor N5 , wherein the drain of the first PMOS transistor P1 is the drain of the fourth current mirror
  • the input terminal, the drain of the fifth PMOS transistor P5 is the output terminal of the fourth current mirror.
  • the fifth current mirror includes a sixth PMOS transistor P 6 and a seventh PMOS transistor P 7 , the source of the sixth PMOS transistor P 6 is connected to the operating voltage V CC , and the sixth PMOS transistor P 6
  • the gate of the sixth PMOS transistor P6 is connected to the drain of the sixth PMOS transistor P6, the drain of the sixth PMOS transistor P6 is connected to the collector of the tenth NPN bipolar transistor Q10 , and the source of the seventh PMOS transistor P7 is connected to the operating voltage V CC , the gate of the seventh PMOS transistor P7 is connected to the gate of the sixth PMOS transistor P6 , wherein the drain of the sixth PMOS transistor P6 is the input terminal of the fifth current mirror, and the drain of the seventh PMOS transistor P7 is the first The output terminals of the five current mirrors output compensation current I 3 .
  • the second-stage temperature compensation unit 2 includes a third NPN bipolar transistor Q 3 , a fourth NPN bipolar transistor Q 4 , a fifth NPN bipolar transistor Q 5 , a sixth NPN bipolar transistor
  • the first current generating module composed of Q 6 , the fifth resistor R 5 and the sixth resistor R 6
  • the second current generating module composed of the seventh NPN bipolar transistor Q 7 , the first NMOS transistor N 1 and the seventh resistor R 7
  • the third current generation module composed of the fourth NMOS transistor N4 , the fifth NMOS transistor N5 , the eighth NPN bipolar transistor Q8 , the ninth NPN bipolar transistor Q9 and the tenth NPN bipolar transistor Q10 .
  • the fifth current mirror composed of the sixth PMOS transistor P 6 and the seventh PMOS transistor P 7 The third current mirror composed of N 3 , the fourth current mirror composed of the first PMOS transistor P 1 and the fifth PMOS transistor P 5 , and the fifth current mirror composed of the sixth PMOS transistor P 6 and the seventh PMOS transistor P 7 .
  • the first current generating module is a positive temperature coefficient current generating module
  • the second current generating module is a negative temperature coefficient current generating module
  • the emitter junction area of the third NPN bipolar transistor Q3 and the fourth NPN bipolar transistor Q4 The ratio is n 2 : 1; the ratio of the emitter junction areas of the fifth NPN bipolar transistor Q 5 and the sixth NPN bipolar transistor Q 6 is 1:n 2 .
  • V be5 +V be4 V be3 +V be6 +I 4 R 6 (13)
  • the ratio of the emitter junction areas of the third NPN bipolar transistor Q3 to the fourth NPN bipolar transistor Q4 is n2 :1; the emitter junctions of the fifth NPN bipolar transistor Q5 and the sixth NPN bipolar transistor Q6
  • the ratio of the area is 1:n 2 , according to the transistor principle:
  • the output current I4 of the first current generating module is a PTAT current proportional to the absolute temperature, and its magnitude has nothing to do with the power supply.
  • I4 is mirrored to the seventh NPN bipolar transistor Q7 , the first NMOS transistor N1 and the seventh resistor R7 .
  • the second current generating module serves as a bias current. For the second current generating module there are:
  • the negative temperature coefficient current I6 passes through the second current mirror composed of the third PMOS transistor P3 and the fourth PMOS transistor P4 , and after the third current mirror composed of the second NMOS transistor N2 and the third NMOS transistor N3 , It is mirrored to the current I 7 and connected to the source end of the fourth NMOS transistor N 4 .
  • the PTAT current I4 is mirrored to I8 , and given to the fifth NMOS transistor N5 and the ninth NPN bipolar Transistor Q9 supplies current.
  • V be10 V be9 + V GS5 - V GS4 (18)
  • the compensation current I3 output by the second-order temperature compensation unit 2 can perform curvature compensation (second-order compensation) on the reference temperature curve.
  • a comparison of temperature curves before and after curvature compensation is shown in FIG. 4 , and the temperature performance of the bandgap reference voltage is greatly improved after curvature compensation.
  • the curvature compensation current is generated by passing the current I 8 with a positive temperature coefficient through the fifth NMOS transistor N 5 to generate the gate-source voltage V GS5 ; passing the current I 7 with a negative temperature coefficient through the fourth NMOS transistor N 4 to generate the gate-source voltage Voltage V GS4 ; in this way, the gate-source voltage difference V GS5 -V GS4 between the fourth NMOS transistor N4 and the fifth NMOS transistor N5 will increase as the temperature increases, and presents a second-order characteristic.
  • the current mirror ratio of each current mirror in the embodiment of the present invention is 1 by default, and the current mirror ratio of each current mirror (that is, the ratio of the width to length ratio of the two MOS transistors in the current mirror) can be adjusted according to actual needs. Adjust the settings, which will not be repeated here.
  • an embodiment of the present invention also provides a compensation method for a bandgap reference voltage, which includes the steps of:
  • the embodiment of the present invention designs a corresponding trimming circuit on the basis of the first embodiment to achieve the purpose of digitally trimming first-order compensation and second-order compensation (curvature compensation), thus making the present invention more practical.
  • the embodiment of the present invention replaces the third resistor R 3 in FIG. 1 with a digitally adjustable resistor shown in a dotted line box, so as to realize first-order temperature-compensated digitally adjustable bandgap reference voltage.
  • the resistance values of resistors R 10 , R 11 , R 12 , R 13 and R 14 are designed in proportions of 1:2:4:8:16, and the corresponding PMOS transistor P 10
  • the width-to-length ratios of P 11 , P 12 , P 13 and P 14 are also designed according to the ratio of 1:2:4:8:16.
  • the minimum resistance value can be designed to be 100 ohms or 10 ohms according to the characteristics of the process used and the trimming accuracy, and the minimum width-to-length ratio can be designed to be 20 or 40 accordingly.
  • the magnitude of the resistance can be controlled by digital signals D 0 , D 1 , D 2 , D 3 and D 4 , thereby realizing first-order temperature-compensated digital adjustment of the bandgap reference voltage.
  • the embodiment of the present invention uses the circuit in the dotted line box to realize the digital adjustment of the second-order temperature compensation current I 3 .
  • the width-to-length ratios of PMOS transistors P 20 , P 21 , P 22 , P 23 and P 24 are designed according to the ratio of 1:2:4:8:16, and the corresponding PMOS transistors
  • the width-to-length ratios of P 30 , P 31 , P 32 , P 33 and P 34 are also designed according to the ratio of 1:2:4:8:16.
  • the minimum width-to-length ratio can be designed to be 20 or 40 according to the characteristics of the process used and the trimming accuracy. In this way, the magnitude of the second-order temperature compensation current I 3 can be controlled by digital signals D 5 , D 6 , D 7 , D 8 and D 9 , so as to realize the second-order temperature compensation digital adjustment of the bandgap reference voltage.
  • the bandgap reference voltage circuit and the compensation method of the bandgap reference voltage of the present invention generate a bandgap reference voltage with first-order temperature compensation through the first-order temperature compensation bandgap reference unit, and generate The compensation current with the second-order positive temperature coefficient is applied to the bandgap reference voltage to effectively realize the second-order temperature compensation of the output bandgap reference voltage.

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Abstract

本发明提供一种带隙基准电压电路及带隙基准电压的补偿方法，所述带隙基准电压电路包括：一阶温度补偿带隙基准单元，输出具有一阶温度补偿的带隙基准电压；二阶温度补偿单元，接一阶温度补偿带隙基准单元，向一阶温度补偿带隙基准单元输出具有二阶正温度系数的补偿电流，对带隙基准电压进行二阶温度补偿。本发明通过一阶温度补偿带隙基准单元产生具有一阶温度补偿的带隙基准电压，通过二阶温度补偿单元产生具有二阶正温度系数的补偿电流，再把具有二阶正温度系数的补偿电流作用到带隙基准电压上，有效实现了输出带隙基准电压的二阶温度补偿。

Description

带隙基准电压电路及带隙基准电压的补偿方法 技术领域
本发明涉及集成电路技术领域，特别是涉及一种带隙基准电压电路及带隙基准电压的补偿方法。
背景技术
基准电压源是一种高精度、高稳定性的电压源，在各种模拟、数模混合集成电路中有着广泛的应用，基准电压源主要采用基准电压产生电路来产生。现有的与温度无关的常见基准电压产生电路有：一是基于增强型NMOS和耗尽型NMOS的开启电压之差形成温度稳定的基准电压，这种方法在不同的工艺角下基准电压偏差较大，不适合高精度的应用；二是基于NPN反向击穿BE结构成的齐纳二极管的击穿电压，这种方法由于击穿电压较高，不适合低电源电压应用场合；三是基于等效热电压的正温度系数和双极晶体管BE结电压的负温度系数相互补偿的一阶带隙基准电路，这种电路可以较好地解决前两种基准电压产生电路存在的问题，但这种一阶带隙基准电路的一阶补偿后温度系数仍然较高，不适用于温度变化较大的场合。
高精度A/D转换器需要高精度的基准电压，往往一阶温度补偿的带隙基准电压不能满足要求，需要使用曲率(二阶)补偿。而现有曲率补偿技术大部分停留在理论或者模型阶段，实用的很少。
因此，目前急需一种带隙基准电压的二阶温度补偿技术方案。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种带隙基准电压的二阶温度补偿技术方案，快速有效地实现带隙基准电压的二阶温度补偿。
为实现上述目的及其他相关目的，本发明提供的技术方案如下。
一种带隙基准电压电路，包括：
一阶温度补偿带隙基准单元，输出具有一阶温度补偿的带隙基准电压；
二阶温度补偿单元，接所述一阶温度补偿带隙基准单元，向所述一阶温度补偿带隙基准单元输出具有二阶正温度系数的补偿电流，对所述带隙基准电压进行二阶温度补偿。
可选地，所述一阶温度补偿带隙基准单元包括第一NPN双极晶体管、第二NPN双极晶体管、第一电阻、第二电阻、第三电阻、第四电阻及运算放大器，所述运算放大器的输出端 经串联的所述第一电阻后接所述第一NPN双极晶体管的集电极，所述第一NPN双极晶体管的集电极接所述第一NPN双极晶体管的基极，所述第一NPN双极晶体管的发射极经串联的所述第二电阻后接地，所述运算放大器的输出端还经串联的所述第三电阻后接所述第二NPN双极晶体管的集电极，所述第二NPN双极晶体管的集电极接所述第二NPN双极晶体管的基极，所述第二NPN双极晶体管的发射极经串接的所述第四电阻后接所述第一NPN双极晶体管的发射极，所述第一NPN双极晶体管的集电极接所述运算放大器的同相输入端，所述第二NPN双极晶体管的集电极接所述运算放大器的反相输入端，所述运算放大器的输出端输出所述带隙基准电压。
可选地，所述二阶温度补偿单元包括第一电流产生模块、第二电流产生模块、第三电流产生模块、第一电流镜、第二电流镜、第三电流镜、第四电流镜及第五电流镜，所述第一电流产生模块的输出端与所述第一电流镜的输入端连接，所述第一电流镜的输出端接所述第二电流产生模块的偏置输入端，所述第二电流产生模块的输出端接所述第二电流镜的输入端，所述第二电流镜的输出端接所述第三电流镜的输入端，所述第三电流镜的输出端接所述第三电流产生模块的第一输入端，所述第四电流镜的输入端接所述第一电流产生模块的输出端，所述第四电流镜的输出端接所述第三电流产生模块的第二输入端，所述第三电流产生模块的第三输入端接工作电压，所述第三电流产生模块的输出端接所述第五电流镜的输入端，所述第五电流镜的输出端输出所述补偿电流。
可选地，所述第一电流产生模块为正温度系数电流产生模块，其包括第三NPN双极晶体管、第四NPN双极晶体管、第五NPN双极晶体管、第六NPN双极晶体管、第五电阻及第六电阻，所述工作电压经串接的所述第五电阻后接所述第三NPN双极晶体管的集电极，所述第三NPN双极晶体管的集电极接所述第三NPN双极晶体管的基极，所述第三NPN双极晶体管的发射极接所述第四NPN双极晶体管的集电极，所述第四NPN双极晶体管的发射极接地，所述第五NPN双极晶体管的基极接所述第三NPN双极晶体管的基极，所述第五NPN双极晶体管的发射极接所述第六NPN双极晶体管的集电极，所述第五NPN双极晶体管的发射极还接所述第四NPN双极晶体管的基极，所述第六NPN双极晶体管的基极接所述第三NPN双极晶体管的发射极，所述第六NPN双极晶体管的发射极经串接的所述第六电阻后接地，其中，所述第五NPN双极晶体管的集电极为所述第一电流产生模块的输出端。
可选地，所述第一电流镜包括第一PMOS管及第二PMOS管，所述第一PMOS管的源极接所述工作电压，所述第一PMOS管的栅极接所述第一PMOS管的漏极，所述第一PMOS管的漏极接所述第五NPN双极晶体管的集电极，所述第二PMOS管的源极接所述工作电压， 所述第二PMOS管的栅极接所述第一PMOS管的栅极，其中，所述第一PMOS管的漏极为所述第一电流镜的输入端，所述第二PMOS管的漏极为所述第一电流镜的输出端。
可选地，所述第二电流产生模块为负温度系数电流产生模块，其包括第七NPN双极晶体管、第一NMOS管及第七电阻，所述第七NPN双极晶体管的集电极接所述第二PMOS管的漏极，所述第七NPN双极晶体管的发射极接地，所述第一NMOS管的栅极接所述第二PMOS管的漏极，所述第一NMOS管的源极经串接的所述第七电阻后接地，所述第一NMOS管的源极还接所述第七NPN双极晶体管的基极，其中，所述第一NMOS管的栅极为所述第二电流产生模块的偏置输入端，所述第一NMOS管的漏极为所述第二电流产生模块的输出端。
可选地，所述第二电流镜包括第三PMOS管及第四PMOS管，所述第三PMOS管的源极接所述工作电压，所述第三PMOS管的栅极接所述第三PMOS管的漏极，所述第三PMOS管的漏极接所述第一NMOS管的漏极，所述第四PMOS管的源极接所述工作电压，所述第四PMOS管的栅极接所述第三PMOS管的栅极，其中，所述第三PMOS管的漏极为所述第二电流镜的输入端，所述第四PMOS管的漏极为所述第二电流镜的输出端。
可选地，所述第三电流镜包括第二NMOS管及第三NMOS管，所述第二NMOS管的漏极接所述第四PMOS管的漏极，所述第二NMOS管的栅极接所述第二NMOS管的漏极，所述第二NMOS管的源极接地，所述第三NMOS管的栅极接所述第二NMOS管的栅极，所述第三NMOS管的源极接地，其中，所述第二NMOS管的漏极为所述第三电流镜的输入端，所述第三NMOS管的漏极为所述第三电流镜的输出端。
可选地，所述第三电流产生模块包括第四NMOS管、第五NMOS管、第八NPN双极晶体管、第九NPN双极晶体管及第十NPN双极晶体管，所述第四NMOS管的漏极接所述工作电压，所述第四NMOS管的源极接所述第三NMOS管的漏极，所述第四NMOS管的源极还接所述第八NPN双极晶体管的集电极，所述第八NPN双极晶体管的发射极接地，所述第五NMOS管的漏极接所述第五NMOS管的栅极，所述第五NMOS管的栅极还接所述第四NMOS管的栅极，所述第五NMOS管的源极接所述第九NPN双极晶体管的集电极，所述第九NPN双极晶体管的集电极接所述第九NPN双极晶体管的基极，所述第九NPN双极晶体管的基极还接所述第八NPN双极晶体管的基极，所述第九NPN双极晶体管的发射极接地，所述第十NPN双极晶体管的基极接所述第四NMOS管的源极，所述第十NPN双极晶体管的发射极接地，其中，所述第四NMOS管的源极为所述第三电流产生模块的第一输入端，所述第五NMOS管的漏极为所述第三电流产生模块的第二输入端，所述第四NMOS管的漏极为所述第三电流产生模块的第三输入端，所述第十NPN双极晶体管的集电极为所述第三电流产生模块的输出 端。
可选地，所述第四电流镜包括所述第一PMOS管及第五PMOS管，所述第五PMOS管的源极接所述工作电压，所述第五PMOS管的栅极接所述第一PMOS管的栅极，所述第五PMOS管的漏极接所述第五NMOS管的漏极，其中，所述第一PMOS管的漏极为所述第四电流镜的输入端，所述第五PMOS管的漏极为所述第四电流镜的输出端。
可选地，所述第五电流镜包括第六PMOS管及第七PMOS管，所述第六PMOS管的源极接所述工作电压，所述第六PMOS管的栅极接所述第六PMOS管的漏极，所述第六PMOS管的漏极接所述第十NPN双极晶体管的集电极，所述第七PMOS管的源极接所述工作电压，所述第七PMOS管的栅极接所述第六PMOS管的栅极，其中，所述第六PMOS管的漏极为所述第五电流镜的输入端，所述第七PMOS管的漏极为所述第五电流镜的输出端。
可选地，所述第三电阻包括数字可调电阻，所述第七PMOS管包括数字可调PMOS管。
一种带隙基准电压的补偿方法，包括步骤：
生成具有一阶温度补偿的带隙基准电压；
利用正温度系数电流和负温度系数电流产生具有二阶正温度系数的补偿电流；
利用所述补偿电流，对所述带隙基准电压进行二阶温度补偿。
如上所述，本发明的带隙基准电压电路及带隙基准电压的补偿方法，至少具有以下有益效果：
通过一阶温度补偿带隙基准单元产生具有一阶温度补偿的带隙基准电压，通过二阶温度补偿单元产生具有二阶正温度系数的补偿电流，再把具有二阶正温度系数的补偿电流作用到带隙基准电压上，有效实现了输出带隙基准电压的二阶温度补偿。
附图说明
图1显示为本发明实施例一中带隙基准电压电路的结构示意图。
图2显示为图1中一阶温度补偿后的带隙基准电压温度曲线。
图3显示为图1中二阶温度补偿单元2的电路图。
图4显示为图1中二阶温度补偿后的带隙基准电压温度曲线。
图5显示为本发明实施例二中带隙基准电压电路的结构示意图。
图6显示为图5中二阶温度补偿单元2的电路图。
具体实施方式
如前述在背景技术中所提及的：在高精度需求的模数转换器等应用场合，一阶温度补偿 的带隙基准电压越来越不能满足要求，迫切需要使用二阶温度补偿的带隙基准电压；而现有二阶补偿技术大部分停留在理论或者模型阶段，实用的很少。
基于此，本发明提出一种带隙基准电压的二阶温度补偿技术方案：在生成具有一阶温度补偿的带隙基准电压的基础上，利用一个正温度系数电流和一个负温度系数电流产生具有二阶正温度系数的补偿电流，再利用补偿电流对带隙基准电压进行二阶温度补偿。
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图6。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
实施例一
如图1所示，本发明实施例提供一种带隙基准电压电路，其包括：
一阶温度补偿带隙基准单元1，输出具有一阶温度补偿的带隙基准电压V ref；
二阶温度补偿单元2，接一阶温度补偿带隙基准单元1，向一阶温度补偿带隙基准单元1输出具有二阶正温度系数的补偿电流I 3，对带隙基准电压V ref进行二阶温度补偿。
详细地，如图1所示，一阶温度补偿带隙基准单元1包括第一NPN双极晶体管Q 1、第二NPN双极晶体管Q 2、第一电阻R 1、第二电阻R 2、第三电阻R 3、第四电阻R 4及运算放大器A，运算放大器A的输出端经串联的第一电阻R 1后接第一NPN双极晶体管Q 1的集电极，第一NPN双极晶体管的Q 1集电极接第一NPN双极晶体管Q 1的基极，第一NPN双极晶体管Q 1的发射极经串联的第二电阻R 2后接地，运算放大器A的输出端还经串联的第三电阻R 3后接第二NPN双极晶体管Q 2的集电极，第二NPN双极晶体管Q 2的集电极接第二NPN双极晶体管Q 2的基极，第二NPN双极晶体管Q 2的发射极经串接的第四电阻R 4后接第一NPN双极晶体管Q 1的发射极，第一NPN双极晶体管Q 1的集电极接运算放大器A的同相输入端，第 二NPN双极晶体管Q 2的集电极接运算放大器A的反相输入端，运算放大器A的输出端输出带隙基准电压V ref。
更详细地，如图1所示，第一NPN双极晶体管Q 1与第二NPN双极晶体管Q 2的发射结面积之比为1：n 1，第一NPN双极晶体管Q 1与第二NPN双极晶体管Q 2为二级管连接方式，运算放大器A使得第一电阻R 1和第三电阻R 3上的压降相等，因此流过第一电阻R 1的电流I 1与流过第三电阻R 3的电流I 2有如下关系：
Figure PCTCN2021143487-appb-000001
同时，由于运算放大器A同相输入端与反相输入端近似相等，因此有：
V be1＝V be2+I 2R 4           (2)
上式中V be1和V be2分别为第一NPN双极晶体管Q 1与第二NPN双极晶体管Q 2的基射结电压降。根据双极晶体管电流电压关系和式(2)有：
Figure PCTCN2021143487-appb-000002
上式中k是玻尔兹曼常数，T是绝对温度，q是电子电荷，I s1和I s2分别是第一NPN双极晶体管Q 1与第二NPN双极晶体管Q 2的反向饱和电流；整理(3)式得到：
Figure PCTCN2021143487-appb-000003
根据双极晶体管原理，反向饱和电流与双极晶体管的发射结面积成正比，而第一NPN双极晶体管Q 1与第二NPN双极晶体管Q 2的发射结面积之比为1：n 1，再结合(1)式，从(4)式可得到
Figure PCTCN2021143487-appb-000004
因此有:
V ref＝V be1+I 1R 1+(I 1+I 2)R 2+I 3R 2         (6)
根据(1)、(5)和(6)式有：
Figure PCTCN2021143487-appb-000005
用泰勒公式V be1展开，只取常数项、一阶项和二阶项得:
V be1＝V be10+b(T-T 0)+a(T-T 0) 2＝(V be10-bT 0)+bT+a(T-T 0) 2   (8)
上式中，V be10为常温下第一NPN双极晶体管Q 1的基射结电压，T 0为常温的绝对温度，b为V be10一阶温度系数，a为V be10二阶温度系数。把(8)代入(7)有
Figure PCTCN2021143487-appb-000006
(9)式等式两边对温度求导得：
Figure PCTCN2021143487-appb-000007
整理得
Figure PCTCN2021143487-appb-000008
(11)式右边第一项、第三项、第四项及第五项均为与温度无关的常数，可以通过调整电路第一电阻R 1、第三电阻R 3及第四电阻R 4的阻值来实现第一项、第三项、第四项及第五项的相互抵消，从而实现基准温度曲线的一阶补偿，一阶温度补偿后的带隙基准电压的温度曲线如图2所示。
(11)式等式两边对温度求导得：
Figure PCTCN2021143487-appb-000009
(12)式右边第一项为V be10的二阶温度系数，其决定图2中抛物线的曲率，从而最终决定一阶温度补偿后带隙基准电压的温度性能。在高精度模数转换器应用中，一阶温度补偿往往不能满足要求。因此，我们利用(12)式右边最后二项对第一项进行部分补偿，以提高一阶温度补偿后的带隙基准电压的温度性能。(12)式右边最后一项的补偿电流I 3由图3所示的二阶温度补偿单元2产生。
详细地，如图3所示，二阶温度补偿单元2包括第一电流产生模块、第二电流产生模块、第三电流产生模块、第一电流镜、第二电流镜、第三电流镜、第四电流镜及第五电流镜，第一电流产生模块的输出端与第一电流镜的输入端连接，第一电流镜的输出端接第二电流产生模块的偏置输入端，第二电流产生模块的输出端接第二电流镜的输入端，第二电流镜的输出端接第三电流镜的输入端，第三电流镜的输出端接第三电流产生模块的第一输入端，第四电流镜的输入端接第一电流产生模块的输出端，第四电流镜的输出端接第三电流产生模块的第二输入端，第三电流产生模块的第三输入端接工作电压V CC，第三电流产生模块的输出端接第五电流镜的输入端，第五电流镜的输出端输出补偿电流I 3。
更详细地，如图3所示，第一电流产生模块为正温度系数电流产生模块，其包括第三NPN双极晶体管Q 3、第四NPN双极晶体管Q 4、第五NPN双极晶体管Q 5、第六NPN双极晶体管Q 6、第五电阻R 5及第六电阻R 6，工作电压V CC经串接的第五电阻R 5后接第三NPN双极晶体管Q 3的集电极，第三NPN双极晶体管Q 3的集电极接第三NPN双极晶体管Q 3的基极，第三NPN双极晶体管Q 3的发射极接第四NPN双极晶体管Q 4的集电极，第四NPN双极晶体管Q 4的发射极接地，第五NPN双极晶体管Q 5的基极接第三NPN双极晶体管Q 3的基极，第五NPN双极晶体管Q 3的发射极接第六NPN双极晶体管Q 6的集电极，第五NPN双极晶体管Q 5的发射极还接第四NPN双极晶体管Q 4的基极，第六NPN双极晶体管Q 6的基极接第三NPN 双极晶体管Q 3的发射极，第六NPN双极晶体管Q 6的发射极经串接的第六电阻R 6后接地，其中，第五NPN双极晶体管Q 5的集电极为第一电流产生模块的输出端。
更详细地，如图3所示，第一电流镜包括第一PMOS管P 1及第二PMOS管P 2，第一PMOS管P 1的源极接工作电压V CC，第一PMOS管P 1的栅极接第一PMOS管P 1的漏极，第一PMOS管P 1的漏极接第五NPN双极晶体管Q 5的集电极，第二PMOS管P 2的源极接工作电压V CC，第二PMOS管P 2的栅极接第一PMOS管P 1的栅极，其中，第一PMOS管P 1的漏极为第一电流镜的输入端，第二PMOS管P 2的漏极为第一电流镜的输出端。
更详细地，如图3所示，第二电流产生模块为负温度系数电流产生模块，其包括第七NPN双极晶体管Q 7、第一NMOS管N 1及第七电阻R 7，第七NPN双极晶体管Q 7的集电极接第二PMOS管P 2的漏极，第七NPN双极晶体管Q 7的发射极接地，第一NMOS管N 1的栅极接第二PMOS管P 2的漏极，第一NMOS管N 1的源极经串接的第七电阻R 7后接地，第一NMOS管N 1的源极还接第七NPN双极晶体管Q 7的基极，其中，第一NMOS管N 1的栅极为第二电流产生模块的偏置输入端，第一NMOS管N 1的漏极为第二电流产生模块的输出端。
更详细地，如图3所示，第二电流镜包括第三PMOS管P 3及第四PMOS管P 4，第三PMOS管P 3的源极接工作电压V CC，第三PMOS管P 3的栅极接第三PMOS管P 3的漏极，第三PMOS管P 3的漏极接第一NMOS管N 1的漏极，第四PMOS管P 4的源极接工作电压V CC，第四PMOS管P 4的栅极接第三PMOS管P 3的栅极，其中，第三PMOS管P 3的漏极为第二电流镜的输入端，第四PMOS管P 4的漏极为第二电流镜的输出端。
更详细地，如图3所示，第三电流镜包括第二NMOS管N 2及第三NMOS管N 3，第二NMOS管N 2的漏极接第四PMOS管P 4的漏极，第二NMOS管N 2的栅极接第二NMOS管N 2的漏极，第二NMOS管N 2的源极接地，第三NMOS管N 3的栅极接第二NMOS管N 2的栅极，第三NMOS管N 3的源极接地，其中，第二NMOS管N 2的漏极为第三电流镜的输入端，第三NMOS管N 3的漏极为第三电流镜的输出端。
更详细地，如图3所示，第三电流产生模块包括第四NMOS管N 4、第五NMOS管N 5、第八NPN双极晶体管Q 8、第九NPN双极晶体管Q 9及第十NPN双极晶体管Q 10，第四NMOS管N 4的漏极接工作电压V CC，第四NMOS管N 4的源极接第三NMOS管N 3的漏极，第四NMOS管N 4的源极还接第八NPN双极晶体管Q 8的集电极，第八NPN双极晶体管Q 8的发射极接地，第五NMOS管N 5的漏极接第五NMOS管N 5的栅极，第五NMOS管N 5的栅极还接第四NMOS管N 4的栅极，第五NMOS管N 5的源极接第九NPN双极晶体管Q 9的集电极，第九NPN双极晶体管Q 9的集电极接第九NPN双极晶体管Q 9的基极，第九NPN双极晶体管Q 9的基极还 接第八NPN双极晶体管Q 8的基极，第九NPN双极晶体管Q 9的发射极接地，第十NPN双极晶体管Q 10的基极接第四NMOS管N 4的源极，第十NPN双极晶体管Q 10的发射极接地，其中，第四NMOS管N 4的源极为第三电流产生模块的第一输入端，第五NMOS管N 5的漏极为第三电流产生模块的第二输入端，第四NMOS管N 4的漏极为第三电流产生模块的第三输入端，第十NPN双极晶体管Q 10的集电极为第三电流产生模块的输出端。
更详细地，如图3所示，第四电流镜包括第一PMOS管P 1及第五PMOS管P 5，第五PMOS管P 5的源极接工作电压V CC，第五PMOS管P 5的栅极接第一PMOS管P 1的栅极，第五PMOS管P 5的漏极接第五NMOS管N 5的漏极，其中，第一PMOS管P 1的漏极为第四电流镜的输入端，第五PMOS管P 5的漏极为第四电流镜的输出端。
更详细地，如图3所示，第五电流镜包括第六PMOS管P 6及第七PMOS管P 7，第六PMOS管P 6的源极接工作电压V CC，第六PMOS管P 6的栅极接第六PMOS管P 6的漏极，第六PMOS管P 6的漏极接第十NPN双极晶体管Q 10的集电极，第七PMOS管P 7的源极接工作电压V CC，第七PMOS管P 7的栅极接第六PMOS管P 6的栅极，其中，第六PMOS管P 6的漏极为第五电流镜的输入端，第七PMOS管P 7的漏极为第五电流镜的输出端，输出补偿电流I 3。
更详细地，如图3所示，二阶温度补偿单元2包括第三NPN双极晶体管Q 3、第四NPN双极晶体管Q 4、第五NPN双极晶体管Q 5、第六NPN双极晶体管Q 6、第五电阻R 5及第六电阻R 6组成的第一电流产生模块，第七NPN双极晶体管Q 7、第一NMOS管N 1及第七电阻R 7组成的第二电流产生模块，第四NMOS管N 4、第五NMOS管N 5、第八NPN双极晶体管Q 8、第九NPN双极晶体管Q 9及第十NPN双极晶体管Q 10组成的第三电流产生模块，第一PMOS管P 1及第二PMOS管P 2组成的第一电流镜，第三PMOS管P 3及第四PMOS管P 4组成的第二电流镜，第二NMOS管N 2及第三NMOS管N 3组成的第三电流镜，第一PMOS管P 1及第五PMOS管P 5组成的第四电流镜，第六PMOS管P 6及第七PMOS管P 7组成的第五电流镜。
其中，第一电流产生模块为正温度系数电流产生模块，第二电流产生模块为负温度系数电流产生模块，第三NPN双极晶体管Q 3与第四NPN双极晶体管Q 4的发射结面积之比为n 2：1；第五NPN双极晶体管Q 5和第六NPN双极晶体管Q 6的发射结面积之比为1：n 2。
更详细地，如图3所示，对于第一电流产生模块，忽略基极电流的影响有以下关系：
V be5+V be4＝V be3+V be6+I 4R 6      (13)
根据双极晶体管电压电流关系有：
Figure PCTCN2021143487-appb-000010
整理(14)式得
Figure PCTCN2021143487-appb-000011
因为第三NPN双极晶体管Q 3与第四NPN双极晶体管Q 4的发射结面积之比为n 2：1；第五NPN双极晶体管Q 5和第六NPN双极晶体管Q 6的发射结面积之比为1：n 2，根据晶体管原理有：
Figure PCTCN2021143487-appb-000012
因此，第一电流产生模块的输出电流I 4是与绝对温度成正比的PTAT电流，其大小与电源无关。通过第一PMOS管P 1及第二PMOS管P 2组成的第一电流镜，I 4被镜相到第七NPN双极晶体管Q 7、第一NMOS管N 1及第七电阻R 7组成的第二电流产生模块，作为偏置电流。对于第二电流产生模块有：
Figure PCTCN2021143487-appb-000013
因为V be7的一阶温度系数为负值，二阶温度系数也为负值；因此，I 6的一、二阶温度系数也为负值。该负温度系数的电流I 6通过第三PMOS管P 3及第四PMOS管P 4组成的第二电流镜，第二NMOS管N 2及第三NMOS管N 3组成的第三电流镜后，被镜相到电流I 7，并接入第四NMOS管N 4的源端。另一方面，通过第一PMOS管P 1及第五PMOS管P 5组成的第四电流镜，PTAT电流I 4被镜相到I 8，并给第五NMOS管N 5及第九NPN双极晶体管Q 9提供电流。
对于第四NMOS管N 4、第五NMOS管N 5、第八NPN双极晶体管Q 8、第九NPN双极晶体管Q 9及第十NPN双极晶体管Q 10组成的第三电流产生模块，有：
V be10＝V be9+V GS5-V GS4        (18)
根据MOS晶体管电压电流关系有：
Figure PCTCN2021143487-appb-000014
因此
Figure PCTCN2021143487-appb-000015
可以证明补偿电流I 3对温度的二阶导数为正数。根据半导体物理知识可知，(12)式中，a为负数。因此，二阶温度补偿单元2输出的补偿电流I 3可以对基准温度曲线进行曲率补偿 (二阶补偿)。在本发明的一可选实施例中，曲率补偿前后温度曲线对比如图4所示，曲率补偿后带隙基准电压的温度性能大大提高了。
由以上分析可知，曲率补偿电流是通过把正温度系数的电流I 8通过第五NMOS管N 5产生栅源电压V GS5；把负温度系数的电流I 7通过第四NMOS管N 4产生栅源电压V GS4；这样，第四NMOS管N 4与第五NMOS管N 5的栅源电压差V GS5-V GS4会随温度升高而升高，并呈现出二阶特性。把这个栅源电压差V GS5-V GS4叠加到第九NPN双极晶体管Q 9的基射结电压V be9上，再作用于第十NPN双极晶体管Q 10的基射结上产生电流I 10。第九NPN双极晶体管Q的基射结电压V be9上是由正温度系数的电流I 8产生的。因此，电流I 10具有正温度特性，并呈现出二阶特性。
需要说明的是，本发明实施例中各个电流镜的电流镜像比例默认为1，而各个电流镜的电流镜像比例(即电流镜中两个MOS管的宽长比的比值)可按实际需要进行调节设置，在此不再赘述。
基于同样的发明构思，本发明实施例还提供一种带隙基准电压的补偿方法，其包括步骤：
S1、生成具有一阶温度补偿的带隙基准电压；
S2、利用正温度系数电流和负温度系数电流产生具有二阶正温度系数的补偿电流；
S3、利用补偿电流，对带隙基准电压进行二阶温度补偿。
实施例二
此外，由于半导体制造工艺的特点，制造出的器件的参数会偏离设计值，并且会在一定范围内波动，存在一定的统计随机性。因此，本发明实施例在实施例一的基础上设计出相应的修调电路，以实现数字修调一阶补偿和二阶补偿(曲率补偿)的目的，从而使得本发明更具有实用性。
如图5所示，本发明实施例用虚线框中所示数字可调电阻代替图1中的第三电阻R 3，以实现带隙基准电压的一阶温度补偿数字可调。为了实现较大的修调范围和修调精度，电阻R 10、R 11、R 12、R 13和R 14的阻值按比例1:2:4:8:16设计，相应的PMOS管P 10、P 11、P 12、P 13和P 14的宽长比也按比例1:2:4:8:16设计。最小阻值根据所采用的工艺的特点和修调精度，可设计成100欧姆，或者10欧姆，相应地最小宽长比可设计成20或者40。这样，可通过数字信号D 0、D 1、D 2、D 3和D 4来控制电阻大小，从而实现带隙基准电压的一阶温度补偿数字调节。
如图6所示，本发明实施例用虚线框中的电路来实现二阶温度补偿电流I 3的数字可调。为了实现较大的修调范围和修调精度，PMOS管P 20、P 21、P 22、P 23和P 24的宽长比按比例1:2:4:8:16设计，相应的PMOS管P 30、P 31、P 32、P 33和P 34的宽长比也按比例1:2:4:8:16设计。 最小宽长比根据所采用的工艺的特点和修调精度，可设计成20或者40。这样，可通过数字信号D 5、D 6、D 7、D 8和D 9来控制二阶温度补偿电流I 3的大小，从而实现带隙基准电压的二阶温度补偿数字调节。
综上所述，本发明的带隙基准电压电路及带隙基准电压的补偿方法，通过一阶温度补偿带隙基准单元产生具有一阶温度补偿的带隙基准电压，通过二阶温度补偿单元产生具有二阶正温度系数的补偿电流，再把具有二阶正温度系数的补偿电流作用到带隙基准电压上，有效实现了输出带隙基准电压的二阶温度补偿。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (13)

  1. 一种带隙基准电压电路，其特征在于，包括：
    一阶温度补偿带隙基准单元，输出具有一阶温度补偿的带隙基准电压；
    二阶温度补偿单元，接所述一阶温度补偿带隙基准单元，向所述一阶温度补偿带隙基准单元输出具有二阶正温度系数的补偿电流，对所述带隙基准电压进行二阶温度补偿。
  2. 根据权利要求1所述的带隙基准电压电路，其特征在于，所述一阶温度补偿带隙基准单元包括第一NPN双极晶体管、第二NPN双极晶体管、第一电阻、第二电阻、第三电阻、第四电阻及运算放大器，所述运算放大器的输出端经串联的所述第一电阻后接所述第一NPN双极晶体管的集电极，所述第一NPN双极晶体管的集电极接所述第一NPN双极晶体管的基极，所述第一NPN双极晶体管的发射极经串联的所述第二电阻后接地，所述运算放大器的输出端还经串联的所述第三电阻后接所述第二NPN双极晶体管的集电极，所述第二NPN双极晶体管的集电极接所述第二NPN双极晶体管的基极，所述第二NPN双极晶体管的发射极经串接的所述第四电阻后接所述第一NPN双极晶体管的发射极，所述第一NPN双极晶体管的集电极接所述运算放大器的同相输入端，所述第二NPN双极晶体管的集电极接所述运算放大器的反相输入端，所述运算放大器的输出端输出所述带隙基准电压。
  3. 根据权利要求1或2所述的带隙基准电压电路，其特征在于，所述二阶温度补偿单元包括第一电流产生模块、第二电流产生模块、第三电流产生模块、第一电流镜、第二电流镜、第三电流镜、第四电流镜及第五电流镜，所述第一电流产生模块的输出端与所述第一电流镜的输入端连接，所述第一电流镜的输出端接所述第二电流产生模块的偏置输入端，所述第二电流产生模块的输出端接所述第二电流镜的输入端，所述第二电流镜的输出端接所述第三电流镜的输入端，所述第三电流镜的输出端接所述第三电流产生模块的第一输入端，所述第四电流镜的输入端接所述第一电流产生模块的输出端，所述第四电流镜的输出端接所述第三电流产生模块的第二输入端，所述第三电流产生模块的第三输入端接工作电压，所述第三电流产生模块的输出端接所述第五电流镜的输入端，所述第五电流镜的输出端输出所述补偿电流。
  4. 根据权利要求3所述的带隙基准电压电路，其特征在于，所述第一电流产生模块为正温度系数电流产生模块，其包括第三NPN双极晶体管、第四NPN双极晶体管、第五NPN双极晶体管、第六NPN双极晶体管、第五电阻及第六电阻，所述工作电压经串接的所述第五电阻后接所述第三NPN双极晶体管的集电极，所述第三NPN双极晶体管的集电极接所述第三NPN双极晶体管的基极，所述第三NPN双极晶体管的发射极接所述第四NPN双极晶体管的 集电极，所述第四NPN双极晶体管的发射极接地，所述第五NPN双极晶体管的基极接所述第三NPN双极晶体管的基极，所述第五NPN双极晶体管的发射极接所述第六NPN双极晶体管的集电极，所述第五NPN双极晶体管的发射极还接所述第四NPN双极晶体管的基极，所述第六NPN双极晶体管的基极接所述第三NPN双极晶体管的发射极，所述第六NPN双极晶体管的发射极经串接的所述第六电阻后接地，其中，所述第五NPN双极晶体管的集电极为所述第一电流产生模块的输出端。
  5. 根据权利要求4所述的带隙基准电压电路，其特征在于，所述第一电流镜包括第一PMOS管及第二PMOS管，所述第一PMOS管的源极接所述工作电压，所述第一PMOS管的栅极接所述第一PMOS管的漏极，所述第一PMOS管的漏极接所述第五NPN双极晶体管的集电极，所述第二PMOS管的源极接所述工作电压，所述第二PMOS管的栅极接所述第一PMOS管的栅极，其中，所述第一PMOS管的漏极为所述第一电流镜的输入端，所述第二PMOS管的漏极为所述第一电流镜的输出端。
  6. 根据权利要求5所述的带隙基准电压电路，其特征在于，所述第二电流产生模块为负温度系数电流产生模块，其包括第七NPN双极晶体管、第一NMOS管及第七电阻，所述第七NPN双极晶体管的集电极接所述第二PMOS管的漏极，所述第七NPN双极晶体管的发射极接地，所述第一NMOS管的栅极接所述第二PMOS管的漏极，所述第一NMOS管的源极经串接的所述第七电阻后接地，所述第一NMOS管的源极还接所述第七NPN双极晶体管的基极，其中，所述第一NMOS管的栅极为所述第二电流产生模块的偏置输入端，所述第一NMOS管的漏极为所述第二电流产生模块的输出端。
  7. 根据权利要求6所述的带隙基准电压电路，其特征在于，所述第二电流镜包括第三PMOS管及第四PMOS管，所述第三PMOS管的源极接所述工作电压，所述第三PMOS管的栅极接所述第三PMOS管的漏极，所述第三PMOS管的漏极接所述第一NMOS管的漏极，所述第四PMOS管的源极接所述工作电压，所述第四PMOS管的栅极接所述第三PMOS管的栅极，其中，所述第三PMOS管的漏极为所述第二电流镜的输入端，所述第四PMOS管的漏极为所述第二电流镜的输出端。
  8. 根据权利要求7所述的带隙基准电压电路，其特征在于，所述第三电流镜包括第二NMOS管及第三NMOS管，所述第二NMOS管的漏极接所述第四PMOS管的漏极，所述第 二NMOS管的栅极接所述第二NMOS管的漏极，所述第二NMOS管的源极接地，所述第三NMOS管的栅极接所述第二NMOS管的栅极，所述第三NMOS管的源极接地，其中，所述第二NMOS管的漏极为所述第三电流镜的输入端，所述第三NMOS管的漏极为所述第三电流镜的输出端。
  9. 根据权利要求8所述的带隙基准电压电路，其特征在于，所述第三电流产生模块包括第四NMOS管、第五NMOS管、第八NPN双极晶体管、第九NPN双极晶体管及第十NPN双极晶体管，所述第四NMOS管的漏极接所述工作电压，所述第四NMOS管的源极接所述第三NMOS管的漏极，所述第四NMOS管的源极还接所述第八NPN双极晶体管的集电极，所述第八NPN双极晶体管的发射极接地，所述第五NMOS管的漏极接所述第五NMOS管的栅极，所述第五NMOS管的栅极还接所述第四NMOS管的栅极，所述第五NMOS管的源极接所述第九NPN双极晶体管的集电极，所述第九NPN双极晶体管的集电极接所述第九NPN双极晶体管的基极，所述第九NPN双极晶体管的基极还接所述第八NPN双极晶体管的基极，所述第九NPN双极晶体管的发射极接地，所述第十NPN双极晶体管的基极接所述第四NMOS管的源极，所述第十NPN双极晶体管的发射极接地，其中，所述第四NMOS管的源极为所述第三电流产生模块的第一输入端，所述第五NMOS管的漏极为所述第三电流产生模块的第二输入端，所述第四NMOS管的漏极为所述第三电流产生模块的第三输入端，所述第十NPN双极晶体管的集电极为所述第三电流产生模块的输出端。
  10. 根据权利要求9所述的带隙基准电压电路，其特征在于，所述第四电流镜包括所述第一PMOS管及第五PMOS管，所述第五PMOS管的源极接所述工作电压，所述第五PMOS管的栅极接所述第一PMOS管的栅极，所述第五PMOS管的漏极接所述第五NMOS管的漏极，其中，所述第一PMOS管的漏极为所述第四电流镜的输入端，所述第五PMOS管的漏极为所述第四电流镜的输出端。
  11. 根据权利要求10所述的带隙基准电压电路，其特征在于，所述第五电流镜包括第六PMOS管及第七PMOS管，所述第六PMOS管的源极接所述工作电压，所述第六PMOS管的栅极接所述第六PMOS管的漏极，所述第六PMOS管的漏极接所述第十NPN双极晶体管的集电极，所述第七PMOS管的源极接所述工作电压，所述第七PMOS管的栅极接所述第六PMOS管的栅极，其中，所述第六PMOS管的漏极为所述第五电流镜的输入端，所述第七PMOS管的漏极为所述第五电流镜的输出端。
  12. 根据权利要求11所述的带隙基准电压电路，其特征在于，所述第三电阻包括数字可调电阻，所述第七PMOS管包括数字可调PMOS管。
  13. 一种带隙基准电压的补偿方法，其特征在于，包括步骤：
    生成具有一阶温度补偿的带隙基准电压；
    利用正温度系数电流和负温度系数电流产生具有二阶正温度系数的补偿电流；
    利用所述补偿电流，对所述带隙基准电压进行二阶温度补偿。
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