WO2023077535A1 - 像素充电方法及显示面板 - Google Patents

像素充电方法及显示面板 Download PDF

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Publication number
WO2023077535A1
WO2023077535A1 PCT/CN2021/129858 CN2021129858W WO2023077535A1 WO 2023077535 A1 WO2023077535 A1 WO 2023077535A1 CN 2021129858 W CN2021129858 W CN 2021129858W WO 2023077535 A1 WO2023077535 A1 WO 2023077535A1
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WO
WIPO (PCT)
Prior art keywords
data line
polarity signal
thin film
film transistor
transistor switch
Prior art date
Application number
PCT/CN2021/129858
Other languages
English (en)
French (fr)
Inventor
潘英一
Original Assignee
Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to KR1020227001228A priority Critical patent/KR20230066260A/ko
Priority to JP2021568782A priority patent/JP2023551609A/ja
Priority to US17/614,734 priority patent/US20240029680A1/en
Publication of WO2023077535A1 publication Critical patent/WO2023077535A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1341—Filling or closing of cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0823—Several active elements per pixel in active matrix panels used to establish symmetry in driving, e.g. with polarity inversion
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame

Definitions

  • the present application relates to the field of display technology, in particular to a pixel charging method and a display panel.
  • FIG. 1 is a schematic diagram of pixel charging of a conventional display panel.
  • the charging time of the conventional display panel is the same for positive polarity and negative polarity.
  • the positive polarity signal P and the negative polarity signal N are transmitted to the data line at the same time. Due to the long falling edge time of the gate signal Gate, there is insufficient time for the positive polarity signal P to charge the pixel V+, and the negative polarity signal N may cause errors in charging the pixel V-. Charge. Based on this, there is a time difference between the output of the positive polarity signal and the negative polarity signal, which can improve charging.
  • the power supply voltage will shift according to the polarity direction, and power supply disturbance will occur.
  • the power supply interference will affect the common electrode voltage, resulting in poor crosstalk in the horizontal direction during display.
  • This application provides a pixel charging method and a display panel to solve the problem that the power supply voltage will shift with the polarity direction when there is a time difference between the output of the positive polarity signal and the negative polarity signal while ensuring a high overall charging rate , and power supply interference occurs, the power supply interference will have an impact on the common electrode voltage, resulting in the technical problem of poor crosstalk in the horizontal direction during display.
  • the present application provides a pixel charging method for a display panel, the display panel includes a pixel array, a first data line, and a second data line, and the first data line and the second data line are both Electrically connected to the pixel array, wherein the pixel charging method includes:
  • a positive polarity signal is input to the first data line, and a negative polarity signal is input to the second data line after a first preset time interval;
  • a negative polarity signal is input to the first data line, and a positive polarity signal is input to the second data line after a second preset time interval;
  • the first preset duration is equal to the second preset duration; both the first preset duration and the second preset duration are between 0.5 microseconds and 1 microsecond.
  • a positive polarity signal is input to the first data line
  • a negative polarity signal is input to the second data line steps, including:
  • the pixel charging method before the step of turning on the thin film transistor switch of the pixel in the current row, it also includes:
  • the first preset duration is the duration of the time difference.
  • the step of turning off the thin film transistor switch of the pixel in the current row includes:
  • the thin film transistor switch corresponding to the first data line inputting the positive polarity signal is turned off after a first time delay
  • the thin film transistor switch corresponding to the second data line inputting the negative polarity signal is turned off after a second time period, and the second time period is longer than the first time period.
  • a signal of negative polarity is input to the first data line, and after a second preset time interval, a signal of positive polarity is input to the second data line steps, including:
  • the pixel charging method before the step of turning on the thin film transistor switch of the pixel in the current row, it also includes:
  • the second preset duration is the duration of the time difference.
  • the step of turning off the thin film transistor switch of the pixel in the current row includes:
  • the thin film transistor switch corresponding to the first data line inputting the negative polarity signal is turned off after a first time delay
  • the thin film transistor switch corresponding to the second data line inputting the positive polarity signal is turned off after a second time delay, and the second time length is longer than the first time length
  • the present application provides a pixel charging method, which is used in a display panel, and the display panel includes a pixel array, a first data line, and a second data line, and the first data line and the second data line Both are electrically connected to the pixel array, and the pixel charging method includes:
  • a positive polarity signal is input to the first data line, and a negative polarity signal is input to the second data line after a first preset time interval;
  • a negative polarity signal is input to the first data line, and a positive polarity signal is input to the second data line after a second preset time interval.
  • the first preset duration is equal to the second preset duration.
  • a positive polarity signal is input to the first data line
  • a negative polarity signal is input to the second data line steps, including:
  • the pixel charging method before the step of turning on the thin film transistor switch of the pixel in the current row, it also includes:
  • the first preset duration is the duration of the time difference.
  • the step of turning off the thin film transistor switch of the pixel in the current row includes:
  • the thin film transistor switch corresponding to the first data line inputting the positive polarity signal is turned off after a first time delay
  • the thin film transistor switch corresponding to the second data line inputting the negative polarity signal is turned off after a second time period, and the second time period is longer than the first time period.
  • a signal of negative polarity is input to the first data line, and after a second preset time interval, a signal of positive polarity is input to the second data line steps, including:
  • the pixel charging method before the step of turning on the thin film transistor switch of the pixel in the current row, it also includes:
  • the second preset duration is the duration of the time difference.
  • the step of turning off the thin film transistor switch of the pixel in the current row includes:
  • the thin film transistor switch corresponding to the first data line inputting the negative polarity signal is turned off after a first time delay
  • the thin film transistor switch corresponding to the second data line inputting the positive polarity signal is turned off after a second time period, and the second time period is longer than the first time period.
  • both the first preset duration and the second preset duration are between 0.5 microseconds and 1 microsecond.
  • the present application also provides a display panel, which includes:
  • a first charging module the first charging module is used to input a positive polarity signal to the first data line in the first frame, and input a negative polarity signal to the second data line after a first preset time interval. Signal;
  • a second charging module the second charging module is used to input a negative polarity signal to the first data line in the second frame, and input a positive polarity signal to the second data line after a second preset time interval. Signal.
  • a positive polarity signal is input to a part of the data lines, and a negative polarity signal is input to other data lines after a first preset time interval to change the positive and negative polarities
  • the phase of the signal (positive polarity first, negative polarity later); in the second frame, input negative polarity signals to some data lines, and then input positive polarity signals to other data lines after a second preset time interval to change
  • the phase of the positive and negative polarity signals (the negative polarity is at the front, and the positive polarity is at the rear); that is, in the first frame, the power supply voltage will shift with the polarity direction, and the first power supply interference will occur; In the second frame, the power supply voltage will shift with the polarity direction, and the second power supply interference will occur; through the mutual cancellation of the two interferences, while ensuring a high overall charging rate, it can avoid the occurrence of horizontal Poor directional crosstalk.
  • FIG. 1 is a schematic diagram of pixel charging of an existing display panel
  • FIG. 2 is a schematic flowchart of a pixel charging method according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a first specific flow chart of a pixel charging method according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of the first charging of the display panel according to the embodiment of the present application.
  • FIG. 5 is a schematic diagram of a second specific flow chart of a pixel charging method according to an embodiment of the present application.
  • FIG. 6 is a second schematic diagram of charging the display panel of the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a pixel charging method according to an embodiment of the present application.
  • An embodiment of the present application provides a pixel charging method for a display panel, where the display panel is a liquid crystal display panel.
  • the display panel includes a pixel array and data lines electrically connected to the pixel array.
  • the data lines include first data lines and second data lines. Both the first data line and the second data line are electrically connected to the pixel array.
  • the pixel charging method of the embodiment of the present application includes:
  • Step S1 In the first frame, input a positive polarity signal to the first data line, and after a first preset time interval, input a negative polarity signal to the second data line;
  • Step S2 In the second frame, input a negative polarity signal to the first data line, and input a positive polarity signal to the second data line after a second preset time interval.
  • a positive polarity signal is input to a part of the data lines, and a negative polarity signal is input to other data lines after a first preset time interval to change the positive and negative polarity signals.
  • Phase positive polarity first, negative polarity later
  • in the second frame input negative polarity signals to some data lines, and then input positive polarity signals to other data lines after a second preset time interval to change the positive and negative
  • the phase of the polarity signal (the negative polarity is at the front and the positive polarity is at the rear); that is, in the first frame, the power supply voltage will shift with the polarity direction, and the first power supply interference will occur; in the second frame In the frame picture, the power supply voltage will shift with the polarity direction, and the second power supply interference will occur; through the mutual cancellation of the two interferences, while ensuring a high overall charging rate, horizontal crosstalk can be avoided during display bad.
  • FIG. 3 is a schematic diagram of a first specific flow chart of a pixel charging method according to an embodiment of the present application.
  • input a positive polarity signal to the first data line and after a first preset time interval, the steps of inputting a negative polarity signal to the second data line include:
  • Step S11 Turn on the TFT switches of the pixels in the current row
  • Step S12 Inputting a positive polarity signal to the first data line
  • Step S13 inputting a negative polarity signal to the second data line at intervals of a first preset duration
  • Step S14 Turn off the TFT switches of the pixels in the current row.
  • the display panel may include a display substrate and multiple rows of scanning lines, multiple columns of data lines, and multiple rows and columns of pixels disposed on the display substrate.
  • each pixel is electrically connected to a row of scan lines and a column of data lines, so that when a certain row of scan lines inputs a gate signal to turn on the thin film transistor switch and a certain column of data lines writes a voltage signal, the voltage signal can be charged into In the pixels connected to the scan line of the row and the data line of the column.
  • the gate of the thin film transistor of each pixel is electrically connected to a scan line
  • the source or drain of the thin film transistor of each pixel is electrically connected to a data line.
  • a positive polarity signal may be input to the first data line according to the confirmation result of the polarity of the voltage signal to be input by the first data line and the second data line respectively.
  • the confirmation result it is necessary to input a positive polarity signal to the first data line in the i-th picture frame, then when the thin film transistor switch of the current row is turned on, just input a positive polarity signal to the first data line, i is a positive integer.
  • step S13 based on the example in step S12, according to the above-mentioned confirmation result: input negative polarity signal to the second data line, then input negative polarity signal to the second data line after a first preset time interval. signal.
  • the first preset duration may be between 0.5 microseconds (inclusive) and 1 microsecond (inclusive).
  • the first preset duration may also be 0.6 microseconds, 0.7 microseconds, 0.8 microseconds or 0.9 microseconds.
  • FIG. 4 is a schematic diagram of a first charging of a display panel according to an embodiment of the present application.
  • the switch of the thin film transistor switch is controlled by the gate signal, and the positive polarity signal is input into the corresponding data line by a preset period of time earlier than the negative polarity signal to change the positive polarity signal P and the negative polarity signal
  • the phase of N (the positive polarity is at the front and the negative polarity is at the back), thereby increasing the charging time of the positive polarity signal P, increasing the charging rate, reducing the charging time of the negative polarity signal N, avoiding wrong charging, and thus improving the charging of the entire display panel Rate.
  • step S14 the step of turning off the thin film transistor switch of the pixel in the current row includes: suspending or stopping sending the gate signal to the pixel in the current row; The duration is turned off; the thin film transistor switch corresponding to the second data line inputting the negative polarity signal is turned off after a delay of the second duration.
  • the second duration is greater than the first duration.
  • the sending of the gate signal to the pixels in the current row is suspended or stopped, that is, the gate signal of the scanning line in the current row is turned off. Since the falling edge of the gate signal takes a long time, and the voltage of the positive signal is high, and the voltage of the negative signal is low, so even with the same gate signal, the thin film transistor switch corresponding to the positive signal will be shorter than that of the thin film transistor corresponding to the negative signal. The transistor switch turns off early.
  • the step of turning on the thin film transistor switch of the pixel in the current row also includes: acquiring the thin film transistor switch corresponding to the first data line inputting the positive polarity signal and the thin film transistor switch corresponding to the second data line inputting the negative polarity signal
  • the time difference of the closing time; the first preset duration is the duration of the time difference.
  • the pixel includes a TFT switch and a pixel electrode electrically connected to the TFT switch.
  • the thin film transistor switch is a P-type transistor switch or an N-type transistor switch.
  • the thin film transistor switch corresponding to the positive polarity signal is turned off earlier than the thin film transistor switch corresponding to the negative polarity signal, there is a time difference between the two, and the embodiment of the present application is to obtain the duration of the time difference.
  • the time difference may be an average value or a median of time differences obtained by turning off the thin-film transistor switch for multiple times in the current row, or other values.
  • the duration of the time difference is between 0.5 microseconds (inclusive) and 1 microsecond (inclusive).
  • the duration of the time difference may be 0.6 microseconds, 0.7 microseconds, 0.8 microseconds or 0.9 microseconds.
  • FIG. 5 is a second specific flowchart of the pixel charging method according to the embodiment of the present application.
  • the step of inputting a negative polarity signal to the first data line, and after a second preset period of time, inputting a positive polarity signal to the second data line includes:
  • Step S21 Turn on the TFT switches of the pixels in the current row
  • Step S22 inputting a negative polarity signal to the first data line
  • Step S23 inputting a positive polarity signal to the second data line at intervals of a second preset duration
  • Step S24 Turn off the TFT switches of the pixels in the current row.
  • the display panel may include a display substrate and multiple rows of scanning lines, multiple columns of data lines, and multiple rows and columns of pixels disposed on the display substrate.
  • each pixel is electrically connected to a row of scan lines and a column of data lines, so that when a certain row of scan lines inputs a gate signal to turn on the thin film transistor switch and a certain column of data lines writes a voltage signal, the voltage signal can be charged into In the pixels connected to the scan line of the row and the data line of the column.
  • the gate of the thin film transistor of each pixel is electrically connected to a scan line
  • the source or drain of the thin film transistor of each pixel is electrically connected to a data line.
  • a signal of negative polarity may be input to the first data line according to the result of confirming the polarity of the voltage signal to be input by the first data line and the second data line respectively. For example, according to the confirmation result, it is necessary to input a negative polarity signal to the first data line in the i-th picture frame, then when the thin film transistor switch of the current row is turned on, just input a negative polarity signal to the first data line, i is a positive integer.
  • step S23 based on the example in step S12, according to the above-mentioned confirmation result: input a negative polarity signal to the second data line, then input a positive polarity signal to the second data line after an interval of a second preset time length. signal.
  • the second preset duration may be between 0.5 microseconds (inclusive) and 1 microsecond (inclusive).
  • the second preset duration may also be 0.6 microseconds, 0.7 microseconds, 0.8 microseconds or 0.9 microseconds.
  • FIG. 6 is a schematic diagram of the second charging of the display panel according to the embodiment of the present application.
  • the switch of the thin film transistor switch is controlled by the gate signal, and the negative polarity signal is used to input the corresponding data line for a second preset time earlier than the positive polarity signal to change the positive polarity signal P and the negative polarity signal.
  • the phase of N (the negative polarity is at the front and the positive polarity is at the back), thereby increasing the charging time of the negative polarity signal N, increasing the charging rate, reducing the charging time of the positive polarity signal N, avoiding wrong charging, and thus improving the charging of the entire display panel Rate.
  • step S24 the step of turning off the thin film transistor switch of the pixel in the current row includes: suspending or stopping sending the gate signal to the pixel in the current row; The duration is turned off; the thin film transistor switch corresponding to the second data line inputting the positive polarity signal is turned off after a second duration delay.
  • the second duration is greater than the first duration.
  • the sending of the gate signal to the pixels in the current row is suspended or stopped, that is, the gate signal of the scanning line in the current row is turned off. Since the falling edge of the gate signal takes a long time, and the voltage of the positive signal is high, and the voltage of the negative signal is low, so even with the same gate signal, the thin film transistor switch corresponding to the positive signal will be shorter than that of the thin film transistor corresponding to the negative signal. The transistor switch turns off early.
  • the step of turning on the thin film transistor switch of the current row of pixels also includes: obtaining the thin film transistor switch corresponding to the first data line inputting the negative polarity signal and the thin film transistor switch corresponding to the second data line inputting the positive polarity signal
  • the time difference of the closing time; the second preset duration is the duration of the time difference.
  • the pixel includes a TFT switch and a pixel electrode electrically connected to the TFT switch.
  • the thin film transistor switch is a P-type transistor switch or an N-type transistor switch.
  • the thin film transistor switch corresponding to the positive polarity signal is turned off earlier than the thin film transistor switch corresponding to the negative polarity signal, there is a time difference between the two, and the embodiment of the present application is to obtain the duration of the time difference.
  • the time difference may be an average value or a median of time differences obtained by turning off the thin-film transistor switch for multiple times in the current row, or other values.
  • the duration of the time difference is between 0.5 microseconds (inclusive) and 1 microsecond (inclusive).
  • the duration of the time difference may be 0.6 microseconds, 0.7 microseconds, 0.8 microseconds or 0.9 microseconds.
  • the first preset duration is equal to the second preset duration. That is to say, in the pixel charging method of the present application, in the first frame of the picture, a positive polarity signal is input to a part of the data lines, and a negative polarity signal is input to other data lines after a first preset time interval to change the positive and negative polarity signals phase (positive polarity is at the front and negative polarity is at the back); in the second frame, input negative polarity signals to some data lines, and then input positive polarity signals to other data lines after a second preset time interval to change the positive polarity.
  • the phase of the negative polarity signal (the negative polarity is at the front, and the positive polarity is at the rear); that is, in the first frame, the power supply voltage will shift with the polarity direction, and the first power supply interference will occur; In the second frame, the power supply voltage will shift with the polarity direction, and the second power supply interference will occur; through the mutual cancellation of the two interferences, while ensuring a high overall charging rate, it can avoid the horizontal direction when displaying Bad crosstalk.
  • FIG. 7 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • the embodiment of the application also relates to a display panel 1000 , which includes a first charging module 1001 and a second charging module 1002 .
  • the first charging module 1001 is used for inputting a positive polarity signal to the first data line in the first frame, and inputting a negative polarity signal to the second data line after a first preset time interval.
  • the second charging module 1002 is used for inputting a negative polarity signal to the first data line in the second frame, and inputting a positive polarity signal to the second data line after a second preset time interval.
  • the display panel in the embodiment of the present application adopts the pixel charging method described above, for details, reference may be made to the above description, which will not be repeated here.
  • a positive polarity signal is input to a part of the data lines in the first frame, and a negative polarity signal is input to other data lines after a first preset time interval to change the phase of the positive and negative polarity signals (positive polarity In the second frame, input negative polarity signals to some data lines, and then input positive polarity signals to other data lines after a second preset time interval to change the positive and negative polarity signals
  • the phase of the phase negative polarity in front, positive polarity in the rear
  • the power supply voltage will shift with the direction of the polarity, and the first power supply interference occurs
  • the power supply voltage will shift with the polarity direction, and the second power supply interference will occur; through the mutual cancellation of the two interferences, while ensuring a high overall charging rate, it can avoid poor crosstalk in the horizontal direction during display.

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Abstract

一种像素充电方法及显示面板(1000)，在第一帧画面，向一部分数据线输入正极性信号(P)，间隔第一预设时长后再向其他的数据线输入负极性信号(N)；在第二帧画面，向一部分数据线输入负极性信号(N)，间隔第二预设时长后再向其他的数据线输入正极性信号(P)，来改变正负极性信号的相位。

Description

像素充电方法及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素充电方法及显示面板。
 背景技术
请参阅图1，图1为现有的显示面板的像素充电示意图。如图1所示，现有的显示面板进行正、负极性的充电时间是一样的。正极性信号P和负极性信号N同时传输到数据线，由于栅极信号Gate下降沿时间较长，存在正极性信号P对像素充电V+时间不足，负极性信号N对像素充电V-可能出现错充。基于此，通过正极性信号和负极性信号的输出存在时间差异，可以对充电起到改善作用。
然而，正极性信号和负极性信号的输出存在时间差异时，电源电压会随着极性方向发生偏移，并发生电源干扰。该电源干扰会对公共电极电压有影响,使得显示时发生水平方向串扰不良。
 技术问题
本申请提供一种像素充电方法及显示面板，以解决在保证整体充电率较高的同时，解决正极性信号和负极性信号的输出存在时间差异时，电源电压会随着极性方向发生偏移，并发生电源干扰，该电源干扰会对公共电极电压有影响,使得显示时发生水平方向串扰不良的技术问题。
 技术解决方案
第一方面，本申请提供一种像素充电方法，用于显示面板，所述显示面板包括像素阵列、第一数据线以及第二数据线，所述第一数据线以及所述第二数据线均与所述像素阵列电连接，其中，所述像素充电方法包括：
在第一帧画面中，向所述第一数据线输入正极性信号，间隔第一预设时长后，向所述第二数据线输入负极性信号；以及
在第二帧画面中，向所述第一数据线输入负极性信号，间隔第二预设时长后，向所述第二数据线输入正极性信号；
所述第一预设时长等于所述第二预设时长；所述第一预设时长与所述第二预设时长均介于0.5微秒至1微秒之间。
在本申请提供的像素充电方法中，所述在第一帧画面中，向所述第一数据线输入正极性信号，间隔第一预设时长后，向所述第二数据线输入负极性信号的步骤，包括：
打开当前行像素的薄膜晶体管开关；
向所述第一数据线输入正极性信号；
间隔第一预设时长，向所述第二数据线输入负极性信号；
关闭所述当前行像素的薄膜晶体管开关。
在本申请提供的像素充电方法中，所述打开当前行像素的薄膜晶体管开关的步骤之前，还包括：
获取输入正极性信号的所述第一数据线对应的薄膜晶体管开关关闭时间与输入负极性信号的所述第二数据线对应的薄膜晶体管开关关闭时间的时间差；其中，所述第一预设时长为所述时间差的时长。
在本申请提供的像素充电方法中，所述关闭当前行像素的薄膜晶体管开关的步骤，包括：
暂停或停止向所述当前行像素发送栅极信号；
输入正极性信号的所述第一数据线对应的薄膜晶体管开关延时第一时长关闭；
输入负极性信号的所述第二数据线对应的薄膜晶体管开关延时第二时长关闭，所述第二时长大于所述第一时长。
在本申请提供的像素充电方法中，所述在第二帧画面中，向所述第一数据线输入负极性信号，间隔第二预设时长后，向所述第二数据线输入正极性信号的步骤，包括：
打开当前行像素的薄膜晶体管开关；
向所述第一数据线输入负极性信号；
间隔第二预设时长，向所述第二数据线输入正极性信号；
关闭所述当前行像素的薄膜晶体管开关。
在本申请提供的像素充电方法中，所述打开当前行像素的薄膜晶体管开关的步骤之前，还包括：
获取输入负极性信号的所述第一数据线对应的薄膜晶体管开关关闭时间与输入正极性信号的所述第二数据线对应的薄膜晶体管开关关闭时间的时间差；其中，所述第二预设时长为所述时间差的时长。
在本申请提供的像素充电方法中，所述关闭当前行像素的薄膜晶体管开关的步骤，包括：
暂停或停止向所述当前行像素发送栅极信号；
输入负极性信号的所述第一数据线对应的薄膜晶体管开关延时第一时长关闭；
输入正极性信号的所述第二数据线对应的薄膜晶体管开关延时第二时长关闭，所述第二时长大于所述第一时长
第二方面，本申请提供一种像素充电方法，其用于显示面板，所述显示面板包括像素阵列、第一数据线以及第二数据线，所述第一数据线以及所述第二数据线均与所述像素阵列电连接，所述像素充电方法包括：
在第一帧画面中，向所述第一数据线输入正极性信号，间隔第一预设时长后，向所述第二数据线输入负极性信号；以及
在第二帧画面中，向所述第一数据线输入负极性信号，间隔第二预设时长后，向所述第二数据线输入正极性信号。
在本申请提供的像素充电方法中，所述第一预设时长等于所述第二预设时长。
在本申请提供的像素充电方法中，所述在第一帧画面中，向所述第一数据线输入正极性信号，间隔第一预设时长后，向所述第二数据线输入负极性信号的步骤，包括：
打开当前行像素的薄膜晶体管开关；
向所述第一数据线输入正极性信号；
间隔第一预设时长，向所述第二数据线输入负极性信号；
关闭所述当前行像素的薄膜晶体管开关。
在本申请提供的像素充电方法中，所述打开当前行像素的薄膜晶体管开关的步骤之前，还包括：
获取输入正极性信号的所述第一数据线对应的薄膜晶体管开关关闭时间与输入负极性信号的所述第二数据线对应的薄膜晶体管开关关闭时间的时间差；其中，所述第一预设时长为所述时间差的时长。
在本申请提供的像素充电方法中，所述关闭当前行像素的薄膜晶体管开关的步骤，包括：
暂停或停止向所述当前行像素发送栅极信号；
输入正极性信号的所述第一数据线对应的薄膜晶体管开关延时第一时长关闭；
输入负极性信号的所述第二数据线对应的薄膜晶体管开关延时第二时长关闭，所述第二时长大于所述第一时长。
在本申请提供的像素充电方法中，所述在第二帧画面中，向所述第一数据线输入负极性信号，间隔第二预设时长后，向所述第二数据线输入正极性信号的步骤，包括：
打开当前行像素的薄膜晶体管开关；
向所述第一数据线输入负极性信号；
间隔第二预设时长，向所述第二数据线输入正极性信号；
关闭所述当前行像素的薄膜晶体管开关。
在本申请提供的像素充电方法中，所述打开当前行像素的薄膜晶体管开关的步骤之前，还包括：
获取输入负极性信号的所述第一数据线对应的薄膜晶体管开关关闭时间与输入正极性信号的所述第二数据线对应的薄膜晶体管开关关闭时间的时间差；其中，所述第二预设时长为所述时间差的时长。
在本申请提供的像素充电方法中，所述关闭当前行像素的薄膜晶体管开关的步骤，包括：
暂停或停止向所述当前行像素发送栅极信号；
输入负极性信号的所述第一数据线对应的薄膜晶体管开关延时第一时长关闭；
输入正极性信号的所述第二数据线对应的薄膜晶体管开关延时第二时长关闭，所述第二时长大于所述第一时长。
在本申请提供的像素充电方法中，所述第一预设时长与所述第二预设时长均介于0.5微秒至1微秒之间。
第三方面，本申请还提供一种显示面板，其包括：
第一充电模块，所述第一充电模块用于在第一帧画面中，向所述第一数据线输入正极性信号，间隔第一预设时长后，向所述第二数据线输入负极性信号；
第二充电模块，所述第二充电模块用于在第二帧画面中，向所述第一数据线输入负极性信号，间隔第二预设时长后，向所述第二数据线输入正极性信号。
 有益效果
本申请的像素充电方法及显示面板中，在第一帧画面，向一部分数据线输入正极性信号，间隔第一预设时长后再向其他的数据线输入负极性信号，来改变正负极性信号的相位（正极性靠前，负极性靠后）；在第二帧画面，向一部分数据线输入负极性信号，间隔第二预设时长后再向其他的数据线输入正极性信号，来改变正负极性信号的相位（负极性靠前，正极性靠后）；也即，在第一帧画面中，电源电压会随着极性方向发生偏移，并发生第一次电源干扰；在第二帧画面中，电源电压会随着极性方向发生偏移，并发生第二次电源干扰；通过两次干扰的相互抵消，在保证整体充电率较高的同时，可以避免显示时发生水平方向串扰不良。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有的显示面板的像素充电示意图；
图2为本申请实施例的像素充电方法的流程示意图；
图3为本申请实施例的像素充电方法的第一种具体流程示意图；
图4为本申请实施例的显示面板的第一种充电示意图；
图5为本申请实施例的像素充电方法的第二种具体流程示意图；
图6为本申请实施例的显示面板的第二种充电示意图;
图7为本申请实施例的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。本申请的权利要求书以及说明书中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。
请参阅图2，图2为本申请实施例的像素充电方法的流程示意图。本申请实施例提供一种像素充电方法，用于显示面板，该显示面板为液晶显示面板。
其中，显示面板包括像素阵列以及电连接像素阵列的数据线。数据线包括第一数据线以及第二数据线。第一数据线以及第二数据线均与像素阵列电性连接。本申请实施例的像素充电方法包括：
步骤S1：在第一帧画面中，向第一数据线输入正极性信号，间隔第一预设时长后，向第二数据线输入负极性信号；
步骤S2：在第二帧画面中，向第一数据线输入负极性信号，间隔第二预设时长后，向第二数据线输入正极性信号。
本申请实施例的像素充电方法，在第一帧画面，向一部分数据线输入正极性信号，间隔第一预设时长后再向其他的数据线输入负极性信号，来改变正负极性信号的相位（正极性靠前，负极性靠后）；在第二帧画面，向一部分数据线输入负极性信号，间隔第二预设时长后再向其他的数据线输入正极性信号，来改变正负极性信号的相位（负极性靠前，正极性靠后）；也即，在第一帧画面中，电源电压会随着极性方向发生偏移，并发生第一次电源干扰；在第二帧画面中，电源电压会随着极性方向发生偏移，并发生第二次电源干扰；通过两次干扰的相互抵消，在保证整体充电率较高的同时，可以避免显示时发生水平方向串扰不良。
具体的，请参阅图3，图3为本申请实施例的像素充电方法的第一种具体流程示意图。结合图2、图3所示，在第一帧画面中，向第一数据线输入正极性信号，间隔第一预设时长后，向第二数据线输入负极性信号的步骤，包括：
步骤S11：打开当前行像素的薄膜晶体管开关；
步骤S12：向第一数据线输入正极性信号；
步骤S13：间隔第一预设时长，向第二数据线输入负极性信号；
步骤S14：关闭当前行像素的薄膜晶体管开关。
其中，在步骤S11中，显示面板可以包括显示基板和设置于显示基板上的多行扫描线、多列数据线、多行多列像素。应理解的是，每一像素分别与一行扫描线和一列数据线电连接，从而当某行扫描线输入栅极信号打开薄膜晶体管开关，某列数据线写入电压信号时，电压信号可以充入与该行扫描线和该列数据线连接的像素中。可选的，每个像素的薄膜晶体管的栅极电连接一扫描线，每个像素的薄膜晶体管的源极或漏极电连接一数据线。
其中，在步骤S12中，可以根据第一数据线和第二数据线各自需输入的电压信号的极性的确认结果；向第一数据线输入正极性信号。举个例子，根据确认结果，需要在第i画面帧中，向第一数据线输入正极性信号，那么当当前行的薄膜晶体管开关打开时，便向第一数据线输入正极性信号即可，i为正整数。
其中，在步骤S13中，以步骤S12中的例子为基础，根据上述的确认结果：向第二数据线输入负极性信号，那么在间隔第一预设时长后，向第二数据线输入负极性信号即可。可选的，第一预设时长可以介于0.5微秒（含0.5微秒）至1微秒（含1微秒）之间。在本实施例中，第一预设时长也可以是0.6微秒、0.7微秒、0.8微秒或0.9微秒。
具体的，可参照图4，图4为本申请实施例的显示面板的第一种充电示意图。本申请实施例的像素充电方法通过栅极信号控制薄膜晶体管开关的开关，采用正极性信号较于负极性信号提前第一预设时长输入对应的数据线，来改变正极性信号P和负极性信号N的相位（正极性靠前，负极性靠后），进而增加正极性信号P的充电时间，提高充电率，减小负极性信号N的充电时间，避免错充，从而提升整个显示面板的充电率。
其中，在步骤S14中，关闭当前行像素的薄膜晶体管开关的步骤，包括：暂停或停止向当前行像素发送栅极信号；输入正极性信号的第一数据线对应的薄膜晶体管开关延时第一时长关闭；输入负极性信号的第二数据线对应的薄膜晶体管开关延时第二时长关闭。第二时长大于第一时长。
具体的，暂停或停止向所述当前行像素发送栅极信号，即关闭当前行扫描线的栅极信号。由于栅极信号下降沿的时间较长，且正极性信号的电压高，负极性信号的电压低，所以即使同样的栅极信号，正极性信号对应的薄膜晶体管开关都会较负极性信号对应的薄膜晶体管开关早关闭。
进一步的，打开当前行像素的薄膜晶体管开关的步骤之前，还包括：获取输入正极性信号的第一数据线对应的薄膜晶体管开关关闭时间与输入负极性信号的第二数据线对应的薄膜晶体管开关关闭时间的时间差；第一预设时长为时间差的时长。
具体的，像素包括薄膜晶体管开关和电连接于薄膜晶体管开关的像素电极。薄膜晶体管开关为P型晶体管开关或N型晶体管开关。通过在显示面板的试运行阶段，关闭当前行像素的栅极信号，使得当前行像素的薄膜晶体管开关关闭。其中，当栅极信号小于其对应的数据线的电压信号时，薄膜晶体管开关视为关闭。而在薄膜晶体管开关关闭的过程中，由于栅极信号下降沿的时间较长，且正极性电压高，负极性的电压低，所以即使同样的栅极信号，正极性对应的薄膜晶体管开关都会较负极性对应的薄膜晶体管开关早关闭，因此在正负极性信号同时输入对应的数据线时，正极充电时间较负极充电时间更短。
也因为正极性信号对应的薄膜晶体管开关较负极性信号对应的薄膜晶体管开关早关闭，所以二者之间具有关闭时间差，而本申请实施例是要获取该时间差的时长。可选的，时间差可以是当前行多次关闭薄膜晶体管开关获取的时间差的平均值或中位数，也可以是其他数值。
可选的，时间差的时长介于0.5微秒（含0.5微秒）至1微秒（含1微秒）之间。在本实施例中，时间差的时长可以是0.6微秒、0.7微秒、0.8微秒或0.9微秒。
具体的，请参阅图5，图5为本申请实施例的像素充电方法的第二种具体流程示意图。结合图2、图5所示，在第二帧画面中，向第一数据线输入负极性信号，间隔第二预设时长后，向第二数据线输入正极性信号的步骤，包括：
步骤S21：打开当前行像素的薄膜晶体管开关；
步骤S22：向第一数据线输入负极性信号；
步骤S23：间隔第二预设时长，向第二数据线输入正极性信号；
步骤S24：关闭当前行像素的薄膜晶体管开关。
其中，在步骤S21中，显示面板可以包括显示基板和设置于显示基板上的多行扫描线、多列数据线、多行多列像素。应理解的是，每一像素分别与一行扫描线和一列数据线电连接，从而当某行扫描线输入栅极信号打开薄膜晶体管开关，某列数据线写入电压信号时，电压信号可以充入与该行扫描线和该列数据线连接的像素中。可选的，每个像素的薄膜晶体管的栅极电连接一扫描线，每个像素的薄膜晶体管的源极或漏极电连接一数据线。
其中，在步骤S22中，可以根据第一数据线和第二数据线各自需输入的电压信号的极性的确认结果；向第一数据线输入负极性信号。举个例子，根据确认结果，需要在第i画面帧中，向第一数据线输入负极性信号，那么当当前行的薄膜晶体管开关打开时，便向第一数据线输入负极性信号即可，i为正整数。
其中，在步骤S23中，以步骤S12中的例子为基础，根据上述的确认结果：向第二数据线输入负极性信号，那么在间隔第二预设时长后，向第二数据线输入正极性信号即可。可选的，第二预设时长可以介于0.5微秒（含0.5微秒）至1微秒（含1微秒）之间。在本实施例中，第二预设时长也可以是0.6微秒、0.7微秒、0.8微秒或0.9微秒。
具体的，可参照图6，图6为本申请实施例的显示面板的第二种充电示意图。本申请实施例的像素充电方法通过栅极信号控制薄膜晶体管开关的开关，采用负极性信号较于正极性信号提前第二预设时长输入对应的数据线，来改变正极性信号P和负极性信号N的相位（负极性靠前，正极性靠后），进而增加负极性信号N的充电时间，提高充电率，减小正极性信号N的充电时间，避免错充，从而提升整个显示面板的充电率。
其中，在步骤S24中，关闭当前行像素的薄膜晶体管开关的步骤，包括：暂停或停止向当前行像素发送栅极信号；输入负极性信号的第一数据线对应的薄膜晶体管开关延时第一时长关闭；输入正极性信号的第二数据线对应的薄膜晶体管开关延时第二时长关闭。第二时长大于第一时长。
具体的，暂停或停止向所述当前行像素发送栅极信号，即关闭当前行扫描线的栅极信号。由于栅极信号下降沿的时间较长，且正极性信号的电压高，负极性信号的电压低，所以即使同样的栅极信号，正极性信号对应的薄膜晶体管开关都会较负极性信号对应的薄膜晶体管开关早关闭。
进一步的，打开当前行像素的薄膜晶体管开关的步骤之前，还包括：获取输入负极性信号的第一数据线对应的薄膜晶体管开关关闭时间与输入正极性信号的第二数据线对应的薄膜晶体管开关关闭时间的时间差；第二预设时长为时间差的时长。
具体的，像素包括薄膜晶体管开关和电连接于薄膜晶体管开关的像素电极。薄膜晶体管开关为P型晶体管开关或N型晶体管开关。通过在显示面板的试运行阶段，关闭当前行像素的栅极信号，使得当前行像素的薄膜晶体管开关关闭。其中，当栅极信号小于其对应的数据线的电压信号时，薄膜晶体管开关视为关闭。而在薄膜晶体管开关关闭的过程中，由于栅极信号下降沿的时间较长，且正极性电压高，负极性的电压低，所以即使同样的栅极信号，正极性对应的薄膜晶体管开关都会较负极性对应的薄膜晶体管开关早关闭，因此在正负极性信号同时输入对应的数据线时，正极充电时间较负极充电时间更短。
也因为正极性信号对应的薄膜晶体管开关较负极性信号对应的薄膜晶体管开关早关闭，所以二者之间具有关闭时间差，而本申请实施例是要获取该时间差的时长。可选的，时间差可以是当前行多次关闭薄膜晶体管开关获取的时间差的平均值或中位数，也可以是其他数值。
可选的，时间差的时长介于0.5微秒（含0.5微秒）至1微秒（含1微秒）之间。在本实施例中，时间差的时长可以是0.6微秒、0.7微秒、0.8微秒或0.9微秒。
其中，在本申请实施例中，第一预设时长等于第二预设时长。也即，本申请的像素充电方法，在第一帧画面，向一部分数据线输入正极性信号，间隔第一预设时长后再向其他的数据线输入负极性信号，来改变正负极性信号的相位（正极性靠前，负极性靠后）；在第二帧画面，向一部分数据线输入负极性信号，间隔第二预设时长后再向其他的数据线输入正极性信号，来改变正负极性信号的相位（负极性靠前，正极性靠后）；也即，在第一帧画面中，电源电压会随着极性方向发生偏移，并发生第一次电源干扰；在第二帧画面中，电源电压会随着极性方向发生偏移，并发生第二次电源干扰；通过两次干扰的相互抵消，在保证整体充电率较高的同时，可以避免显示时发生水平方向串扰不良。
请参阅图7，图7为本申请实施例的显示面板的结构示意图。如图7所示，申请实施例还涉及一种显示面板1000，其包括第一充电模块1001和第二充电模块1002。其中，第一充电模块1001用于在第一帧画面中，向第一数据线输入正极性信号，间隔第一预设时长后，向第二数据线输入负极性信号。第二充电模块1002用于在第二帧画面中，向第一数据线输入负极性信号，间隔第二预设时长后，向第二数据线输入正极性信号。需要说明的是，本申请实施例中的显示面板采用以上所述的像素充电方法，具体可参照以上所示，在此不做赘述。
本申请的显示面板，在第一帧画面，向一部分数据线输入正极性信号，间隔第一预设时长后再向其他的数据线输入负极性信号，来改变正负极性信号的相位（正极性靠前，负极性靠后）；在第二帧画面，向一部分数据线输入负极性信号，间隔第二预设时长后再向其他的数据线输入正极性信号，来改变正负极性信号的相位（负极性靠前，正极性靠后）；也即，在第一帧画面中，电源电压会随着极性方向发生偏移，并发生第一次电源干扰；在第二帧画面中，电源电压会随着极性方向发生偏移，并发生第二次电源干扰；通过两次干扰的相互抵消，在保证整体充电率较高的同时，可以避免显示时发生水平方向串扰不良。
以上对本申请实施例所提供的像素充电方法及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (17)

  1. 一种像素充电方法，用于显示面板，所述显示面板包括像素阵列、第一数据线以及第二数据线，所述第一数据线以及所述第二数据线均与所述像素阵列电连接，其中，所述像素充电方法包括：
    在第一帧画面中，向所述第一数据线输入正极性信号，间隔第一预设时长后，向所述第二数据线输入负极性信号；以及
    在第二帧画面中，向所述第一数据线输入负极性信号，间隔第二预设时长后，向所述第二数据线输入正极性信号；
    所述第一预设时长等于所述第二预设时长；所述第一预设时长与所述第二预设时长均介于0.5微秒至1微秒之间。
  2. 根据权利要求1所述的像素充电方法，其中，所述在第一帧画面中，向所述第一数据线输入正极性信号，间隔第一预设时长后，向所述第二数据线输入负极性信号的步骤，包括：
    打开当前行像素的薄膜晶体管开关；
    向所述第一数据线输入正极性信号；
    间隔第一预设时长，向所述第二数据线输入负极性信号；
    关闭所述当前行像素的薄膜晶体管开关。
  3. 根据权利要求2所述的像素充电方法，其中，所述打开当前行像素的薄膜晶体管开关的步骤之前，还包括：
    获取输入正极性信号的所述第一数据线对应的薄膜晶体管开关关闭时间与输入负极性信号的所述第二数据线对应的薄膜晶体管开关关闭时间的时间差；其中，所述第一预设时长为所述时间差的时长。
  4. 根据权利要求2所述的像素充电方法，其中，所述关闭当前行像素的薄膜晶体管开关的步骤，包括：
    暂停或停止向所述当前行像素发送栅极信号；
    输入正极性信号的所述第一数据线对应的薄膜晶体管开关延时第一时长关闭；
    输入负极性信号的所述第二数据线对应的薄膜晶体管开关延时第二时长关闭，所述第二时长大于所述第一时长。
  5. 根据权利要求1所述的像素充电方法，其中，所述在第二帧画面中，向所述第一数据线输入负极性信号，间隔第二预设时长后，向所述第二数据线输入正极性信号的步骤，包括：
    打开当前行像素的薄膜晶体管开关；
    向所述第一数据线输入负极性信号；
    间隔第二预设时长，向所述第二数据线输入正极性信号；
    关闭所述当前行像素的薄膜晶体管开关。
  6. 根据权利要求5所述的像素充电方法，其中，所述打开当前行像素的薄膜晶体管开关的步骤之前，还包括：
    获取输入负极性信号的所述第一数据线对应的薄膜晶体管开关关闭时间与输入正极性信号的所述第二数据线对应的薄膜晶体管开关关闭时间的时间差；其中，所述第二预设时长为所述时间差的时长。
  7. 根据权利要求5所述的像素充电方法，其中，所述关闭当前行像素的薄膜晶体管开关的步骤，包括：
    暂停或停止向所述当前行像素发送栅极信号；
    输入负极性信号的所述第一数据线对应的薄膜晶体管开关延时第一时长关闭；
    输入正极性信号的所述第二数据线对应的薄膜晶体管开关延时第二时长关闭，所述第二时长大于所述第一时长。
  8. 一种像素充电方法，用于显示面板，所述显示面板包括像素阵列、第一数据线以及第二数据线，所述第一数据线以及所述第二数据线均与所述像素阵列电连接，其中，所述像素充电方法包括：
    在第一帧画面中，向所述第一数据线输入正极性信号，间隔第一预设时长后，向所述第二数据线输入负极性信号；以及
    在第二帧画面中，向所述第一数据线输入负极性信号，间隔第二预设时长后，向所述第二数据线输入正极性信号。
  9. 根据权利要求8所述的像素充电方法，其中，所述第一预设时长等于所述第二预设时长。
  10. 根据权利要求8所述的像素充电方法，其中，所述在第一帧画面中，向所述第一数据线输入正极性信号，间隔第一预设时长后，向所述第二数据线输入负极性信号的步骤，包括：
    打开当前行像素的薄膜晶体管开关；
    向所述第一数据线输入正极性信号；
    间隔第一预设时长，向所述第二数据线输入负极性信号；
    关闭所述当前行像素的薄膜晶体管开关。
  11. 根据权利要求10所述的像素充电方法，其中，所述打开当前行像素的薄膜晶体管开关的步骤之前，还包括：
    获取输入正极性信号的所述第一数据线对应的薄膜晶体管开关关闭时间与输入负极性信号的所述第二数据线对应的薄膜晶体管开关关闭时间的时间差；其中，所述第一预设时长为所述时间差的时长。
  12. 根据权利要求10所述的像素充电方法，其中，所述关闭当前行像素的薄膜晶体管开关的步骤，包括：
    暂停或停止向所述当前行像素发送栅极信号；
    输入正极性信号的所述第一数据线对应的薄膜晶体管开关延时第一时长关闭；
    输入负极性信号的所述第二数据线对应的薄膜晶体管开关延时第二时长关闭，所述第二时长大于所述第一时长。
  13. 根据权利要求8所述的像素充电方法，其中，所述在第二帧画面中，向所述第一数据线输入负极性信号，间隔第二预设时长后，向所述第二数据线输入正极性信号的步骤，包括：
    打开当前行像素的薄膜晶体管开关；
    向所述第一数据线输入负极性信号；
    间隔第二预设时长，向所述第二数据线输入正极性信号；
    关闭所述当前行像素的薄膜晶体管开关。
  14. 根据权利要求13所述的像素充电方法，其中，所述打开当前行像素的薄膜晶体管开关的步骤之前，还包括：
    获取输入负极性信号的所述第一数据线对应的薄膜晶体管开关关闭时间与输入正极性信号的所述第二数据线对应的薄膜晶体管开关关闭时间的时间差；其中，所述第二预设时长为所述时间差的时长。
  15. 根据权利要求13所述的像素充电方法，其中，所述关闭当前行像素的薄膜晶体管开关的步骤，包括：
    暂停或停止向所述当前行像素发送栅极信号；
    输入负极性信号的所述第一数据线对应的薄膜晶体管开关延时第一时长关闭；
    输入正极性信号的所述第二数据线对应的薄膜晶体管开关延时第二时长关闭，所述第二时长大于所述第一时长。
  16. 根据权利要求8所述的像素充电方法，其中，所述第一预设时长与所述第二预设时长均介于0.5微秒至1微秒之间。
  17. 一种显示面板，其包括：
    第一充电模块，所述第一充电模块用于在第一帧画面中，向所述第一数据线输入正极性信号，间隔第一预设时长后，向所述第二数据线输入负极性信号；
    第二充电模块，所述第二充电模块用于在第二帧画面中，向所述第一数据线输入负极性信号，间隔第二预设时长后，向所述第二数据线输入正极性信号。
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